1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is the top level entry point for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 // Get the target-independent interfaces which we are implementing.
16 include "llvm/Target/Target.td"
18 //===----------------------------------------------------------------------===//
19 // PowerPC Subtarget features.
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
35 def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
36 def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
37 def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
38 def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
39 "PPC::DIR_E500mc", "">;
40 def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective",
41 "PPC::DIR_E5500", "">;
42 def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
43 def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
44 def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
45 def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
46 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
47 def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
48 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
49 def DirectivePwr8: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR8", "">;
51 def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
52 "Enable 64-bit instructions">;
53 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
54 "Enable 64-bit registers usage for ppc32 [beta]">;
55 def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true",
56 "Use condition-register bits individually">;
57 def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
58 "Enable Altivec instructions">;
59 def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true",
60 "Enable SPE instructions">;
61 def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
62 "Enable the MFOCRF instruction">;
63 def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
64 "Enable the fsqrt instruction">;
65 def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
66 "Enable the fcpsgn instruction">;
67 def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true",
68 "Enable the fre instruction">;
69 def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true",
70 "Enable the fres instruction">;
71 def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
72 "Enable the frsqrte instruction">;
73 def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
74 "Enable the frsqrtes instruction">;
75 def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
76 "Assume higher precision reciprocal estimates">;
77 def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
78 "Enable the stfiwx instruction">;
79 def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
80 "Enable the lfiwax instruction">;
81 def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true",
82 "Enable the fri[mnpz] instructions">;
83 def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
84 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">;
85 def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",
86 "Enable the isel instruction">;
87 def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
88 "Enable the popcnt[dw] instructions">;
89 def FeatureBPERMD : SubtargetFeature<"bpermd", "HasBPERMD", "true",
90 "Enable the bpermd instruction">;
91 def FeatureExtDiv : SubtargetFeature<"extdiv", "HasExtDiv", "true",
92 "Enable extended divide instructions">;
93 def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true",
94 "Enable the ldbrx instruction">;
95 def FeatureCMPB : SubtargetFeature<"cmpb", "HasCMPB", "true",
96 "Enable the cmpb instruction">;
97 def FeatureICBT : SubtargetFeature<"icbt","HasICBT", "true",
98 "Enable icbt instruction">;
99 def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
100 "Enable Book E instructions",
102 def FeatureMSYNC : SubtargetFeature<"msync", "HasOnlyMSYNC", "true",
103 "Has only the msync instruction instead of sync",
105 def FeatureE500 : SubtargetFeature<"e500", "IsE500", "true",
106 "Enable E500/E500mc instructions">;
107 def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
108 "Enable PPC 4xx instructions">;
109 def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",
110 "Enable PPC 6xx instructions">;
111 def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true",
112 "Enable QPX instructions">;
113 def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true",
114 "Enable VSX instructions",
116 def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true",
117 "Enable POWER8 Altivec instructions",
119 def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true",
120 "Enable POWER8 Crypto instructions",
122 def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
123 "Enable POWER8 vector instructions",
124 [FeatureVSX, FeatureP8Altivec]>;
125 def FeatureDirectMove :
126 SubtargetFeature<"direct-move", "HasDirectMove", "true",
127 "Enable Power8 direct move instructions",
129 def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics",
130 "HasPartwordAtomics", "true",
131 "Enable l[bh]arx and st[bh]cx.">;
132 def FeatureInvariantFunctionDescriptors :
133 SubtargetFeature<"invariant-function-descriptors",
134 "HasInvariantFunctionDescriptors", "true",
135 "Assume function descriptors are invariant">;
136 def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true",
137 "Enable Hardware Transactional Memory instructions">;
138 def FeatureMFTB : SubtargetFeature<"", "FeatureMFTB", "true",
139 "Implement mftb using the mfspr instruction">;
140 def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true",
141 "Target supports add/load integer fusion.">;
143 def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true",
144 "Treat vector data stream cache control instructions as deprecated">;
146 /* Since new processors generally contain a superset of features of those that
147 came before them, the idea is to make implementations of new processors
148 less error prone and easier to read.
150 list<SubtargetFeature> Power8FeatureList = ...
151 list<SubtargetFeature> FutureProcessorSpecificFeatureList =
152 [ features that Power8 does not support ]
153 list<SubtargetFeature> FutureProcessorFeatureList =
154 !listconcat(Power8FeatureList, FutureProcessorSpecificFeatureList)
156 Makes it explicit and obvious what is new in FutureProcesor vs. Power8 as
157 well as providing a single point of definition if the feature set will be
160 def ProcessorFeatures {
161 list<SubtargetFeature> Power7FeatureList =
162 [DirectivePwr7, FeatureAltivec, FeatureVSX,
163 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
164 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
165 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
166 FeatureFPRND, FeatureFPCVT, FeatureISEL,
167 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX,
168 Feature64Bit /*, Feature64BitRegs */,
169 FeatureBPERMD, FeatureExtDiv,
170 FeatureMFTB, DeprecatedDST];
171 list<SubtargetFeature> Power8SpecificFeatures =
172 [DirectivePwr8, FeatureP8Altivec, FeatureP8Vector, FeatureP8Crypto,
173 FeatureHTM, FeatureDirectMove, FeatureICBT, FeaturePartwordAtomic,
175 list<SubtargetFeature> Power8FeatureList =
176 !listconcat(Power7FeatureList, Power8SpecificFeatures);
179 // Note: Future features to add when support is extended to more
180 // recent ISA levels:
182 // DFP p6, p6x, p7 decimal floating-point instructions
183 // POPCNTB p5 through p7 popcntb and related instructions
185 //===----------------------------------------------------------------------===//
186 // Classes used for relation maps.
187 //===----------------------------------------------------------------------===//
188 // RecFormRel - Filter class used to relate non-record-form instructions with
189 // their record-form variants.
192 // AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
193 // FMA instruction forms with their corresponding factor-killing forms.
198 //===----------------------------------------------------------------------===//
199 // Relation Map Definitions.
200 //===----------------------------------------------------------------------===//
202 def getRecordFormOpcode : InstrMapping {
203 let FilterClass = "RecFormRel";
204 // Instructions with the same BaseName and Interpretation64Bit values
206 let RowFields = ["BaseName", "Interpretation64Bit"];
207 // Instructions with the same RC value form a column.
208 let ColFields = ["RC"];
209 // The key column are the non-record-form instructions.
211 // Value columns RC=1
212 let ValueCols = [["1"]];
215 def getNonRecordFormOpcode : InstrMapping {
216 let FilterClass = "RecFormRel";
217 // Instructions with the same BaseName and Interpretation64Bit values
219 let RowFields = ["BaseName", "Interpretation64Bit"];
220 // Instructions with the same RC value form a column.
221 let ColFields = ["RC"];
222 // The key column are the record-form instructions.
224 // Value columns are RC=0
225 let ValueCols = [["0"]];
228 def getAltVSXFMAOpcode : InstrMapping {
229 let FilterClass = "AltVSXFMARel";
230 // Instructions with the same BaseName and Interpretation64Bit values
232 let RowFields = ["BaseName"];
233 // Instructions with the same RC value form a column.
234 let ColFields = ["IsVSXFMAAlt"];
235 // The key column are the (default) addend-killing instructions.
237 // Value columns IsVSXFMAAlt=1
238 let ValueCols = [["1"]];
241 //===----------------------------------------------------------------------===//
242 // Register File Description
243 //===----------------------------------------------------------------------===//
245 include "PPCRegisterInfo.td"
246 include "PPCSchedule.td"
247 include "PPCInstrInfo.td"
249 //===----------------------------------------------------------------------===//
250 // PowerPC processors supported.
253 def : Processor<"generic", G3Itineraries, [Directive32, FeatureMFTB]>;
254 def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
255 FeatureFRES, FeatureFRSQRTE,
256 FeatureICBT, FeatureBookE,
257 FeatureMSYNC, FeatureMFTB]>;
258 def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
259 FeatureFRES, FeatureFRSQRTE,
260 FeatureICBT, FeatureBookE,
261 FeatureMSYNC, FeatureMFTB]>;
262 def : Processor<"601", G3Itineraries, [Directive601]>;
263 def : Processor<"602", G3Itineraries, [Directive602,
265 def : Processor<"603", G3Itineraries, [Directive603,
266 FeatureFRES, FeatureFRSQRTE,
268 def : Processor<"603e", G3Itineraries, [Directive603,
269 FeatureFRES, FeatureFRSQRTE,
271 def : Processor<"603ev", G3Itineraries, [Directive603,
272 FeatureFRES, FeatureFRSQRTE,
274 def : Processor<"604", G3Itineraries, [Directive604,
275 FeatureFRES, FeatureFRSQRTE,
277 def : Processor<"604e", G3Itineraries, [Directive604,
278 FeatureFRES, FeatureFRSQRTE,
280 def : Processor<"620", G3Itineraries, [Directive620,
281 FeatureFRES, FeatureFRSQRTE,
283 def : Processor<"750", G4Itineraries, [Directive750,
284 FeatureFRES, FeatureFRSQRTE,
286 def : Processor<"g3", G3Itineraries, [Directive750,
287 FeatureFRES, FeatureFRSQRTE,
289 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
290 FeatureFRES, FeatureFRSQRTE,
292 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
293 FeatureFRES, FeatureFRSQRTE,
295 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
296 FeatureFRES, FeatureFRSQRTE,
298 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
299 FeatureFRES, FeatureFRSQRTE,
302 def : ProcessorModel<"970", G5Model,
303 [Directive970, FeatureAltivec,
304 FeatureMFOCRF, FeatureFSqrt,
305 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
306 Feature64Bit /*, Feature64BitRegs */,
308 def : ProcessorModel<"g5", G5Model,
309 [Directive970, FeatureAltivec,
310 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
311 FeatureFRES, FeatureFRSQRTE,
312 Feature64Bit /*, Feature64BitRegs */,
313 FeatureMFTB, DeprecatedDST]>;
314 def : ProcessorModel<"e500mc", PPCE500mcModel,
316 FeatureSTFIWX, FeatureICBT, FeatureBookE,
317 FeatureISEL, FeatureMFTB]>;
318 def : ProcessorModel<"e5500", PPCE5500Model,
319 [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
320 FeatureSTFIWX, FeatureICBT, FeatureBookE,
321 FeatureISEL, FeatureMFTB]>;
322 def : ProcessorModel<"a2", PPCA2Model,
323 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
324 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
325 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
326 FeatureSTFIWX, FeatureLFIWAX,
327 FeatureFPRND, FeatureFPCVT, FeatureISEL,
328 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit
329 /*, Feature64BitRegs */, FeatureMFTB]>;
330 def : ProcessorModel<"a2q", PPCA2Model,
331 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
332 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
333 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
334 FeatureSTFIWX, FeatureLFIWAX,
335 FeatureFPRND, FeatureFPCVT, FeatureISEL,
336 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit
337 /*, Feature64BitRegs */, FeatureQPX, FeatureMFTB]>;
338 def : ProcessorModel<"pwr3", G5Model,
339 [DirectivePwr3, FeatureAltivec,
340 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
341 FeatureSTFIWX, Feature64Bit]>;
342 def : ProcessorModel<"pwr4", G5Model,
343 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
344 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
345 FeatureSTFIWX, Feature64Bit, FeatureMFTB]>;
346 def : ProcessorModel<"pwr5", G5Model,
347 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
348 FeatureFSqrt, FeatureFRE, FeatureFRES,
349 FeatureFRSQRTE, FeatureFRSQRTES,
350 FeatureSTFIWX, Feature64Bit,
351 FeatureMFTB, DeprecatedDST]>;
352 def : ProcessorModel<"pwr5x", G5Model,
353 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
354 FeatureFSqrt, FeatureFRE, FeatureFRES,
355 FeatureFRSQRTE, FeatureFRSQRTES,
356 FeatureSTFIWX, FeatureFPRND, Feature64Bit,
357 FeatureMFTB, DeprecatedDST]>;
358 def : ProcessorModel<"pwr6", G5Model,
359 [DirectivePwr6, FeatureAltivec,
360 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
361 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
362 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
363 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
364 FeatureMFTB, DeprecatedDST]>;
365 def : ProcessorModel<"pwr6x", G5Model,
366 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
367 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
368 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
369 FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
370 FeatureFPRND, Feature64Bit,
371 FeatureMFTB, DeprecatedDST]>;
372 def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.Power7FeatureList>;
373 def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.Power8FeatureList>;
374 def : Processor<"ppc", G3Itineraries, [Directive32, FeatureMFTB]>;
375 def : ProcessorModel<"ppc64", G5Model,
376 [Directive64, FeatureAltivec,
377 FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
378 FeatureFRSQRTE, FeatureSTFIWX,
379 Feature64Bit /*, Feature64BitRegs */,
381 def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.Power8FeatureList>;
383 //===----------------------------------------------------------------------===//
384 // Calling Conventions
385 //===----------------------------------------------------------------------===//
387 include "PPCCallingConv.td"
389 def PPCInstrInfo : InstrInfo {
390 let isLittleEndianEncoding = 1;
392 // FIXME: Unset this when no longer needed!
393 let decodePositionallyEncodedOperands = 1;
395 let noNamedPositionallyEncodedOperands = 1;
398 def PPCAsmParser : AsmParser {
399 let ShouldEmitMatchRegisterName = 0;
402 def PPCAsmParserVariant : AsmParserVariant {
405 // We do not use hard coded registers in asm strings. However, some
406 // InstAlias definitions use immediate literals. Set RegisterPrefix
407 // so that those are not misinterpreted as registers.
408 string RegisterPrefix = "%";
409 string BreakCharacters = ".";
413 // Information about the instructions.
414 let InstructionSet = PPCInstrInfo;
416 let AssemblyParsers = [PPCAsmParser];
417 let AssemblyParserVariants = [PPCAsmParserVariant];