1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is the top level entry point for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 // Get the target-independent interfaces which we are implementing.
16 include "llvm/Target/Target.td"
18 //===----------------------------------------------------------------------===//
19 // PowerPC Subtarget features.
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
35 def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
36 def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
37 def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
38 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
39 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
41 def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
42 "Enable 64-bit instructions">;
43 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
44 "Enable 64-bit registers usage for ppc32 [beta]">;
45 def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
46 "Enable Altivec instructions">;
47 def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
48 "Enable the MFOCRF instruction">;
49 def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
50 "Enable the fsqrt instruction">;
51 def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
52 "Enable the stfiwx instruction">;
53 def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
54 "Enable Book E instructions">;
56 //===----------------------------------------------------------------------===//
57 // Register File Description
58 //===----------------------------------------------------------------------===//
60 include "PPCRegisterInfo.td"
61 include "PPCSchedule.td"
62 include "PPCInstrInfo.td"
64 //===----------------------------------------------------------------------===//
65 // PowerPC processors supported.
68 def : Processor<"generic", G3Itineraries, [Directive32]>;
69 def : Processor<"440", PPC440Itineraries, [Directive440, FeatureBookE]>;
70 def : Processor<"450", PPC440Itineraries, [Directive440, FeatureBookE]>;
71 def : Processor<"601", G3Itineraries, [Directive601]>;
72 def : Processor<"602", G3Itineraries, [Directive602]>;
73 def : Processor<"603", G3Itineraries, [Directive603]>;
74 def : Processor<"603e", G3Itineraries, [Directive603]>;
75 def : Processor<"603ev", G3Itineraries, [Directive603]>;
76 def : Processor<"604", G3Itineraries, [Directive604]>;
77 def : Processor<"604e", G3Itineraries, [Directive604]>;
78 def : Processor<"620", G3Itineraries, [Directive620]>;
79 def : Processor<"750", G4Itineraries, [Directive750]>;
80 def : Processor<"g3", G3Itineraries, [Directive750]>;
81 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec]>;
82 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec]>;
83 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec]>;
84 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec]>;
85 def : Processor<"970", G5Itineraries,
86 [Directive970, FeatureAltivec,
87 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
88 Feature64Bit /*, Feature64BitRegs */]>;
89 def : Processor<"g5", G5Itineraries,
90 [Directive970, FeatureAltivec,
91 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
92 Feature64Bit /*, Feature64BitRegs */]>;
93 def : Processor<"a2", PPCA2Itineraries, [DirectiveA2, FeatureBookE,
94 FeatureMFOCRF, FeatureFSqrt,
95 FeatureSTFIWX, Feature64Bit
96 /*, Feature64BitRegs */]>;
97 def : Processor<"pwr6", G5Itineraries,
98 [DirectivePwr6, FeatureAltivec,
99 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
100 Feature64Bit /*, Feature64BitRegs */]>;
101 def : Processor<"pwr7", G5Itineraries,
102 [DirectivePwr7, FeatureAltivec,
103 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
104 Feature64Bit /*, Feature64BitRegs */]>;
105 def : Processor<"ppc", G3Itineraries, [Directive32]>;
106 def : Processor<"ppc64", G5Itineraries,
107 [Directive64, FeatureAltivec,
108 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
109 Feature64Bit /*, Feature64BitRegs */]>;
112 //===----------------------------------------------------------------------===//
113 // Calling Conventions
114 //===----------------------------------------------------------------------===//
116 include "PPCCallingConv.td"
118 def PPCInstrInfo : InstrInfo {
119 let isLittleEndianEncoding = 1;
122 def PPCAsmWriter : AsmWriter {
123 string AsmWriterClassName = "InstPrinter";
124 bit isMCAsmWriter = 1;
128 // Information about the instructions.
129 let InstructionSet = PPCInstrInfo;
131 let AssemblyWriters = [PPCAsmWriter];