1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is the top level entry point for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 // Get the target-independent interfaces which we are implementing.
16 include "llvm/Target/Target.td"
18 //===----------------------------------------------------------------------===//
19 // PowerPC Subtarget features.
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
35 def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
36 def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
37 def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
38 def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
39 "PPC::DIR_E500mc", "">;
40 def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective",
41 "PPC::DIR_E5500", "">;
42 def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
43 def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
44 def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
45 def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
46 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
47 def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
48 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
49 def DirectivePwr8: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR8", "">;
51 def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
52 "Enable 64-bit instructions">;
53 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
54 "Enable 64-bit registers usage for ppc32 [beta]">;
55 def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true",
56 "Use condition-register bits individually">;
57 def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
58 "Enable Altivec instructions">;
59 def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true",
60 "Enable SPE instructions">;
61 def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
62 "Enable the MFOCRF instruction">;
63 def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
64 "Enable the fsqrt instruction">;
65 def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
66 "Enable the fcpsgn instruction">;
67 def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true",
68 "Enable the fre instruction">;
69 def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true",
70 "Enable the fres instruction">;
71 def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
72 "Enable the frsqrte instruction">;
73 def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
74 "Enable the frsqrtes instruction">;
75 def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
76 "Assume higher precision reciprocal estimates">;
77 def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
78 "Enable the stfiwx instruction">;
79 def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
80 "Enable the lfiwax instruction">;
81 def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true",
82 "Enable the fri[mnpz] instructions">;
83 def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
84 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">;
85 def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",
86 "Enable the isel instruction">;
87 def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
88 "Enable the popcnt[dw] instructions">;
89 def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true",
90 "Enable the ldbrx instruction">;
91 def FeatureCMPB : SubtargetFeature<"cmpb", "HasCMPB", "true",
92 "Enable the cmpb instruction">;
93 def FeatureICBT : SubtargetFeature<"icbt","HasICBT", "true",
94 "Enable icbt instruction">;
95 def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
96 "Enable Book E instructions",
98 def FeatureMSYNC : SubtargetFeature<"msync", "HasOnlyMSYNC", "true",
99 "Has only the msync instruction instead of sync",
101 def FeatureE500 : SubtargetFeature<"e500", "IsE500", "true",
102 "Enable E500/E500mc instructions">;
103 def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
104 "Enable PPC 4xx instructions">;
105 def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",
106 "Enable PPC 6xx instructions">;
107 def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true",
108 "Enable QPX instructions">;
109 def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true",
110 "Enable VSX instructions",
112 def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
113 "Enable POWER8 vector instructions",
114 [FeatureVSX, FeatureAltivec]>;
116 def FeatureInvariantFunctionDescriptors :
117 SubtargetFeature<"invariant-function-descriptors",
118 "HasInvariantFunctionDescriptors", "true",
119 "Assume function descriptors are invariant">;
121 def DeprecatedMFTB : SubtargetFeature<"", "DeprecatedMFTB", "true",
122 "Treat mftb as deprecated">;
123 def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true",
124 "Treat vector data stream cache control instructions as deprecated">;
126 // Note: Future features to add when support is extended to more
127 // recent ISA levels:
129 // DFP p6, p6x, p7 decimal floating-point instructions
130 // POPCNTB p5 through p7 popcntb and related instructions
132 //===----------------------------------------------------------------------===//
134 //===----------------------------------------------------------------------===//
136 def FeatureELFv1 : SubtargetFeature<"elfv1", "TargetABI", "PPC_ABI_ELFv1",
137 "Use the ELFv1 ABI">;
139 def FeatureELFv2 : SubtargetFeature<"elfv2", "TargetABI", "PPC_ABI_ELFv2",
140 "Use the ELFv2 ABI">;
142 //===----------------------------------------------------------------------===//
143 // Classes used for relation maps.
144 //===----------------------------------------------------------------------===//
145 // RecFormRel - Filter class used to relate non-record-form instructions with
146 // their record-form variants.
149 // AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
150 // FMA instruction forms with their corresponding factor-killing forms.
155 //===----------------------------------------------------------------------===//
156 // Relation Map Definitions.
157 //===----------------------------------------------------------------------===//
159 def getRecordFormOpcode : InstrMapping {
160 let FilterClass = "RecFormRel";
161 // Instructions with the same BaseName and Interpretation64Bit values
163 let RowFields = ["BaseName", "Interpretation64Bit"];
164 // Instructions with the same RC value form a column.
165 let ColFields = ["RC"];
166 // The key column are the non-record-form instructions.
168 // Value columns RC=1
169 let ValueCols = [["1"]];
172 def getNonRecordFormOpcode : InstrMapping {
173 let FilterClass = "RecFormRel";
174 // Instructions with the same BaseName and Interpretation64Bit values
176 let RowFields = ["BaseName", "Interpretation64Bit"];
177 // Instructions with the same RC value form a column.
178 let ColFields = ["RC"];
179 // The key column are the record-form instructions.
181 // Value columns are RC=0
182 let ValueCols = [["0"]];
185 def getAltVSXFMAOpcode : InstrMapping {
186 let FilterClass = "AltVSXFMARel";
187 // Instructions with the same BaseName and Interpretation64Bit values
189 let RowFields = ["BaseName"];
190 // Instructions with the same RC value form a column.
191 let ColFields = ["IsVSXFMAAlt"];
192 // The key column are the (default) addend-killing instructions.
194 // Value columns IsVSXFMAAlt=1
195 let ValueCols = [["1"]];
198 //===----------------------------------------------------------------------===//
199 // Register File Description
200 //===----------------------------------------------------------------------===//
202 include "PPCRegisterInfo.td"
203 include "PPCSchedule.td"
204 include "PPCInstrInfo.td"
206 //===----------------------------------------------------------------------===//
207 // PowerPC processors supported.
210 def : Processor<"generic", G3Itineraries, [Directive32]>;
211 def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
212 FeatureFRES, FeatureFRSQRTE,
213 FeatureICBT, FeatureBookE,
214 FeatureMSYNC, DeprecatedMFTB]>;
215 def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
216 FeatureFRES, FeatureFRSQRTE,
217 FeatureICBT, FeatureBookE,
218 FeatureMSYNC, DeprecatedMFTB]>;
219 def : Processor<"601", G3Itineraries, [Directive601]>;
220 def : Processor<"602", G3Itineraries, [Directive602]>;
221 def : Processor<"603", G3Itineraries, [Directive603,
222 FeatureFRES, FeatureFRSQRTE]>;
223 def : Processor<"603e", G3Itineraries, [Directive603,
224 FeatureFRES, FeatureFRSQRTE]>;
225 def : Processor<"603ev", G3Itineraries, [Directive603,
226 FeatureFRES, FeatureFRSQRTE]>;
227 def : Processor<"604", G3Itineraries, [Directive604,
228 FeatureFRES, FeatureFRSQRTE]>;
229 def : Processor<"604e", G3Itineraries, [Directive604,
230 FeatureFRES, FeatureFRSQRTE]>;
231 def : Processor<"620", G3Itineraries, [Directive620,
232 FeatureFRES, FeatureFRSQRTE]>;
233 def : Processor<"750", G4Itineraries, [Directive750,
234 FeatureFRES, FeatureFRSQRTE]>;
235 def : Processor<"g3", G3Itineraries, [Directive750,
236 FeatureFRES, FeatureFRSQRTE]>;
237 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
238 FeatureFRES, FeatureFRSQRTE]>;
239 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
240 FeatureFRES, FeatureFRSQRTE]>;
241 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
242 FeatureFRES, FeatureFRSQRTE]>;
243 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
244 FeatureFRES, FeatureFRSQRTE]>;
246 /* Since new processors generally contain a superset of features of those that
247 came before them, the idea is to make implementations of new processors
248 less error prone and easier to read.
250 list<SubtargetFeature> Power8FeatureList = ...
251 list<SubtargetFeature> FutureProcessorSpecificFeatureList =
252 [ features that Power8 does not support ]
253 list<SubtargetFeature> FutureProcessorFeatureList =
254 !listconcat(Power8FeatureList, FutureProcessorSpecificFeatureList)
256 Makes it explicit and obvious what is new in FutureProcesor vs. Power8 as
257 well as providing a single point of definition if the feature set will be
261 def ProcessorFeatures {
262 list<SubtargetFeature> Power8FeatureList =
263 [DirectivePwr8, FeatureAltivec, FeatureVSX, FeatureP8Vector,
264 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
265 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
266 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
267 FeatureFPRND, FeatureFPCVT, FeatureISEL,
268 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX,
269 Feature64Bit /*, Feature64BitRegs */, FeatureICBT,
270 DeprecatedMFTB, DeprecatedDST];
273 def : ProcessorModel<"970", G5Model,
274 [Directive970, FeatureAltivec,
275 FeatureMFOCRF, FeatureFSqrt,
276 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
277 Feature64Bit /*, Feature64BitRegs */]>;
278 def : ProcessorModel<"g5", G5Model,
279 [Directive970, FeatureAltivec,
280 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
281 FeatureFRES, FeatureFRSQRTE,
282 Feature64Bit /*, Feature64BitRegs */,
283 DeprecatedMFTB, DeprecatedDST]>;
284 def : ProcessorModel<"e500mc", PPCE500mcModel,
285 [DirectiveE500mc, FeatureMFOCRF,
286 FeatureSTFIWX, FeatureICBT, FeatureBookE,
287 FeatureISEL, DeprecatedMFTB]>;
288 def : ProcessorModel<"e5500", PPCE5500Model,
289 [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
290 FeatureSTFIWX, FeatureICBT, FeatureBookE,
291 FeatureISEL, DeprecatedMFTB]>;
292 def : ProcessorModel<"a2", PPCA2Model,
293 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
294 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
295 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
296 FeatureSTFIWX, FeatureLFIWAX,
297 FeatureFPRND, FeatureFPCVT, FeatureISEL,
298 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit
299 /*, Feature64BitRegs */, DeprecatedMFTB]>;
300 def : ProcessorModel<"a2q", PPCA2Model,
301 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
302 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
303 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
304 FeatureSTFIWX, FeatureLFIWAX,
305 FeatureFPRND, FeatureFPCVT, FeatureISEL,
306 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit
307 /*, Feature64BitRegs */, FeatureQPX, DeprecatedMFTB]>;
308 def : ProcessorModel<"pwr3", G5Model,
309 [DirectivePwr3, FeatureAltivec,
310 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
311 FeatureSTFIWX, Feature64Bit]>;
312 def : ProcessorModel<"pwr4", G5Model,
313 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
314 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
315 FeatureSTFIWX, Feature64Bit]>;
316 def : ProcessorModel<"pwr5", G5Model,
317 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
318 FeatureFSqrt, FeatureFRE, FeatureFRES,
319 FeatureFRSQRTE, FeatureFRSQRTES,
320 FeatureSTFIWX, Feature64Bit,
321 DeprecatedMFTB, DeprecatedDST]>;
322 def : ProcessorModel<"pwr5x", G5Model,
323 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
324 FeatureFSqrt, FeatureFRE, FeatureFRES,
325 FeatureFRSQRTE, FeatureFRSQRTES,
326 FeatureSTFIWX, FeatureFPRND, Feature64Bit,
327 DeprecatedMFTB, DeprecatedDST]>;
328 def : ProcessorModel<"pwr6", G5Model,
329 [DirectivePwr6, FeatureAltivec,
330 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
331 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
332 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
333 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
334 DeprecatedMFTB, DeprecatedDST]>;
335 def : ProcessorModel<"pwr6x", G5Model,
336 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
337 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
338 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
339 FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
340 FeatureFPRND, Feature64Bit,
341 DeprecatedMFTB, DeprecatedDST]>;
342 def : ProcessorModel<"pwr7", P7Model,
343 [DirectivePwr7, FeatureAltivec, FeatureVSX,
344 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
345 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
346 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
347 FeatureFPRND, FeatureFPCVT, FeatureISEL,
348 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX,
349 Feature64Bit /*, Feature64BitRegs */,
350 DeprecatedMFTB, DeprecatedDST]>;
351 def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.Power8FeatureList>;
352 def : Processor<"ppc", G3Itineraries, [Directive32]>;
353 def : ProcessorModel<"ppc64", G5Model,
354 [Directive64, FeatureAltivec,
355 FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
356 FeatureFRSQRTE, FeatureSTFIWX,
357 Feature64Bit /*, Feature64BitRegs */]>;
358 def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.Power8FeatureList>;
360 //===----------------------------------------------------------------------===//
361 // Calling Conventions
362 //===----------------------------------------------------------------------===//
364 include "PPCCallingConv.td"
366 def PPCInstrInfo : InstrInfo {
367 let isLittleEndianEncoding = 1;
369 // FIXME: Unset this when no longer needed!
370 let decodePositionallyEncodedOperands = 1;
372 let noNamedPositionallyEncodedOperands = 1;
375 def PPCAsmParser : AsmParser {
376 let ShouldEmitMatchRegisterName = 0;
379 def PPCAsmParserVariant : AsmParserVariant {
382 // We do not use hard coded registers in asm strings. However, some
383 // InstAlias definitions use immediate literals. Set RegisterPrefix
384 // so that those are not misinterpreted as registers.
385 string RegisterPrefix = "%";
389 // Information about the instructions.
390 let InstructionSet = PPCInstrInfo;
392 let AssemblyParsers = [PPCAsmParser];
393 let AssemblyParserVariants = [PPCAsmParserVariant];