1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is the top level entry point for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 // Get the target-independent interfaces which we are implementing.
16 include "llvm/Target/Target.td"
18 //===----------------------------------------------------------------------===//
19 // PowerPC Subtarget features.
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
35 def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
36 def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
37 def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
39 def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
40 "Enable 64-bit instructions">;
41 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
42 "Enable 64-bit registers usage for ppc32 [beta]">;
43 def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
44 "Enable Altivec instructions">;
45 def FeatureGPUL : SubtargetFeature<"gpul","IsGigaProcessor", "true",
46 "Enable GPUL instructions">;
47 def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
48 "Enable the fsqrt instruction">;
49 def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
50 "Enable the stfiwx instruction">;
51 def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
52 "Enable Book E instructions">;
54 //===----------------------------------------------------------------------===//
55 // Register File Description
56 //===----------------------------------------------------------------------===//
58 include "PPCRegisterInfo.td"
59 include "PPCSchedule.td"
60 include "PPCInstrInfo.td"
62 //===----------------------------------------------------------------------===//
63 // PowerPC processors supported.
66 def : Processor<"generic", G3Itineraries, [Directive32]>;
67 def : Processor<"440", PPC440Itineraries, [Directive440, FeatureBookE]>;
68 def : Processor<"450", PPC440Itineraries, [Directive440, FeatureBookE]>;
69 def : Processor<"601", G3Itineraries, [Directive601]>;
70 def : Processor<"602", G3Itineraries, [Directive602]>;
71 def : Processor<"603", G3Itineraries, [Directive603]>;
72 def : Processor<"603e", G3Itineraries, [Directive603]>;
73 def : Processor<"603ev", G3Itineraries, [Directive603]>;
74 def : Processor<"604", G3Itineraries, [Directive604]>;
75 def : Processor<"604e", G3Itineraries, [Directive604]>;
76 def : Processor<"620", G3Itineraries, [Directive620]>;
77 def : Processor<"g3", G3Itineraries, [Directive7400]>;
78 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec]>;
79 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec]>;
80 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec]>;
81 def : Processor<"g4+", G4PlusItineraries, [Directive750, FeatureAltivec]>;
82 def : Processor<"750", G4Itineraries, [Directive750, FeatureAltivec]>;
83 def : Processor<"970", G5Itineraries,
84 [Directive970, FeatureAltivec,
85 FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
86 Feature64Bit /*, Feature64BitRegs */]>;
87 def : Processor<"g5", G5Itineraries,
88 [Directive970, FeatureAltivec,
89 FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
90 Feature64Bit /*, Feature64BitRegs */]>;
91 def : Processor<"a2", PPCA2Itineraries, [DirectiveA2, FeatureBookE,
92 FeatureFSqrt, FeatureSTFIWX,
93 Feature64Bit /*, Feature64BitRegs */]>;
94 def : Processor<"ppc", G3Itineraries, [Directive32]>;
95 def : Processor<"ppc64", G5Itineraries,
96 [Directive64, FeatureAltivec,
97 FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
98 Feature64Bit /*, Feature64BitRegs */]>;
101 //===----------------------------------------------------------------------===//
102 // Calling Conventions
103 //===----------------------------------------------------------------------===//
105 include "PPCCallingConv.td"
107 def PPCInstrInfo : InstrInfo {
108 let isLittleEndianEncoding = 1;
111 def PPCAsmWriter : AsmWriter {
112 string AsmWriterClassName = "InstPrinter";
113 bit isMCAsmWriter = 1;
117 // Information about the instructions.
118 let InstructionSet = PPCInstrInfo;
120 let AssemblyWriters = [PPCAsmWriter];