1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is the top level entry point for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 // Get the target-independent interfaces which we are implementing.
16 include "llvm/Target/Target.td"
18 //===----------------------------------------------------------------------===//
19 // PowerPC Subtarget features.
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
35 def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
36 def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
37 def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
38 def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
39 "PPC::DIR_E500mc", "">;
40 def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective",
41 "PPC::DIR_E5500", "">;
42 def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
43 def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
44 def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
45 def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
46 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
47 def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
48 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
50 def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
51 "Enable 64-bit instructions">;
52 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
53 "Enable 64-bit registers usage for ppc32 [beta]">;
54 def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
55 "Enable Altivec instructions">;
56 def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
57 "Enable the MFOCRF instruction">;
58 def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
59 "Enable the fsqrt instruction">;
60 def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true",
61 "Enable the fre instruction">;
62 def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true",
63 "Enable the fres instruction">;
64 def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
65 "Enable the frsqrte instruction">;
66 def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
67 "Enable the frsqrtes instruction">;
68 def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
69 "Assume higher precision reciprocal estimates">;
70 def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
71 "Enable the stfiwx instruction">;
72 def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
73 "Enable the lfiwax instruction">;
74 def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true",
75 "Enable the fri[mnpz] instructions">;
76 def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
77 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">;
78 def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",
79 "Enable the isel instruction">;
80 def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
81 "Enable the popcnt[dw] instructions">;
82 def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true",
83 "Enable the ldbrx instruction">;
84 def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
85 "Enable Book E instructions">;
86 def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true",
87 "Enable QPX instructions">;
89 // Note: Future features to add when support is extended to more
92 // CMPB p6, p6x, p7 cmpb
93 // DFP p6, p6x, p7 decimal floating-point instructions
94 // POPCNTB p5 through p7 popcntb and related instructions
95 // VSX p7 vector-scalar instruction set
97 //===----------------------------------------------------------------------===//
98 // Register File Description
99 //===----------------------------------------------------------------------===//
101 include "PPCRegisterInfo.td"
102 include "PPCSchedule.td"
103 include "PPCInstrInfo.td"
105 //===----------------------------------------------------------------------===//
106 // PowerPC processors supported.
109 def : Processor<"generic", G3Itineraries, [Directive32]>;
110 def : Processor<"440", PPC440Itineraries, [Directive440, FeatureISEL,
111 FeatureFRES, FeatureFRSQRTE,
113 def : Processor<"450", PPC440Itineraries, [Directive440, FeatureISEL,
114 FeatureFRES, FeatureFRSQRTE,
116 def : Processor<"601", G3Itineraries, [Directive601]>;
117 def : Processor<"602", G3Itineraries, [Directive602]>;
118 def : Processor<"603", G3Itineraries, [Directive603,
119 FeatureFRES, FeatureFRSQRTE]>;
120 def : Processor<"603e", G3Itineraries, [Directive603,
121 FeatureFRES, FeatureFRSQRTE]>;
122 def : Processor<"603ev", G3Itineraries, [Directive603,
123 FeatureFRES, FeatureFRSQRTE]>;
124 def : Processor<"604", G3Itineraries, [Directive604,
125 FeatureFRES, FeatureFRSQRTE]>;
126 def : Processor<"604e", G3Itineraries, [Directive604,
127 FeatureFRES, FeatureFRSQRTE]>;
128 def : Processor<"620", G3Itineraries, [Directive620,
129 FeatureFRES, FeatureFRSQRTE]>;
130 def : Processor<"750", G4Itineraries, [Directive750,
131 FeatureFRES, FeatureFRSQRTE]>;
132 def : Processor<"g3", G3Itineraries, [Directive750,
133 FeatureFRES, FeatureFRSQRTE]>;
134 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
135 FeatureFRES, FeatureFRSQRTE]>;
136 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
137 FeatureFRES, FeatureFRSQRTE]>;
138 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
139 FeatureFRES, FeatureFRSQRTE]>;
140 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
141 FeatureFRES, FeatureFRSQRTE]>;
142 def : Processor<"970", G5Itineraries,
143 [Directive970, FeatureAltivec,
144 FeatureMFOCRF, FeatureFSqrt,
145 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
146 Feature64Bit /*, Feature64BitRegs */]>;
147 def : Processor<"g5", G5Itineraries,
148 [Directive970, FeatureAltivec,
149 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
150 FeatureFRES, FeatureFRSQRTE,
151 Feature64Bit /*, Feature64BitRegs */]>;
152 def : ProcessorModel<"e500mc", PPCE500mcModel,
153 [DirectiveE500mc, FeatureMFOCRF,
154 FeatureSTFIWX, FeatureBookE, FeatureISEL]>;
155 def : ProcessorModel<"e5500", PPCE5500Model,
156 [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
157 FeatureSTFIWX, FeatureBookE, FeatureISEL]>;
158 def : Processor<"a2", PPCA2Itineraries,
159 [DirectiveA2, FeatureBookE, FeatureMFOCRF,
160 FeatureFSqrt, FeatureFRE, FeatureFRES,
161 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
162 FeatureSTFIWX, FeatureLFIWAX,
163 FeatureFPRND, FeatureFPCVT, FeatureISEL,
164 FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
165 /*, Feature64BitRegs */]>;
166 def : Processor<"a2q", PPCA2Itineraries,
167 [DirectiveA2, FeatureBookE, FeatureMFOCRF,
168 FeatureFSqrt, FeatureFRE, FeatureFRES,
169 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
170 FeatureSTFIWX, FeatureLFIWAX,
171 FeatureFPRND, FeatureFPCVT, FeatureISEL,
172 FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
173 /*, Feature64BitRegs */, FeatureQPX]>;
174 def : Processor<"pwr3", G5Itineraries,
175 [DirectivePwr3, FeatureAltivec,
176 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
177 FeatureSTFIWX, Feature64Bit]>;
178 def : Processor<"pwr4", G5Itineraries,
179 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
180 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
181 FeatureSTFIWX, Feature64Bit]>;
182 def : Processor<"pwr5", G5Itineraries,
183 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
184 FeatureFSqrt, FeatureFRE, FeatureFRES,
185 FeatureFRSQRTE, FeatureFRSQRTES,
186 FeatureSTFIWX, Feature64Bit]>;
187 def : Processor<"pwr5x", G5Itineraries,
188 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
189 FeatureFSqrt, FeatureFRE, FeatureFRES,
190 FeatureFRSQRTE, FeatureFRSQRTES,
191 FeatureSTFIWX, FeatureFPRND, Feature64Bit]>;
192 def : Processor<"pwr6", G5Itineraries,
193 [DirectivePwr6, FeatureAltivec,
194 FeatureMFOCRF, FeatureFSqrt, FeatureFRE,
195 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
196 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
197 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */]>;
198 def : Processor<"pwr6x", G5Itineraries,
199 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
200 FeatureFSqrt, FeatureFRE, FeatureFRES,
201 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
202 FeatureSTFIWX, FeatureLFIWAX,
203 FeatureFPRND, Feature64Bit]>;
204 def : Processor<"pwr7", G5Itineraries,
205 [DirectivePwr7, FeatureAltivec,
206 FeatureMFOCRF, FeatureFSqrt, FeatureFRE,
207 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
208 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
209 FeatureFPRND, FeatureFPCVT, FeatureISEL,
210 FeaturePOPCNTD, FeatureLDBRX,
211 Feature64Bit /*, Feature64BitRegs */]>;
212 def : Processor<"ppc", G3Itineraries, [Directive32]>;
213 def : Processor<"ppc64", G5Itineraries,
214 [Directive64, FeatureAltivec,
215 FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
216 FeatureFRSQRTE, FeatureSTFIWX,
217 Feature64Bit /*, Feature64BitRegs */]>;
220 //===----------------------------------------------------------------------===//
221 // Calling Conventions
222 //===----------------------------------------------------------------------===//
224 include "PPCCallingConv.td"
226 def PPCInstrInfo : InstrInfo {
227 let isLittleEndianEncoding = 1;
230 def PPCAsmWriter : AsmWriter {
231 string AsmWriterClassName = "InstPrinter";
232 bit isMCAsmWriter = 1;
236 // Information about the instructions.
237 let InstructionSet = PPCInstrInfo;
239 let AssemblyWriters = [PPCAsmWriter];