1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is the top level entry point for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 // Get the target-independent interfaces which we are implementing.
16 include "llvm/Target/Target.td"
18 //===----------------------------------------------------------------------===//
19 // PowerPC Subtarget features.
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
35 def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
36 def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
37 def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
38 def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
39 "PPC::DIR_E500mc", "">;
40 def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective",
41 "PPC::DIR_E5500", "">;
42 def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
43 def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
44 def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
45 def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
46 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
47 def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
48 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
49 def DirectivePwr8: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR8", "">;
51 def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
52 "Enable 64-bit instructions">;
53 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
54 "Enable 64-bit registers usage for ppc32 [beta]">;
55 def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true",
56 "Use condition-register bits individually">;
57 def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
58 "Enable Altivec instructions">;
59 def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true",
60 "Enable SPE instructions">;
61 def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
62 "Enable the MFOCRF instruction">;
63 def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
64 "Enable the fsqrt instruction">;
65 def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
66 "Enable the fcpsgn instruction">;
67 def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true",
68 "Enable the fre instruction">;
69 def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true",
70 "Enable the fres instruction">;
71 def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
72 "Enable the frsqrte instruction">;
73 def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
74 "Enable the frsqrtes instruction">;
75 def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
76 "Assume higher precision reciprocal estimates">;
77 def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
78 "Enable the stfiwx instruction">;
79 def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
80 "Enable the lfiwax instruction">;
81 def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true",
82 "Enable the fri[mnpz] instructions">;
83 def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
84 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">;
85 def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",
86 "Enable the isel instruction">;
87 def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
88 "Enable the popcnt[dw] instructions">;
89 def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true",
90 "Enable the ldbrx instruction">;
91 def FeatureCMPB : SubtargetFeature<"cmpb", "HasCMPB", "true",
92 "Enable the cmpb instruction">;
93 def FeatureICBT : SubtargetFeature<"icbt","HasICBT", "true",
94 "Enable icbt instruction">;
95 def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
96 "Enable Book E instructions",
98 def FeatureMSYNC : SubtargetFeature<"msync", "HasOnlyMSYNC", "true",
99 "Has only the msync instruction instead of sync",
101 def FeatureE500 : SubtargetFeature<"e500", "IsE500", "true",
102 "Enable E500/E500mc instructions">;
103 def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
104 "Enable PPC 4xx instructions">;
105 def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",
106 "Enable PPC 6xx instructions">;
107 def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true",
108 "Enable QPX instructions">;
109 def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true",
110 "Enable VSX instructions",
112 def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true",
113 "Enable POWER8 Altivec instructions",
115 def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
116 "Enable POWER8 vector instructions",
117 [FeatureVSX, FeatureP8Altivec]>;
119 def FeatureInvariantFunctionDescriptors :
120 SubtargetFeature<"invariant-function-descriptors",
121 "HasInvariantFunctionDescriptors", "true",
122 "Assume function descriptors are invariant">;
124 def DeprecatedMFTB : SubtargetFeature<"", "DeprecatedMFTB", "true",
125 "Treat mftb as deprecated">;
126 def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true",
127 "Treat vector data stream cache control instructions as deprecated">;
129 // Note: Future features to add when support is extended to more
130 // recent ISA levels:
132 // DFP p6, p6x, p7 decimal floating-point instructions
133 // POPCNTB p5 through p7 popcntb and related instructions
135 //===----------------------------------------------------------------------===//
136 // Classes used for relation maps.
137 //===----------------------------------------------------------------------===//
138 // RecFormRel - Filter class used to relate non-record-form instructions with
139 // their record-form variants.
142 // AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
143 // FMA instruction forms with their corresponding factor-killing forms.
148 //===----------------------------------------------------------------------===//
149 // Relation Map Definitions.
150 //===----------------------------------------------------------------------===//
152 def getRecordFormOpcode : InstrMapping {
153 let FilterClass = "RecFormRel";
154 // Instructions with the same BaseName and Interpretation64Bit values
156 let RowFields = ["BaseName", "Interpretation64Bit"];
157 // Instructions with the same RC value form a column.
158 let ColFields = ["RC"];
159 // The key column are the non-record-form instructions.
161 // Value columns RC=1
162 let ValueCols = [["1"]];
165 def getNonRecordFormOpcode : InstrMapping {
166 let FilterClass = "RecFormRel";
167 // Instructions with the same BaseName and Interpretation64Bit values
169 let RowFields = ["BaseName", "Interpretation64Bit"];
170 // Instructions with the same RC value form a column.
171 let ColFields = ["RC"];
172 // The key column are the record-form instructions.
174 // Value columns are RC=0
175 let ValueCols = [["0"]];
178 def getAltVSXFMAOpcode : InstrMapping {
179 let FilterClass = "AltVSXFMARel";
180 // Instructions with the same BaseName and Interpretation64Bit values
182 let RowFields = ["BaseName"];
183 // Instructions with the same RC value form a column.
184 let ColFields = ["IsVSXFMAAlt"];
185 // The key column are the (default) addend-killing instructions.
187 // Value columns IsVSXFMAAlt=1
188 let ValueCols = [["1"]];
191 //===----------------------------------------------------------------------===//
192 // Register File Description
193 //===----------------------------------------------------------------------===//
195 include "PPCRegisterInfo.td"
196 include "PPCSchedule.td"
197 include "PPCInstrInfo.td"
199 //===----------------------------------------------------------------------===//
200 // PowerPC processors supported.
203 def : Processor<"generic", G3Itineraries, [Directive32]>;
204 def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
205 FeatureFRES, FeatureFRSQRTE,
206 FeatureICBT, FeatureBookE,
207 FeatureMSYNC, DeprecatedMFTB]>;
208 def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
209 FeatureFRES, FeatureFRSQRTE,
210 FeatureICBT, FeatureBookE,
211 FeatureMSYNC, DeprecatedMFTB]>;
212 def : Processor<"601", G3Itineraries, [Directive601]>;
213 def : Processor<"602", G3Itineraries, [Directive602]>;
214 def : Processor<"603", G3Itineraries, [Directive603,
215 FeatureFRES, FeatureFRSQRTE]>;
216 def : Processor<"603e", G3Itineraries, [Directive603,
217 FeatureFRES, FeatureFRSQRTE]>;
218 def : Processor<"603ev", G3Itineraries, [Directive603,
219 FeatureFRES, FeatureFRSQRTE]>;
220 def : Processor<"604", G3Itineraries, [Directive604,
221 FeatureFRES, FeatureFRSQRTE]>;
222 def : Processor<"604e", G3Itineraries, [Directive604,
223 FeatureFRES, FeatureFRSQRTE]>;
224 def : Processor<"620", G3Itineraries, [Directive620,
225 FeatureFRES, FeatureFRSQRTE]>;
226 def : Processor<"750", G4Itineraries, [Directive750,
227 FeatureFRES, FeatureFRSQRTE]>;
228 def : Processor<"g3", G3Itineraries, [Directive750,
229 FeatureFRES, FeatureFRSQRTE]>;
230 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
231 FeatureFRES, FeatureFRSQRTE]>;
232 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
233 FeatureFRES, FeatureFRSQRTE]>;
234 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
235 FeatureFRES, FeatureFRSQRTE]>;
236 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
237 FeatureFRES, FeatureFRSQRTE]>;
239 /* Since new processors generally contain a superset of features of those that
240 came before them, the idea is to make implementations of new processors
241 less error prone and easier to read.
243 list<SubtargetFeature> Power8FeatureList = ...
244 list<SubtargetFeature> FutureProcessorSpecificFeatureList =
245 [ features that Power8 does not support ]
246 list<SubtargetFeature> FutureProcessorFeatureList =
247 !listconcat(Power8FeatureList, FutureProcessorSpecificFeatureList)
249 Makes it explicit and obvious what is new in FutureProcesor vs. Power8 as
250 well as providing a single point of definition if the feature set will be
254 def ProcessorFeatures {
255 list<SubtargetFeature> Power8FeatureList =
256 [DirectivePwr8, FeatureAltivec, FeatureP8Altivec, FeatureVSX,
257 FeatureP8Vector, FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt,
258 FeatureFRE, FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
259 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
260 FeatureFPRND, FeatureFPCVT, FeatureISEL,
261 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX,
262 Feature64Bit /*, Feature64BitRegs */, FeatureICBT,
263 DeprecatedMFTB, DeprecatedDST];
266 def : ProcessorModel<"970", G5Model,
267 [Directive970, FeatureAltivec,
268 FeatureMFOCRF, FeatureFSqrt,
269 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
270 Feature64Bit /*, Feature64BitRegs */]>;
271 def : ProcessorModel<"g5", G5Model,
272 [Directive970, FeatureAltivec,
273 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
274 FeatureFRES, FeatureFRSQRTE,
275 Feature64Bit /*, Feature64BitRegs */,
276 DeprecatedMFTB, DeprecatedDST]>;
277 def : ProcessorModel<"e500mc", PPCE500mcModel,
278 [DirectiveE500mc, FeatureMFOCRF,
279 FeatureSTFIWX, FeatureICBT, FeatureBookE,
280 FeatureISEL, DeprecatedMFTB]>;
281 def : ProcessorModel<"e5500", PPCE5500Model,
282 [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
283 FeatureSTFIWX, FeatureICBT, FeatureBookE,
284 FeatureISEL, DeprecatedMFTB]>;
285 def : ProcessorModel<"a2", PPCA2Model,
286 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
287 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
288 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
289 FeatureSTFIWX, FeatureLFIWAX,
290 FeatureFPRND, FeatureFPCVT, FeatureISEL,
291 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit
292 /*, Feature64BitRegs */, DeprecatedMFTB]>;
293 def : ProcessorModel<"a2q", PPCA2Model,
294 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF,
295 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
296 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
297 FeatureSTFIWX, FeatureLFIWAX,
298 FeatureFPRND, FeatureFPCVT, FeatureISEL,
299 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit
300 /*, Feature64BitRegs */, FeatureQPX, DeprecatedMFTB]>;
301 def : ProcessorModel<"pwr3", G5Model,
302 [DirectivePwr3, FeatureAltivec,
303 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
304 FeatureSTFIWX, Feature64Bit]>;
305 def : ProcessorModel<"pwr4", G5Model,
306 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
307 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
308 FeatureSTFIWX, Feature64Bit]>;
309 def : ProcessorModel<"pwr5", G5Model,
310 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
311 FeatureFSqrt, FeatureFRE, FeatureFRES,
312 FeatureFRSQRTE, FeatureFRSQRTES,
313 FeatureSTFIWX, Feature64Bit,
314 DeprecatedMFTB, DeprecatedDST]>;
315 def : ProcessorModel<"pwr5x", G5Model,
316 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
317 FeatureFSqrt, FeatureFRE, FeatureFRES,
318 FeatureFRSQRTE, FeatureFRSQRTES,
319 FeatureSTFIWX, FeatureFPRND, Feature64Bit,
320 DeprecatedMFTB, DeprecatedDST]>;
321 def : ProcessorModel<"pwr6", G5Model,
322 [DirectivePwr6, FeatureAltivec,
323 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
324 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
325 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
326 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
327 DeprecatedMFTB, DeprecatedDST]>;
328 def : ProcessorModel<"pwr6x", G5Model,
329 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
330 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
331 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
332 FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
333 FeatureFPRND, Feature64Bit,
334 DeprecatedMFTB, DeprecatedDST]>;
335 def : ProcessorModel<"pwr7", P7Model,
336 [DirectivePwr7, FeatureAltivec, FeatureVSX,
337 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
338 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
339 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
340 FeatureFPRND, FeatureFPCVT, FeatureISEL,
341 FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX,
342 Feature64Bit /*, Feature64BitRegs */,
343 DeprecatedMFTB, DeprecatedDST]>;
344 def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.Power8FeatureList>;
345 def : Processor<"ppc", G3Itineraries, [Directive32]>;
346 def : ProcessorModel<"ppc64", G5Model,
347 [Directive64, FeatureAltivec,
348 FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
349 FeatureFRSQRTE, FeatureSTFIWX,
350 Feature64Bit /*, Feature64BitRegs */]>;
351 def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.Power8FeatureList>;
353 //===----------------------------------------------------------------------===//
354 // Calling Conventions
355 //===----------------------------------------------------------------------===//
357 include "PPCCallingConv.td"
359 def PPCInstrInfo : InstrInfo {
360 let isLittleEndianEncoding = 1;
362 // FIXME: Unset this when no longer needed!
363 let decodePositionallyEncodedOperands = 1;
365 let noNamedPositionallyEncodedOperands = 1;
368 def PPCAsmParser : AsmParser {
369 let ShouldEmitMatchRegisterName = 0;
372 def PPCAsmParserVariant : AsmParserVariant {
375 // We do not use hard coded registers in asm strings. However, some
376 // InstAlias definitions use immediate literals. Set RegisterPrefix
377 // so that those are not misinterpreted as registers.
378 string RegisterPrefix = "%";
382 // Information about the instructions.
383 let InstructionSet = PPCInstrInfo;
385 let AssemblyParsers = [PPCAsmParser];
386 let AssemblyParserVariants = [PPCAsmParserVariant];