1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is the top level entry point for the PowerPC target.
12 //===----------------------------------------------------------------------===//
14 // Get the target-independent interfaces which we are implementing.
16 include "llvm/Target/Target.td"
18 //===----------------------------------------------------------------------===//
19 // PowerPC Subtarget features.
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
35 def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
36 def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
37 def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
38 def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
39 "PPC::DIR_E500mc", "">;
40 def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective",
41 "PPC::DIR_E5500", "">;
42 def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
43 def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
44 def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
45 def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
46 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
47 def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
48 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
49 def DirectivePwr8: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR8", "">;
51 def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
52 "Enable 64-bit instructions">;
53 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
54 "Enable 64-bit registers usage for ppc32 [beta]">;
55 def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true",
56 "Use condition-register bits individually">;
57 def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
58 "Enable Altivec instructions">;
59 def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true",
60 "Enable SPE instructions">;
61 def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
62 "Enable the MFOCRF instruction">;
63 def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
64 "Enable the fsqrt instruction">;
65 def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
66 "Enable the fcpsgn instruction">;
67 def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true",
68 "Enable the fre instruction">;
69 def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true",
70 "Enable the fres instruction">;
71 def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
72 "Enable the frsqrte instruction">;
73 def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
74 "Enable the frsqrtes instruction">;
75 def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
76 "Assume higher precision reciprocal estimates">;
77 def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
78 "Enable the stfiwx instruction">;
79 def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
80 "Enable the lfiwax instruction">;
81 def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true",
82 "Enable the fri[mnpz] instructions">;
83 def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
84 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">;
85 def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",
86 "Enable the isel instruction">;
87 def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
88 "Enable the popcnt[dw] instructions">;
89 def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true",
90 "Enable the ldbrx instruction">;
91 def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
92 "Enable Book E instructions">;
93 def FeatureE500 : SubtargetFeature<"e500", "IsE500", "true",
94 "Enable E500/E500mc instructions">;
95 def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
96 "Enable PPC 4xx instructions">;
97 def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",
98 "Enable PPC 6xx instructions">;
99 def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true",
100 "Enable QPX instructions">;
101 def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true",
102 "Enable VSX instructions",
105 def DeprecatedMFTB : SubtargetFeature<"", "DeprecatedMFTB", "true",
106 "Treat mftb as deprecated">;
107 def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true",
108 "Treat vector data stream cache control instructions as deprecated">;
110 // Note: Future features to add when support is extended to more
111 // recent ISA levels:
113 // CMPB p6, p6x, p7 cmpb
114 // DFP p6, p6x, p7 decimal floating-point instructions
115 // POPCNTB p5 through p7 popcntb and related instructions
116 // VSX p7 vector-scalar instruction set
118 //===----------------------------------------------------------------------===//
120 //===----------------------------------------------------------------------===//
122 def FeatureELFv1 : SubtargetFeature<"elfv1", "TargetABI", "PPC_ABI_ELFv1",
123 "Use the ELFv1 ABI">;
125 def FeatureELFv2 : SubtargetFeature<"elfv2", "TargetABI", "PPC_ABI_ELFv2",
126 "Use the ELFv2 ABI">;
128 //===----------------------------------------------------------------------===//
129 // Classes used for relation maps.
130 //===----------------------------------------------------------------------===//
131 // RecFormRel - Filter class used to relate non-record-form instructions with
132 // their record-form variants.
135 // AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
136 // FMA instruction forms with their corresponding factor-killing forms.
141 //===----------------------------------------------------------------------===//
142 // Relation Map Definitions.
143 //===----------------------------------------------------------------------===//
145 def getRecordFormOpcode : InstrMapping {
146 let FilterClass = "RecFormRel";
147 // Instructions with the same BaseName and Interpretation64Bit values
149 let RowFields = ["BaseName", "Interpretation64Bit"];
150 // Instructions with the same RC value form a column.
151 let ColFields = ["RC"];
152 // The key column are the non-record-form instructions.
154 // Value columns RC=1
155 let ValueCols = [["1"]];
158 def getNonRecordFormOpcode : InstrMapping {
159 let FilterClass = "RecFormRel";
160 // Instructions with the same BaseName and Interpretation64Bit values
162 let RowFields = ["BaseName", "Interpretation64Bit"];
163 // Instructions with the same RC value form a column.
164 let ColFields = ["RC"];
165 // The key column are the record-form instructions.
167 // Value columns are RC=0
168 let ValueCols = [["0"]];
171 def getAltVSXFMAOpcode : InstrMapping {
172 let FilterClass = "AltVSXFMARel";
173 // Instructions with the same BaseName and Interpretation64Bit values
175 let RowFields = ["BaseName"];
176 // Instructions with the same RC value form a column.
177 let ColFields = ["IsVSXFMAAlt"];
178 // The key column are the (default) addend-killing instructions.
180 // Value columns IsVSXFMAAlt=1
181 let ValueCols = [["1"]];
184 //===----------------------------------------------------------------------===//
185 // Register File Description
186 //===----------------------------------------------------------------------===//
188 include "PPCRegisterInfo.td"
189 include "PPCSchedule.td"
190 include "PPCInstrInfo.td"
192 //===----------------------------------------------------------------------===//
193 // PowerPC processors supported.
196 def : Processor<"generic", G3Itineraries, [Directive32]>;
197 def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
198 FeatureFRES, FeatureFRSQRTE,
199 FeatureBookE, DeprecatedMFTB]>;
200 def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
201 FeatureFRES, FeatureFRSQRTE,
202 FeatureBookE, DeprecatedMFTB]>;
203 def : Processor<"601", G3Itineraries, [Directive601]>;
204 def : Processor<"602", G3Itineraries, [Directive602]>;
205 def : Processor<"603", G3Itineraries, [Directive603,
206 FeatureFRES, FeatureFRSQRTE]>;
207 def : Processor<"603e", G3Itineraries, [Directive603,
208 FeatureFRES, FeatureFRSQRTE]>;
209 def : Processor<"603ev", G3Itineraries, [Directive603,
210 FeatureFRES, FeatureFRSQRTE]>;
211 def : Processor<"604", G3Itineraries, [Directive604,
212 FeatureFRES, FeatureFRSQRTE]>;
213 def : Processor<"604e", G3Itineraries, [Directive604,
214 FeatureFRES, FeatureFRSQRTE]>;
215 def : Processor<"620", G3Itineraries, [Directive620,
216 FeatureFRES, FeatureFRSQRTE]>;
217 def : Processor<"750", G4Itineraries, [Directive750,
218 FeatureFRES, FeatureFRSQRTE]>;
219 def : Processor<"g3", G3Itineraries, [Directive750,
220 FeatureFRES, FeatureFRSQRTE]>;
221 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
222 FeatureFRES, FeatureFRSQRTE]>;
223 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
224 FeatureFRES, FeatureFRSQRTE]>;
225 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
226 FeatureFRES, FeatureFRSQRTE]>;
227 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
228 FeatureFRES, FeatureFRSQRTE]>;
229 def : ProcessorModel<"970", G5Model,
230 [Directive970, FeatureAltivec,
231 FeatureMFOCRF, FeatureFSqrt,
232 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
233 Feature64Bit /*, Feature64BitRegs */]>;
234 def : ProcessorModel<"g5", G5Model,
235 [Directive970, FeatureAltivec,
236 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
237 FeatureFRES, FeatureFRSQRTE,
238 Feature64Bit /*, Feature64BitRegs */,
239 DeprecatedMFTB, DeprecatedDST]>;
240 def : ProcessorModel<"e500mc", PPCE500mcModel,
241 [DirectiveE500mc, FeatureMFOCRF,
242 FeatureSTFIWX, FeatureBookE, FeatureISEL,
244 def : ProcessorModel<"e5500", PPCE5500Model,
245 [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
246 FeatureSTFIWX, FeatureBookE, FeatureISEL,
248 def : ProcessorModel<"a2", PPCA2Model,
249 [DirectiveA2, FeatureBookE, FeatureMFOCRF,
250 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
251 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
252 FeatureSTFIWX, FeatureLFIWAX,
253 FeatureFPRND, FeatureFPCVT, FeatureISEL,
254 FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
255 /*, Feature64BitRegs */, DeprecatedMFTB]>;
256 def : ProcessorModel<"a2q", PPCA2Model,
257 [DirectiveA2, FeatureBookE, FeatureMFOCRF,
258 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
259 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
260 FeatureSTFIWX, FeatureLFIWAX,
261 FeatureFPRND, FeatureFPCVT, FeatureISEL,
262 FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
263 /*, Feature64BitRegs */, FeatureQPX, DeprecatedMFTB]>;
264 def : ProcessorModel<"pwr3", G5Model,
265 [DirectivePwr3, FeatureAltivec,
266 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
267 FeatureSTFIWX, Feature64Bit]>;
268 def : ProcessorModel<"pwr4", G5Model,
269 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
270 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
271 FeatureSTFIWX, Feature64Bit]>;
272 def : ProcessorModel<"pwr5", G5Model,
273 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
274 FeatureFSqrt, FeatureFRE, FeatureFRES,
275 FeatureFRSQRTE, FeatureFRSQRTES,
276 FeatureSTFIWX, Feature64Bit,
277 DeprecatedMFTB, DeprecatedDST]>;
278 def : ProcessorModel<"pwr5x", G5Model,
279 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
280 FeatureFSqrt, FeatureFRE, FeatureFRES,
281 FeatureFRSQRTE, FeatureFRSQRTES,
282 FeatureSTFIWX, FeatureFPRND, Feature64Bit,
283 DeprecatedMFTB, DeprecatedDST]>;
284 def : ProcessorModel<"pwr6", G5Model,
285 [DirectivePwr6, FeatureAltivec,
286 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
287 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
288 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
289 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
290 DeprecatedMFTB, DeprecatedDST]>;
291 def : ProcessorModel<"pwr6x", G5Model,
292 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
293 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
294 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
295 FeatureSTFIWX, FeatureLFIWAX,
296 FeatureFPRND, Feature64Bit,
297 DeprecatedMFTB, DeprecatedDST]>;
298 def : ProcessorModel<"pwr7", P7Model,
299 [DirectivePwr7, FeatureAltivec,
300 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
301 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
302 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
303 FeatureFPRND, FeatureFPCVT, FeatureISEL,
304 FeaturePOPCNTD, FeatureLDBRX,
305 Feature64Bit /*, Feature64BitRegs */,
306 DeprecatedMFTB, DeprecatedDST]>;
307 def : ProcessorModel<"pwr8", P7Model /* FIXME: Update to P8Model when available */,
308 [DirectivePwr8, FeatureAltivec,
309 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
310 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
311 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
312 FeatureFPRND, FeatureFPCVT, FeatureISEL,
313 FeaturePOPCNTD, FeatureLDBRX,
314 Feature64Bit /*, Feature64BitRegs */,
315 DeprecatedMFTB, DeprecatedDST]>;
316 def : Processor<"ppc", G3Itineraries, [Directive32]>;
317 def : ProcessorModel<"ppc64", G5Model,
318 [Directive64, FeatureAltivec,
319 FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
320 FeatureFRSQRTE, FeatureSTFIWX,
321 Feature64Bit /*, Feature64BitRegs */]>;
322 def : ProcessorModel<"ppc64le", G5Model,
323 [Directive64, FeatureAltivec,
324 FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
325 FeatureFRSQRTE, FeatureSTFIWX,
326 Feature64Bit /*, Feature64BitRegs */]>;
328 //===----------------------------------------------------------------------===//
329 // Calling Conventions
330 //===----------------------------------------------------------------------===//
332 include "PPCCallingConv.td"
334 def PPCInstrInfo : InstrInfo {
335 let isLittleEndianEncoding = 1;
337 // FIXME: Unset this when no longer needed!
338 let decodePositionallyEncodedOperands = 1;
340 let noNamedPositionallyEncodedOperands = 1;
343 def PPCAsmParser : AsmParser {
344 let ShouldEmitMatchRegisterName = 0;
347 def PPCAsmParserVariant : AsmParserVariant {
350 // We do not use hard coded registers in asm strings. However, some
351 // InstAlias definitions use immediate literals. Set RegisterPrefix
352 // so that those are not misinterpreted as registers.
353 string RegisterPrefix = "%";
357 // Information about the instructions.
358 let InstructionSet = PPCInstrInfo;
360 let AssemblyParsers = [PPCAsmParser];
361 let AssemblyParserVariants = [PPCAsmParserVariant];