lib/Target/PowerPC/PPC.td

   1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is the top level entry point for the PowerPC target.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // Get the target-independent interfaces which we are implementing.
  15 //
  16 include "llvm/Target/Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // PowerPC Subtarget features.
  20 //
  21
  22 //===----------------------------------------------------------------------===//
  23 // CPU Directives                                                             //
  24 //===----------------------------------------------------------------------===//
  25
  26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
  27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
  28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
  29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
  33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
  34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
  35 def Directive32  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
  36 def Directive64  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
  37 def DirectiveA2  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
  38 def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
  39                                        "PPC::DIR_E500mc", "">;
  40 def DirectiveE5500  : SubtargetFeature<"", "DarwinDirective",
  41                                        "PPC::DIR_E5500", "">;
  42 def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
  43 def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
  44 def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
  45 def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
  46 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
  47 def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
  48 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
  49
  50 def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",
  51                                         "Enable 64-bit instructions">;
  52 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
  53                               "Enable 64-bit registers usage for ppc32 [beta]">;
  54 def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true",
  55                                         "Enable Altivec instructions">;
  56 def FeatureMFOCRF    : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
  57                                         "Enable the MFOCRF instruction">;
  58 def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
  59                                         "Enable the fsqrt instruction">;
  60 def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
  61                                         "Enable the stfiwx instruction">;
  62 def FeatureISEL      : SubtargetFeature<"isel","HasISEL", "true",
  63                                         "Enable the isel instruction">;
  64 def FeatureBookE     : SubtargetFeature<"booke", "IsBookE", "true",
  65                                         "Enable Book E instructions">;
  66 def FeatureQPX       : SubtargetFeature<"qpx","HasQPX", "true",
  67                                         "Enable QPX instructions">;
  68
  69 //===----------------------------------------------------------------------===//
  70 // Register File Description
  71 //===----------------------------------------------------------------------===//
  72
  73 include "PPCRegisterInfo.td"
  74 include "PPCSchedule.td"
  75 include "PPCInstrInfo.td"
  76
  77 //===----------------------------------------------------------------------===//
  78 // PowerPC processors supported.
  79 //
  80
  81 def : Processor<"generic", G3Itineraries, [Directive32]>;
  82 def : Processor<"440", PPC440Itineraries, [Directive440, FeatureISEL,
  83                                            FeatureBookE]>;
  84 def : Processor<"450", PPC440Itineraries, [Directive440, FeatureISEL,
  85                                            FeatureBookE]>;
  86 def : Processor<"601", G3Itineraries, [Directive601]>;
  87 def : Processor<"602", G3Itineraries, [Directive602]>;
  88 def : Processor<"603", G3Itineraries, [Directive603]>;
  89 def : Processor<"603e", G3Itineraries, [Directive603]>;
  90 def : Processor<"603ev", G3Itineraries, [Directive603]>;
  91 def : Processor<"604", G3Itineraries, [Directive604]>;
  92 def : Processor<"604e", G3Itineraries, [Directive604]>;
  93 def : Processor<"620", G3Itineraries, [Directive620]>;
  94 def : Processor<"750", G4Itineraries, [Directive750]>;
  95 def : Processor<"g3", G3Itineraries, [Directive750]>;
  96 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec]>;
  97 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec]>;
  98 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec]>;
  99 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec]>;
 100 def : Processor<"970", G5Itineraries,
 101                   [Directive970, FeatureAltivec,
 102                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
 103                    Feature64Bit /*, Feature64BitRegs */]>;
 104 def : Processor<"g5", G5Itineraries,
 105                   [Directive970, FeatureAltivec,
 106                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
 107                    Feature64Bit /*, Feature64BitRegs */]>;
 108 def : ProcessorModel<"e500mc", PPCE500mcModel,
 109                   [DirectiveE500mc, FeatureMFOCRF,
 110                    FeatureSTFIWX, FeatureBookE, FeatureISEL]>;
 111 def : ProcessorModel<"e5500", PPCE5500Model,
 112                   [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
 113                    FeatureSTFIWX, FeatureBookE, FeatureISEL]>;
 114 def : Processor<"a2", PPCA2Itineraries, [DirectiveA2, FeatureBookE,
 115                                          FeatureMFOCRF, FeatureFSqrt,
 116                                          FeatureSTFIWX, FeatureISEL,
 117                                          Feature64Bit
 118                                      /*, Feature64BitRegs */]>;
 119 def : Processor<"a2q", PPCA2Itineraries, [DirectiveA2, FeatureBookE,
 120                                           FeatureMFOCRF, FeatureFSqrt,
 121                                           FeatureSTFIWX, FeatureISEL,
 122                                           Feature64Bit /*, Feature64BitRegs */,
 123                                           FeatureQPX]>;
 124 def : Processor<"pwr3", G5Itineraries,
 125                   [DirectivePwr3, FeatureAltivec, FeatureMFOCRF,
 126                    FeatureSTFIWX, Feature64Bit]>;
 127 def : Processor<"pwr4", G5Itineraries,
 128                   [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
 129                    FeatureFSqrt, FeatureSTFIWX, Feature64Bit]>;
 130 def : Processor<"pwr5", G5Itineraries,
 131                   [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
 132                    FeatureFSqrt, FeatureSTFIWX, Feature64Bit]>;
 133 def : Processor<"pwr5x", G5Itineraries,
 134                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
 135                    FeatureFSqrt, FeatureSTFIWX, Feature64Bit]>;
 136 def : Processor<"pwr6", G5Itineraries,
 137                   [DirectivePwr6, FeatureAltivec,
 138                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
 139                    Feature64Bit /*, Feature64BitRegs */]>;
 140 def : Processor<"pwr6x", G5Itineraries,
 141                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
 142                    FeatureFSqrt, FeatureSTFIWX, Feature64Bit]>;
 143 def : Processor<"pwr7", G5Itineraries,
 144                   [DirectivePwr7, FeatureAltivec,
 145                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
 146                    FeatureISEL, Feature64Bit /*, Feature64BitRegs */]>;
 147 def : Processor<"ppc", G3Itineraries, [Directive32]>;
 148 def : Processor<"ppc64", G5Itineraries,
 149                   [Directive64, FeatureAltivec,
 150                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
 151                    Feature64Bit /*, Feature64BitRegs */]>;
 152
 153
 154 //===----------------------------------------------------------------------===//
 155 // Calling Conventions
 156 //===----------------------------------------------------------------------===//
 157
 158 include "PPCCallingConv.td"
 159
 160 def PPCInstrInfo : InstrInfo {
 161   let isLittleEndianEncoding = 1;
 162 }
 163
 164 def PPCAsmWriter : AsmWriter {
 165   string AsmWriterClassName  = "InstPrinter";
 166   bit isMCAsmWriter = 1;
 167 }
 168
 169 def PPC : Target {
 170   // Information about the instructions.
 171   let InstructionSet = PPCInstrInfo;
 172
 173   let AssemblyWriters = [PPCAsmWriter];
 174 }