1 //===-- PPC32ISelSimple.cpp - A simple instruction selector PowerPC32 -----===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "isel"
12 #include "PowerPCInstrBuilder.h"
13 #include "PowerPCInstrInfo.h"
14 #include "PPC32TargetMachine.h"
15 #include "llvm/Constants.h"
16 #include "llvm/DerivedTypes.h"
17 #include "llvm/Function.h"
18 #include "llvm/Instructions.h"
19 #include "llvm/Pass.h"
20 #include "llvm/CodeGen/IntrinsicLowering.h"
21 #include "llvm/CodeGen/MachineConstantPool.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/SSARegMap.h"
25 #include "llvm/Target/MRegisterInfo.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Support/GetElementPtrTypeIterator.h"
28 #include "llvm/Support/InstVisitor.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/ADT/Statistic.h"
35 /// TypeClass - Used by the PowerPC backend to group LLVM types by their basic
36 /// PPC Representation.
39 cByte, cShort, cInt, cFP32, cFP64, cLong
43 /// getClass - Turn a primitive type into a "class" number which is based on the
44 /// size of the type, and whether or not it is floating point.
46 static inline TypeClass getClass(const Type *Ty) {
47 switch (Ty->getTypeID()) {
49 case Type::UByteTyID: return cByte; // Byte operands are class #0
51 case Type::UShortTyID: return cShort; // Short operands are class #1
54 case Type::PointerTyID: return cInt; // Ints and pointers are class #2
56 case Type::FloatTyID: return cFP32; // Single float is #3
57 case Type::DoubleTyID: return cFP64; // Double Point is #4
60 case Type::ULongTyID: return cLong; // Longs are class #5
62 assert(0 && "Invalid type to getClass!");
63 return cByte; // not reached
67 // getClassB - Just like getClass, but treat boolean values as ints.
68 static inline TypeClass getClassB(const Type *Ty) {
69 if (Ty == Type::BoolTy) return cByte;
74 struct PPC32ISel : public FunctionPass, InstVisitor<PPC32ISel> {
75 PPC32TargetMachine &TM;
76 MachineFunction *F; // The function we are compiling into
77 MachineBasicBlock *BB; // The current MBB we are compiling
78 int VarArgsFrameIndex; // FrameIndex for start of varargs area
80 /// CollapsedGepOp - This struct is for recording the intermediate results
81 /// used to calculate the base, index, and offset of a GEP instruction.
82 struct CollapsedGepOp {
83 ConstantSInt *offset; // the current offset into the struct/array
84 Value *index; // the index of the array element
85 ConstantUInt *size; // the size of each array element
86 CollapsedGepOp(ConstantSInt *o, Value *i, ConstantUInt *s) :
87 offset(o), index(i), size(s) {}
90 /// FoldedGEP - This struct is for recording the necessary information to
91 /// emit the GEP in a load or store instruction, used by emitGEPOperation.
96 FoldedGEP() : base(0), index(0), offset(0) {}
97 FoldedGEP(unsigned b, unsigned i, ConstantSInt *o) :
98 base(b), index(i), offset(o) {}
101 /// RlwimiRec - This struct is for recording the arguments to a PowerPC
102 /// rlwimi instruction to be output for a particular Instruction::Or when
103 /// we recognize the pattern for rlwimi, starting with a shift or and.
105 Value *Target, *Insert;
106 unsigned Shift, MB, ME;
107 RlwimiRec() : Target(0), Insert(0), Shift(0), MB(0), ME(0) {}
108 RlwimiRec(Value *tgt, Value *ins, unsigned s, unsigned b, unsigned e) :
109 Target(tgt), Insert(ins), Shift(s), MB(b), ME(e) {}
112 // External functions we may use in compiling the Module
113 Function *fmodfFn, *fmodFn, *__cmpdi2Fn, *__moddi3Fn, *__divdi3Fn,
114 *__umoddi3Fn, *__udivdi3Fn, *__fixsfdiFn, *__fixdfdiFn, *__fixunssfdiFn,
115 *__fixunsdfdiFn, *__floatdisfFn, *__floatdidfFn, *mallocFn, *freeFn;
117 // Mapping between Values and SSA Regs
118 std::map<Value*, unsigned> RegMap;
120 // MBBMap - Mapping between LLVM BB -> Machine BB
121 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
123 // AllocaMap - Mapping from fixed sized alloca instructions to the
124 // FrameIndex for the alloca.
125 std::map<AllocaInst*, unsigned> AllocaMap;
127 // GEPMap - Mapping between basic blocks and GEP definitions
128 std::map<GetElementPtrInst*, FoldedGEP> GEPMap;
130 // RlwimiMap - Mapping between BinaryOperand (Or) instructions and info
131 // needed to properly emit a rlwimi instruction in its place.
132 std::map<Instruction *, RlwimiRec> InsertMap;
134 // A rlwimi instruction is the combination of at least three instructions.
135 // Keep a vector of instructions to skip around so that we do not try to
136 // emit instructions that were folded into a rlwimi.
137 std::vector<Instruction *> SkipList;
139 // A Reg to hold the base address used for global loads and stores, and a
140 // flag to set whether or not we need to emit it for this function.
141 unsigned GlobalBaseReg;
142 bool GlobalBaseInitialized;
144 PPC32ISel(TargetMachine &tm):TM(reinterpret_cast<PPC32TargetMachine&>(tm)),
147 bool doInitialization(Module &M) {
148 // Add external functions that we may call
149 Type *i = Type::IntTy;
150 Type *d = Type::DoubleTy;
151 Type *f = Type::FloatTy;
152 Type *l = Type::LongTy;
153 Type *ul = Type::ULongTy;
154 Type *voidPtr = PointerType::get(Type::SByteTy);
155 // float fmodf(float, float);
156 fmodfFn = M.getOrInsertFunction("fmodf", f, f, f, 0);
157 // double fmod(double, double);
158 fmodFn = M.getOrInsertFunction("fmod", d, d, d, 0);
159 // int __cmpdi2(long, long);
160 __cmpdi2Fn = M.getOrInsertFunction("__cmpdi2", i, l, l, 0);
161 // long __moddi3(long, long);
162 __moddi3Fn = M.getOrInsertFunction("__moddi3", l, l, l, 0);
163 // long __divdi3(long, long);
164 __divdi3Fn = M.getOrInsertFunction("__divdi3", l, l, l, 0);
165 // unsigned long __umoddi3(unsigned long, unsigned long);
166 __umoddi3Fn = M.getOrInsertFunction("__umoddi3", ul, ul, ul, 0);
167 // unsigned long __udivdi3(unsigned long, unsigned long);
168 __udivdi3Fn = M.getOrInsertFunction("__udivdi3", ul, ul, ul, 0);
169 // long __fixsfdi(float)
170 __fixsfdiFn = M.getOrInsertFunction("__fixsfdi", l, f, 0);
171 // long __fixdfdi(double)
172 __fixdfdiFn = M.getOrInsertFunction("__fixdfdi", l, d, 0);
173 // unsigned long __fixunssfdi(float)
174 __fixunssfdiFn = M.getOrInsertFunction("__fixunssfdi", ul, f, 0);
175 // unsigned long __fixunsdfdi(double)
176 __fixunsdfdiFn = M.getOrInsertFunction("__fixunsdfdi", ul, d, 0);
177 // float __floatdisf(long)
178 __floatdisfFn = M.getOrInsertFunction("__floatdisf", f, l, 0);
179 // double __floatdidf(long)
180 __floatdidfFn = M.getOrInsertFunction("__floatdidf", d, l, 0);
181 // void* malloc(size_t)
182 mallocFn = M.getOrInsertFunction("malloc", voidPtr, Type::UIntTy, 0);
184 freeFn = M.getOrInsertFunction("free", Type::VoidTy, voidPtr, 0);
188 /// runOnFunction - Top level implementation of instruction selection for
189 /// the entire function.
191 bool runOnFunction(Function &Fn) {
192 // First pass over the function, lower any unknown intrinsic functions
193 // with the IntrinsicLowering class.
194 LowerUnknownIntrinsicFunctionCalls(Fn);
196 F = &MachineFunction::construct(&Fn, TM);
198 // Create all of the machine basic blocks for the function...
199 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
200 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
204 // Make sure we re-emit a set of the global base reg if necessary
205 GlobalBaseInitialized = false;
207 // Copy incoming arguments off of the stack...
208 LoadArgumentsToVirtualRegs(Fn);
210 // Instruction select everything except PHI nodes
213 // Select the PHI nodes
223 // We always build a machine code representation for the function
227 virtual const char *getPassName() const {
228 return "PowerPC Simple Instruction Selection";
231 /// visitBasicBlock - This method is called when we are visiting a new basic
232 /// block. This simply creates a new MachineBasicBlock to emit code into
233 /// and adds it to the current MachineFunction. Subsequent visit* for
234 /// instructions will be invoked for all instructions in the basic block.
236 void visitBasicBlock(BasicBlock &LLVM_BB) {
237 BB = MBBMap[&LLVM_BB];
240 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
241 /// function, lowering any calls to unknown intrinsic functions into the
242 /// equivalent LLVM code.
244 void LowerUnknownIntrinsicFunctionCalls(Function &F);
246 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function
247 /// from the stack into virtual registers.
249 void LoadArgumentsToVirtualRegs(Function &F);
251 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
252 /// because we have to generate our sources into the source basic blocks,
253 /// not the current one.
255 void SelectPHINodes();
257 // Visitation methods for various instructions. These methods simply emit
258 // fixed PowerPC code for each instruction.
260 // Control flow operators.
261 void visitReturnInst(ReturnInst &RI);
262 void visitBranchInst(BranchInst &BI);
263 void visitUnreachableInst(UnreachableInst &UI) {}
269 ValueRecord(unsigned R, const Type *T) : Val(0), Reg(R), Ty(T) {}
270 ValueRecord(Value *V) : Val(V), Reg(0), Ty(V->getType()) {}
273 void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
274 const std::vector<ValueRecord> &Args, bool isVarArg);
275 void visitCallInst(CallInst &I);
276 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &I);
278 // Arithmetic operators
279 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
280 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
281 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
282 void visitMul(BinaryOperator &B);
284 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
285 void visitRem(BinaryOperator &B) { visitDivRem(B); }
286 void visitDivRem(BinaryOperator &B);
289 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
290 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
291 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
293 // Comparison operators...
294 void visitSetCondInst(SetCondInst &I);
295 void EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
296 MachineBasicBlock *MBB,
297 MachineBasicBlock::iterator MBBI);
298 void visitSelectInst(SelectInst &SI);
301 // Memory Instructions
302 void visitLoadInst(LoadInst &I);
303 void visitStoreInst(StoreInst &I);
304 void visitGetElementPtrInst(GetElementPtrInst &I);
305 void visitAllocaInst(AllocaInst &I);
306 void visitMallocInst(MallocInst &I);
307 void visitFreeInst(FreeInst &I);
310 void visitShiftInst(ShiftInst &I);
311 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
312 void visitCastInst(CastInst &I);
313 void visitVANextInst(VANextInst &I);
314 void visitVAArgInst(VAArgInst &I);
316 void visitInstruction(Instruction &I) {
317 std::cerr << "Cannot instruction select: " << I;
321 unsigned ExtendOrClear(MachineBasicBlock *MBB,
322 MachineBasicBlock::iterator IP,
325 /// promote32 - Make a value 32-bits wide, and put it somewhere.
327 void promote32(unsigned targetReg, const ValueRecord &VR);
329 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
330 /// constant expression GEP support.
332 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
333 GetElementPtrInst *GEPI, bool foldGEP);
335 /// emitCastOperation - Common code shared between visitCastInst and
336 /// constant expression cast support.
338 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator IP,
339 Value *Src, const Type *DestTy, unsigned TargetReg);
342 /// emitBitfieldInsert - return true if we were able to fold the sequence of
343 /// instructions into a bitfield insert (rlwimi).
344 bool emitBitfieldInsert(User *OpUser, unsigned DestReg);
346 /// emitBitfieldExtract - return true if we were able to fold the sequence
347 /// of instructions into a bitfield extract (rlwinm).
348 bool emitBitfieldExtract(MachineBasicBlock *MBB,
349 MachineBasicBlock::iterator IP,
350 User *OpUser, unsigned DestReg);
352 /// emitBinaryConstOperation - Used by several functions to emit simple
353 /// arithmetic and logical operations with constants on a register rather
356 void emitBinaryConstOperation(MachineBasicBlock *MBB,
357 MachineBasicBlock::iterator IP,
358 unsigned Op0Reg, ConstantInt *Op1,
359 unsigned Opcode, unsigned DestReg);
361 /// emitSimpleBinaryOperation - Implement simple binary operators for
362 /// integral types. OperatorClass is one of: 0 for Add, 1 for Sub,
363 /// 2 for And, 3 for Or, 4 for Xor.
365 void emitSimpleBinaryOperation(MachineBasicBlock *BB,
366 MachineBasicBlock::iterator IP,
367 BinaryOperator *BO, Value *Op0, Value *Op1,
368 unsigned OperatorClass, unsigned TargetReg);
370 /// emitBinaryFPOperation - This method handles emission of floating point
371 /// Add (0), Sub (1), Mul (2), and Div (3) operations.
372 void emitBinaryFPOperation(MachineBasicBlock *BB,
373 MachineBasicBlock::iterator IP,
374 Value *Op0, Value *Op1,
375 unsigned OperatorClass, unsigned TargetReg);
377 void emitMultiply(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
378 Value *Op0, Value *Op1, unsigned TargetReg);
380 void doMultiply(MachineBasicBlock *MBB,
381 MachineBasicBlock::iterator IP,
382 unsigned DestReg, Value *Op0, Value *Op1);
384 /// doMultiplyConst - This method will multiply the value in Op0Reg by the
385 /// value of the ContantInt *CI
386 void doMultiplyConst(MachineBasicBlock *MBB,
387 MachineBasicBlock::iterator IP,
388 unsigned DestReg, Value *Op0, ConstantInt *CI);
390 void emitDivRemOperation(MachineBasicBlock *BB,
391 MachineBasicBlock::iterator IP,
392 Value *Op0, Value *Op1, bool isDiv,
395 /// emitSetCCOperation - Common code shared between visitSetCondInst and
396 /// constant expression support.
398 void emitSetCCOperation(MachineBasicBlock *BB,
399 MachineBasicBlock::iterator IP,
400 Value *Op0, Value *Op1, unsigned Opcode,
403 /// emitShiftOperation - Common code shared between visitShiftInst and
404 /// constant expression support.
406 void emitShiftOperation(MachineBasicBlock *MBB,
407 MachineBasicBlock::iterator IP,
408 Value *Op, Value *ShiftAmount, bool isLeftShift,
409 const Type *ResultTy, ShiftInst *SI,
412 /// emitSelectOperation - Common code shared between visitSelectInst and the
413 /// constant expression support.
415 void emitSelectOperation(MachineBasicBlock *MBB,
416 MachineBasicBlock::iterator IP,
417 Value *Cond, Value *TrueVal, Value *FalseVal,
420 /// getGlobalBaseReg - Output the instructions required to put the
421 /// base address to use for accessing globals into a register. Returns the
422 /// register containing the base address.
424 unsigned getGlobalBaseReg();
426 /// copyConstantToRegister - Output the instructions required to put the
427 /// specified constant into the specified register.
429 void copyConstantToRegister(MachineBasicBlock *MBB,
430 MachineBasicBlock::iterator MBBI,
431 Constant *C, unsigned Reg);
433 void emitUCOM(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
434 unsigned LHS, unsigned RHS);
436 /// makeAnotherReg - This method returns the next register number we haven't
439 /// Long values are handled somewhat specially. They are always allocated
440 /// as pairs of 32 bit integer values. The register number returned is the
441 /// high 32 bits of the long value, and the regNum+1 is the low 32 bits.
443 unsigned makeAnotherReg(const Type *Ty) {
444 assert(dynamic_cast<const PPC32RegisterInfo*>(TM.getRegisterInfo()) &&
445 "Current target doesn't have PPC reg info??");
446 const PPC32RegisterInfo *PPCRI =
447 static_cast<const PPC32RegisterInfo*>(TM.getRegisterInfo());
448 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
449 const TargetRegisterClass *RC = PPCRI->getRegClassForType(Type::IntTy);
450 // Create the upper part
451 F->getSSARegMap()->createVirtualRegister(RC);
452 // Create the lower part.
453 return F->getSSARegMap()->createVirtualRegister(RC)-1;
456 // Add the mapping of regnumber => reg class to MachineFunction
457 const TargetRegisterClass *RC = PPCRI->getRegClassForType(Ty);
458 return F->getSSARegMap()->createVirtualRegister(RC);
461 /// getReg - This method turns an LLVM value into a register number.
463 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
464 unsigned getReg(Value *V) {
465 // Just append to the end of the current bb.
466 MachineBasicBlock::iterator It = BB->end();
467 return getReg(V, BB, It);
469 unsigned getReg(Value *V, MachineBasicBlock *MBB,
470 MachineBasicBlock::iterator IPt);
472 /// canUseAsImmediateForOpcode - This method returns whether a ConstantInt
473 /// is okay to use as an immediate argument to a certain binary operation
474 bool canUseAsImmediateForOpcode(ConstantInt *CI, unsigned Opcode,
477 /// getFixedSizedAllocaFI - Return the frame index for a fixed sized alloca
478 /// that is to be statically allocated with the initial stack frame
480 unsigned getFixedSizedAllocaFI(AllocaInst *AI);
484 /// dyn_castFixedAlloca - If the specified value is a fixed size alloca
485 /// instruction in the entry block, return it. Otherwise, return a null
487 static AllocaInst *dyn_castFixedAlloca(Value *V) {
488 if (AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
489 BasicBlock *BB = AI->getParent();
490 if (isa<ConstantUInt>(AI->getArraySize()) && BB ==&BB->getParent()->front())
496 /// getReg - This method turns an LLVM value into a register number.
498 unsigned PPC32ISel::getReg(Value *V, MachineBasicBlock *MBB,
499 MachineBasicBlock::iterator IPt) {
500 if (Constant *C = dyn_cast<Constant>(V)) {
501 unsigned Reg = makeAnotherReg(V->getType());
502 copyConstantToRegister(MBB, IPt, C, Reg);
504 } else if (CastInst *CI = dyn_cast<CastInst>(V)) {
505 // Do not emit noop casts at all, unless it's a double -> float cast.
506 if (getClassB(CI->getType()) == getClassB(CI->getOperand(0)->getType()))
507 return getReg(CI->getOperand(0), MBB, IPt);
508 } else if (AllocaInst *AI = dyn_castFixedAlloca(V)) {
509 unsigned Reg = makeAnotherReg(V->getType());
510 unsigned FI = getFixedSizedAllocaFI(AI);
511 addFrameReference(BuildMI(*MBB, IPt, PPC::ADDI, 2, Reg), FI, 0, false);
515 unsigned &Reg = RegMap[V];
517 Reg = makeAnotherReg(V->getType());
524 /// canUseAsImmediateForOpcode - This method returns whether a ConstantInt
525 /// is okay to use as an immediate argument to a certain binary operator.
526 /// The shifted argument determines if the immediate is suitable to be used with
527 /// the PowerPC instructions such as addis which concatenate 16 bits of the
528 /// immediate with 16 bits of zeroes.
530 bool PPC32ISel::canUseAsImmediateForOpcode(ConstantInt *CI, unsigned Opcode,
535 // For shifted immediates, any value with the low halfword cleared may be used
537 if (((int32_t)CI->getRawValue() & 0x0000FFFF) == 0)
543 // Treat subfic like addi for the purposes of constant validation
544 if (Opcode == 5) Opcode = 0;
546 // addi, subfic, compare, and non-indexed load take SIMM
547 bool cond1 = (Opcode < 2)
548 && ((int32_t)CI->getRawValue() <= 32767)
549 && ((int32_t)CI->getRawValue() >= -32768);
551 // ANDIo, ORI, and XORI take unsigned values
552 bool cond2 = (Opcode >= 2)
553 && (Op1Cs = dyn_cast<ConstantSInt>(CI))
554 && (Op1Cs->getValue() >= 0)
555 && (Op1Cs->getValue() <= 65535);
557 // ANDIo, ORI, and XORI take UIMMs, so they can be larger
558 bool cond3 = (Opcode >= 2)
559 && (Op1Cu = dyn_cast<ConstantUInt>(CI))
560 && (Op1Cu->getValue() <= 65535);
562 if (cond1 || cond2 || cond3)
568 /// getFixedSizedAllocaFI - Return the frame index for a fixed sized alloca
569 /// that is to be statically allocated with the initial stack frame
571 unsigned PPC32ISel::getFixedSizedAllocaFI(AllocaInst *AI) {
572 // Already computed this?
573 std::map<AllocaInst*, unsigned>::iterator I = AllocaMap.lower_bound(AI);
574 if (I != AllocaMap.end() && I->first == AI) return I->second;
576 const Type *Ty = AI->getAllocatedType();
577 ConstantUInt *CUI = cast<ConstantUInt>(AI->getArraySize());
578 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
579 TySize *= CUI->getValue(); // Get total allocated size...
580 unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
582 // Create a new stack object using the frame manager...
583 int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
584 AllocaMap.insert(I, std::make_pair(AI, FrameIdx));
589 /// getGlobalBaseReg - Output the instructions required to put the
590 /// base address to use for accessing globals into a register.
592 unsigned PPC32ISel::getGlobalBaseReg() {
593 if (!GlobalBaseInitialized) {
594 // Insert the set of GlobalBaseReg into the first MBB of the function
595 MachineBasicBlock &FirstMBB = F->front();
596 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
597 GlobalBaseReg = makeAnotherReg(Type::IntTy);
598 BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
599 BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg).addReg(PPC::LR);
600 GlobalBaseInitialized = true;
602 return GlobalBaseReg;
605 /// copyConstantToRegister - Output the instructions required to put the
606 /// specified constant into the specified register.
608 void PPC32ISel::copyConstantToRegister(MachineBasicBlock *MBB,
609 MachineBasicBlock::iterator IP,
610 Constant *C, unsigned R) {
611 if (isa<UndefValue>(C)) {
612 BuildMI(*MBB, IP, PPC::IMPLICIT_DEF, 0, R);
613 if (getClassB(C->getType()) == cLong)
614 BuildMI(*MBB, IP, PPC::IMPLICIT_DEF, 0, R+1);
617 if (C->getType()->isIntegral()) {
618 unsigned Class = getClassB(C->getType());
620 if (Class == cLong) {
621 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(C)) {
622 uint64_t uval = CUI->getValue();
623 unsigned hiUVal = uval >> 32;
624 unsigned loUVal = uval;
625 ConstantUInt *CUHi = ConstantUInt::get(Type::UIntTy, hiUVal);
626 ConstantUInt *CULo = ConstantUInt::get(Type::UIntTy, loUVal);
627 copyConstantToRegister(MBB, IP, CUHi, R);
628 copyConstantToRegister(MBB, IP, CULo, R+1);
630 } else if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(C)) {
631 int64_t sval = CSI->getValue();
632 int hiSVal = sval >> 32;
634 ConstantSInt *CSHi = ConstantSInt::get(Type::IntTy, hiSVal);
635 ConstantSInt *CSLo = ConstantSInt::get(Type::IntTy, loSVal);
636 copyConstantToRegister(MBB, IP, CSHi, R);
637 copyConstantToRegister(MBB, IP, CSLo, R+1);
640 std::cerr << "Unhandled long constant type!\n";
645 assert(Class <= cInt && "Type not handled yet!");
648 if (C->getType() == Type::BoolTy) {
649 BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(C == ConstantBool::True);
654 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(C)) {
655 unsigned uval = CUI->getValue();
657 BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(uval);
659 unsigned Temp = makeAnotherReg(Type::IntTy);
660 BuildMI(*MBB, IP, PPC::LIS, 1, Temp).addSImm(uval >> 16);
661 BuildMI(*MBB, IP, PPC::ORI, 2, R).addReg(Temp).addImm(uval & 0xFFFF);
664 } else if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(C)) {
665 int sval = CSI->getValue();
666 if (sval < 32768 && sval >= -32768) {
667 BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(sval);
669 unsigned Temp = makeAnotherReg(Type::IntTy);
670 BuildMI(*MBB, IP, PPC::LIS, 1, Temp).addSImm(sval >> 16);
671 BuildMI(*MBB, IP, PPC::ORI, 2, R).addReg(Temp).addImm(sval & 0xFFFF);
675 std::cerr << "Unhandled integer constant!\n";
677 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
678 // We need to spill the constant to memory...
679 MachineConstantPool *CP = F->getConstantPool();
680 unsigned CPI = CP->getConstantPoolIndex(CFP);
681 const Type *Ty = CFP->getType();
683 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
685 // Load addr of constant to reg; constant is located at base + distance
686 unsigned Reg1 = makeAnotherReg(Type::IntTy);
687 unsigned Opcode = (Ty == Type::FloatTy) ? PPC::LFS : PPC::LFD;
688 // Move value at base + distance into return reg
689 BuildMI(*MBB, IP, PPC::LOADHiAddr, 2, Reg1)
690 .addReg(getGlobalBaseReg()).addConstantPoolIndex(CPI);
691 BuildMI(*MBB, IP, Opcode, 2, R).addConstantPoolIndex(CPI).addReg(Reg1);
692 } else if (isa<ConstantPointerNull>(C)) {
693 // Copy zero (null pointer) to the register.
694 BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(0);
695 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
696 // GV is located at base + distance
697 unsigned TmpReg = makeAnotherReg(GV->getType());
699 // Move value at base + distance into return reg
700 BuildMI(*MBB, IP, PPC::LOADHiAddr, 2, TmpReg)
701 .addReg(getGlobalBaseReg()).addGlobalAddress(GV);
703 if (GV->hasWeakLinkage() || GV->isExternal()) {
704 BuildMI(*MBB, IP, PPC::LWZ, 2, R).addGlobalAddress(GV).addReg(TmpReg);
706 BuildMI(*MBB, IP, PPC::LA, 2, R).addReg(TmpReg).addGlobalAddress(GV);
709 std::cerr << "Offending constant: " << *C << "\n";
710 assert(0 && "Type not handled yet!");
714 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function from
715 /// the stack into virtual registers.
716 void PPC32ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
717 unsigned ArgOffset = 24;
718 unsigned GPR_remaining = 8;
719 unsigned FPR_remaining = 13;
720 unsigned GPR_idx = 0, FPR_idx = 0;
721 static const unsigned GPR[] = {
722 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
723 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
725 static const unsigned FPR[] = {
726 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
727 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
730 MachineFrameInfo *MFI = F->getFrameInfo();
732 for (Function::arg_iterator I = Fn.arg_begin(), E = Fn.arg_end();
734 bool ArgLive = !I->use_empty();
735 unsigned Reg = ArgLive ? getReg(*I) : 0;
736 int FI; // Frame object index
738 switch (getClassB(I->getType())) {
741 FI = MFI->CreateFixedObject(4, ArgOffset);
742 if (GPR_remaining > 0) {
743 F->addLiveIn(GPR[GPR_idx]);
744 BuildMI(BB, PPC::OR, 2, Reg).addReg(GPR[GPR_idx])
745 .addReg(GPR[GPR_idx]);
747 addFrameReference(BuildMI(BB, PPC::LBZ, 2, Reg), FI);
753 FI = MFI->CreateFixedObject(4, ArgOffset);
754 if (GPR_remaining > 0) {
755 F->addLiveIn(GPR[GPR_idx]);
756 BuildMI(BB, PPC::OR, 2, Reg).addReg(GPR[GPR_idx])
757 .addReg(GPR[GPR_idx]);
759 addFrameReference(BuildMI(BB, PPC::LHZ, 2, Reg), FI);
765 FI = MFI->CreateFixedObject(4, ArgOffset);
766 if (GPR_remaining > 0) {
767 F->addLiveIn(GPR[GPR_idx]);
768 BuildMI(BB, PPC::OR, 2, Reg).addReg(GPR[GPR_idx])
769 .addReg(GPR[GPR_idx]);
771 addFrameReference(BuildMI(BB, PPC::LWZ, 2, Reg), FI);
777 FI = MFI->CreateFixedObject(8, ArgOffset);
778 if (GPR_remaining > 1) {
779 F->addLiveIn(GPR[GPR_idx]);
780 F->addLiveIn(GPR[GPR_idx+1]);
781 BuildMI(BB, PPC::OR, 2, Reg).addReg(GPR[GPR_idx])
782 .addReg(GPR[GPR_idx]);
783 BuildMI(BB, PPC::OR, 2, Reg+1).addReg(GPR[GPR_idx+1])
784 .addReg(GPR[GPR_idx+1]);
786 addFrameReference(BuildMI(BB, PPC::LWZ, 2, Reg), FI);
787 addFrameReference(BuildMI(BB, PPC::LWZ, 2, Reg+1), FI, 4);
790 // longs require 4 additional bytes and use 2 GPRs
792 if (GPR_remaining > 1) {
799 FI = MFI->CreateFixedObject(4, ArgOffset);
801 if (FPR_remaining > 0) {
802 F->addLiveIn(FPR[FPR_idx]);
803 BuildMI(BB, PPC::FMR, 1, Reg).addReg(FPR[FPR_idx]);
807 addFrameReference(BuildMI(BB, PPC::LFS, 2, Reg), FI);
813 FI = MFI->CreateFixedObject(8, ArgOffset);
815 if (FPR_remaining > 0) {
816 F->addLiveIn(FPR[FPR_idx]);
817 BuildMI(BB, PPC::FMR, 1, Reg).addReg(FPR[FPR_idx]);
821 addFrameReference(BuildMI(BB, PPC::LFD, 2, Reg), FI);
825 // doubles require 4 additional bytes and use 2 GPRs of param space
827 if (GPR_remaining > 0) {
833 assert(0 && "Unhandled argument type!");
835 ArgOffset += 4; // Each argument takes at least 4 bytes on the stack...
836 if (GPR_remaining > 0) {
837 GPR_remaining--; // uses up 2 GPRs
842 // If the function takes variable number of arguments, add a frame offset for
843 // the start of the first vararg value... this is used to expand
845 if (Fn.getFunctionType()->isVarArg())
846 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
848 if (Fn.getReturnType() != Type::VoidTy)
849 switch (getClassB(Fn.getReturnType())) {
853 F->addLiveOut(PPC::R3);
856 F->addLiveOut(PPC::R3);
857 F->addLiveOut(PPC::R4);
861 F->addLiveOut(PPC::F1);
867 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
868 /// because we have to generate our sources into the source basic blocks, not
871 void PPC32ISel::SelectPHINodes() {
872 const TargetInstrInfo &TII = *TM.getInstrInfo();
873 const Function &LF = *F->getFunction(); // The LLVM function...
875 MachineBasicBlock::iterator MFLRIt = F->begin()->begin();
876 if (GlobalBaseInitialized) {
877 // If we emitted a MFLR for the global base reg, get an iterator to an
878 // instruction after it.
879 while (MFLRIt->getOpcode() != PPC::MFLR)
881 ++MFLRIt; // step one MI past it.
884 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
885 const BasicBlock *BB = I;
886 MachineBasicBlock &MBB = *MBBMap[I];
888 // Loop over all of the PHI nodes in the LLVM basic block...
889 MachineBasicBlock::iterator PHIInsertPoint = MBB.begin();
890 for (BasicBlock::const_iterator I = BB->begin();
891 PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
893 // Create a new machine instr PHI node, and insert it.
894 unsigned PHIReg = getReg(*PN);
895 MachineInstr *PhiMI = BuildMI(MBB, PHIInsertPoint,
896 PPC::PHI, PN->getNumOperands(), PHIReg);
898 MachineInstr *LongPhiMI = 0;
899 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy)
900 LongPhiMI = BuildMI(MBB, PHIInsertPoint,
901 PPC::PHI, PN->getNumOperands(), PHIReg+1);
903 // PHIValues - Map of blocks to incoming virtual registers. We use this
904 // so that we only initialize one incoming value for a particular block,
905 // even if the block has multiple entries in the PHI node.
907 std::map<MachineBasicBlock*, unsigned> PHIValues;
909 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
910 MachineBasicBlock *PredMBB = 0;
911 for (MachineBasicBlock::pred_iterator PI = MBB.pred_begin (),
912 PE = MBB.pred_end (); PI != PE; ++PI)
913 if (PN->getIncomingBlock(i) == (*PI)->getBasicBlock()) {
917 assert (PredMBB && "Couldn't find incoming machine-cfg edge for phi");
920 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
921 PHIValues.lower_bound(PredMBB);
923 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
924 // We already inserted an initialization of the register for this
925 // predecessor. Recycle it.
926 ValReg = EntryIt->second;
928 // Get the incoming value into a virtual register.
930 Value *Val = PN->getIncomingValue(i);
932 // If this is a constant or GlobalValue, we may have to insert code
933 // into the basic block to compute it into a virtual register.
934 if ((isa<Constant>(Val) && !isa<ConstantExpr>(Val)) ||
935 isa<GlobalValue>(Val)) {
936 // Simple constants get emitted at the end of the basic block,
937 // before any terminator instructions. We "know" that the code to
938 // move a constant into a register will never clobber any flags.
939 ValReg = getReg(Val, PredMBB, PredMBB->getFirstTerminator());
941 // Because we don't want to clobber any values which might be in
942 // physical registers with the computation of this constant (which
943 // might be arbitrarily complex if it is a constant expression),
944 // just insert the computation at the top of the basic block.
945 MachineBasicBlock::iterator PI = PredMBB->begin();
947 // Skip over any PHI nodes though!
948 while (PI != PredMBB->end() && PI->getOpcode() == PPC::PHI)
951 // If this is the entry block, and if the entry block contains a
952 // MFLR instruction, emit this operation after it. This is needed
953 // because global addresses use it.
954 if (PredMBB == F->begin())
957 ValReg = getReg(Val, PredMBB, PI);
960 // Remember that we inserted a value for this PHI for this predecessor
961 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
964 PhiMI->addRegOperand(ValReg);
965 PhiMI->addMachineBasicBlockOperand(PredMBB);
967 LongPhiMI->addRegOperand(ValReg+1);
968 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
972 // Now that we emitted all of the incoming values for the PHI node, make
973 // sure to reposition the InsertPoint after the PHI that we just added.
974 // This is needed because we might have inserted a constant into this
975 // block, right after the PHI's which is before the old insert point!
976 PHIInsertPoint = LongPhiMI ? LongPhiMI : PhiMI;
983 // canFoldSetCCIntoBranchOrSelect - Return the setcc instruction if we can fold
984 // it into the conditional branch or select instruction which is the only user
985 // of the cc instruction. This is the case if the conditional branch is the
986 // only user of the setcc, and if the setcc is in the same basic block as the
987 // conditional branch.
989 static SetCondInst *canFoldSetCCIntoBranchOrSelect(Value *V) {
990 if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
991 if (SCI->hasOneUse()) {
992 Instruction *User = cast<Instruction>(SCI->use_back());
993 if ((isa<BranchInst>(User) ||
994 (isa<SelectInst>(User) && User->getOperand(0) == V)) &&
995 SCI->getParent() == User->getParent())
1001 // canFoldGEPIntoLoadOrStore - Return the GEP instruction if we can fold it into
1002 // the load or store instruction that is the only user of the GEP.
1004 static GetElementPtrInst *canFoldGEPIntoLoadOrStore(Value *V) {
1005 if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(V)) {
1006 bool AllUsesAreMem = true;
1007 for (Value::use_iterator I = GEPI->use_begin(), E = GEPI->use_end();
1009 Instruction *User = cast<Instruction>(*I);
1011 // If the GEP is the target of a store, but not the source, then we are ok
1013 if (isa<StoreInst>(User) &&
1014 GEPI->getParent() == User->getParent() &&
1015 User->getOperand(0) != GEPI &&
1016 User->getOperand(1) == GEPI)
1019 // If the GEP is the source of a load, then we're always ok to fold it
1020 if (isa<LoadInst>(User) &&
1021 GEPI->getParent() == User->getParent() &&
1022 User->getOperand(0) == GEPI)
1025 // if we got to this point, than the instruction was not a load or store
1026 // that we are capable of folding the GEP into.
1027 AllUsesAreMem = false;
1037 // Return a fixed numbering for setcc instructions which does not depend on the
1038 // order of the opcodes.
1040 static unsigned getSetCCNumber(unsigned Opcode) {
1042 default: assert(0 && "Unknown setcc instruction!");
1043 case Instruction::SetEQ: return 0;
1044 case Instruction::SetNE: return 1;
1045 case Instruction::SetLT: return 2;
1046 case Instruction::SetGE: return 3;
1047 case Instruction::SetGT: return 4;
1048 case Instruction::SetLE: return 5;
1052 static unsigned getPPCOpcodeForSetCCOpcode(unsigned Opcode) {
1054 default: assert(0 && "Unknown setcc instruction!");
1055 case Instruction::SetEQ: return PPC::BEQ;
1056 case Instruction::SetNE: return PPC::BNE;
1057 case Instruction::SetLT: return PPC::BLT;
1058 case Instruction::SetGE: return PPC::BGE;
1059 case Instruction::SetGT: return PPC::BGT;
1060 case Instruction::SetLE: return PPC::BLE;
1064 /// emitUCOM - emits an unordered FP compare.
1065 void PPC32ISel::emitUCOM(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
1066 unsigned LHS, unsigned RHS) {
1067 BuildMI(*MBB, IP, PPC::FCMPU, 2, PPC::CR0).addReg(LHS).addReg(RHS);
1070 unsigned PPC32ISel::ExtendOrClear(MachineBasicBlock *MBB,
1071 MachineBasicBlock::iterator IP,
1073 const Type *CompTy = Op0->getType();
1074 unsigned Reg = getReg(Op0, MBB, IP);
1075 unsigned Class = getClassB(CompTy);
1077 // Since we know that boolean values will be either zero or one, we don't
1078 // have to extend or clear them.
1079 if (CompTy == Type::BoolTy)
1082 // Before we do a comparison or SetCC, we have to make sure that we truncate
1083 // the source registers appropriately.
1084 if (Class == cByte) {
1085 unsigned TmpReg = makeAnotherReg(CompTy);
1086 if (CompTy->isSigned())
1087 BuildMI(*MBB, IP, PPC::EXTSB, 1, TmpReg).addReg(Reg);
1089 BuildMI(*MBB, IP, PPC::RLWINM, 4, TmpReg).addReg(Reg).addImm(0)
1090 .addImm(24).addImm(31);
1092 } else if (Class == cShort) {
1093 unsigned TmpReg = makeAnotherReg(CompTy);
1094 if (CompTy->isSigned())
1095 BuildMI(*MBB, IP, PPC::EXTSH, 1, TmpReg).addReg(Reg);
1097 BuildMI(*MBB, IP, PPC::RLWINM, 4, TmpReg).addReg(Reg).addImm(0)
1098 .addImm(16).addImm(31);
1104 /// EmitComparison - emits a comparison of the two operands. The result is in
1107 void PPC32ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
1108 MachineBasicBlock *MBB,
1109 MachineBasicBlock::iterator IP) {
1110 // The arguments are already supposed to be of the same type.
1111 const Type *CompTy = Op0->getType();
1112 unsigned Class = getClassB(CompTy);
1113 unsigned Op0r = ExtendOrClear(MBB, IP, Op0);
1115 // Use crand for lt, gt and crandc for le, ge
1116 unsigned CROpcode = (OpNum == 2 || OpNum == 4) ? PPC::CRAND : PPC::CRANDC;
1117 // ? cr1[lt] : cr1[gt]
1118 unsigned CR1field = (OpNum == 2 || OpNum == 3) ? 0 : 1;
1119 // ? cr0[lt] : cr0[gt]
1120 unsigned CR0field = (OpNum == 2 || OpNum == 5) ? 0 : 1;
1121 unsigned Opcode = CompTy->isSigned() ? PPC::CMPW : PPC::CMPLW;
1122 unsigned OpcodeImm = CompTy->isSigned() ? PPC::CMPWI : PPC::CMPLWI;
1124 // Special case handling of: cmp R, i
1125 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
1126 if (Class == cByte || Class == cShort || Class == cInt) {
1127 unsigned Op1v = CI->getRawValue() & 0xFFFF;
1128 unsigned OpClass = (CompTy->isSigned()) ? 0 : 2;
1130 // Treat compare like ADDI for the purposes of immediate suitability
1131 if (canUseAsImmediateForOpcode(CI, OpClass, false)) {
1132 BuildMI(*MBB, IP, OpcodeImm, 2, PPC::CR0).addReg(Op0r).addSImm(Op1v);
1134 unsigned Op1r = getReg(Op1, MBB, IP);
1135 BuildMI(*MBB, IP, Opcode, 2, PPC::CR0).addReg(Op0r).addReg(Op1r);
1139 assert(Class == cLong && "Unknown integer class!");
1140 unsigned LowCst = CI->getRawValue();
1141 unsigned HiCst = CI->getRawValue() >> 32;
1142 if (OpNum < 2) { // seteq, setne
1143 unsigned LoLow = makeAnotherReg(Type::IntTy);
1144 unsigned LoTmp = makeAnotherReg(Type::IntTy);
1145 unsigned HiLow = makeAnotherReg(Type::IntTy);
1146 unsigned HiTmp = makeAnotherReg(Type::IntTy);
1147 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
1149 BuildMI(*MBB, IP, PPC::XORI, 2, LoLow).addReg(Op0r+1)
1150 .addImm(LowCst & 0xFFFF);
1151 BuildMI(*MBB, IP, PPC::XORIS, 2, LoTmp).addReg(LoLow)
1152 .addImm(LowCst >> 16);
1153 BuildMI(*MBB, IP, PPC::XORI, 2, HiLow).addReg(Op0r)
1154 .addImm(HiCst & 0xFFFF);
1155 BuildMI(*MBB, IP, PPC::XORIS, 2, HiTmp).addReg(HiLow)
1156 .addImm(HiCst >> 16);
1157 BuildMI(*MBB, IP, PPC::ORo, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
1160 unsigned ConstReg = makeAnotherReg(CompTy);
1161 copyConstantToRegister(MBB, IP, CI, ConstReg);
1163 // cr0 = r3 ccOpcode r5 or (r3 == r5 AND r4 ccOpcode r6)
1164 BuildMI(*MBB, IP, Opcode, 2, PPC::CR0).addReg(Op0r)
1166 BuildMI(*MBB, IP, Opcode, 2, PPC::CR1).addReg(Op0r+1)
1167 .addReg(ConstReg+1);
1168 BuildMI(*MBB, IP, PPC::CRAND, 5, PPC::CR0).addImm(2)
1169 .addReg(PPC::CR0).addImm(2).addReg(PPC::CR1).addImm(CR1field);
1170 BuildMI(*MBB, IP, PPC::CROR, 5, PPC::CR0).addImm(CR0field)
1171 .addReg(PPC::CR0).addImm(CR0field).addReg(PPC::CR0).addImm(2);
1177 unsigned Op1r = getReg(Op1, MBB, IP);
1180 default: assert(0 && "Unknown type class!");
1184 BuildMI(*MBB, IP, Opcode, 2, PPC::CR0).addReg(Op0r).addReg(Op1r);
1189 emitUCOM(MBB, IP, Op0r, Op1r);
1193 if (OpNum < 2) { // seteq, setne
1194 unsigned LoTmp = makeAnotherReg(Type::IntTy);
1195 unsigned HiTmp = makeAnotherReg(Type::IntTy);
1196 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
1197 BuildMI(*MBB, IP, PPC::XOR, 2, HiTmp).addReg(Op0r).addReg(Op1r);
1198 BuildMI(*MBB, IP, PPC::XOR, 2, LoTmp).addReg(Op0r+1).addReg(Op1r+1);
1199 BuildMI(*MBB, IP, PPC::ORo, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
1200 break; // Allow the sete or setne to be generated from flags set by OR
1202 unsigned TmpReg1 = makeAnotherReg(Type::IntTy);
1203 unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
1205 // cr0 = r3 ccOpcode r5 or (r3 == r5 AND r4 ccOpcode r6)
1206 BuildMI(*MBB, IP, Opcode, 2, PPC::CR0).addReg(Op0r).addReg(Op1r);
1207 BuildMI(*MBB, IP, Opcode, 2, PPC::CR1).addReg(Op0r+1).addReg(Op1r+1);
1208 BuildMI(*MBB, IP, PPC::CRAND, 5, PPC::CR0).addImm(2)
1209 .addReg(PPC::CR0).addImm(2).addReg(PPC::CR1).addImm(CR1field);
1210 BuildMI(*MBB, IP, PPC::CROR, 5, PPC::CR0).addImm(CR0field)
1211 .addReg(PPC::CR0).addImm(CR0field).addReg(PPC::CR0).addImm(2);
1218 /// visitSetCondInst - emit code to calculate the condition via
1219 /// EmitComparison(), and possibly store a 0 or 1 to a register as a result
1221 void PPC32ISel::visitSetCondInst(SetCondInst &I) {
1222 if (canFoldSetCCIntoBranchOrSelect(&I))
1225 MachineBasicBlock::iterator MI = BB->end();
1226 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
1227 const Type *Ty = Op0->getType();
1228 unsigned Class = getClassB(Ty);
1229 unsigned Opcode = I.getOpcode();
1230 unsigned OpNum = getSetCCNumber(Opcode);
1231 unsigned DestReg = getReg(I);
1233 // If the comparison type is byte, short, or int, then we can emit a
1234 // branchless version of the SetCC that puts 0 (false) or 1 (true) in the
1235 // destination register.
1236 if (Class <= cInt) {
1237 ConstantInt *CI = dyn_cast<ConstantInt>(Op1);
1239 if (CI && CI->getRawValue() == 0) {
1240 unsigned Op0Reg = ExtendOrClear(BB, MI, Op0);
1242 // comparisons against constant zero and negative one often have shorter
1243 // and/or faster sequences than the set-and-branch general case, handled
1247 unsigned TempReg = makeAnotherReg(Type::IntTy);
1248 BuildMI(*BB, MI, PPC::CNTLZW, 1, TempReg).addReg(Op0Reg);
1249 BuildMI(*BB, MI, PPC::RLWINM, 4, DestReg).addReg(TempReg).addImm(27)
1250 .addImm(5).addImm(31);
1254 unsigned TempReg = makeAnotherReg(Type::IntTy);
1255 BuildMI(*BB, MI, PPC::ADDIC, 2, TempReg).addReg(Op0Reg).addSImm(-1);
1256 BuildMI(*BB, MI, PPC::SUBFE, 2, DestReg).addReg(TempReg).addReg(Op0Reg);
1259 case 2: { // lt0, always false if unsigned
1261 BuildMI(*BB, MI, PPC::RLWINM, 4, DestReg).addReg(Op0Reg).addImm(1)
1262 .addImm(31).addImm(31);
1264 BuildMI(*BB, MI, PPC::LI, 1, DestReg).addSImm(0);
1267 case 3: { // ge0, always true if unsigned
1268 if (Ty->isSigned()) {
1269 unsigned TempReg = makeAnotherReg(Type::IntTy);
1270 BuildMI(*BB, MI, PPC::RLWINM, 4, TempReg).addReg(Op0Reg).addImm(1)
1271 .addImm(31).addImm(31);
1272 BuildMI(*BB, MI, PPC::XORI, 2, DestReg).addReg(TempReg).addImm(1);
1274 BuildMI(*BB, MI, PPC::LI, 1, DestReg).addSImm(1);
1278 case 4: { // gt0, equivalent to ne0 if unsigned
1279 unsigned Temp1 = makeAnotherReg(Type::IntTy);
1280 unsigned Temp2 = makeAnotherReg(Type::IntTy);
1281 if (Ty->isSigned()) {
1282 BuildMI(*BB, MI, PPC::NEG, 2, Temp1).addReg(Op0Reg);
1283 BuildMI(*BB, MI, PPC::ANDC, 2, Temp2).addReg(Temp1).addReg(Op0Reg);
1284 BuildMI(*BB, MI, PPC::RLWINM, 4, DestReg).addReg(Temp2).addImm(1)
1285 .addImm(31).addImm(31);
1287 BuildMI(*BB, MI, PPC::ADDIC, 2, Temp1).addReg(Op0Reg).addSImm(-1);
1288 BuildMI(*BB, MI, PPC::SUBFE, 2, DestReg).addReg(Temp1).addReg(Op0Reg);
1292 case 5: { // le0, equivalent to eq0 if unsigned
1293 unsigned Temp1 = makeAnotherReg(Type::IntTy);
1294 unsigned Temp2 = makeAnotherReg(Type::IntTy);
1295 if (Ty->isSigned()) {
1296 BuildMI(*BB, MI, PPC::NEG, 2, Temp1).addReg(Op0Reg);
1297 BuildMI(*BB, MI, PPC::ORC, 2, Temp2).addReg(Op0Reg).addReg(Temp1);
1298 BuildMI(*BB, MI, PPC::RLWINM, 4, DestReg).addReg(Temp2).addImm(1)
1299 .addImm(31).addImm(31);
1301 BuildMI(*BB, MI, PPC::CNTLZW, 1, Temp1).addReg(Op0Reg);
1302 BuildMI(*BB, MI, PPC::RLWINM, 4, DestReg).addReg(Temp1).addImm(27)
1303 .addImm(5).addImm(31);
1311 unsigned PPCOpcode = getPPCOpcodeForSetCCOpcode(Opcode);
1313 // Create an iterator with which to insert the MBB for copying the false value
1314 // and the MBB to hold the PHI instruction for this SetCC.
1315 MachineBasicBlock *thisMBB = BB;
1316 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1317 ilist<MachineBasicBlock>::iterator It = BB;
1322 // cmpTY cr0, r1, r2
1323 // %TrueValue = li 1
1325 EmitComparison(OpNum, Op0, Op1, BB, BB->end());
1326 unsigned TrueValue = makeAnotherReg(I.getType());
1327 BuildMI(BB, PPC::LI, 1, TrueValue).addSImm(1);
1328 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
1329 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
1330 BuildMI(BB, PPCOpcode, 2).addReg(PPC::CR0).addMBB(sinkMBB);
1331 F->getBasicBlockList().insert(It, copy0MBB);
1332 F->getBasicBlockList().insert(It, sinkMBB);
1333 // Update machine-CFG edges
1334 BB->addSuccessor(copy0MBB);
1335 BB->addSuccessor(sinkMBB);
1338 // %FalseValue = li 0
1341 unsigned FalseValue = makeAnotherReg(I.getType());
1342 BuildMI(BB, PPC::LI, 1, FalseValue).addSImm(0);
1343 // Update machine-CFG edges
1344 BB->addSuccessor(sinkMBB);
1347 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1350 BuildMI(BB, PPC::PHI, 4, DestReg).addReg(FalseValue)
1351 .addMBB(copy0MBB).addReg(TrueValue).addMBB(thisMBB);
1354 void PPC32ISel::visitSelectInst(SelectInst &SI) {
1355 unsigned DestReg = getReg(SI);
1356 MachineBasicBlock::iterator MII = BB->end();
1357 emitSelectOperation(BB, MII, SI.getCondition(), SI.getTrueValue(),
1358 SI.getFalseValue(), DestReg);
1361 /// emitSelect - Common code shared between visitSelectInst and the constant
1362 /// expression support.
1363 void PPC32ISel::emitSelectOperation(MachineBasicBlock *MBB,
1364 MachineBasicBlock::iterator IP,
1365 Value *Cond, Value *TrueVal,
1366 Value *FalseVal, unsigned DestReg) {
1367 unsigned SelectClass = getClassB(TrueVal->getType());
1370 // See if we can fold the setcc into the select instruction, or if we have
1371 // to get the register of the Cond value
1372 if (SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(Cond)) {
1373 // We successfully folded the setcc into the select instruction.
1374 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
1375 if (OpNum >= 2 && OpNum <= 5) {
1376 unsigned SetCondClass = getClassB(SCI->getOperand(0)->getType());
1377 if ((SetCondClass == cFP32 || SetCondClass == cFP64) &&
1378 (SelectClass == cFP32 || SelectClass == cFP64)) {
1379 unsigned CondReg = getReg(SCI->getOperand(0), MBB, IP);
1380 unsigned TrueReg = getReg(TrueVal, MBB, IP);
1381 unsigned FalseReg = getReg(FalseVal, MBB, IP);
1382 // if the comparison of the floating point value used to for the select
1383 // is against 0, then we can emit an fsel without subtraction.
1384 ConstantFP *Op1C = dyn_cast<ConstantFP>(SCI->getOperand(1));
1385 if (Op1C && (Op1C->isExactlyValue(-0.0) || Op1C->isExactlyValue(0.0))) {
1388 BuildMI(*MBB, IP, PPC::FSEL, 3, DestReg).addReg(CondReg)
1389 .addReg(FalseReg).addReg(TrueReg);
1391 case 3: // GE == !LT
1392 BuildMI(*MBB, IP, PPC::FSEL, 3, DestReg).addReg(CondReg)
1393 .addReg(TrueReg).addReg(FalseReg);
1396 unsigned NegatedReg = makeAnotherReg(SCI->getOperand(0)->getType());
1397 BuildMI(*MBB, IP, PPC::FNEG, 1, NegatedReg).addReg(CondReg);
1398 BuildMI(*MBB, IP, PPC::FSEL, 3, DestReg).addReg(NegatedReg)
1399 .addReg(FalseReg).addReg(TrueReg);
1402 case 5: { // LE == !GT
1403 unsigned NegatedReg = makeAnotherReg(SCI->getOperand(0)->getType());
1404 BuildMI(*MBB, IP, PPC::FNEG, 1, NegatedReg).addReg(CondReg);
1405 BuildMI(*MBB, IP, PPC::FSEL, 3, DestReg).addReg(NegatedReg)
1406 .addReg(TrueReg).addReg(FalseReg);
1410 assert(0 && "Invalid SetCC opcode to fsel");
1415 unsigned OtherCondReg = getReg(SCI->getOperand(1), MBB, IP);
1416 unsigned SelectReg = makeAnotherReg(SCI->getOperand(0)->getType());
1419 BuildMI(*MBB, IP, PPC::FSUB, 2, SelectReg).addReg(CondReg)
1420 .addReg(OtherCondReg);
1421 BuildMI(*MBB, IP, PPC::FSEL, 3, DestReg).addReg(SelectReg)
1422 .addReg(FalseReg).addReg(TrueReg);
1424 case 3: // GE == !LT
1425 BuildMI(*MBB, IP, PPC::FSUB, 2, SelectReg).addReg(CondReg)
1426 .addReg(OtherCondReg);
1427 BuildMI(*MBB, IP, PPC::FSEL, 3, DestReg).addReg(SelectReg)
1428 .addReg(TrueReg).addReg(FalseReg);
1431 BuildMI(*MBB, IP, PPC::FSUB, 2, SelectReg).addReg(OtherCondReg)
1433 BuildMI(*MBB, IP, PPC::FSEL, 3, DestReg).addReg(SelectReg)
1434 .addReg(FalseReg).addReg(TrueReg);
1436 case 5: // LE == !GT
1437 BuildMI(*MBB, IP, PPC::FSUB, 2, SelectReg).addReg(OtherCondReg)
1439 BuildMI(*MBB, IP, PPC::FSEL, 3, DestReg).addReg(SelectReg)
1440 .addReg(TrueReg).addReg(FalseReg);
1443 assert(0 && "Invalid SetCC opcode to fsel");
1451 EmitComparison(OpNum, SCI->getOperand(0),SCI->getOperand(1),MBB,IP);
1452 Opcode = getPPCOpcodeForSetCCOpcode(SCI->getOpcode());
1454 unsigned CondReg = getReg(Cond, MBB, IP);
1455 BuildMI(*MBB, IP, PPC::CMPWI, 2, PPC::CR0).addReg(CondReg).addSImm(0);
1456 Opcode = getPPCOpcodeForSetCCOpcode(Instruction::SetNE);
1459 MachineBasicBlock *thisMBB = BB;
1460 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1461 ilist<MachineBasicBlock>::iterator It = BB;
1467 // cmpTY cr0, r1, r2
1469 // fallthrough --> copy0MBB
1470 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
1471 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
1472 unsigned TrueValue = getReg(TrueVal);
1473 BuildMI(BB, Opcode, 2).addReg(PPC::CR0).addMBB(sinkMBB);
1474 F->getBasicBlockList().insert(It, copy0MBB);
1475 F->getBasicBlockList().insert(It, sinkMBB);
1476 // Update machine-CFG edges
1477 BB->addSuccessor(copy0MBB);
1478 BB->addSuccessor(sinkMBB);
1481 // %FalseValue = ...
1482 // # fallthrough to sinkMBB
1484 unsigned FalseValue = getReg(FalseVal);
1485 // Update machine-CFG edges
1486 BB->addSuccessor(sinkMBB);
1489 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1492 BuildMI(BB, PPC::PHI, 4, DestReg).addReg(FalseValue)
1493 .addMBB(copy0MBB).addReg(TrueValue).addMBB(thisMBB);
1495 // For a register pair representing a long value, define the top part.
1496 if (getClassB(TrueVal->getType()) == cLong)
1497 BuildMI(BB, PPC::PHI, 4, DestReg+1).addReg(FalseValue+1)
1498 .addMBB(copy0MBB).addReg(TrueValue+1).addMBB(thisMBB);
1503 /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
1504 /// operand, in the specified target register.
1506 void PPC32ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
1507 bool isUnsigned = VR.Ty->isUnsigned() || VR.Ty == Type::BoolTy;
1509 Value *Val = VR.Val;
1510 const Type *Ty = VR.Ty;
1512 if (Constant *C = dyn_cast<Constant>(Val)) {
1513 Val = ConstantExpr::getCast(C, Type::IntTy);
1514 if (isa<ConstantExpr>(Val)) // Could not fold
1517 Ty = Type::IntTy; // Folded!
1520 // If this is a simple constant, just emit a load directly to avoid the copy
1521 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
1522 copyConstantToRegister(BB, BB->end(), CI, targetReg);
1527 // Make sure we have the register number for this value...
1528 unsigned Reg = Val ? getReg(Val) : VR.Reg;
1529 switch (getClassB(Ty)) {
1531 // Extend value into target register (8->32)
1532 if (Ty == Type::BoolTy)
1533 BuildMI(BB, PPC::OR, 2, targetReg).addReg(Reg).addReg(Reg);
1534 else if (isUnsigned)
1535 BuildMI(BB, PPC::RLWINM, 4, targetReg).addReg(Reg).addZImm(0)
1536 .addZImm(24).addZImm(31);
1538 BuildMI(BB, PPC::EXTSB, 1, targetReg).addReg(Reg);
1541 // Extend value into target register (16->32)
1543 BuildMI(BB, PPC::RLWINM, 4, targetReg).addReg(Reg).addZImm(0)
1544 .addZImm(16).addZImm(31);
1546 BuildMI(BB, PPC::EXTSH, 1, targetReg).addReg(Reg);
1549 // Move value into target register (32->32)
1550 BuildMI(BB, PPC::OR, 2, targetReg).addReg(Reg).addReg(Reg);
1553 assert(0 && "Unpromotable operand class in promote32");
1557 /// visitReturnInst - implemented with BLR
1559 void PPC32ISel::visitReturnInst(ReturnInst &I) {
1560 // Only do the processing if this is a non-void return
1561 if (I.getNumOperands() > 0) {
1562 Value *RetVal = I.getOperand(0);
1563 switch (getClassB(RetVal->getType())) {
1564 case cByte: // integral return values: extend or move into r3 and return
1567 promote32(PPC::R3, ValueRecord(RetVal));
1570 case cFP64: { // Floats & Doubles: Return in f1
1571 unsigned RetReg = getReg(RetVal);
1572 BuildMI(BB, PPC::FMR, 1, PPC::F1).addReg(RetReg);
1576 unsigned RetReg = getReg(RetVal);
1577 BuildMI(BB, PPC::OR, 2, PPC::R3).addReg(RetReg).addReg(RetReg);
1578 BuildMI(BB, PPC::OR, 2, PPC::R4).addReg(RetReg+1).addReg(RetReg+1);
1582 visitInstruction(I);
1585 BuildMI(BB, PPC::BLR, 1).addImm(0);
1588 // getBlockAfter - Return the basic block which occurs lexically after the
1590 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
1591 Function::iterator I = BB; ++I; // Get iterator to next block
1592 return I != BB->getParent()->end() ? &*I : 0;
1595 /// visitBranchInst - Handle conditional and unconditional branches here. Note
1596 /// that since code layout is frozen at this point, that if we are trying to
1597 /// jump to a block that is the immediate successor of the current block, we can
1598 /// just make a fall-through (but we don't currently).
1600 void PPC32ISel::visitBranchInst(BranchInst &BI) {
1601 // Update machine-CFG edges
1602 BB->addSuccessor(MBBMap[BI.getSuccessor(0)]);
1603 if (BI.isConditional())
1604 BB->addSuccessor(MBBMap[BI.getSuccessor(1)]);
1606 BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
1608 if (!BI.isConditional()) { // Unconditional branch?
1609 if (BI.getSuccessor(0) != NextBB)
1610 BuildMI(BB, PPC::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
1614 // See if we can fold the setcc into the branch itself...
1615 SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(BI.getCondition());
1617 // Nope, cannot fold setcc into this branch. Emit a branch on a condition
1618 // computed some other way...
1619 unsigned condReg = getReg(BI.getCondition());
1620 BuildMI(BB, PPC::CMPLI, 3, PPC::CR0).addImm(0).addReg(condReg)
1622 if (BI.getSuccessor(1) == NextBB) {
1623 if (BI.getSuccessor(0) != NextBB)
1624 BuildMI(BB, PPC::COND_BRANCH, 4).addReg(PPC::CR0).addImm(PPC::BNE)
1625 .addMBB(MBBMap[BI.getSuccessor(0)])
1626 .addMBB(MBBMap[BI.getSuccessor(1)]);
1628 BuildMI(BB, PPC::COND_BRANCH, 4).addReg(PPC::CR0).addImm(PPC::BEQ)
1629 .addMBB(MBBMap[BI.getSuccessor(1)])
1630 .addMBB(MBBMap[BI.getSuccessor(0)]);
1631 if (BI.getSuccessor(0) != NextBB)
1632 BuildMI(BB, PPC::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
1637 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
1638 unsigned Opcode = getPPCOpcodeForSetCCOpcode(SCI->getOpcode());
1639 MachineBasicBlock::iterator MII = BB->end();
1640 EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
1642 if (BI.getSuccessor(0) != NextBB) {
1643 BuildMI(BB, PPC::COND_BRANCH, 4).addReg(PPC::CR0).addImm(Opcode)
1644 .addMBB(MBBMap[BI.getSuccessor(0)])
1645 .addMBB(MBBMap[BI.getSuccessor(1)]);
1646 if (BI.getSuccessor(1) != NextBB)
1647 BuildMI(BB, PPC::B, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
1649 // Change to the inverse condition...
1650 if (BI.getSuccessor(1) != NextBB) {
1651 Opcode = PPC32InstrInfo::invertPPCBranchOpcode(Opcode);
1652 BuildMI(BB, PPC::COND_BRANCH, 4).addReg(PPC::CR0).addImm(Opcode)
1653 .addMBB(MBBMap[BI.getSuccessor(1)])
1654 .addMBB(MBBMap[BI.getSuccessor(0)]);
1659 /// doCall - This emits an abstract call instruction, setting up the arguments
1660 /// and the return value as appropriate. For the actual function call itself,
1661 /// it inserts the specified CallMI instruction into the stream.
1663 /// FIXME: See Documentation at the following URL for "correct" behavior
1664 /// <http://developer.apple.com/documentation/DeveloperTools/Conceptual/MachORuntime/PowerPCConventions/chapter_3_section_5.html>
1665 void PPC32ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
1666 const std::vector<ValueRecord> &Args, bool isVarArg) {
1667 // Count how many bytes are to be pushed on the stack, including the linkage
1668 // area, and parameter passing area.
1669 unsigned NumBytes = 24;
1670 unsigned ArgOffset = 24;
1672 if (!Args.empty()) {
1673 for (unsigned i = 0, e = Args.size(); i != e; ++i)
1674 switch (getClassB(Args[i].Ty)) {
1675 case cByte: case cShort: case cInt:
1676 NumBytes += 4; break;
1678 NumBytes += 8; break;
1680 NumBytes += 4; break;
1682 NumBytes += 8; break;
1684 default: assert(0 && "Unknown class!");
1687 // Just to be safe, we'll always reserve the full 24 bytes of linkage area
1688 // plus 32 bytes of argument space in case any called code gets funky on us.
1689 if (NumBytes < 56) NumBytes = 56;
1691 // Adjust the stack pointer for the new arguments...
1692 // These operations are automatically eliminated by the prolog/epilog pass
1693 BuildMI(BB, PPC::ADJCALLSTACKDOWN, 1).addImm(NumBytes);
1695 // Arguments go on the stack in reverse order, as specified by the ABI.
1696 // Offset to the paramater area on the stack is 24.
1697 int GPR_remaining = 8, FPR_remaining = 13;
1698 unsigned GPR_idx = 0, FPR_idx = 0;
1699 static const unsigned GPR[] = {
1700 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1701 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1703 static const unsigned FPR[] = {
1704 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6,
1705 PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12,
1709 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
1711 switch (getClassB(Args[i].Ty)) {
1714 // Promote arg to 32 bits wide into a temporary register...
1715 ArgReg = makeAnotherReg(Type::UIntTy);
1716 promote32(ArgReg, Args[i]);
1719 if (GPR_remaining > 0) {
1720 BuildMI(BB, PPC::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
1722 CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
1724 if (GPR_remaining <= 0 || isVarArg) {
1725 BuildMI(BB, PPC::STW, 3).addReg(ArgReg).addSImm(ArgOffset)
1730 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1733 if (GPR_remaining > 0) {
1734 BuildMI(BB, PPC::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
1736 CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
1738 if (GPR_remaining <= 0 || isVarArg) {
1739 BuildMI(BB, PPC::STW, 3).addReg(ArgReg).addSImm(ArgOffset)
1744 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1746 // Reg or stack? Note that PPC calling conventions state that long args
1747 // are passed rN = hi, rN+1 = lo, opposite of LLVM.
1748 if (GPR_remaining > 1) {
1749 BuildMI(BB, PPC::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
1751 BuildMI(BB, PPC::OR, 2, GPR[GPR_idx+1]).addReg(ArgReg+1)
1753 CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
1754 CallMI->addRegOperand(GPR[GPR_idx+1], MachineOperand::Use);
1756 if (GPR_remaining <= 1 || isVarArg) {
1757 BuildMI(BB, PPC::STW, 3).addReg(ArgReg).addSImm(ArgOffset)
1759 BuildMI(BB, PPC::STW, 3).addReg(ArgReg+1).addSImm(ArgOffset+4)
1763 ArgOffset += 4; // 8 byte entry, not 4.
1764 GPR_remaining -= 1; // uses up 2 GPRs
1768 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1770 if (FPR_remaining > 0) {
1771 BuildMI(BB, PPC::FMR, 1, FPR[FPR_idx]).addReg(ArgReg);
1772 CallMI->addRegOperand(FPR[FPR_idx], MachineOperand::Use);
1776 // If this is a vararg function, and there are GPRs left, also
1777 // pass the float in an int. Otherwise, put it on the stack.
1779 BuildMI(BB, PPC::STFS, 3).addReg(ArgReg).addSImm(ArgOffset)
1781 if (GPR_remaining > 0) {
1782 BuildMI(BB, PPC::LWZ, 2, GPR[GPR_idx])
1783 .addSImm(ArgOffset).addReg(PPC::R1);
1784 CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
1788 BuildMI(BB, PPC::STFS, 3).addReg(ArgReg).addSImm(ArgOffset)
1793 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1795 if (FPR_remaining > 0) {
1796 BuildMI(BB, PPC::FMR, 1, FPR[FPR_idx]).addReg(ArgReg);
1797 CallMI->addRegOperand(FPR[FPR_idx], MachineOperand::Use);
1800 // For vararg functions, must pass doubles via int regs as well
1802 BuildMI(BB, PPC::STFD, 3).addReg(ArgReg).addSImm(ArgOffset)
1805 // Doubles can be split across reg + stack for varargs
1806 if (GPR_remaining > 0) {
1807 BuildMI(BB, PPC::LWZ, 2, GPR[GPR_idx]).addSImm(ArgOffset)
1809 CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
1811 if (GPR_remaining > 1) {
1812 BuildMI(BB, PPC::LWZ, 2, GPR[GPR_idx+1])
1813 .addSImm(ArgOffset+4).addReg(PPC::R1);
1814 CallMI->addRegOperand(GPR[GPR_idx+1], MachineOperand::Use);
1818 BuildMI(BB, PPC::STFD, 3).addReg(ArgReg).addSImm(ArgOffset)
1821 // Doubles use 8 bytes, and 2 GPRs worth of param space
1827 default: assert(0 && "Unknown class!");
1834 BuildMI(BB, PPC::ADJCALLSTACKDOWN, 1).addImm(NumBytes);
1837 BuildMI(BB, PPC::IMPLICIT_DEF, 0, PPC::LR);
1838 BB->push_back(CallMI);
1840 // These functions are automatically eliminated by the prolog/epilog pass
1841 BuildMI(BB, PPC::ADJCALLSTACKUP, 1).addImm(NumBytes);
1843 // If there is a return value, scavenge the result from the location the call
1846 if (Ret.Ty != Type::VoidTy) {
1847 unsigned DestClass = getClassB(Ret.Ty);
1848 switch (DestClass) {
1852 // Integral results are in r3
1853 BuildMI(BB, PPC::OR, 2, Ret.Reg).addReg(PPC::R3).addReg(PPC::R3);
1855 case cFP32: // Floating-point return values live in f1
1857 BuildMI(BB, PPC::FMR, 1, Ret.Reg).addReg(PPC::F1);
1859 case cLong: // Long values are in r3:r4
1860 BuildMI(BB, PPC::OR, 2, Ret.Reg).addReg(PPC::R3).addReg(PPC::R3);
1861 BuildMI(BB, PPC::OR, 2, Ret.Reg+1).addReg(PPC::R4).addReg(PPC::R4);
1863 default: assert(0 && "Unknown class!");
1869 /// visitCallInst - Push args on stack and do a procedure call instruction.
1870 void PPC32ISel::visitCallInst(CallInst &CI) {
1871 MachineInstr *TheCall;
1872 Function *F = CI.getCalledFunction();
1874 // Is it an intrinsic function call?
1875 if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
1876 visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here
1879 // Emit a CALL instruction with PC-relative displacement.
1880 TheCall = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(F, true);
1881 } else { // Emit an indirect call through the CTR
1882 unsigned Reg = getReg(CI.getCalledValue());
1883 BuildMI(BB, PPC::OR, 2, PPC::R12).addReg(Reg).addReg(Reg);
1884 BuildMI(BB, PPC::MTCTR, 1).addReg(PPC::R12);
1885 TheCall = BuildMI(PPC::CALLindirect, 3).addZImm(20).addZImm(0)
1889 std::vector<ValueRecord> Args;
1890 for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i)
1891 Args.push_back(ValueRecord(CI.getOperand(i)));
1893 unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
1894 bool isVarArg = F ? F->getFunctionType()->isVarArg() : true;
1895 doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args, isVarArg);
1899 /// dyncastIsNan - Return the operand of an isnan operation if this is an isnan.
1901 static Value *dyncastIsNan(Value *V) {
1902 if (CallInst *CI = dyn_cast<CallInst>(V))
1903 if (Function *F = CI->getCalledFunction())
1904 if (F->getIntrinsicID() == Intrinsic::isunordered)
1905 return CI->getOperand(1);
1909 /// isOnlyUsedByUnorderedComparisons - Return true if this value is only used by
1910 /// or's whos operands are all calls to the isnan predicate.
1911 static bool isOnlyUsedByUnorderedComparisons(Value *V) {
1912 assert(dyncastIsNan(V) && "The value isn't an isnan call!");
1914 // Check all uses, which will be or's of isnans if this predicate is true.
1915 for (Value::use_iterator UI = V->use_begin(), E = V->use_end(); UI != E;++UI){
1916 Instruction *I = cast<Instruction>(*UI);
1917 if (I->getOpcode() != Instruction::Or) return false;
1918 if (I->getOperand(0) != V && !dyncastIsNan(I->getOperand(0))) return false;
1919 if (I->getOperand(1) != V && !dyncastIsNan(I->getOperand(1))) return false;
1925 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
1926 /// function, lowering any calls to unknown intrinsic functions into the
1927 /// equivalent LLVM code.
1929 void PPC32ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
1930 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
1931 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
1932 if (CallInst *CI = dyn_cast<CallInst>(I++))
1933 if (Function *F = CI->getCalledFunction())
1934 switch (F->getIntrinsicID()) {
1935 case Intrinsic::not_intrinsic:
1936 case Intrinsic::vastart:
1937 case Intrinsic::vacopy:
1938 case Intrinsic::vaend:
1939 case Intrinsic::returnaddress:
1940 case Intrinsic::frameaddress:
1941 // FIXME: should lower these ourselves
1942 // case Intrinsic::isunordered:
1943 // case Intrinsic::memcpy: -> doCall(). system memcpy almost
1944 // guaranteed to be faster than anything we generate ourselves
1945 // We directly implement these intrinsics
1947 case Intrinsic::readio: {
1948 // On PPC, memory operations are in-order. Lower this intrinsic
1949 // into a volatile load.
1950 LoadInst * LI = new LoadInst(CI->getOperand(1), "", true, CI);
1951 CI->replaceAllUsesWith(LI);
1952 BB->getInstList().erase(CI);
1955 case Intrinsic::writeio: {
1956 // On PPC, memory operations are in-order. Lower this intrinsic
1957 // into a volatile store.
1958 StoreInst *SI = new StoreInst(CI->getOperand(1),
1959 CI->getOperand(2), true, CI);
1960 CI->replaceAllUsesWith(SI);
1961 BB->getInstList().erase(CI);
1965 // All other intrinsic calls we must lower.
1966 BasicBlock::iterator me(CI);
1967 bool atBegin(BB->begin() == me);
1970 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
1971 // Move iterator to instruction after call
1972 I = atBegin ? BB->begin() : ++me;
1977 void PPC32ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
1978 unsigned TmpReg1, TmpReg2, TmpReg3;
1980 case Intrinsic::vastart:
1981 // Get the address of the first vararg value...
1982 TmpReg1 = getReg(CI);
1983 addFrameReference(BuildMI(BB, PPC::ADDI, 2, TmpReg1), VarArgsFrameIndex,
1987 case Intrinsic::vacopy:
1988 TmpReg1 = getReg(CI);
1989 TmpReg2 = getReg(CI.getOperand(1));
1990 BuildMI(BB, PPC::OR, 2, TmpReg1).addReg(TmpReg2).addReg(TmpReg2);
1992 case Intrinsic::vaend: return;
1994 case Intrinsic::returnaddress:
1995 TmpReg1 = getReg(CI);
1996 if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
1997 MachineFrameInfo *MFI = F->getFrameInfo();
1998 unsigned NumBytes = MFI->getStackSize();
2000 BuildMI(BB, PPC::LWZ, 2, TmpReg1).addSImm(NumBytes+8)
2003 // Values other than zero are not implemented yet.
2004 BuildMI(BB, PPC::LI, 1, TmpReg1).addSImm(0);
2008 case Intrinsic::frameaddress:
2009 TmpReg1 = getReg(CI);
2010 if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
2011 BuildMI(BB, PPC::OR, 2, TmpReg1).addReg(PPC::R1).addReg(PPC::R1);
2013 // Values other than zero are not implemented yet.
2014 BuildMI(BB, PPC::LI, 1, TmpReg1).addSImm(0);
2019 // This may be useful for supporting isunordered
2020 case Intrinsic::isnan:
2021 // If this is only used by 'isunordered' style comparisons, don't emit it.
2022 if (isOnlyUsedByUnorderedComparisons(&CI)) return;
2023 TmpReg1 = getReg(CI.getOperand(1));
2024 emitUCOM(BB, BB->end(), TmpReg1, TmpReg1);
2025 TmpReg2 = makeAnotherReg(Type::IntTy);
2026 BuildMI(BB, PPC::MFCR, TmpReg2);
2027 TmpReg3 = getReg(CI);
2028 BuildMI(BB, PPC::RLWINM, 4, TmpReg3).addReg(TmpReg2).addImm(4).addImm(31).addImm(31);
2032 default: assert(0 && "Error: unknown intrinsics should have been lowered!");
2036 /// visitSimpleBinary - Implement simple binary operators for integral types...
2037 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for
2040 void PPC32ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
2041 if (std::find(SkipList.begin(), SkipList.end(), &B) != SkipList.end())
2044 unsigned DestReg = getReg(B);
2045 MachineBasicBlock::iterator MI = BB->end();
2046 RlwimiRec RR = InsertMap[&B];
2047 if (RR.Target != 0) {
2048 unsigned TargetReg = getReg(RR.Target, BB, MI);
2049 unsigned InsertReg = getReg(RR.Insert, BB, MI);
2050 BuildMI(*BB, MI, PPC::RLWIMI, 5, DestReg).addReg(TargetReg)
2051 .addReg(InsertReg).addImm(RR.Shift).addImm(RR.MB).addImm(RR.ME);
2055 unsigned Class = getClassB(B.getType());
2056 Value *Op0 = B.getOperand(0), *Op1 = B.getOperand(1);
2057 emitSimpleBinaryOperation(BB, MI, &B, Op0, Op1, OperatorClass, DestReg);
2060 /// emitBinaryFPOperation - This method handles emission of floating point
2061 /// Add (0), Sub (1), Mul (2), and Div (3) operations.
2062 void PPC32ISel::emitBinaryFPOperation(MachineBasicBlock *BB,
2063 MachineBasicBlock::iterator IP,
2064 Value *Op0, Value *Op1,
2065 unsigned OperatorClass, unsigned DestReg){
2067 static const unsigned OpcodeTab[][4] = {
2068 { PPC::FADDS, PPC::FSUBS, PPC::FMULS, PPC::FDIVS }, // Float
2069 { PPC::FADD, PPC::FSUB, PPC::FMUL, PPC::FDIV }, // Double
2072 // Special case: R1 = op <const fp>, R2
2073 if (ConstantFP *Op0C = dyn_cast<ConstantFP>(Op0))
2074 if (Op0C->isExactlyValue(-0.0) && OperatorClass == 1) {
2076 unsigned op1Reg = getReg(Op1, BB, IP);
2077 BuildMI(*BB, IP, PPC::FNEG, 1, DestReg).addReg(op1Reg);
2081 unsigned Opcode = OpcodeTab[Op0->getType() == Type::DoubleTy][OperatorClass];
2082 unsigned Op0r = getReg(Op0, BB, IP);
2083 unsigned Op1r = getReg(Op1, BB, IP);
2084 BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
2087 // ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
2088 // returns zero when the input is not exactly a power of two.
2089 static unsigned ExactLog2(unsigned Val) {
2090 if (Val == 0 || (Val & (Val-1))) return 0;
2099 // isRunOfOnes - returns true if Val consists of one contiguous run of 1's with
2100 // any number of 0's on either side. the 1's are allowed to wrap from LSB to
2101 // MSB. so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is
2102 // not, since all 1's are not contiguous.
2103 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
2108 // look for first set bit
2110 for (; i < 32; i++) {
2111 if ((Val & (1 << (31 - i))) != 0) {
2118 // look for last set bit
2119 for (; i < 32; i++) {
2120 if ((Val & (1 << (31 - i))) == 0)
2125 // look for next set bit
2126 for (; i < 32; i++) {
2127 if ((Val & (1 << (31 - i))) != 0)
2131 // if we exhausted all the bits, we found a match at this point for 0*1*0*
2135 // since we just encountered more 1's, if it doesn't wrap around to the
2136 // most significant bit of the word, then we did not find a match to 1*0*1* so
2141 // look for last set bit
2142 for (MB = i; i < 32; i++) {
2143 if ((Val & (1 << (31 - i))) == 0)
2147 // if we exhausted all the bits, then we found a match for 1*0*1*, otherwise,
2148 // the value is not a run of ones.
2154 /// isInsertAndHalf - Helper function for emitBitfieldInsert. Returns true if
2155 /// OpUser has one use, is used by an or instruction, and is itself an and whose
2156 /// second operand is a constant int. Optionally, set OrI to the Or instruction
2157 /// that is the sole user of OpUser, and Op1User to the other operand of the Or
2159 static bool isInsertAndHalf(User *OpUser, Instruction **Op1User,
2160 Instruction **OrI, unsigned &Mask) {
2161 // If this instruction doesn't have one use, then return false.
2162 if (!OpUser->hasOneUse())
2166 if (BinaryOperator *BO = dyn_cast<BinaryOperator>(OpUser))
2167 if (BO->getOpcode() == Instruction::And) {
2168 Value *AndUse = *(OpUser->use_begin());
2169 if (BinaryOperator *Or = dyn_cast<BinaryOperator>(AndUse)) {
2170 if (Or->getOpcode() == Instruction::Or) {
2171 if (ConstantInt *CI = dyn_cast<ConstantInt>(OpUser->getOperand(1))) {
2174 if (Or->getOperand(0) == OpUser)
2175 *Op1User = dyn_cast<Instruction>(Or->getOperand(1));
2177 *Op1User = dyn_cast<Instruction>(Or->getOperand(0));
2179 Mask &= CI->getRawValue();
2188 /// isInsertShiftHalf - Helper function for emitBitfieldInsert. Returns true if
2189 /// OpUser has one use, is used by an or instruction, and is itself a shift
2190 /// instruction that is either used directly by the or instruction, or is used
2191 /// by an and instruction whose second operand is a constant int, and which is
2192 /// used by the or instruction.
2193 static bool isInsertShiftHalf(User *OpUser, Instruction **Op1User,
2194 Instruction **OrI, Instruction **OptAndI,
2195 unsigned &Shift, unsigned &Mask) {
2196 // If this instruction doesn't have one use, then return false.
2197 if (!OpUser->hasOneUse())
2201 if (ShiftInst *SI = dyn_cast<ShiftInst>(OpUser)) {
2202 if (ConstantInt *CI = dyn_cast<ConstantInt>(SI->getOperand(1))) {
2203 Shift = CI->getRawValue();
2204 if (SI->getOpcode() == Instruction::Shl)
2206 else if (!SI->getOperand(0)->getType()->isSigned()) {
2211 // Now check to see if the shift instruction is used by an or.
2212 Value *ShiftUse = *(OpUser->use_begin());
2213 Value *OptAndICopy = 0;
2214 if (BinaryOperator *BO = dyn_cast<BinaryOperator>(ShiftUse)) {
2215 if (BO->getOpcode() == Instruction::And && BO->hasOneUse()) {
2216 if (ConstantInt *ACI = dyn_cast<ConstantInt>(BO->getOperand(1))) {
2217 if (OptAndI) *OptAndI = BO;
2219 Mask &= ACI->getRawValue();
2220 BO = dyn_cast<BinaryOperator>(*(BO->use_begin()));
2223 if (BO && BO->getOpcode() == Instruction::Or) {
2226 if (BO->getOperand(0) == OpUser || BO->getOperand(0) == OptAndICopy)
2227 *Op1User = dyn_cast<Instruction>(BO->getOperand(1));
2229 *Op1User = dyn_cast<Instruction>(BO->getOperand(0));
2239 /// emitBitfieldInsert - turn a shift used only by an and with immediate into
2240 /// the rotate left word immediate then mask insert (rlwimi) instruction.
2241 /// Patterns matched:
2242 /// 1. or shl, and 5. or (shl-and), and 9. or and, and
2243 /// 2. or and, shl 6. or and, (shl-and)
2244 /// 3. or shr, and 7. or (shr-and), and
2245 /// 4. or and, shr 8. or and, (shr-and)
2246 bool PPC32ISel::emitBitfieldInsert(User *OpUser, unsigned DestReg) {
2247 // Instructions to skip if we match any of the patterns
2248 Instruction *Op0User, *Op1User = 0, *OptAndI = 0, *OrI = 0;
2249 unsigned TgtMask, InsMask, Amount = 0;
2250 bool matched = false;
2252 // We require OpUser to be an instruction to continue
2253 Op0User = dyn_cast<Instruction>(OpUser);
2257 // Look for cases 2, 4, 6, 8, and 9
2258 if (isInsertAndHalf(Op0User, &Op1User, &OrI, TgtMask))
2260 if (isInsertAndHalf(Op1User, 0, 0, InsMask))
2262 else if (isInsertShiftHalf(Op1User, 0, 0, &OptAndI, Amount, InsMask))
2265 // Look for cases 1, 3, 5, and 7. Force the shift argument to be the one
2266 // inserted into the target, since rlwimi can only rotate the value inserted,
2267 // not the value being inserted into.
2268 if (matched == false)
2269 if (isInsertShiftHalf(Op0User, &Op1User, &OrI, &OptAndI, Amount, InsMask))
2270 if (Op1User && isInsertAndHalf(Op1User, 0, 0, TgtMask)) {
2271 std::swap(Op0User, Op1User);
2275 // We didn't succeed in matching one of the patterns, so return false
2276 if (matched == false)
2279 // If the masks xor to -1, and the insert mask is a run of ones, then we have
2280 // succeeded in matching one of the cases for generating rlwimi. Update the
2281 // skip lists and users of the Instruction::Or.
2283 if (((TgtMask ^ InsMask) == 0xFFFFFFFF) && isRunOfOnes(InsMask, MB, ME)) {
2284 SkipList.push_back(Op0User);
2285 SkipList.push_back(Op1User);
2286 SkipList.push_back(OptAndI);
2287 InsertMap[OrI] = RlwimiRec(Op0User->getOperand(0), Op1User->getOperand(0),
2294 /// emitBitfieldExtract - turn a shift used only by an and with immediate into the
2295 /// rotate left word immediate then and with mask (rlwinm) instruction.
2296 bool PPC32ISel::emitBitfieldExtract(MachineBasicBlock *MBB,
2297 MachineBasicBlock::iterator IP,
2298 User *OpUser, unsigned DestReg) {
2301 // Instructions to skip if we match any of the patterns
2302 Instruction *Op0User, *Op1User = 0;
2303 unsigned ShiftMask, AndMask, Amount = 0;
2304 bool matched = false;
2306 // We require OpUser to be an instruction to continue
2307 Op0User = dyn_cast<Instruction>(OpUser);
2311 if (isExtractShiftHalf)
2312 if (isExtractAndHalf)
2315 if (matched == false && isExtractAndHalf)
2316 if (isExtractShiftHalf)
2319 if (matched == false)
2322 if (isRunOfOnes(Imm, MB, ME)) {
2323 unsigned SrcReg = getReg(Op, MBB, IP);
2324 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg).addImm(Rotate)
2325 .addImm(MB).addImm(ME);
2326 Op1User->replaceAllUsesWith(Op0User);
2327 SkipList.push_back(BO);
2333 /// emitBinaryConstOperation - Implement simple binary operators for integral
2334 /// types with a constant operand. Opcode is one of: 0 for Add, 1 for Sub,
2335 /// 2 for And, 3 for Or, 4 for Xor, and 5 for Subtract-From.
2337 void PPC32ISel::emitBinaryConstOperation(MachineBasicBlock *MBB,
2338 MachineBasicBlock::iterator IP,
2339 unsigned Op0Reg, ConstantInt *Op1,
2340 unsigned Opcode, unsigned DestReg) {
2341 static const unsigned OpTab[] = {
2342 PPC::ADD, PPC::SUB, PPC::AND, PPC::OR, PPC::XOR, PPC::SUBF
2344 static const unsigned ImmOpTab[2][6] = {
2345 { PPC::ADDI, PPC::ADDI, PPC::ANDIo, PPC::ORI, PPC::XORI, PPC::SUBFIC },
2346 { PPC::ADDIS, PPC::ADDIS, PPC::ANDISo, PPC::ORIS, PPC::XORIS, PPC::SUBFIC }
2349 // Handle subtract now by inverting the constant value: X-4 == X+(-4)
2351 Op1 = cast<ConstantInt>(ConstantExpr::getNeg(Op1));
2355 // xor X, -1 -> not X
2356 if (Opcode == 4 && Op1->isAllOnesValue()) {
2357 BuildMI(*MBB, IP, PPC::NOR, 2, DestReg).addReg(Op0Reg).addReg(Op0Reg);
2361 if (Opcode == 2 && !Op1->isNullValue()) {
2362 unsigned MB, ME, mask = Op1->getRawValue();
2363 if (isRunOfOnes(mask, MB, ME)) {
2364 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(Op0Reg).addImm(0)
2365 .addImm(MB).addImm(ME);
2370 // PowerPC 16 bit signed immediates are sign extended before use by the
2371 // instruction. Therefore, we can only split up an add of a reg with a 32 bit
2372 // immediate into addis and addi if the sign bit of the low 16 bits is cleared
2373 // so that for register A, const imm X, we don't end up with
2374 // A + XXXX0000 + FFFFXXXX.
2375 bool WontSignExtend = (0 == (Op1->getRawValue() & 0x8000));
2377 // For Add, Sub, and SubF the instruction takes a signed immediate. For And,
2378 // Or, and Xor, the instruction takes an unsigned immediate. There is no
2379 // shifted immediate form of SubF so disallow its opcode for those constants.
2380 if (canUseAsImmediateForOpcode(Op1, Opcode, false)) {
2381 if (Opcode < 2 || Opcode == 5)
2382 BuildMI(*MBB, IP, ImmOpTab[0][Opcode], 2, DestReg).addReg(Op0Reg)
2383 .addSImm(Op1->getRawValue());
2385 BuildMI(*MBB, IP, ImmOpTab[0][Opcode], 2, DestReg).addReg(Op0Reg)
2386 .addZImm(Op1->getRawValue());
2387 } else if (canUseAsImmediateForOpcode(Op1, Opcode, true) && (Opcode < 5)) {
2389 BuildMI(*MBB, IP, ImmOpTab[1][Opcode], 2, DestReg).addReg(Op0Reg)
2390 .addSImm(Op1->getRawValue() >> 16);
2392 BuildMI(*MBB, IP, ImmOpTab[1][Opcode], 2, DestReg).addReg(Op0Reg)
2393 .addZImm(Op1->getRawValue() >> 16);
2394 } else if ((Opcode < 2 && WontSignExtend) || Opcode == 3 || Opcode == 4) {
2395 unsigned TmpReg = makeAnotherReg(Op1->getType());
2397 BuildMI(*MBB, IP, ImmOpTab[1][Opcode], 2, TmpReg).addReg(Op0Reg)
2398 .addSImm(Op1->getRawValue() >> 16);
2399 BuildMI(*MBB, IP, ImmOpTab[0][Opcode], 2, DestReg).addReg(TmpReg)
2400 .addSImm(Op1->getRawValue());
2402 BuildMI(*MBB, IP, ImmOpTab[1][Opcode], 2, TmpReg).addReg(Op0Reg)
2403 .addZImm(Op1->getRawValue() >> 16);
2404 BuildMI(*MBB, IP, ImmOpTab[0][Opcode], 2, DestReg).addReg(TmpReg)
2405 .addZImm(Op1->getRawValue());
2408 unsigned Op1Reg = getReg(Op1, MBB, IP);
2409 BuildMI(*MBB, IP, OpTab[Opcode], 2, DestReg).addReg(Op0Reg).addReg(Op1Reg);
2413 /// emitSimpleBinaryOperation - Implement simple binary operators for integral
2414 /// types... OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for
2417 void PPC32ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
2418 MachineBasicBlock::iterator IP,
2420 Value *Op0, Value *Op1,
2421 unsigned OperatorClass,
2423 // Arithmetic and Bitwise operators
2424 static const unsigned OpcodeTab[] = {
2425 PPC::ADD, PPC::SUBF, PPC::AND, PPC::OR, PPC::XOR
2427 static const unsigned LongOpTab[2][5] = {
2428 { PPC::ADDC, PPC::SUBFC, PPC::AND, PPC::OR, PPC::XOR },
2429 { PPC::ADDE, PPC::SUBFE, PPC::AND, PPC::OR, PPC::XOR }
2432 unsigned Class = getClassB(Op0->getType());
2434 if (Class == cFP32 || Class == cFP64) {
2435 assert(OperatorClass < 2 && "No logical ops for FP!");
2436 emitBinaryFPOperation(MBB, IP, Op0, Op1, OperatorClass, DestReg);
2440 if (Op0->getType() == Type::BoolTy) {
2441 if (OperatorClass == 3)
2442 // If this is an or of two isnan's, emit an FP comparison directly instead
2443 // of or'ing two isnan's together.
2444 if (Value *LHS = dyncastIsNan(Op0))
2445 if (Value *RHS = dyncastIsNan(Op1)) {
2446 unsigned Op0Reg = getReg(RHS, MBB, IP), Op1Reg = getReg(LHS, MBB, IP);
2447 unsigned TmpReg = makeAnotherReg(Type::IntTy);
2448 emitUCOM(MBB, IP, Op0Reg, Op1Reg);
2449 BuildMI(*MBB, IP, PPC::MFCR, TmpReg);
2450 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(TmpReg).addImm(4)
2451 .addImm(31).addImm(31);
2456 // Special case: op <const int>, Reg
2457 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op0))
2458 if (Class != cLong) {
2459 unsigned Opcode = (OperatorClass == 1) ? 5 : OperatorClass;
2460 unsigned Op1r = getReg(Op1, MBB, IP);
2461 emitBinaryConstOperation(MBB, IP, Op1r, CI, Opcode, DestReg);
2464 // Special case: op Reg, <const int>
2465 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1))
2466 if (Class != cLong) {
2467 if (emitBitfieldInsert(BO, DestReg))
2470 unsigned Op0r = getReg(Op0, MBB, IP);
2471 emitBinaryConstOperation(MBB, IP, Op0r, CI, OperatorClass, DestReg);
2475 // We couldn't generate an immediate variant of the op, load both halves into
2476 // registers and emit the appropriate opcode.
2477 unsigned Op0r = getReg(Op0, MBB, IP);
2478 unsigned Op1r = getReg(Op1, MBB, IP);
2480 // Subtracts have their operands swapped
2481 if (OperatorClass == 1) {
2482 if (Class != cLong) {
2483 BuildMI(*MBB, IP, PPC::SUBF, 2, DestReg).addReg(Op1r).addReg(Op0r);
2485 BuildMI(*MBB, IP, PPC::SUBFC, 2, DestReg+1).addReg(Op1r+1).addReg(Op0r+1);
2486 BuildMI(*MBB, IP, PPC::SUBFE, 2, DestReg).addReg(Op1r).addReg(Op0r);
2491 if (Class != cLong) {
2492 unsigned Opcode = OpcodeTab[OperatorClass];
2493 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
2495 BuildMI(*MBB, IP, LongOpTab[0][OperatorClass], 2, DestReg+1).addReg(Op0r+1)
2497 BuildMI(*MBB, IP, LongOpTab[1][OperatorClass], 2, DestReg).addReg(Op0r)
2503 /// doMultiply - Emit appropriate instructions to multiply together the
2504 /// Values Op0 and Op1, and put the result in DestReg.
2506 void PPC32ISel::doMultiply(MachineBasicBlock *MBB,
2507 MachineBasicBlock::iterator IP,
2508 unsigned DestReg, Value *Op0, Value *Op1) {
2509 unsigned Class0 = getClass(Op0->getType());
2510 unsigned Class1 = getClass(Op1->getType());
2512 unsigned Op0r = getReg(Op0, MBB, IP);
2513 unsigned Op1r = getReg(Op1, MBB, IP);
2516 if (Class0 == cLong && Class1 == cLong) {
2517 unsigned Tmp1 = makeAnotherReg(Type::IntTy);
2518 unsigned Tmp2 = makeAnotherReg(Type::IntTy);
2519 unsigned Tmp3 = makeAnotherReg(Type::IntTy);
2520 unsigned Tmp4 = makeAnotherReg(Type::IntTy);
2521 BuildMI(*MBB, IP, PPC::MULHWU, 2, Tmp1).addReg(Op0r+1).addReg(Op1r+1);
2522 BuildMI(*MBB, IP, PPC::MULLW, 2, DestReg+1).addReg(Op0r+1).addReg(Op1r+1);
2523 BuildMI(*MBB, IP, PPC::MULLW, 2, Tmp2).addReg(Op0r+1).addReg(Op1r);
2524 BuildMI(*MBB, IP, PPC::ADD, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
2525 BuildMI(*MBB, IP, PPC::MULLW, 2, Tmp4).addReg(Op0r).addReg(Op1r+1);
2526 BuildMI(*MBB, IP, PPC::ADD, 2, DestReg).addReg(Tmp3).addReg(Tmp4);
2530 // 64 x 32 or less, promote 32 to 64 and do a 64 x 64
2531 if (Class0 == cLong && Class1 <= cInt) {
2532 unsigned Tmp0 = makeAnotherReg(Type::IntTy);
2533 unsigned Tmp1 = makeAnotherReg(Type::IntTy);
2534 unsigned Tmp2 = makeAnotherReg(Type::IntTy);
2535 unsigned Tmp3 = makeAnotherReg(Type::IntTy);
2536 unsigned Tmp4 = makeAnotherReg(Type::IntTy);
2537 if (Op1->getType()->isSigned())
2538 BuildMI(*MBB, IP, PPC::SRAWI, 2, Tmp0).addReg(Op1r).addImm(31);
2540 BuildMI(*MBB, IP, PPC::LI, 2, Tmp0).addSImm(0);
2541 BuildMI(*MBB, IP, PPC::MULHWU, 2, Tmp1).addReg(Op0r+1).addReg(Op1r);
2542 BuildMI(*MBB, IP, PPC::MULLW, 2, DestReg+1).addReg(Op0r+1).addReg(Op1r);
2543 BuildMI(*MBB, IP, PPC::MULLW, 2, Tmp2).addReg(Op0r+1).addReg(Tmp0);
2544 BuildMI(*MBB, IP, PPC::ADD, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
2545 BuildMI(*MBB, IP, PPC::MULLW, 2, Tmp4).addReg(Op0r).addReg(Op1r);
2546 BuildMI(*MBB, IP, PPC::ADD, 2, DestReg).addReg(Tmp3).addReg(Tmp4);
2551 if (Class0 <= cInt && Class1 <= cInt) {
2552 BuildMI(*MBB, IP, PPC::MULLW, 2, DestReg).addReg(Op0r).addReg(Op1r);
2556 assert(0 && "doMultiply cannot operate on unknown type!");
2559 /// doMultiplyConst - This method will multiply the value in Op0 by the
2560 /// value of the ContantInt *CI
2561 void PPC32ISel::doMultiplyConst(MachineBasicBlock *MBB,
2562 MachineBasicBlock::iterator IP,
2563 unsigned DestReg, Value *Op0, ConstantInt *CI) {
2564 unsigned Class = getClass(Op0->getType());
2567 if (CI->isNullValue()) {
2568 BuildMI(*MBB, IP, PPC::LI, 1, DestReg).addSImm(0);
2570 BuildMI(*MBB, IP, PPC::LI, 1, DestReg+1).addSImm(0);
2574 // Mul op0, 1 ==> op0
2575 if (CI->equalsInt(1)) {
2576 unsigned Op0r = getReg(Op0, MBB, IP);
2577 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(Op0r).addReg(Op0r);
2579 BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(Op0r+1).addReg(Op0r+1);
2583 // If the element size is exactly a power of 2, use a shift to get it.
2584 if (unsigned Shift = ExactLog2(CI->getRawValue())) {
2585 ConstantUInt *ShiftCI = ConstantUInt::get(Type::UByteTy, Shift);
2586 emitShiftOperation(MBB, IP, Op0, ShiftCI, true, Op0->getType(), 0, DestReg);
2590 // If 32 bits or less and immediate is in right range, emit mul by immediate
2591 if (Class == cByte || Class == cShort || Class == cInt) {
2592 if (canUseAsImmediateForOpcode(CI, 0, false)) {
2593 unsigned Op0r = getReg(Op0, MBB, IP);
2594 unsigned imm = CI->getRawValue() & 0xFFFF;
2595 BuildMI(*MBB, IP, PPC::MULLI, 2, DestReg).addReg(Op0r).addSImm(imm);
2600 doMultiply(MBB, IP, DestReg, Op0, CI);
2603 void PPC32ISel::visitMul(BinaryOperator &I) {
2604 unsigned ResultReg = getReg(I);
2606 Value *Op0 = I.getOperand(0);
2607 Value *Op1 = I.getOperand(1);
2609 MachineBasicBlock::iterator IP = BB->end();
2610 emitMultiply(BB, IP, Op0, Op1, ResultReg);
2613 void PPC32ISel::emitMultiply(MachineBasicBlock *MBB,
2614 MachineBasicBlock::iterator IP,
2615 Value *Op0, Value *Op1, unsigned DestReg) {
2616 TypeClass Class = getClass(Op0->getType());
2623 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
2624 doMultiplyConst(MBB, IP, DestReg, Op0, CI);
2626 doMultiply(MBB, IP, DestReg, Op0, Op1);
2631 emitBinaryFPOperation(MBB, IP, Op0, Op1, 2, DestReg);
2638 /// visitDivRem - Handle division and remainder instructions... these
2639 /// instruction both require the same instructions to be generated, they just
2640 /// select the result from a different register. Note that both of these
2641 /// instructions work differently for signed and unsigned operands.
2643 void PPC32ISel::visitDivRem(BinaryOperator &I) {
2644 unsigned ResultReg = getReg(I);
2645 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
2647 MachineBasicBlock::iterator IP = BB->end();
2648 emitDivRemOperation(BB, IP, Op0, Op1, I.getOpcode() == Instruction::Div,
2652 void PPC32ISel::emitDivRemOperation(MachineBasicBlock *MBB,
2653 MachineBasicBlock::iterator IP,
2654 Value *Op0, Value *Op1, bool isDiv,
2655 unsigned ResultReg) {
2656 const Type *Ty = Op0->getType();
2657 unsigned Class = getClass(Ty);
2661 // Floating point divide...
2662 emitBinaryFPOperation(MBB, IP, Op0, Op1, 3, ResultReg);
2665 // Floating point remainder via fmodf(float x, float y);
2666 unsigned Op0Reg = getReg(Op0, MBB, IP);
2667 unsigned Op1Reg = getReg(Op1, MBB, IP);
2668 MachineInstr *TheCall =
2669 BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(fmodfFn, true);
2670 std::vector<ValueRecord> Args;
2671 Args.push_back(ValueRecord(Op0Reg, Type::FloatTy));
2672 Args.push_back(ValueRecord(Op1Reg, Type::FloatTy));
2673 doCall(ValueRecord(ResultReg, Type::FloatTy), TheCall, Args, false);
2678 // Floating point divide...
2679 emitBinaryFPOperation(MBB, IP, Op0, Op1, 3, ResultReg);
2682 // Floating point remainder via fmod(double x, double y);
2683 unsigned Op0Reg = getReg(Op0, MBB, IP);
2684 unsigned Op1Reg = getReg(Op1, MBB, IP);
2685 MachineInstr *TheCall =
2686 BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(fmodFn, true);
2687 std::vector<ValueRecord> Args;
2688 Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy));
2689 Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy));
2690 doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args, false);
2694 static Function* const Funcs[] =
2695 { __moddi3Fn, __divdi3Fn, __umoddi3Fn, __udivdi3Fn };
2696 unsigned Op0Reg = getReg(Op0, MBB, IP);
2697 unsigned Op1Reg = getReg(Op1, MBB, IP);
2698 unsigned NameIdx = Ty->isUnsigned()*2 + isDiv;
2699 MachineInstr *TheCall =
2700 BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(Funcs[NameIdx], true);
2702 std::vector<ValueRecord> Args;
2703 Args.push_back(ValueRecord(Op0Reg, Type::LongTy));
2704 Args.push_back(ValueRecord(Op1Reg, Type::LongTy));
2705 doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args, false);
2708 case cByte: case cShort: case cInt:
2709 break; // Small integrals, handled below...
2710 default: assert(0 && "Unknown class!");
2713 // Special case signed division by power of 2.
2715 if (ConstantSInt *CI = dyn_cast<ConstantSInt>(Op1)) {
2716 assert(Class != cLong && "This doesn't handle 64-bit divides!");
2717 int V = CI->getValue();
2719 if (V == 1) { // X /s 1 => X
2720 unsigned Op0Reg = getReg(Op0, MBB, IP);
2721 BuildMI(*MBB, IP, PPC::OR, 2, ResultReg).addReg(Op0Reg).addReg(Op0Reg);
2725 if (V == -1) { // X /s -1 => -X
2726 unsigned Op0Reg = getReg(Op0, MBB, IP);
2727 BuildMI(*MBB, IP, PPC::NEG, 1, ResultReg).addReg(Op0Reg);
2731 unsigned log2V = ExactLog2(V);
2732 if (log2V != 0 && Ty->isSigned()) {
2733 unsigned Op0Reg = getReg(Op0, MBB, IP);
2734 unsigned TmpReg = makeAnotherReg(Op0->getType());
2736 BuildMI(*MBB, IP, PPC::SRAWI, 2, TmpReg).addReg(Op0Reg).addImm(log2V);
2737 BuildMI(*MBB, IP, PPC::ADDZE, 1, ResultReg).addReg(TmpReg);
2742 unsigned Op0Reg = getReg(Op0, MBB, IP);
2745 unsigned Op1Reg = getReg(Op1, MBB, IP);
2746 unsigned Opcode = Ty->isSigned() ? PPC::DIVW : PPC::DIVWU;
2747 BuildMI(*MBB, IP, Opcode, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
2748 } else { // Remainder
2749 // FIXME: don't load the CI part of a CI divide twice
2750 ConstantInt *CI = dyn_cast<ConstantInt>(Op1);
2751 unsigned TmpReg1 = makeAnotherReg(Op0->getType());
2752 unsigned TmpReg2 = makeAnotherReg(Op0->getType());
2753 emitDivRemOperation(MBB, IP, Op0, Op1, true, TmpReg1);
2754 if (CI && canUseAsImmediateForOpcode(CI, 0, false)) {
2755 BuildMI(*MBB, IP, PPC::MULLI, 2, TmpReg2).addReg(TmpReg1)
2756 .addSImm(CI->getRawValue());
2758 unsigned Op1Reg = getReg(Op1, MBB, IP);
2759 BuildMI(*MBB, IP, PPC::MULLW, 2, TmpReg2).addReg(TmpReg1).addReg(Op1Reg);
2761 BuildMI(*MBB, IP, PPC::SUBF, 2, ResultReg).addReg(TmpReg2).addReg(Op0Reg);
2766 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
2767 /// for constant immediate shift values, and for constant immediate
2768 /// shift values equal to 1. Even the general case is sort of special,
2769 /// because the shift amount has to be in CL, not just any old register.
2771 void PPC32ISel::visitShiftInst(ShiftInst &I) {
2772 if (std::find(SkipList.begin(), SkipList.end(), &I) != SkipList.end())
2775 MachineBasicBlock::iterator IP = BB->end();
2776 emitShiftOperation(BB, IP, I.getOperand(0), I.getOperand(1),
2777 I.getOpcode() == Instruction::Shl, I.getType(),
2781 /// emitShiftOperation - Common code shared between visitShiftInst and
2782 /// constant expression support.
2784 void PPC32ISel::emitShiftOperation(MachineBasicBlock *MBB,
2785 MachineBasicBlock::iterator IP,
2786 Value *Op, Value *ShiftAmount,
2787 bool isLeftShift, const Type *ResultTy,
2788 ShiftInst *SI, unsigned DestReg) {
2789 bool isSigned = ResultTy->isSigned ();
2790 unsigned Class = getClass (ResultTy);
2792 // Longs, as usual, are handled specially...
2793 if (Class == cLong) {
2794 unsigned SrcReg = getReg (Op, MBB, IP);
2795 // If we have a constant shift, we can generate much more efficient code
2796 // than for a variable shift by using the rlwimi instruction.
2797 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
2798 unsigned Amount = CUI->getValue();
2800 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2801 BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1)
2802 .addReg(SrcReg+1).addReg(SrcReg+1);
2804 } else if (Amount < 32) {
2805 unsigned TempReg = makeAnotherReg(ResultTy);
2807 BuildMI(*MBB, IP, PPC::RLWINM, 4, TempReg).addReg(SrcReg)
2808 .addImm(Amount).addImm(0).addImm(31-Amount);
2809 BuildMI(*MBB, IP, PPC::RLWIMI, 5, DestReg).addReg(TempReg)
2810 .addReg(SrcReg+1).addImm(Amount).addImm(32-Amount).addImm(31);
2811 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg+1).addReg(SrcReg+1)
2812 .addImm(Amount).addImm(0).addImm(31-Amount);
2814 BuildMI(*MBB, IP, PPC::RLWINM, 4, TempReg).addReg(SrcReg+1)
2815 .addImm(32-Amount).addImm(Amount).addImm(31);
2816 BuildMI(*MBB, IP, PPC::RLWIMI, 5, DestReg+1).addReg(TempReg)
2817 .addReg(SrcReg).addImm(32-Amount).addImm(0).addImm(Amount-1);
2819 BuildMI(*MBB, IP, PPC::SRAWI, 2, DestReg).addReg(SrcReg)
2822 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
2823 .addImm(32-Amount).addImm(Amount).addImm(31);
2826 } else { // Shifting more than 32 bits
2830 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg+1)
2831 .addImm(Amount).addImm(0).addImm(31-Amount);
2833 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg+1)
2836 BuildMI(*MBB, IP, PPC::LI, 1, DestReg+1).addSImm(0);
2840 BuildMI(*MBB, IP, PPC::SRAWI, 2, DestReg+1).addReg(SrcReg)
2843 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg+1).addReg(SrcReg)
2844 .addImm(32-Amount).addImm(Amount).addImm(31);
2846 BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg)
2850 BuildMI(*MBB, IP, PPC::SRAWI, 2, DestReg).addReg(SrcReg)
2853 BuildMI(*MBB, IP,PPC::LI, 1, DestReg).addSImm(0);
2857 unsigned TmpReg1 = makeAnotherReg(Type::IntTy);
2858 unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
2859 unsigned TmpReg3 = makeAnotherReg(Type::IntTy);
2860 unsigned TmpReg4 = makeAnotherReg(Type::IntTy);
2861 unsigned TmpReg5 = makeAnotherReg(Type::IntTy);
2862 unsigned TmpReg6 = makeAnotherReg(Type::IntTy);
2863 unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
2866 BuildMI(*MBB, IP, PPC::SUBFIC, 2, TmpReg1).addReg(ShiftAmountReg)
2868 BuildMI(*MBB, IP, PPC::SLW, 2, TmpReg2).addReg(SrcReg)
2869 .addReg(ShiftAmountReg);
2870 BuildMI(*MBB, IP, PPC::SRW, 2, TmpReg3).addReg(SrcReg+1)
2872 BuildMI(*MBB, IP, PPC::OR, 2,TmpReg4).addReg(TmpReg2).addReg(TmpReg3);
2873 BuildMI(*MBB, IP, PPC::ADDI, 2, TmpReg5).addReg(ShiftAmountReg)
2875 BuildMI(*MBB, IP, PPC::SLW, 2, TmpReg6).addReg(SrcReg+1)
2877 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(TmpReg4)
2879 BuildMI(*MBB, IP, PPC::SLW, 2, DestReg+1).addReg(SrcReg+1)
2880 .addReg(ShiftAmountReg);
2882 if (isSigned) { // shift right algebraic
2883 MachineBasicBlock *TmpMBB =new MachineBasicBlock(BB->getBasicBlock());
2884 MachineBasicBlock *PhiMBB =new MachineBasicBlock(BB->getBasicBlock());
2885 MachineBasicBlock *OldMBB = BB;
2886 ilist<MachineBasicBlock>::iterator It = BB; ++It;
2887 F->getBasicBlockList().insert(It, TmpMBB);
2888 F->getBasicBlockList().insert(It, PhiMBB);
2889 BB->addSuccessor(TmpMBB);
2890 BB->addSuccessor(PhiMBB);
2892 BuildMI(*MBB, IP, PPC::SUBFIC, 2, TmpReg1).addReg(ShiftAmountReg)
2894 BuildMI(*MBB, IP, PPC::SRW, 2, TmpReg2).addReg(SrcReg+1)
2895 .addReg(ShiftAmountReg);
2896 BuildMI(*MBB, IP, PPC::SLW, 2, TmpReg3).addReg(SrcReg)
2898 BuildMI(*MBB, IP, PPC::OR, 2, TmpReg4).addReg(TmpReg2)
2900 BuildMI(*MBB, IP, PPC::ADDICo, 2, TmpReg5).addReg(ShiftAmountReg)
2902 BuildMI(*MBB, IP, PPC::SRAW, 2, TmpReg6).addReg(SrcReg)
2904 BuildMI(*MBB, IP, PPC::SRAW, 2, DestReg).addReg(SrcReg)
2905 .addReg(ShiftAmountReg);
2906 BuildMI(*MBB, IP, PPC::BLE, 2).addReg(PPC::CR0).addMBB(PhiMBB);
2909 // Select correct least significant half if the shift amount > 32
2911 unsigned OrReg = makeAnotherReg(Type::IntTy);
2912 BuildMI(BB, PPC::OR, 2, OrReg).addReg(TmpReg6).addReg(TmpReg6);
2913 TmpMBB->addSuccessor(PhiMBB);
2916 BuildMI(BB, PPC::PHI, 4, DestReg+1).addReg(TmpReg4).addMBB(OldMBB)
2917 .addReg(OrReg).addMBB(TmpMBB);
2918 } else { // shift right logical
2919 BuildMI(*MBB, IP, PPC::SUBFIC, 2, TmpReg1).addReg(ShiftAmountReg)
2921 BuildMI(*MBB, IP, PPC::SRW, 2, TmpReg2).addReg(SrcReg+1)
2922 .addReg(ShiftAmountReg);
2923 BuildMI(*MBB, IP, PPC::SLW, 2, TmpReg3).addReg(SrcReg)
2925 BuildMI(*MBB, IP, PPC::OR, 2, TmpReg4).addReg(TmpReg2)
2927 BuildMI(*MBB, IP, PPC::ADDI, 2, TmpReg5).addReg(ShiftAmountReg)
2929 BuildMI(*MBB, IP, PPC::SRW, 2, TmpReg6).addReg(SrcReg)
2931 BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(TmpReg4)
2933 BuildMI(*MBB, IP, PPC::SRW, 2, DestReg).addReg(SrcReg)
2934 .addReg(ShiftAmountReg);
2941 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
2942 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
2943 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
2944 unsigned Amount = CUI->getValue();
2946 // If this is a shift with one use, and that use is an And instruction,
2947 // then attempt to emit a bitfield operation.
2948 if (SI && emitBitfieldInsert(SI, DestReg))
2951 unsigned SrcReg = getReg (Op, MBB, IP);
2953 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2954 } else if (isLeftShift) {
2955 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
2956 .addImm(Amount).addImm(0).addImm(31-Amount);
2959 BuildMI(*MBB, IP, PPC::SRAWI,2,DestReg).addReg(SrcReg).addImm(Amount);
2961 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
2962 .addImm(32-Amount).addImm(Amount).addImm(31);
2965 } else { // The shift amount is non-constant.
2966 unsigned SrcReg = getReg (Op, MBB, IP);
2967 unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
2970 BuildMI(*MBB, IP, PPC::SLW, 2, DestReg).addReg(SrcReg)
2971 .addReg(ShiftAmountReg);
2973 BuildMI(*MBB, IP, isSigned ? PPC::SRAW : PPC::SRW, 2, DestReg)
2974 .addReg(SrcReg).addReg(ShiftAmountReg);
2979 /// LoadNeedsSignExtend - On PowerPC, there is no load byte with sign extend.
2980 /// Therefore, if this is a byte load and the destination type is signed, we
2981 /// would normally need to also emit a sign extend instruction after the load.
2982 /// However, store instructions don't care whether a signed type was sign
2983 /// extended across a whole register. Also, a SetCC instruction will emit its
2984 /// own sign extension to force the value into the appropriate range, so we
2985 /// need not emit it here. Ideally, this kind of thing wouldn't be necessary
2986 /// once LLVM's type system is improved.
2987 static bool LoadNeedsSignExtend(LoadInst &LI) {
2988 if (cByte == getClassB(LI.getType()) && LI.getType()->isSigned()) {
2989 bool AllUsesAreStoresOrSetCC = true;
2990 for (Value::use_iterator I = LI.use_begin(), E = LI.use_end(); I != E; ++I){
2991 if (isa<SetCondInst>(*I))
2993 if (StoreInst *SI = dyn_cast<StoreInst>(*I))
2994 if (cByte == getClassB(SI->getOperand(0)->getType()))
2996 AllUsesAreStoresOrSetCC = false;
2999 if (!AllUsesAreStoresOrSetCC)
3005 /// visitLoadInst - Implement LLVM load instructions. Pretty straightforward
3006 /// mapping of LLVM classes to PPC load instructions, with the exception of
3007 /// signed byte loads, which need a sign extension following them.
3009 void PPC32ISel::visitLoadInst(LoadInst &I) {
3010 // Immediate opcodes, for reg+imm addressing
3011 static const unsigned ImmOpcodes[] = {
3012 PPC::LBZ, PPC::LHZ, PPC::LWZ,
3013 PPC::LFS, PPC::LFD, PPC::LWZ
3015 // Indexed opcodes, for reg+reg addressing
3016 static const unsigned IdxOpcodes[] = {
3017 PPC::LBZX, PPC::LHZX, PPC::LWZX,
3018 PPC::LFSX, PPC::LFDX, PPC::LWZX
3021 unsigned Class = getClassB(I.getType());
3022 unsigned ImmOpcode = ImmOpcodes[Class];
3023 unsigned IdxOpcode = IdxOpcodes[Class];
3024 unsigned DestReg = getReg(I);
3025 Value *SourceAddr = I.getOperand(0);
3027 if (Class == cShort && I.getType()->isSigned()) ImmOpcode = PPC::LHA;
3028 if (Class == cShort && I.getType()->isSigned()) IdxOpcode = PPC::LHAX;
3030 // If this is a fixed size alloca, emit a load directly from the stack slot
3031 // corresponding to it.
3032 if (AllocaInst *AI = dyn_castFixedAlloca(SourceAddr)) {
3033 unsigned FI = getFixedSizedAllocaFI(AI);
3034 if (Class == cLong) {
3035 addFrameReference(BuildMI(BB, ImmOpcode, 2, DestReg), FI);
3036 addFrameReference(BuildMI(BB, ImmOpcode, 2, DestReg+1), FI, 4);
3037 } else if (LoadNeedsSignExtend(I)) {
3038 unsigned TmpReg = makeAnotherReg(I.getType());
3039 addFrameReference(BuildMI(BB, ImmOpcode, 2, TmpReg), FI);
3040 BuildMI(BB, PPC::EXTSB, 1, DestReg).addReg(TmpReg);
3042 addFrameReference(BuildMI(BB, ImmOpcode, 2, DestReg), FI);
3047 // If the offset fits in 16 bits, we can emit a reg+imm load, otherwise, we
3048 // use the index from the FoldedGEP struct and use reg+reg addressing.
3049 if (GetElementPtrInst *GEPI = canFoldGEPIntoLoadOrStore(SourceAddr)) {
3051 // Generate the code for the GEP and get the components of the folded GEP
3052 emitGEPOperation(BB, BB->end(), GEPI, true);
3053 unsigned baseReg = GEPMap[GEPI].base;
3054 unsigned indexReg = GEPMap[GEPI].index;
3055 ConstantSInt *offset = GEPMap[GEPI].offset;
3057 if (Class != cLong) {
3058 unsigned TmpReg = LoadNeedsSignExtend(I) ? makeAnotherReg(I.getType())
3061 BuildMI(BB, ImmOpcode, 2, TmpReg).addSImm(offset->getValue())
3064 BuildMI(BB, IdxOpcode, 2, TmpReg).addReg(indexReg).addReg(baseReg);
3065 if (LoadNeedsSignExtend(I))
3066 BuildMI(BB, PPC::EXTSB, 1, DestReg).addReg(TmpReg);
3068 indexReg = (indexReg != 0) ? indexReg : getReg(offset);
3069 unsigned indexPlus4 = makeAnotherReg(Type::IntTy);
3070 BuildMI(BB, PPC::ADDI, 2, indexPlus4).addReg(indexReg).addSImm(4);
3071 BuildMI(BB, IdxOpcode, 2, DestReg).addReg(indexReg).addReg(baseReg);
3072 BuildMI(BB, IdxOpcode, 2, DestReg+1).addReg(indexPlus4).addReg(baseReg);
3077 // The fallback case, where the load was from a source that could not be
3078 // folded into the load instruction.
3079 unsigned SrcAddrReg = getReg(SourceAddr);
3081 if (Class == cLong) {
3082 BuildMI(BB, ImmOpcode, 2, DestReg).addSImm(0).addReg(SrcAddrReg);
3083 BuildMI(BB, ImmOpcode, 2, DestReg+1).addSImm(4).addReg(SrcAddrReg);
3084 } else if (LoadNeedsSignExtend(I)) {
3085 unsigned TmpReg = makeAnotherReg(I.getType());
3086 BuildMI(BB, ImmOpcode, 2, TmpReg).addSImm(0).addReg(SrcAddrReg);
3087 BuildMI(BB, PPC::EXTSB, 1, DestReg).addReg(TmpReg);
3089 BuildMI(BB, ImmOpcode, 2, DestReg).addSImm(0).addReg(SrcAddrReg);
3093 /// visitStoreInst - Implement LLVM store instructions
3095 void PPC32ISel::visitStoreInst(StoreInst &I) {
3096 // Immediate opcodes, for reg+imm addressing
3097 static const unsigned ImmOpcodes[] = {
3098 PPC::STB, PPC::STH, PPC::STW,
3099 PPC::STFS, PPC::STFD, PPC::STW
3101 // Indexed opcodes, for reg+reg addressing
3102 static const unsigned IdxOpcodes[] = {
3103 PPC::STBX, PPC::STHX, PPC::STWX,
3104 PPC::STFSX, PPC::STFDX, PPC::STWX
3107 Value *SourceAddr = I.getOperand(1);
3108 const Type *ValTy = I.getOperand(0)->getType();
3109 unsigned Class = getClassB(ValTy);
3110 unsigned ImmOpcode = ImmOpcodes[Class];
3111 unsigned IdxOpcode = IdxOpcodes[Class];
3112 unsigned ValReg = getReg(I.getOperand(0));
3114 // If this is a fixed size alloca, emit a store directly to the stack slot
3115 // corresponding to it.
3116 if (AllocaInst *AI = dyn_castFixedAlloca(SourceAddr)) {
3117 unsigned FI = getFixedSizedAllocaFI(AI);
3118 addFrameReference(BuildMI(BB, ImmOpcode, 3).addReg(ValReg), FI);
3120 addFrameReference(BuildMI(BB, ImmOpcode, 3).addReg(ValReg+1), FI, 4);
3124 // If the offset fits in 16 bits, we can emit a reg+imm store, otherwise, we
3125 // use the index from the FoldedGEP struct and use reg+reg addressing.
3126 if (GetElementPtrInst *GEPI = canFoldGEPIntoLoadOrStore(SourceAddr)) {
3127 // Generate the code for the GEP and get the components of the folded GEP
3128 emitGEPOperation(BB, BB->end(), GEPI, true);
3129 unsigned baseReg = GEPMap[GEPI].base;
3130 unsigned indexReg = GEPMap[GEPI].index;
3131 ConstantSInt *offset = GEPMap[GEPI].offset;
3133 if (Class != cLong) {
3135 BuildMI(BB, ImmOpcode, 3).addReg(ValReg).addSImm(offset->getValue())
3138 BuildMI(BB, IdxOpcode, 3).addReg(ValReg).addReg(indexReg)
3141 indexReg = (indexReg != 0) ? indexReg : getReg(offset);
3142 unsigned indexPlus4 = makeAnotherReg(Type::IntTy);
3143 BuildMI(BB, PPC::ADDI, 2, indexPlus4).addReg(indexReg).addSImm(4);
3144 BuildMI(BB, IdxOpcode, 3).addReg(ValReg).addReg(indexReg).addReg(baseReg);
3145 BuildMI(BB, IdxOpcode, 3).addReg(ValReg+1).addReg(indexPlus4)
3151 // If the store address wasn't the only use of a GEP, we fall back to the
3152 // standard path: store the ValReg at the value in AddressReg.
3153 unsigned AddressReg = getReg(I.getOperand(1));
3154 if (Class == cLong) {
3155 BuildMI(BB, ImmOpcode, 3).addReg(ValReg).addSImm(0).addReg(AddressReg);
3156 BuildMI(BB, ImmOpcode, 3).addReg(ValReg+1).addSImm(4).addReg(AddressReg);
3159 BuildMI(BB, ImmOpcode, 3).addReg(ValReg).addSImm(0).addReg(AddressReg);
3163 /// visitCastInst - Here we have various kinds of copying with or without sign
3164 /// extension going on.
3166 void PPC32ISel::visitCastInst(CastInst &CI) {
3167 Value *Op = CI.getOperand(0);
3169 unsigned SrcClass = getClassB(Op->getType());
3170 unsigned DestClass = getClassB(CI.getType());
3172 // Noop casts are not emitted: getReg will return the source operand as the
3173 // register to use for any uses of the noop cast.
3174 if (DestClass == SrcClass) return;
3176 // If this is a cast from a 32-bit integer to a Long type, and the only uses
3177 // of the cast are GEP instructions, then the cast does not need to be
3178 // generated explicitly, it will be folded into the GEP.
3179 if (DestClass == cLong && SrcClass == cInt) {
3180 bool AllUsesAreGEPs = true;
3181 for (Value::use_iterator I = CI.use_begin(), E = CI.use_end(); I != E; ++I)
3182 if (!isa<GetElementPtrInst>(*I)) {
3183 AllUsesAreGEPs = false;
3186 if (AllUsesAreGEPs) return;
3189 unsigned DestReg = getReg(CI);
3190 MachineBasicBlock::iterator MI = BB->end();
3192 // If this is a cast from an integer type to a ubyte, with one use where the
3193 // use is the shift amount argument of a shift instruction, just emit a move
3194 // instead (since the shift instruction will only look at the low 5 bits
3195 // regardless of how it is sign extended)
3196 if (CI.getType() == Type::UByteTy && SrcClass <= cInt && CI.hasOneUse()) {
3197 ShiftInst *SI = dyn_cast<ShiftInst>(*(CI.use_begin()));
3198 if (SI && (SI->getOperand(1) == &CI)) {
3199 unsigned SrcReg = getReg(Op, BB, MI);
3200 BuildMI(*BB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
3205 // If this is a cast from an byte, short, or int to an integer type of equal
3206 // or lesser width, and all uses of the cast are store instructions then dont
3207 // emit them, as the store instruction will implicitly not store the zero or
3208 // sign extended bytes.
3209 if (SrcClass <= cInt && SrcClass >= DestClass) {
3210 bool AllUsesAreStores = true;
3211 for (Value::use_iterator I = CI.use_begin(), E = CI.use_end(); I != E; ++I)
3212 if (!isa<StoreInst>(*I)) {
3213 AllUsesAreStores = false;
3216 // Turn this cast directly into a move instruction, which the register
3217 // allocator will deal with.
3218 if (AllUsesAreStores) {
3219 unsigned SrcReg = getReg(Op, BB, MI);
3220 BuildMI(*BB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
3224 emitCastOperation(BB, MI, Op, CI.getType(), DestReg);
3227 /// emitCastOperation - Common code shared between visitCastInst and constant
3228 /// expression cast support.
3230 void PPC32ISel::emitCastOperation(MachineBasicBlock *MBB,
3231 MachineBasicBlock::iterator IP,
3232 Value *Src, const Type *DestTy,
3234 const Type *SrcTy = Src->getType();
3235 unsigned SrcClass = getClassB(SrcTy);
3236 unsigned DestClass = getClassB(DestTy);
3237 unsigned SrcReg = getReg(Src, MBB, IP);
3239 // Implement casts from bool to integer types as a move operation
3240 if (SrcTy == Type::BoolTy) {
3241 switch (DestClass) {
3245 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
3248 BuildMI(*MBB, IP, PPC::LI, 1, DestReg).addImm(0);
3249 BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg).addReg(SrcReg);
3256 // Implement casts to bool by using compare on the operand followed by set if
3257 // not zero on the result.
3258 if (DestTy == Type::BoolTy) {
3263 unsigned TmpReg = makeAnotherReg(Type::IntTy);
3264 BuildMI(*MBB, IP, PPC::ADDIC, 2, TmpReg).addReg(SrcReg).addSImm(-1);
3265 BuildMI(*MBB, IP, PPC::SUBFE, 2, DestReg).addReg(TmpReg).addReg(SrcReg);
3269 unsigned TmpReg = makeAnotherReg(Type::IntTy);
3270 unsigned SrcReg2 = makeAnotherReg(Type::IntTy);
3271 BuildMI(*MBB, IP, PPC::OR, 2, SrcReg2).addReg(SrcReg).addReg(SrcReg+1);
3272 BuildMI(*MBB, IP, PPC::ADDIC, 2, TmpReg).addReg(SrcReg2).addSImm(-1);
3273 BuildMI(*MBB, IP, PPC::SUBFE, 2, DestReg).addReg(TmpReg)
3279 unsigned TmpReg = makeAnotherReg(Type::IntTy);
3280 unsigned ConstZero = getReg(ConstantFP::get(Type::DoubleTy, 0.0), BB, IP);
3281 BuildMI(*MBB, IP, PPC::FCMPU, PPC::CR7).addReg(SrcReg).addReg(ConstZero);
3282 BuildMI(*MBB, IP, PPC::MFCR, TmpReg);
3283 BuildMI(*MBB, IP, PPC::RLWINM, DestReg).addReg(TmpReg).addImm(31)
3284 .addImm(31).addImm(31);
3289 // Handle cast of Float -> Double
3290 if (SrcClass == cFP32 && DestClass == cFP64) {
3291 BuildMI(*MBB, IP, PPC::FMR, 1, DestReg).addReg(SrcReg);
3295 // Handle cast of Double -> Float
3296 if (SrcClass == cFP64 && DestClass == cFP32) {
3297 BuildMI(*MBB, IP, PPC::FRSP, 1, DestReg).addReg(SrcReg);
3301 // Handle casts from integer to floating point now...
3302 if (DestClass == cFP32 || DestClass == cFP64) {
3304 // Emit a library call for long to float conversion
3305 if (SrcClass == cLong) {
3306 Function *floatFn = (DestClass == cFP32) ? __floatdisfFn : __floatdidfFn;
3307 if (SrcTy->isSigned()) {
3308 std::vector<ValueRecord> Args;
3309 Args.push_back(ValueRecord(SrcReg, SrcTy));
3310 MachineInstr *TheCall =
3311 BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(floatFn, true);
3312 doCall(ValueRecord(DestReg, DestTy), TheCall, Args, false);
3314 std::vector<ValueRecord> CmpArgs, ClrArgs, SetArgs;
3315 unsigned ZeroLong = getReg(ConstantUInt::get(SrcTy, 0));
3316 unsigned CondReg = makeAnotherReg(Type::IntTy);
3318 // Update machine-CFG edges
3319 MachineBasicBlock *ClrMBB = new MachineBasicBlock(BB->getBasicBlock());
3320 MachineBasicBlock *SetMBB = new MachineBasicBlock(BB->getBasicBlock());
3321 MachineBasicBlock *PhiMBB = new MachineBasicBlock(BB->getBasicBlock());
3322 MachineBasicBlock *OldMBB = BB;
3323 ilist<MachineBasicBlock>::iterator It = BB; ++It;
3324 F->getBasicBlockList().insert(It, ClrMBB);
3325 F->getBasicBlockList().insert(It, SetMBB);
3326 F->getBasicBlockList().insert(It, PhiMBB);
3327 BB->addSuccessor(ClrMBB);
3328 BB->addSuccessor(SetMBB);
3330 CmpArgs.push_back(ValueRecord(SrcReg, SrcTy));
3331 CmpArgs.push_back(ValueRecord(ZeroLong, SrcTy));
3332 MachineInstr *TheCall =
3333 BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(__cmpdi2Fn, true);
3334 doCall(ValueRecord(CondReg, Type::IntTy), TheCall, CmpArgs, false);
3335 BuildMI(*MBB, IP, PPC::CMPWI, 2, PPC::CR0).addReg(CondReg).addSImm(0);
3336 BuildMI(*MBB, IP, PPC::BLE, 2).addReg(PPC::CR0).addMBB(SetMBB);
3340 unsigned ClrReg = makeAnotherReg(DestTy);
3341 ClrArgs.push_back(ValueRecord(SrcReg, SrcTy));
3342 TheCall = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(floatFn, true);
3343 doCall(ValueRecord(ClrReg, DestTy), TheCall, ClrArgs, false);
3344 BuildMI(BB, PPC::B, 1).addMBB(PhiMBB);
3345 BB->addSuccessor(PhiMBB);
3349 unsigned SetReg = makeAnotherReg(DestTy);
3350 unsigned CallReg = makeAnotherReg(DestTy);
3351 unsigned ShiftedReg = makeAnotherReg(SrcTy);
3352 ConstantSInt *Const1 = ConstantSInt::get(Type::IntTy, 1);
3353 emitShiftOperation(BB, BB->end(), Src, Const1, false, SrcTy, 0,
3355 SetArgs.push_back(ValueRecord(ShiftedReg, SrcTy));
3356 TheCall = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(floatFn, true);
3357 doCall(ValueRecord(CallReg, DestTy), TheCall, SetArgs, false);
3358 unsigned SetOpcode = (DestClass == cFP32) ? PPC::FADDS : PPC::FADD;
3359 BuildMI(BB, SetOpcode, 2, SetReg).addReg(CallReg).addReg(CallReg);
3360 BB->addSuccessor(PhiMBB);
3364 BuildMI(BB, PPC::PHI, 4, DestReg).addReg(ClrReg).addMBB(ClrMBB)
3365 .addReg(SetReg).addMBB(SetMBB);
3370 // Make sure we're dealing with a full 32 bits
3371 if (SrcClass < cInt) {
3372 unsigned TmpReg = makeAnotherReg(Type::IntTy);
3373 promote32(TmpReg, ValueRecord(SrcReg, SrcTy));
3377 // Spill the integer to memory and reload it from there.
3378 // Also spill room for a special conversion constant
3380 F->getFrameInfo()->CreateStackObject(Type::DoubleTy, TM.getTargetData());
3382 unsigned constantHi = makeAnotherReg(Type::IntTy);
3383 unsigned TempF = makeAnotherReg(Type::DoubleTy);
3385 if (!SrcTy->isSigned()) {
3386 ConstantFP *CFP = ConstantFP::get(Type::DoubleTy, 0x1.000000p52);
3387 unsigned ConstF = getReg(CFP, BB, IP);
3388 BuildMI(*MBB, IP, PPC::LIS, 1, constantHi).addSImm(0x4330);
3389 addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(constantHi),
3391 addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(SrcReg),
3393 addFrameReference(BuildMI(*MBB, IP, PPC::LFD, 2, TempF), ValueFrameIdx);
3394 BuildMI(*MBB, IP, PPC::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF);
3396 ConstantFP *CFP = ConstantFP::get(Type::DoubleTy, 0x1.000008p52);
3397 unsigned ConstF = getReg(CFP, BB, IP);
3398 unsigned TempLo = makeAnotherReg(Type::IntTy);
3399 BuildMI(*MBB, IP, PPC::LIS, 1, constantHi).addSImm(0x4330);
3400 addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(constantHi),
3402 BuildMI(*MBB, IP, PPC::XORIS, 2, TempLo).addReg(SrcReg).addImm(0x8000);
3403 addFrameReference(BuildMI(*MBB, IP, PPC::STW, 3).addReg(TempLo),
3405 addFrameReference(BuildMI(*MBB, IP, PPC::LFD, 2, TempF), ValueFrameIdx);
3406 BuildMI(*MBB, IP, PPC::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF);
3411 // Handle casts from floating point to integer now...
3412 if (SrcClass == cFP32 || SrcClass == cFP64) {
3413 static Function* const Funcs[] =
3414 { __fixsfdiFn, __fixdfdiFn, __fixunssfdiFn, __fixunsdfdiFn };
3415 // emit library call
3416 if (DestClass == cLong) {
3417 bool isDouble = SrcClass == cFP64;
3418 unsigned nameIndex = 2 * DestTy->isSigned() + isDouble;
3419 std::vector<ValueRecord> Args;
3420 Args.push_back(ValueRecord(SrcReg, SrcTy));
3421 Function *floatFn = Funcs[nameIndex];
3422 MachineInstr *TheCall =
3423 BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(floatFn, true);
3424 doCall(ValueRecord(DestReg, DestTy), TheCall, Args, false);
3429 F->getFrameInfo()->CreateStackObject(Type::DoubleTy, TM.getTargetData());
3431 if (DestTy->isSigned()) {
3432 unsigned TempReg = makeAnotherReg(Type::DoubleTy);
3434 // Convert to integer in the FP reg and store it to a stack slot
3435 BuildMI(*MBB, IP, PPC::FCTIWZ, 1, TempReg).addReg(SrcReg);
3436 addFrameReference(BuildMI(*MBB, IP, PPC::STFD, 3)
3437 .addReg(TempReg), ValueFrameIdx);
3439 // There is no load signed byte opcode, so we must emit a sign extend for
3440 // that particular size. Make sure to source the new integer from the
3442 if (DestClass == cByte) {
3443 unsigned TempReg2 = makeAnotherReg(DestTy);
3444 addFrameReference(BuildMI(*MBB, IP, PPC::LBZ, 2, TempReg2),
3446 BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(TempReg2);
3448 int offset = (DestClass == cShort) ? 6 : 4;
3449 unsigned LoadOp = (DestClass == cShort) ? PPC::LHA : PPC::LWZ;
3450 addFrameReference(BuildMI(*MBB, IP, LoadOp, 2, DestReg),
3451 ValueFrameIdx, offset);
3454 unsigned Zero = getReg(ConstantFP::get(Type::DoubleTy, 0.0f));
3455 double maxInt = (1LL << 32) - 1;
3456 unsigned MaxInt = getReg(ConstantFP::get(Type::DoubleTy, maxInt));
3457 double border = 1LL << 31;
3458 unsigned Border = getReg(ConstantFP::get(Type::DoubleTy, border));
3459 unsigned UseZero = makeAnotherReg(Type::DoubleTy);
3460 unsigned UseMaxInt = makeAnotherReg(Type::DoubleTy);
3461 unsigned UseChoice = makeAnotherReg(Type::DoubleTy);
3462 unsigned TmpReg = makeAnotherReg(Type::DoubleTy);
3463 unsigned TmpReg2 = makeAnotherReg(Type::DoubleTy);
3464 unsigned ConvReg = makeAnotherReg(Type::DoubleTy);
3465 unsigned IntTmp = makeAnotherReg(Type::IntTy);
3466 unsigned XorReg = makeAnotherReg(Type::IntTy);
3468 F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
3469 // Update machine-CFG edges
3470 MachineBasicBlock *XorMBB = new MachineBasicBlock(BB->getBasicBlock());
3471 MachineBasicBlock *PhiMBB = new MachineBasicBlock(BB->getBasicBlock());
3472 MachineBasicBlock *OldMBB = BB;
3473 ilist<MachineBasicBlock>::iterator It = BB; ++It;
3474 F->getBasicBlockList().insert(It, XorMBB);
3475 F->getBasicBlockList().insert(It, PhiMBB);
3476 BB->addSuccessor(XorMBB);
3477 BB->addSuccessor(PhiMBB);
3479 // Convert from floating point to unsigned 32-bit value
3480 // Use 0 if incoming value is < 0.0
3481 BuildMI(*MBB, IP, PPC::FSEL, 3, UseZero).addReg(SrcReg).addReg(SrcReg)
3483 // Use 2**32 - 1 if incoming value is >= 2**32
3484 BuildMI(*MBB, IP, PPC::FSUB, 2, UseMaxInt).addReg(MaxInt).addReg(SrcReg);
3485 BuildMI(*MBB, IP, PPC::FSEL, 3, UseChoice).addReg(UseMaxInt)
3486 .addReg(UseZero).addReg(MaxInt);
3488 BuildMI(*MBB, IP, PPC::FSUB, 2, TmpReg).addReg(UseChoice).addReg(Border);
3489 // Use difference if >= 2**31
3490 BuildMI(*MBB, IP, PPC::FCMPU, 2, PPC::CR0).addReg(UseChoice)
3492 BuildMI(*MBB, IP, PPC::FSEL, 3, TmpReg2).addReg(TmpReg).addReg(TmpReg)
3494 // Convert to integer
3495 BuildMI(*MBB, IP, PPC::FCTIWZ, 1, ConvReg).addReg(TmpReg2);
3496 addFrameReference(BuildMI(*MBB, IP, PPC::STFD, 3).addReg(ConvReg),
3498 if (DestClass == cByte) {
3499 addFrameReference(BuildMI(*MBB, IP, PPC::LBZ, 2, DestReg),
3501 } else if (DestClass == cShort) {
3502 addFrameReference(BuildMI(*MBB, IP, PPC::LHZ, 2, DestReg),
3504 } if (DestClass == cInt) {
3505 addFrameReference(BuildMI(*MBB, IP, PPC::LWZ, 2, IntTmp),
3507 BuildMI(*MBB, IP, PPC::BLT, 2).addReg(PPC::CR0).addMBB(PhiMBB);
3508 BuildMI(*MBB, IP, PPC::B, 1).addMBB(XorMBB);
3511 // add 2**31 if input was >= 2**31
3513 BuildMI(BB, PPC::XORIS, 2, XorReg).addReg(IntTmp).addImm(0x8000);
3514 XorMBB->addSuccessor(PhiMBB);
3517 // DestReg = phi [ IntTmp, OldMBB ], [ XorReg, XorMBB ]
3519 BuildMI(BB, PPC::PHI, 4, DestReg).addReg(IntTmp).addMBB(OldMBB)
3520 .addReg(XorReg).addMBB(XorMBB);
3526 // Check our invariants
3527 assert((SrcClass <= cInt || SrcClass == cLong) &&
3528 "Unhandled source class for cast operation!");
3529 assert((DestClass <= cInt || DestClass == cLong) &&
3530 "Unhandled destination class for cast operation!");
3532 bool sourceUnsigned = SrcTy->isUnsigned() || SrcTy == Type::BoolTy;
3533 bool destUnsigned = DestTy->isUnsigned();
3535 // Unsigned -> Unsigned, clear if larger,
3536 if (sourceUnsigned && destUnsigned) {
3537 // handle long dest class now to keep switch clean
3538 if (DestClass == cLong) {
3539 BuildMI(*MBB, IP, PPC::LI, 1, DestReg).addSImm(0);
3540 BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg)
3545 // handle u{ byte, short, int } x u{ byte, short, int }
3546 unsigned clearBits = (SrcClass == cByte || DestClass == cByte) ? 24 : 16;
3550 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
3551 .addImm(0).addImm(clearBits).addImm(31);
3557 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
3558 .addImm(0).addImm(clearBits).addImm(31);
3565 if (!sourceUnsigned && !destUnsigned) {
3566 // handle long dest class now to keep switch clean
3567 if (DestClass == cLong) {
3568 BuildMI(*MBB, IP, PPC::SRAWI, 2, DestReg).addReg(SrcReg).addImm(31);
3569 BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg)
3574 // handle { byte, short, int } x { byte, short, int }
3577 BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
3580 if (DestClass == cByte)
3581 BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
3583 BuildMI(*MBB, IP, PPC::EXTSH, 1, DestReg).addReg(SrcReg);
3589 if (DestClass == cByte)
3590 BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
3591 else if (DestClass == cShort)
3592 BuildMI(*MBB, IP, PPC::EXTSH, 1, DestReg).addReg(SrcReg);
3594 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
3600 // Unsigned -> Signed
3601 if (sourceUnsigned && !destUnsigned) {
3602 // handle long dest class now to keep switch clean
3603 if (DestClass == cLong) {
3604 BuildMI(*MBB, IP, PPC::LI, 1, DestReg).addSImm(0);
3605 BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg)
3610 // handle u{ byte, short, int } -> { byte, short, int }
3613 // uByte 255 -> signed short/int == 255
3614 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg).addImm(0)
3615 .addImm(24).addImm(31);
3618 if (DestClass == cByte)
3619 BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
3621 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg).addImm(0)
3622 .addImm(16).addImm(31);
3628 if (DestClass == cByte)
3629 BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
3630 else if (DestClass == cShort)
3631 BuildMI(*MBB, IP, PPC::EXTSH, 1, DestReg).addReg(SrcReg);
3633 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
3639 // Signed -> Unsigned
3640 if (!sourceUnsigned && destUnsigned) {
3641 // handle long dest class now to keep switch clean
3642 if (DestClass == cLong) {
3643 BuildMI(*MBB, IP, PPC::SRAWI, 2, DestReg).addReg(SrcReg).addImm(31);
3644 BuildMI(*MBB, IP, PPC::OR, 2, DestReg+1).addReg(SrcReg)
3649 // handle { byte, short, int } -> u{ byte, short, int }
3650 unsigned clearBits = (DestClass == cByte) ? 24 : 16;
3653 BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
3656 if (DestClass == cByte)
3657 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
3658 .addImm(0).addImm(clearBits).addImm(31);
3660 BuildMI(*MBB, IP, PPC::EXTSH, 1, DestReg).addReg(SrcReg);
3666 if (DestClass == cInt)
3667 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
3669 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
3670 .addImm(0).addImm(clearBits).addImm(31);
3676 // Anything we haven't handled already, we can't (yet) handle at all.
3677 std::cerr << "Unhandled cast from " << SrcTy->getDescription()
3678 << "to " << DestTy->getDescription() << '\n';
3682 /// visitVANextInst - Implement the va_next instruction...
3684 void PPC32ISel::visitVANextInst(VANextInst &I) {
3685 unsigned VAList = getReg(I.getOperand(0));
3686 unsigned DestReg = getReg(I);
3689 switch (I.getArgType()->getTypeID()) {
3692 assert(0 && "Error: bad type for va_next instruction!");
3694 case Type::PointerTyID:
3695 case Type::UIntTyID:
3699 case Type::ULongTyID:
3700 case Type::LongTyID:
3701 case Type::DoubleTyID:
3706 // Increment the VAList pointer...
3707 BuildMI(BB, PPC::ADDI, 2, DestReg).addReg(VAList).addSImm(Size);
3710 void PPC32ISel::visitVAArgInst(VAArgInst &I) {
3711 unsigned VAList = getReg(I.getOperand(0));
3712 unsigned DestReg = getReg(I);
3714 switch (I.getType()->getTypeID()) {
3717 assert(0 && "Error: bad type for va_next instruction!");
3719 case Type::PointerTyID:
3720 case Type::UIntTyID:
3722 BuildMI(BB, PPC::LWZ, 2, DestReg).addSImm(0).addReg(VAList);
3724 case Type::ULongTyID:
3725 case Type::LongTyID:
3726 BuildMI(BB, PPC::LWZ, 2, DestReg).addSImm(0).addReg(VAList);
3727 BuildMI(BB, PPC::LWZ, 2, DestReg+1).addSImm(4).addReg(VAList);
3729 case Type::FloatTyID:
3730 BuildMI(BB, PPC::LFS, 2, DestReg).addSImm(0).addReg(VAList);
3732 case Type::DoubleTyID:
3733 BuildMI(BB, PPC::LFD, 2, DestReg).addSImm(0).addReg(VAList);
3738 /// visitGetElementPtrInst - instruction-select GEP instructions
3740 void PPC32ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
3741 if (canFoldGEPIntoLoadOrStore(&I))
3744 emitGEPOperation(BB, BB->end(), &I, false);
3747 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
3748 /// constant expression GEP support.
3750 void PPC32ISel::emitGEPOperation(MachineBasicBlock *MBB,
3751 MachineBasicBlock::iterator IP,
3752 GetElementPtrInst *GEPI, bool GEPIsFolded) {
3753 // If we've already emitted this particular GEP, just return to avoid
3754 // multiple definitions of the base register.
3755 if (GEPIsFolded && (GEPMap[GEPI].base != 0))
3758 Value *Src = GEPI->getOperand(0);
3759 User::op_iterator IdxBegin = GEPI->op_begin()+1;
3760 User::op_iterator IdxEnd = GEPI->op_end();
3761 const TargetData &TD = TM.getTargetData();
3762 const Type *Ty = Src->getType();
3763 int32_t constValue = 0;
3765 // Record the operations to emit the GEP in a vector so that we can emit them
3766 // after having analyzed the entire instruction.
3767 std::vector<CollapsedGepOp> ops;
3769 // GEPs have zero or more indices; we must perform a struct access
3770 // or array access for each one.
3771 for (GetElementPtrInst::op_iterator oi = IdxBegin, oe = IdxEnd; oi != oe;
3774 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
3775 // It's a struct access. idx is the index into the structure,
3776 // which names the field. Use the TargetData structure to
3777 // pick out what the layout of the structure is in memory.
3778 // Use the (constant) structure index's value to find the
3779 // right byte offset from the StructLayout class's list of
3780 // structure member offsets.
3781 unsigned fieldIndex = cast<ConstantUInt>(idx)->getValue();
3783 // StructType member offsets are always constant values. Add it to the
3785 constValue += TD.getStructLayout(StTy)->MemberOffsets[fieldIndex];
3787 // The next type is the member of the structure selected by the index.
3788 Ty = StTy->getElementType (fieldIndex);
3789 } else if (const SequentialType *SqTy = dyn_cast<SequentialType>(Ty)) {
3790 // Many GEP instructions use a [cast (int/uint) to LongTy] as their
3791 // operand. Handle this case directly now...
3792 if (CastInst *CI = dyn_cast<CastInst>(idx))
3793 if (CI->getOperand(0)->getType() == Type::IntTy ||
3794 CI->getOperand(0)->getType() == Type::UIntTy)
3795 idx = CI->getOperand(0);
3797 // It's an array or pointer access: [ArraySize x ElementType].
3798 // We want to add basePtrReg to (idxReg * sizeof ElementType). First, we
3799 // must find the size of the pointed-to type (Not coincidentally, the next
3800 // type is the type of the elements in the array).
3801 Ty = SqTy->getElementType();
3802 unsigned elementSize = TD.getTypeSize(Ty);
3804 if (ConstantInt *C = dyn_cast<ConstantInt>(idx)) {
3805 if (ConstantSInt *CS = dyn_cast<ConstantSInt>(C))
3806 constValue += CS->getValue() * elementSize;
3807 else if (ConstantUInt *CU = dyn_cast<ConstantUInt>(C))
3808 constValue += CU->getValue() * elementSize;
3810 assert(0 && "Invalid ConstantInt GEP index type!");
3812 // Push current gep state to this point as an add and multiply
3813 ops.push_back(CollapsedGepOp(
3814 ConstantSInt::get(Type::IntTy, constValue),
3815 idx, ConstantUInt::get(Type::UIntTy, elementSize)));
3821 // Emit instructions for all the collapsed ops
3822 unsigned indexReg = 0;
3823 for(std::vector<CollapsedGepOp>::iterator cgo_i = ops.begin(),
3824 cgo_e = ops.end(); cgo_i != cgo_e; ++cgo_i) {
3825 CollapsedGepOp& cgo = *cgo_i;
3827 // Avoid emitting known move instructions here for the register allocator
3828 // to deal with later. val * 1 == val. val + 0 == val.
3830 if (cgo.size->getValue() == 1) {
3831 TmpReg1 = getReg(cgo.index, MBB, IP);
3833 TmpReg1 = makeAnotherReg(Type::IntTy);
3834 doMultiplyConst(MBB, IP, TmpReg1, cgo.index, cgo.size);
3838 if (cgo.offset->isNullValue()) {
3841 TmpReg2 = makeAnotherReg(Type::IntTy);
3842 emitBinaryConstOperation(MBB, IP, TmpReg1, cgo.offset, 0, TmpReg2);
3848 unsigned TmpReg3 = makeAnotherReg(Type::IntTy);
3849 BuildMI(*MBB, IP, PPC::ADD, 2, TmpReg3).addReg(indexReg).addReg(TmpReg2);
3854 // We now have a base register, an index register, and possibly a constant
3855 // remainder. If the GEP is going to be folded, we try to generate the
3856 // optimal addressing mode.
3857 ConstantSInt *remainder = ConstantSInt::get(Type::IntTy, constValue);
3859 // If we are emitting this during a fold, copy the current base register to
3860 // the target, and save the current constant offset so the folding load or
3861 // store can try and use it as an immediate.
3863 if (indexReg == 0) {
3864 if (!canUseAsImmediateForOpcode(remainder, 0, false)) {
3865 indexReg = getReg(remainder, MBB, IP);
3868 } else if (!remainder->isNullValue()) {
3869 unsigned TmpReg = makeAnotherReg(Type::IntTy);
3870 emitBinaryConstOperation(MBB, IP, indexReg, remainder, 0, TmpReg);
3874 unsigned basePtrReg = getReg(Src, MBB, IP);
3875 GEPMap[GEPI] = FoldedGEP(basePtrReg, indexReg, remainder);
3879 // We're not folding, so collapse the base, index, and any remainder into the
3880 // destination register.
3881 unsigned TargetReg = getReg(GEPI, MBB, IP);
3882 unsigned basePtrReg = getReg(Src, MBB, IP);
3884 if ((indexReg == 0) && remainder->isNullValue()) {
3885 BuildMI(*MBB, IP, PPC::OR, 2, TargetReg).addReg(basePtrReg)
3886 .addReg(basePtrReg);
3889 if (!remainder->isNullValue()) {
3890 unsigned TmpReg = (indexReg == 0) ? TargetReg : makeAnotherReg(Type::IntTy);
3891 emitBinaryConstOperation(MBB, IP, basePtrReg, remainder, 0, TmpReg);
3892 basePtrReg = TmpReg;
3895 BuildMI(*MBB, IP, PPC::ADD, 2, TargetReg).addReg(indexReg)
3896 .addReg(basePtrReg);
3899 /// visitAllocaInst - If this is a fixed size alloca, allocate space from the
3900 /// frame manager, otherwise do it the hard way.
3902 void PPC32ISel::visitAllocaInst(AllocaInst &I) {
3903 // If this is a fixed size alloca in the entry block for the function, we
3904 // statically stack allocate the space, so we don't need to do anything here.
3906 if (dyn_castFixedAlloca(&I)) return;
3908 // Find the data size of the alloca inst's getAllocatedType.
3909 const Type *Ty = I.getAllocatedType();
3910 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
3912 // Create a register to hold the temporary result of multiplying the type size
3913 // constant by the variable amount.
3914 unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
3916 // TotalSizeReg = mul <numelements>, <TypeSize>
3917 MachineBasicBlock::iterator MBBI = BB->end();
3918 ConstantUInt *CUI = ConstantUInt::get(Type::UIntTy, TySize);
3919 doMultiplyConst(BB, MBBI, TotalSizeReg, I.getArraySize(), CUI);
3921 // AddedSize = add <TotalSizeReg>, 15
3922 unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy);
3923 BuildMI(BB, PPC::ADDI, 2, AddedSizeReg).addReg(TotalSizeReg).addSImm(15);
3925 // AlignedSize = and <AddedSize>, ~15
3926 unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
3927 BuildMI(BB, PPC::RLWINM, 4, AlignedSize).addReg(AddedSizeReg).addImm(0)
3928 .addImm(0).addImm(27);
3930 // Subtract size from stack pointer, thereby allocating some space.
3931 BuildMI(BB, PPC::SUBF, 2, PPC::R1).addReg(AlignedSize).addReg(PPC::R1);
3933 // Put a pointer to the space into the result register, by copying
3934 // the stack pointer.
3935 BuildMI(BB, PPC::OR, 2, getReg(I)).addReg(PPC::R1).addReg(PPC::R1);
3937 // Inform the Frame Information that we have just allocated a variable-sized
3939 F->getFrameInfo()->CreateVariableSizedObject();
3942 /// visitMallocInst - Malloc instructions are code generated into direct calls
3943 /// to the library malloc.
3945 void PPC32ISel::visitMallocInst(MallocInst &I) {
3946 unsigned AllocSize = TM.getTargetData().getTypeSize(I.getAllocatedType());
3949 if (ConstantUInt *C = dyn_cast<ConstantUInt>(I.getOperand(0))) {
3950 Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize));
3952 Arg = makeAnotherReg(Type::UIntTy);
3953 MachineBasicBlock::iterator MBBI = BB->end();
3954 ConstantUInt *CUI = ConstantUInt::get(Type::UIntTy, AllocSize);
3955 doMultiplyConst(BB, MBBI, Arg, I.getOperand(0), CUI);
3958 std::vector<ValueRecord> Args;
3959 Args.push_back(ValueRecord(Arg, Type::UIntTy));
3960 MachineInstr *TheCall =
3961 BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(mallocFn, true);
3962 doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args, false);
3965 /// visitFreeInst - Free instructions are code gen'd to call the free libc
3968 void PPC32ISel::visitFreeInst(FreeInst &I) {
3969 std::vector<ValueRecord> Args;
3970 Args.push_back(ValueRecord(I.getOperand(0)));
3971 MachineInstr *TheCall =
3972 BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(freeFn, true);
3973 doCall(ValueRecord(0, Type::VoidTy), TheCall, Args, false);
3976 /// createPPC32ISelSimple - This pass converts an LLVM function into a machine
3977 /// code representation is a very simple peep-hole fashion.
3979 FunctionPass *llvm::createPPC32ISelSimple(TargetMachine &TM) {
3980 return new PPC32ISel(TM);