1 //===-- InstSelectSimple.cpp - A simple instruction selector for PowerPC --===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "PowerPCInstrBuilder.h"
12 #include "PowerPCInstrInfo.h"
13 #include "llvm/Constants.h"
14 #include "llvm/DerivedTypes.h"
15 #include "llvm/Function.h"
16 #include "llvm/Instructions.h"
17 #include "llvm/IntrinsicLowering.h"
18 #include "llvm/Pass.h"
19 #include "llvm/CodeGen/MachineConstantPool.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/SSARegMap.h"
23 #include "llvm/Target/MRegisterInfo.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Support/GetElementPtrTypeIterator.h"
26 #include "llvm/Support/InstVisitor.h"
30 /// TypeClass - Used by the PowerPC backend to group LLVM types by their basic
31 /// PPC Representation.
34 cByte, cShort, cInt, cFP, cLong
38 /// getClass - Turn a primitive type into a "class" number which is based on the
39 /// size of the type, and whether or not it is floating point.
41 static inline TypeClass getClass(const Type *Ty) {
42 switch (Ty->getTypeID()) {
44 case Type::UByteTyID: return cByte; // Byte operands are class #0
46 case Type::UShortTyID: return cShort; // Short operands are class #1
49 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
52 case Type::DoubleTyID: return cFP; // Floating Point is #3
55 case Type::ULongTyID: return cLong; // Longs are class #4
57 assert(0 && "Invalid type to getClass!");
58 return cByte; // not reached
62 // getClassB - Just like getClass, but treat boolean values as ints.
63 static inline TypeClass getClassB(const Type *Ty) {
64 if (Ty == Type::BoolTy) return cInt;
69 struct ISel : public FunctionPass, InstVisitor<ISel> {
71 MachineFunction *F; // The function we are compiling into
72 MachineBasicBlock *BB; // The current MBB we are compiling
73 int VarArgsFrameIndex; // FrameIndex for start of varargs area
74 int ReturnAddressIndex; // FrameIndex for the return address
76 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
78 // MBBMap - Mapping between LLVM BB -> Machine BB
79 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
81 // AllocaMap - Mapping from fixed sized alloca instructions to the
82 // FrameIndex for the alloca.
83 std::map<AllocaInst*, unsigned> AllocaMap;
85 ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
87 /// runOnFunction - Top level implementation of instruction selection for
88 /// the entire function.
90 bool runOnFunction(Function &Fn) {
91 // First pass over the function, lower any unknown intrinsic functions
92 // with the IntrinsicLowering class.
93 LowerUnknownIntrinsicFunctionCalls(Fn);
95 F = &MachineFunction::construct(&Fn, TM);
97 // Create all of the machine basic blocks for the function...
98 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
99 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
103 // Set up a frame object for the return address. This is used by the
104 // llvm.returnaddress & llvm.frameaddress intrinisics.
105 ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
107 // Copy incoming arguments off of the stack...
108 LoadArgumentsToVirtualRegs(Fn);
110 // Instruction select everything except PHI nodes
113 // Select the PHI nodes
120 // We always build a machine code representation for the function
124 virtual const char *getPassName() const {
125 return "PowerPC Simple Instruction Selection";
128 /// visitBasicBlock - This method is called when we are visiting a new basic
129 /// block. This simply creates a new MachineBasicBlock to emit code into
130 /// and adds it to the current MachineFunction. Subsequent visit* for
131 /// instructions will be invoked for all instructions in the basic block.
133 void visitBasicBlock(BasicBlock &LLVM_BB) {
134 BB = MBBMap[&LLVM_BB];
137 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
138 /// function, lowering any calls to unknown intrinsic functions into the
139 /// equivalent LLVM code.
141 void LowerUnknownIntrinsicFunctionCalls(Function &F);
143 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function
144 /// from the stack into virtual registers.
146 void LoadArgumentsToVirtualRegs(Function &F);
148 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
149 /// because we have to generate our sources into the source basic blocks,
150 /// not the current one.
152 void SelectPHINodes();
154 // Visitation methods for various instructions. These methods simply emit
155 // fixed PowerPC code for each instruction.
157 // Control flow operators
158 void visitReturnInst(ReturnInst &RI);
159 void visitBranchInst(BranchInst &BI);
165 ValueRecord(unsigned R, const Type *T) : Val(0), Reg(R), Ty(T) {}
166 ValueRecord(Value *V) : Val(V), Reg(0), Ty(V->getType()) {}
168 void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
169 const std::vector<ValueRecord> &Args);
170 void visitCallInst(CallInst &I);
171 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &I);
173 // Arithmetic operators
174 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
175 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
176 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
177 void visitMul(BinaryOperator &B);
179 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
180 void visitRem(BinaryOperator &B) { visitDivRem(B); }
181 void visitDivRem(BinaryOperator &B);
184 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
185 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
186 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
188 // Comparison operators...
189 void visitSetCondInst(SetCondInst &I);
190 unsigned EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
191 MachineBasicBlock *MBB,
192 MachineBasicBlock::iterator MBBI);
193 void visitSelectInst(SelectInst &SI);
196 // Memory Instructions
197 void visitLoadInst(LoadInst &I);
198 void visitStoreInst(StoreInst &I);
199 void visitGetElementPtrInst(GetElementPtrInst &I);
200 void visitAllocaInst(AllocaInst &I);
201 void visitMallocInst(MallocInst &I);
202 void visitFreeInst(FreeInst &I);
205 void visitShiftInst(ShiftInst &I);
206 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
207 void visitCastInst(CastInst &I);
208 void visitVANextInst(VANextInst &I);
209 void visitVAArgInst(VAArgInst &I);
211 void visitInstruction(Instruction &I) {
212 std::cerr << "Cannot instruction select: " << I;
216 /// promote32 - Make a value 32-bits wide, and put it somewhere.
218 void promote32(unsigned targetReg, const ValueRecord &VR);
220 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
221 /// constant expression GEP support.
223 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
224 Value *Src, User::op_iterator IdxBegin,
225 User::op_iterator IdxEnd, unsigned TargetReg);
227 /// emitCastOperation - Common code shared between visitCastInst and
228 /// constant expression cast support.
230 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator IP,
231 Value *Src, const Type *DestTy, unsigned TargetReg);
233 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
234 /// and constant expression support.
236 void emitSimpleBinaryOperation(MachineBasicBlock *BB,
237 MachineBasicBlock::iterator IP,
238 Value *Op0, Value *Op1,
239 unsigned OperatorClass, unsigned TargetReg);
241 /// emitBinaryFPOperation - This method handles emission of floating point
242 /// Add (0), Sub (1), Mul (2), and Div (3) operations.
243 void emitBinaryFPOperation(MachineBasicBlock *BB,
244 MachineBasicBlock::iterator IP,
245 Value *Op0, Value *Op1,
246 unsigned OperatorClass, unsigned TargetReg);
248 void emitMultiply(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
249 Value *Op0, Value *Op1, unsigned TargetReg);
251 void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
252 unsigned DestReg, const Type *DestTy,
253 unsigned Op0Reg, unsigned Op1Reg);
254 void doMultiplyConst(MachineBasicBlock *MBB,
255 MachineBasicBlock::iterator MBBI,
256 unsigned DestReg, const Type *DestTy,
257 unsigned Op0Reg, unsigned Op1Val);
259 void emitDivRemOperation(MachineBasicBlock *BB,
260 MachineBasicBlock::iterator IP,
261 Value *Op0, Value *Op1, bool isDiv,
264 /// emitSetCCOperation - Common code shared between visitSetCondInst and
265 /// constant expression support.
267 void emitSetCCOperation(MachineBasicBlock *BB,
268 MachineBasicBlock::iterator IP,
269 Value *Op0, Value *Op1, unsigned Opcode,
272 /// emitShiftOperation - Common code shared between visitShiftInst and
273 /// constant expression support.
275 void emitShiftOperation(MachineBasicBlock *MBB,
276 MachineBasicBlock::iterator IP,
277 Value *Op, Value *ShiftAmount, bool isLeftShift,
278 const Type *ResultTy, unsigned DestReg);
280 /// emitSelectOperation - Common code shared between visitSelectInst and the
281 /// constant expression support.
282 void emitSelectOperation(MachineBasicBlock *MBB,
283 MachineBasicBlock::iterator IP,
284 Value *Cond, Value *TrueVal, Value *FalseVal,
287 /// copyConstantToRegister - Output the instructions required to put the
288 /// specified constant into the specified register.
290 void copyConstantToRegister(MachineBasicBlock *MBB,
291 MachineBasicBlock::iterator MBBI,
292 Constant *C, unsigned Reg);
294 void emitUCOM(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
295 unsigned LHS, unsigned RHS);
297 /// makeAnotherReg - This method returns the next register number we haven't
300 /// Long values are handled somewhat specially. They are always allocated
301 /// as pairs of 32 bit integer values. The register number returned is the
302 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
303 /// of the long value.
305 unsigned makeAnotherReg(const Type *Ty) {
306 assert(dynamic_cast<const PowerPCRegisterInfo*>(TM.getRegisterInfo()) &&
307 "Current target doesn't have PPC reg info??");
308 const PowerPCRegisterInfo *MRI =
309 static_cast<const PowerPCRegisterInfo*>(TM.getRegisterInfo());
310 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
311 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
312 // Create the lower part
313 F->getSSARegMap()->createVirtualRegister(RC);
314 // Create the upper part.
315 return F->getSSARegMap()->createVirtualRegister(RC)-1;
318 // Add the mapping of regnumber => reg class to MachineFunction
319 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
320 return F->getSSARegMap()->createVirtualRegister(RC);
323 /// getReg - This method turns an LLVM value into a register number.
325 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
326 unsigned getReg(Value *V) {
327 // Just append to the end of the current bb.
328 MachineBasicBlock::iterator It = BB->end();
329 return getReg(V, BB, It);
331 unsigned getReg(Value *V, MachineBasicBlock *MBB,
332 MachineBasicBlock::iterator IPt);
334 /// getFixedSizedAllocaFI - Return the frame index for a fixed sized alloca
335 /// that is to be statically allocated with the initial stack frame
337 unsigned getFixedSizedAllocaFI(AllocaInst *AI);
341 /// dyn_castFixedAlloca - If the specified value is a fixed size alloca
342 /// instruction in the entry block, return it. Otherwise, return a null
344 static AllocaInst *dyn_castFixedAlloca(Value *V) {
345 if (AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
346 BasicBlock *BB = AI->getParent();
347 if (isa<ConstantUInt>(AI->getArraySize()) && BB ==&BB->getParent()->front())
353 /// getReg - This method turns an LLVM value into a register number.
355 unsigned ISel::getReg(Value *V, MachineBasicBlock *MBB,
356 MachineBasicBlock::iterator IPt) {
357 // If this operand is a constant, emit the code to copy the constant into
358 // the register here...
360 if (Constant *C = dyn_cast<Constant>(V)) {
361 unsigned Reg = makeAnotherReg(V->getType());
362 copyConstantToRegister(MBB, IPt, C, Reg);
364 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
365 unsigned Reg1 = makeAnotherReg(V->getType());
366 unsigned Reg2 = makeAnotherReg(V->getType());
367 // Move the address of the global into the register
368 BuildMI(*MBB, IPt, PPC32::LOADHiAddr, 2, Reg1).addReg(PPC32::R0).addGlobalAddress(GV);
369 BuildMI(*MBB, IPt, PPC32::LOADLoAddr, 2, Reg2).addReg(Reg1).addGlobalAddress(GV);
371 } else if (CastInst *CI = dyn_cast<CastInst>(V)) {
372 // Do not emit noop casts at all.
373 if (getClassB(CI->getType()) == getClassB(CI->getOperand(0)->getType()))
374 return getReg(CI->getOperand(0), MBB, IPt);
375 } else if (AllocaInst *AI = dyn_castFixedAlloca(V)) {
376 unsigned Reg = makeAnotherReg(V->getType());
377 unsigned FI = getFixedSizedAllocaFI(AI);
378 addFrameReference(BuildMI(*MBB, IPt, PPC32::ADDI, 2, Reg), FI, 0, false);
382 unsigned &Reg = RegMap[V];
384 Reg = makeAnotherReg(V->getType());
391 /// getFixedSizedAllocaFI - Return the frame index for a fixed sized alloca
392 /// that is to be statically allocated with the initial stack frame
394 unsigned ISel::getFixedSizedAllocaFI(AllocaInst *AI) {
395 // Already computed this?
396 std::map<AllocaInst*, unsigned>::iterator I = AllocaMap.lower_bound(AI);
397 if (I != AllocaMap.end() && I->first == AI) return I->second;
399 const Type *Ty = AI->getAllocatedType();
400 ConstantUInt *CUI = cast<ConstantUInt>(AI->getArraySize());
401 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
402 TySize *= CUI->getValue(); // Get total allocated size...
403 unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
405 // Create a new stack object using the frame manager...
406 int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
407 AllocaMap.insert(I, std::make_pair(AI, FrameIdx));
412 /// copyConstantToRegister - Output the instructions required to put the
413 /// specified constant into the specified register.
415 void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
416 MachineBasicBlock::iterator IP,
417 Constant *C, unsigned R) {
418 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
420 switch (CE->getOpcode()) {
421 case Instruction::GetElementPtr:
422 emitGEPOperation(MBB, IP, CE->getOperand(0),
423 CE->op_begin()+1, CE->op_end(), R);
425 case Instruction::Cast:
426 emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
429 case Instruction::Xor: ++Class; // FALL THROUGH
430 case Instruction::Or: ++Class; // FALL THROUGH
431 case Instruction::And: ++Class; // FALL THROUGH
432 case Instruction::Sub: ++Class; // FALL THROUGH
433 case Instruction::Add:
434 emitSimpleBinaryOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
438 case Instruction::Mul:
439 emitMultiply(MBB, IP, CE->getOperand(0), CE->getOperand(1), R);
442 case Instruction::Div:
443 case Instruction::Rem:
444 emitDivRemOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
445 CE->getOpcode() == Instruction::Div, R);
448 case Instruction::SetNE:
449 case Instruction::SetEQ:
450 case Instruction::SetLT:
451 case Instruction::SetGT:
452 case Instruction::SetLE:
453 case Instruction::SetGE:
454 emitSetCCOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
458 case Instruction::Shl:
459 case Instruction::Shr:
460 emitShiftOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
461 CE->getOpcode() == Instruction::Shl, CE->getType(), R);
464 case Instruction::Select:
465 emitSelectOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
466 CE->getOperand(2), R);
470 std::cerr << "Offending expr: " << C << "\n";
471 assert(0 && "Constant expression not yet handled!\n");
475 if (C->getType()->isIntegral()) {
476 unsigned Class = getClassB(C->getType());
478 if (Class == cLong) {
479 // Copy the value into the register pair.
480 uint64_t Val = cast<ConstantInt>(C)->getRawValue();
481 unsigned hiTmp = makeAnotherReg(Type::IntTy);
482 unsigned loTmp = makeAnotherReg(Type::IntTy);
483 BuildMI(*MBB, IP, PPC32::ADDIS, 2, loTmp).addReg(PPC32::R0).addImm(Val >> 48);
484 BuildMI(*MBB, IP, PPC32::ORI, 2, R).addReg(loTmp).addImm((Val >> 32) & 0xFFFF);
485 BuildMI(*MBB, IP, PPC32::ADDIS, 2, hiTmp).addReg(PPC32::R0).addImm((Val >> 16) & 0xFFFF);
486 BuildMI(*MBB, IP, PPC32::ORI, 2, R+1).addReg(hiTmp).addImm(Val & 0xFFFF);
490 assert(Class <= cInt && "Type not handled yet!");
492 if (C->getType() == Type::BoolTy) {
493 BuildMI(*MBB, IP, PPC32::ADDI, 2, R).addReg(PPC32::R0).addImm(C == ConstantBool::True);
494 } else if (Class == cByte || Class == cShort) {
495 ConstantInt *CI = cast<ConstantInt>(C);
496 BuildMI(*MBB, IP, PPC32::ADDI, 2, R).addReg(PPC32::R0).addImm(CI->getRawValue());
498 ConstantInt *CI = cast<ConstantInt>(C);
499 int TheVal = CI->getRawValue() & 0xFFFFFFFF;
500 if (TheVal < 32768 && TheVal >= -32768) {
501 BuildMI(*MBB, IP, PPC32::ADDI, 2, R).addReg(PPC32::R0).addImm(CI->getRawValue());
503 unsigned TmpReg = makeAnotherReg(Type::IntTy);
504 BuildMI(*MBB, IP, PPC32::ADDIS, 2, TmpReg).addReg(PPC32::R0).addImm(CI->getRawValue() >> 16);
505 BuildMI(*MBB, IP, PPC32::ORI, 2, R).addReg(TmpReg).addImm(CI->getRawValue() & 0xFFFF);
508 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
509 // We need to spill the constant to memory...
510 MachineConstantPool *CP = F->getConstantPool();
511 unsigned CPI = CP->getConstantPoolIndex(CFP);
512 const Type *Ty = CFP->getType();
514 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
515 unsigned LoadOpcode = Ty == Type::FloatTy ? PPC32::LFS : PPC32::LFD;
516 addConstantPoolReference(BuildMI(*MBB, IP, LoadOpcode, 2, R), CPI);
517 } else if (isa<ConstantPointerNull>(C)) {
518 // Copy zero (null pointer) to the register.
519 BuildMI(*MBB, IP, PPC32::ADDI, 2, R).addReg(PPC32::R0).addImm(0);
520 } else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) {
521 BuildMI(*MBB, IP, PPC32::ADDIS, 2, R).addReg(PPC32::R0).addGlobalAddress(CPR->getValue());
522 BuildMI(*MBB, IP, PPC32::ORI, 2, R).addReg(PPC32::R0).addGlobalAddress(CPR->getValue());
524 std::cerr << "Offending constant: " << C << "\n";
525 assert(0 && "Type not handled yet!");
529 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function from
530 /// the stack into virtual registers.
532 /// FIXME: When we can calculate which args are coming in via registers
533 /// source them from there instead.
534 void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
535 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
536 unsigned GPR_remaining = 8;
537 unsigned FPR_remaining = 13;
538 unsigned GPR_idx = 3;
539 unsigned FPR_idx = 1;
541 MachineFrameInfo *MFI = F->getFrameInfo();
543 for (Function::aiterator I = Fn.abegin(), E = Fn.aend(); I != E; ++I) {
544 bool ArgLive = !I->use_empty();
545 unsigned Reg = ArgLive ? getReg(*I) : 0;
546 int FI; // Frame object index
548 switch (getClassB(I->getType())) {
551 FI = MFI->CreateFixedObject(1, ArgOffset);
552 if (GPR_remaining > 0) {
553 BuildMI(BB, PPC32::OR, 2, Reg).addReg(PPC32::R0+GPR_idx).addReg(PPC32::R0+GPR_idx);
555 addFrameReference(BuildMI(BB, PPC32::LBZ, 2, Reg), FI);
561 FI = MFI->CreateFixedObject(2, ArgOffset);
562 if (GPR_remaining > 0) {
563 BuildMI(BB, PPC32::OR, 2, Reg).addReg(PPC32::R0+GPR_idx).addReg(PPC32::R0+GPR_idx);
565 addFrameReference(BuildMI(BB, PPC32::LHZ, 2, Reg), FI);
571 FI = MFI->CreateFixedObject(4, ArgOffset);
572 if (GPR_remaining > 0) {
573 BuildMI(BB, PPC32::OR, 2, Reg).addReg(PPC32::R0+GPR_idx).addReg(PPC32::R0+GPR_idx);
575 addFrameReference(BuildMI(BB, PPC32::LWZ, 2, Reg), FI);
581 FI = MFI->CreateFixedObject(8, ArgOffset);
582 if (GPR_remaining > 1) {
583 BuildMI(BB, PPC32::OR, 2, Reg).addReg(PPC32::R0+GPR_idx).addReg(PPC32::R0+GPR_idx);
584 BuildMI(BB, PPC32::OR, 2, Reg+1).addReg(PPC32::R0+GPR_idx+1).addReg(PPC32::R0+GPR_idx+1);
586 addFrameReference(BuildMI(BB, PPC32::LWZ, 2, Reg), FI);
587 addFrameReference(BuildMI(BB, PPC32::LWZ, 2, Reg+1), FI, 4);
590 ArgOffset += 4; // longs require 4 additional bytes
591 if (GPR_remaining > 1) {
592 GPR_remaining--; // uses up 2 GPRs
599 if (I->getType() == Type::FloatTy) {
601 FI = MFI->CreateFixedObject(4, ArgOffset);
604 FI = MFI->CreateFixedObject(8, ArgOffset);
606 if (FPR_remaining > 0) {
607 BuildMI(BB, PPC32::FMR, 1, Reg).addReg(PPC32::F0+FPR_idx);
611 addFrameReference(BuildMI(BB, Opcode, 2, Reg), FI);
614 if (I->getType() == Type::DoubleTy) {
615 ArgOffset += 4; // doubles require 4 additional bytes
616 if (GPR_remaining > 0) {
617 GPR_remaining--; // uses up 2 GPRs
623 assert(0 && "Unhandled argument type!");
625 ArgOffset += 4; // Each argument takes at least 4 bytes on the stack...
626 if (GPR_remaining > 0) {
627 GPR_remaining--; // uses up 2 GPRs
632 // If the function takes variable number of arguments, add a frame offset for
633 // the start of the first vararg value... this is used to expand
635 if (Fn.getFunctionType()->isVarArg())
636 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
640 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
641 /// because we have to generate our sources into the source basic blocks, not
644 void ISel::SelectPHINodes() {
645 const TargetInstrInfo &TII = *TM.getInstrInfo();
646 const Function &LF = *F->getFunction(); // The LLVM function...
647 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
648 const BasicBlock *BB = I;
649 MachineBasicBlock &MBB = *MBBMap[I];
651 // Loop over all of the PHI nodes in the LLVM basic block...
652 MachineBasicBlock::iterator PHIInsertPoint = MBB.begin();
653 for (BasicBlock::const_iterator I = BB->begin();
654 PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
656 // Create a new machine instr PHI node, and insert it.
657 unsigned PHIReg = getReg(*PN);
658 MachineInstr *PhiMI = BuildMI(MBB, PHIInsertPoint,
659 PPC32::PHI, PN->getNumOperands(), PHIReg);
661 MachineInstr *LongPhiMI = 0;
662 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy)
663 LongPhiMI = BuildMI(MBB, PHIInsertPoint,
664 PPC32::PHI, PN->getNumOperands(), PHIReg+1);
666 // PHIValues - Map of blocks to incoming virtual registers. We use this
667 // so that we only initialize one incoming value for a particular block,
668 // even if the block has multiple entries in the PHI node.
670 std::map<MachineBasicBlock*, unsigned> PHIValues;
672 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
673 MachineBasicBlock *PredMBB = MBBMap[PN->getIncomingBlock(i)];
675 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
676 PHIValues.lower_bound(PredMBB);
678 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
679 // We already inserted an initialization of the register for this
680 // predecessor. Recycle it.
681 ValReg = EntryIt->second;
684 // Get the incoming value into a virtual register.
686 Value *Val = PN->getIncomingValue(i);
688 // If this is a constant or GlobalValue, we may have to insert code
689 // into the basic block to compute it into a virtual register.
690 if ((isa<Constant>(Val) && !isa<ConstantExpr>(Val)) ||
691 isa<GlobalValue>(Val)) {
692 // Simple constants get emitted at the end of the basic block,
693 // before any terminator instructions. We "know" that the code to
694 // move a constant into a register will never clobber any flags.
695 ValReg = getReg(Val, PredMBB, PredMBB->getFirstTerminator());
697 // Because we don't want to clobber any values which might be in
698 // physical registers with the computation of this constant (which
699 // might be arbitrarily complex if it is a constant expression),
700 // just insert the computation at the top of the basic block.
701 MachineBasicBlock::iterator PI = PredMBB->begin();
703 // Skip over any PHI nodes though!
704 while (PI != PredMBB->end() && PI->getOpcode() == PPC32::PHI)
707 ValReg = getReg(Val, PredMBB, PI);
710 // Remember that we inserted a value for this PHI for this predecessor
711 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
714 PhiMI->addRegOperand(ValReg);
715 PhiMI->addMachineBasicBlockOperand(PredMBB);
717 LongPhiMI->addRegOperand(ValReg+1);
718 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
722 // Now that we emitted all of the incoming values for the PHI node, make
723 // sure to reposition the InsertPoint after the PHI that we just added.
724 // This is needed because we might have inserted a constant into this
725 // block, right after the PHI's which is before the old insert point!
726 PHIInsertPoint = LongPhiMI ? LongPhiMI : PhiMI;
733 // canFoldSetCCIntoBranchOrSelect - Return the setcc instruction if we can fold
734 // it into the conditional branch or select instruction which is the only user
735 // of the cc instruction. This is the case if the conditional branch is the
736 // only user of the setcc, and if the setcc is in the same basic block as the
737 // conditional branch. We also don't handle long arguments below, so we reject
738 // them here as well.
740 static SetCondInst *canFoldSetCCIntoBranchOrSelect(Value *V) {
741 if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
742 if (SCI->hasOneUse()) {
743 Instruction *User = cast<Instruction>(SCI->use_back());
744 if ((isa<BranchInst>(User) || isa<SelectInst>(User)) &&
745 SCI->getParent() == User->getParent() &&
746 (getClassB(SCI->getOperand(0)->getType()) != cLong ||
747 SCI->getOpcode() == Instruction::SetEQ ||
748 SCI->getOpcode() == Instruction::SetNE))
754 // Return a fixed numbering for setcc instructions which does not depend on the
755 // order of the opcodes.
757 static unsigned getSetCCNumber(unsigned Opcode) {
759 default: assert(0 && "Unknown setcc instruction!");
760 case Instruction::SetEQ: return 0;
761 case Instruction::SetNE: return 1;
762 case Instruction::SetLT: return 2;
763 case Instruction::SetGE: return 3;
764 case Instruction::SetGT: return 4;
765 case Instruction::SetLE: return 5;
769 /// emitUCOM - emits an unordered FP compare.
770 void ISel::emitUCOM(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
771 unsigned LHS, unsigned RHS) {
772 BuildMI(*MBB, IP, PPC32::FCMPU, 2, PPC32::CR0).addReg(LHS).addReg(RHS);
775 // EmitComparison - This function emits a comparison of the two operands,
776 // returning the extended setcc code to use.
777 unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
778 MachineBasicBlock *MBB,
779 MachineBasicBlock::iterator IP) {
780 // The arguments are already supposed to be of the same type.
781 const Type *CompTy = Op0->getType();
782 unsigned Class = getClassB(CompTy);
783 unsigned Op0r = getReg(Op0, MBB, IP);
785 // Special case handling of: cmp R, i
786 if (isa<ConstantPointerNull>(Op1)) {
787 BuildMI(*MBB, IP, PPC32::CMPI, 2, PPC32::CR0).addReg(Op0r).addImm(0);
788 } else if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
789 if (Class == cByte || Class == cShort || Class == cInt) {
790 unsigned Op1v = CI->getRawValue();
792 // Mask off any upper bits of the constant, if there are any...
793 Op1v &= (1ULL << (8 << Class)) - 1;
795 // Compare immediate or promote to reg?
797 BuildMI(*MBB, IP, CompTy->isSigned() ? PPC32::CMPI : PPC32::CMPLI, 3, PPC32::CR0).addImm(0).addReg(Op0r).addImm(Op1v);
799 unsigned Op1r = getReg(Op1, MBB, IP);
800 BuildMI(*MBB, IP, CompTy->isSigned() ? PPC32::CMP : PPC32::CMPL, 3, PPC32::CR0).addImm(0).addReg(Op0r).addReg(Op1r);
804 assert(Class == cLong && "Unknown integer class!");
805 unsigned LowCst = CI->getRawValue();
806 unsigned HiCst = CI->getRawValue() >> 32;
807 if (OpNum < 2) { // seteq, setne
808 unsigned LoTmp = Op0r;
810 unsigned LoLow = makeAnotherReg(Type::IntTy);
811 unsigned LoTmp = makeAnotherReg(Type::IntTy);
812 BuildMI(*MBB, IP, PPC32::XORI, 2, LoLow).addReg(Op0r).addImm(LowCst);
813 BuildMI(*MBB, IP, PPC32::XORIS, 2, LoTmp).addReg(LoLow).addImm(LowCst >> 16);
815 unsigned HiTmp = Op0r+1;
817 unsigned HiLow = makeAnotherReg(Type::IntTy);
818 unsigned HiTmp = makeAnotherReg(Type::IntTy);
819 BuildMI(*MBB, IP, PPC32::XORI, 2, HiLow).addReg(Op0r+1).addImm(HiCst);
820 BuildMI(*MBB, IP, PPC32::XORIS, 2, HiTmp).addReg(HiLow).addImm(HiCst >> 16);
822 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
823 BuildMI(*MBB, IP, PPC32::ORo, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
824 //BuildMI(*MBB, IP, PPC32::CMPLI, 2, PPC32::CR0).addReg(FinalTmp).addImm(0);
827 // Emit a sequence of code which compares the high and low parts once
828 // each, then uses a conditional move to handle the overflow case. For
829 // example, a setlt for long would generate code like this:
831 // AL = lo(op1) < lo(op2) // Always unsigned comparison
832 // BL = hi(op1) < hi(op2) // Signedness depends on operands
833 // dest = hi(op1) == hi(op2) ? BL : AL;
836 // FIXME: Not Yet Implemented
842 unsigned Op1r = getReg(Op1, MBB, IP);
844 default: assert(0 && "Unknown type class!");
848 BuildMI(*MBB, IP, CompTy->isSigned() ? PPC32::CMP : PPC32::CMPL, 2, PPC32::CR0).addReg(Op0r).addReg(Op1r);
851 emitUCOM(MBB, IP, Op0r, Op1r);
855 if (OpNum < 2) { // seteq, setne
856 unsigned LoTmp = makeAnotherReg(Type::IntTy);
857 unsigned HiTmp = makeAnotherReg(Type::IntTy);
858 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
859 BuildMI(*MBB, IP, PPC32::XOR, 2, LoTmp).addReg(Op0r).addReg(Op1r);
860 BuildMI(*MBB, IP, PPC32::XOR, 2, HiTmp).addReg(Op0r+1).addReg(Op1r+1);
861 BuildMI(*MBB, IP, PPC32::ORo, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
862 //BuildMI(*MBB, IP, PPC32::CMPLI, 2, PPC32::CR0).addReg(FinalTmp).addImm(0);
863 break; // Allow the sete or setne to be generated from flags set by OR
865 // Emit a sequence of code which compares the high and low parts once
866 // each, then uses a conditional move to handle the overflow case. For
867 // example, a setlt for long would generate code like this:
869 // AL = lo(op1) < lo(op2) // Signedness depends on operands
870 // BL = hi(op1) < hi(op2) // Always unsigned comparison
871 // dest = hi(op1) == hi(op2) ? BL : AL;
874 // FIXME: Not Yet Implemented
881 /// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
882 /// register, then move it to wherever the result should be.
884 void ISel::visitSetCondInst(SetCondInst &I) {
885 if (canFoldSetCCIntoBranchOrSelect(&I))
886 return; // Fold this into a branch or select.
888 unsigned DestReg = getReg(I);
889 MachineBasicBlock::iterator MII = BB->end();
890 emitSetCCOperation(BB, MII, I.getOperand(0), I.getOperand(1), I.getOpcode(),DestReg);
893 /// emitSetCCOperation - Common code shared between visitSetCondInst and
894 /// constant expression support.
896 /// FIXME: this is wrong. we should figure out a way to guarantee
897 /// TargetReg is a CR and then make it a no-op
898 void ISel::emitSetCCOperation(MachineBasicBlock *MBB,
899 MachineBasicBlock::iterator IP,
900 Value *Op0, Value *Op1, unsigned Opcode,
901 unsigned TargetReg) {
902 unsigned OpNum = getSetCCNumber(Opcode);
903 OpNum = EmitComparison(OpNum, Op0, Op1, MBB, IP);
905 // The value is already in CR0 at this point, do nothing.
909 void ISel::visitSelectInst(SelectInst &SI) {
910 unsigned DestReg = getReg(SI);
911 MachineBasicBlock::iterator MII = BB->end();
912 emitSelectOperation(BB, MII, SI.getCondition(), SI.getTrueValue(),SI.getFalseValue(), DestReg);
915 /// emitSelect - Common code shared between visitSelectInst and the constant
916 /// expression support.
917 /// FIXME: this is most likely broken in one or more ways. Namely, PowerPC has
918 /// no select instruction. FSEL only works for comparisons against zero.
919 void ISel::emitSelectOperation(MachineBasicBlock *MBB,
920 MachineBasicBlock::iterator IP,
921 Value *Cond, Value *TrueVal, Value *FalseVal,
923 unsigned SelectClass = getClassB(TrueVal->getType());
925 unsigned TrueReg = getReg(TrueVal, MBB, IP);
926 unsigned FalseReg = getReg(FalseVal, MBB, IP);
928 if (TrueReg == FalseReg) {
929 if (SelectClass == cFP) {
930 BuildMI(*MBB, IP, PPC32::FMR, 1, DestReg).addReg(TrueReg);
932 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(TrueReg).addReg(TrueReg);
935 if (SelectClass == cLong)
936 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg+1).addReg(TrueReg+1).addReg(TrueReg+1);
940 unsigned CondReg = getReg(Cond, MBB, IP);
941 unsigned numZeros = makeAnotherReg(Type::IntTy);
942 unsigned falseHi = makeAnotherReg(Type::IntTy);
943 unsigned falseAll = makeAnotherReg(Type::IntTy);
944 unsigned trueAll = makeAnotherReg(Type::IntTy);
945 unsigned Temp1 = makeAnotherReg(Type::IntTy);
946 unsigned Temp2 = makeAnotherReg(Type::IntTy);
948 BuildMI(*MBB, IP, PPC32::CNTLZW, 1, numZeros).addReg(CondReg);
949 BuildMI(*MBB, IP, PPC32::RLWINM, 4, falseHi).addReg(numZeros).addImm(26).addImm(0).addImm(0);
950 BuildMI(*MBB, IP, PPC32::SRAWI, 2, falseAll).addReg(falseHi).addImm(31);
951 BuildMI(*MBB, IP, PPC32::NOR, 2, trueAll).addReg(falseAll).addReg(falseAll);
952 BuildMI(*MBB, IP, PPC32::AND, 2, Temp1).addReg(TrueReg).addReg(trueAll);
953 BuildMI(*MBB, IP, PPC32::AND, 2, Temp2).addReg(FalseReg).addReg(falseAll);
954 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(Temp1).addReg(Temp2);
956 if (SelectClass == cLong) {
957 unsigned Temp3 = makeAnotherReg(Type::IntTy);
958 unsigned Temp4 = makeAnotherReg(Type::IntTy);
959 BuildMI(*MBB, IP, PPC32::AND, 2, Temp3).addReg(TrueReg+1).addReg(trueAll);
960 BuildMI(*MBB, IP, PPC32::AND, 2, Temp4).addReg(FalseReg+1).addReg(falseAll);
961 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg+1).addReg(Temp3).addReg(Temp4);
969 /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
970 /// operand, in the specified target register.
972 void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
973 bool isUnsigned = VR.Ty->isUnsigned() || VR.Ty == Type::BoolTy;
976 const Type *Ty = VR.Ty;
978 if (Constant *C = dyn_cast<Constant>(Val)) {
979 Val = ConstantExpr::getCast(C, Type::IntTy);
983 // If this is a simple constant, just emit a load directly to avoid the copy.
984 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
985 int TheVal = CI->getRawValue() & 0xFFFFFFFF;
987 if (TheVal < 32768 && TheVal >= -32768) {
988 BuildMI(BB, PPC32::ADDI, 2, targetReg).addReg(PPC32::R0).addImm(TheVal);
990 unsigned TmpReg = makeAnotherReg(Type::IntTy);
991 BuildMI(BB, PPC32::ADDIS, 2, TmpReg).addReg(PPC32::R0).addImm(TheVal >> 16);
992 BuildMI(BB, PPC32::ORI, 2, targetReg).addReg(TmpReg).addImm(TheVal & 0xFFFF);
998 // Make sure we have the register number for this value...
999 unsigned Reg = Val ? getReg(Val) : VR.Reg;
1001 switch (getClassB(Ty)) {
1003 // Extend value into target register (8->32)
1005 BuildMI(BB, PPC32::RLWINM, 4, targetReg).addReg(Reg).addZImm(0).addZImm(24).addZImm(31);
1007 BuildMI(BB, PPC32::EXTSB, 1, targetReg).addReg(Reg);
1010 // Extend value into target register (16->32)
1012 BuildMI(BB, PPC32::RLWINM, 4, targetReg).addReg(Reg).addZImm(0).addZImm(16).addZImm(31);
1014 BuildMI(BB, PPC32::EXTSH, 1, targetReg).addReg(Reg);
1017 // Move value into target register (32->32)
1018 BuildMI(BB, PPC32::ORI, 2, targetReg).addReg(Reg).addReg(Reg);
1021 assert(0 && "Unpromotable operand class in promote32");
1026 void ISel::visitReturnInst(ReturnInst &I) {
1027 Value *RetVal = I.getOperand(0);
1029 switch (getClassB(RetVal->getType())) {
1030 case cByte: // integral return values: extend or move into r3 and return
1033 promote32(PPC32::R3, ValueRecord(RetVal));
1035 case cFP: { // Floats & Doubles: Return in f1
1036 unsigned RetReg = getReg(RetVal);
1037 BuildMI(BB, PPC32::FMR, 1, PPC32::F1).addReg(RetReg);
1041 unsigned RetReg = getReg(RetVal);
1042 BuildMI(BB, PPC32::OR, 2, PPC32::R3).addReg(RetReg).addReg(RetReg);
1043 BuildMI(BB, PPC32::OR, 2, PPC32::R4).addReg(RetReg+1).addReg(RetReg+1);
1047 visitInstruction(I);
1049 BuildMI(BB, PPC32::BLR, 1).addImm(0);
1052 // getBlockAfter - Return the basic block which occurs lexically after the
1054 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
1055 Function::iterator I = BB; ++I; // Get iterator to next block
1056 return I != BB->getParent()->end() ? &*I : 0;
1059 /// visitBranchInst - Handle conditional and unconditional branches here. Note
1060 /// that since code layout is frozen at this point, that if we are trying to
1061 /// jump to a block that is the immediate successor of the current block, we can
1062 /// just make a fall-through (but we don't currently).
1064 void ISel::visitBranchInst(BranchInst &BI) {
1065 // Update machine-CFG edges
1066 BB->addSuccessor (MBBMap[BI.getSuccessor(0)]);
1067 if (BI.isConditional())
1068 BB->addSuccessor (MBBMap[BI.getSuccessor(1)]);
1070 BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
1072 if (!BI.isConditional()) { // Unconditional branch?
1073 if (BI.getSuccessor(0) != NextBB)
1074 BuildMI(BB, PPC32::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
1078 // See if we can fold the setcc into the branch itself...
1079 SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(BI.getCondition());
1081 // Nope, cannot fold setcc into this branch. Emit a branch on a condition
1082 // computed some other way...
1083 unsigned condReg = getReg(BI.getCondition());
1084 BuildMI(BB, PPC32::CMPLI, 3, PPC32::CR0).addImm(0).addReg(condReg).addImm(0);
1085 if (BI.getSuccessor(1) == NextBB) {
1086 if (BI.getSuccessor(0) != NextBB)
1087 BuildMI(BB, PPC32::BC, 3).addImm(4).addImm(2).addMBB(MBBMap[BI.getSuccessor(0)]);
1089 BuildMI(BB, PPC32::BC, 3).addImm(12).addImm(2).addMBB(MBBMap[BI.getSuccessor(1)]);
1091 if (BI.getSuccessor(0) != NextBB)
1092 BuildMI(BB, PPC32::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
1098 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
1099 MachineBasicBlock::iterator MII = BB->end();
1100 OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
1102 const Type *CompTy = SCI->getOperand(0)->getType();
1103 bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
1105 // LLVM -> X86 signed X86 unsigned
1106 // ----- ---------- ------------
1114 static const unsigned BITab[6] = { 2, 2, 0, 0, 1, 1 };
1115 unsigned BO_true = (OpNum % 2 == 0) ? 12 : 4;
1116 unsigned BO_false = (OpNum % 2 == 0) ? 4 : 12;
1117 unsigned BIval = BITab[0];
1119 if (BI.getSuccessor(0) != NextBB) {
1120 BuildMI(BB, PPC32::BC, 3).addImm(BO_true).addImm(BIval).addMBB(MBBMap[BI.getSuccessor(0)]);
1121 if (BI.getSuccessor(1) != NextBB)
1122 BuildMI(BB, PPC32::B, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
1124 // Change to the inverse condition...
1125 if (BI.getSuccessor(1) != NextBB) {
1126 BuildMI(BB, PPC32::BC, 3).addImm(BO_false).addImm(BIval).addMBB(MBBMap[BI.getSuccessor(1)]);
1132 /// doCall - This emits an abstract call instruction, setting up the arguments
1133 /// and the return value as appropriate. For the actual function call itself,
1134 /// it inserts the specified CallMI instruction into the stream.
1136 /// FIXME: See Documentation at the following URL for "correct" behavior
1137 /// <http://developer.apple.com/documentation/DeveloperTools/Conceptual/MachORuntime/2rt_powerpc_abi/chapter_9_section_5.html>
1138 void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
1139 const std::vector<ValueRecord> &Args) {
1140 // Count how many bytes are to be pushed on the stack...
1141 unsigned NumBytes = 0;
1143 if (!Args.empty()) {
1144 for (unsigned i = 0, e = Args.size(); i != e; ++i)
1145 switch (getClassB(Args[i].Ty)) {
1146 case cByte: case cShort: case cInt:
1147 NumBytes += 4; break;
1149 NumBytes += 8; break;
1151 NumBytes += Args[i].Ty == Type::FloatTy ? 4 : 8;
1153 default: assert(0 && "Unknown class!");
1156 // Adjust the stack pointer for the new arguments...
1157 BuildMI(BB, PPC32::ADJCALLSTACKDOWN, 1).addImm(NumBytes);
1159 // Arguments go on the stack in reverse order, as specified by the ABI.
1160 unsigned ArgOffset = 0;
1161 unsigned GPR_remaining = 8;
1162 unsigned FPR_remaining = 13;
1163 unsigned GPR_idx = 3;
1164 unsigned FPR_idx = 1;
1166 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
1168 switch (getClassB(Args[i].Ty)) {
1171 // Promote arg to 32 bits wide into a temporary register...
1172 ArgReg = makeAnotherReg(Type::UIntTy);
1173 promote32(ArgReg, Args[i]);
1176 if (GPR_remaining > 0) {
1177 BuildMI(BB, PPC32::OR, 2, PPC32::R0 + GPR_idx).addReg(ArgReg).addReg(ArgReg);
1179 BuildMI(BB, PPC32::STW, 3).addReg(ArgReg).addImm(ArgOffset).addReg(PPC32::R1);
1183 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1186 if (GPR_remaining > 0) {
1187 BuildMI(BB, PPC32::OR, 2, PPC32::R0 + GPR_idx).addReg(ArgReg).addReg(ArgReg);
1189 BuildMI(BB, PPC32::STW, 3).addReg(ArgReg).addImm(ArgOffset).addReg(PPC32::R1);
1193 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1196 if (GPR_remaining > 1) {
1197 BuildMI(BB, PPC32::OR, 2, PPC32::R0 + GPR_idx).addReg(ArgReg).addReg(ArgReg);
1198 BuildMI(BB, PPC32::OR, 2, PPC32::R0 + GPR_idx + 1).addReg(ArgReg+1).addReg(ArgReg+1);
1200 BuildMI(BB, PPC32::STW, 3).addReg(ArgReg).addImm(ArgOffset).addReg(PPC32::R1);
1201 BuildMI(BB, PPC32::STW, 3).addReg(ArgReg+1).addImm(ArgOffset+4).addReg(PPC32::R1);
1204 ArgOffset += 4; // 8 byte entry, not 4.
1205 if (GPR_remaining > 0) {
1206 GPR_remaining -= 1; // uses up 2 GPRs
1211 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1212 if (Args[i].Ty == Type::FloatTy) {
1214 if (FPR_remaining > 0) {
1215 BuildMI(BB, PPC32::FMR, 1, PPC32::F0 + FPR_idx).addReg(ArgReg);
1219 BuildMI(BB, PPC32::STFS, 3).addReg(ArgReg).addImm(ArgOffset).addReg(PPC32::R1);
1222 assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
1224 if (FPR_remaining > 0) {
1225 BuildMI(BB, PPC32::FMR, 1, PPC32::F0 + FPR_idx).addReg(ArgReg);
1229 BuildMI(BB, PPC32::STFD, 3).addReg(ArgReg).addImm(ArgOffset).addReg(PPC32::R1);
1232 ArgOffset += 4; // 8 byte entry, not 4.
1233 if (GPR_remaining > 0) {
1234 GPR_remaining--; // uses up 2 GPRs
1240 default: assert(0 && "Unknown class!");
1243 if (GPR_remaining > 0) {
1244 GPR_remaining--; // uses up 2 GPRs
1249 BuildMI(BB, PPC32::ADJCALLSTACKDOWN, 1).addImm(0);
1252 BB->push_back(CallMI);
1254 BuildMI(BB, PPC32::ADJCALLSTACKUP, 1).addImm(NumBytes);
1256 // If there is a return value, scavenge the result from the location the call
1259 if (Ret.Ty != Type::VoidTy) {
1260 unsigned DestClass = getClassB(Ret.Ty);
1261 switch (DestClass) {
1265 // Integral results are in r3
1266 BuildMI(BB, PPC32::OR, 2, Ret.Reg).addReg(PPC32::R3).addReg(PPC32::R3);
1267 case cFP: // Floating-point return values live in f1
1268 BuildMI(BB, PPC32::FMR, 1, Ret.Reg).addReg(PPC32::F1);
1270 case cLong: // Long values are in r3:r4
1271 BuildMI(BB, PPC32::OR, 2, Ret.Reg).addReg(PPC32::R3).addReg(PPC32::R3);
1272 BuildMI(BB, PPC32::OR, 2, Ret.Reg+1).addReg(PPC32::R4).addReg(PPC32::R4);
1274 default: assert(0 && "Unknown class!");
1280 /// visitCallInst - Push args on stack and do a procedure call instruction.
1281 void ISel::visitCallInst(CallInst &CI) {
1282 MachineInstr *TheCall;
1283 if (Function *F = CI.getCalledFunction()) {
1284 // Is it an intrinsic function call?
1285 if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
1286 visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here
1290 // Emit a CALL instruction with PC-relative displacement.
1291 TheCall = BuildMI(PPC32::CALLpcrel, 1).addGlobalAddress(F, true);
1292 } else { // Emit an indirect call through the CTR
1293 unsigned Reg = getReg(CI.getCalledValue());
1294 BuildMI(PPC32::MTSPR, 2).addZImm(9).addReg(Reg);
1295 TheCall = BuildMI(PPC32::CALLindirect, 1).addZImm(20).addZImm(0);
1298 std::vector<ValueRecord> Args;
1299 for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i)
1300 Args.push_back(ValueRecord(CI.getOperand(i)));
1302 unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
1303 doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args);
1307 /// dyncastIsNan - Return the operand of an isnan operation if this is an isnan.
1309 static Value *dyncastIsNan(Value *V) {
1310 if (CallInst *CI = dyn_cast<CallInst>(V))
1311 if (Function *F = CI->getCalledFunction())
1312 if (F->getIntrinsicID() == Intrinsic::isunordered)
1313 return CI->getOperand(1);
1317 /// isOnlyUsedByUnorderedComparisons - Return true if this value is only used by
1318 /// or's whos operands are all calls to the isnan predicate.
1319 static bool isOnlyUsedByUnorderedComparisons(Value *V) {
1320 assert(dyncastIsNan(V) && "The value isn't an isnan call!");
1322 // Check all uses, which will be or's of isnans if this predicate is true.
1323 for (Value::use_iterator UI = V->use_begin(), E = V->use_end(); UI != E;++UI){
1324 Instruction *I = cast<Instruction>(*UI);
1325 if (I->getOpcode() != Instruction::Or) return false;
1326 if (I->getOperand(0) != V && !dyncastIsNan(I->getOperand(0))) return false;
1327 if (I->getOperand(1) != V && !dyncastIsNan(I->getOperand(1))) return false;
1333 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
1334 /// function, lowering any calls to unknown intrinsic functions into the
1335 /// equivalent LLVM code.
1337 void ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
1338 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
1339 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
1340 if (CallInst *CI = dyn_cast<CallInst>(I++))
1341 if (Function *F = CI->getCalledFunction())
1342 switch (F->getIntrinsicID()) {
1343 case Intrinsic::not_intrinsic:
1344 case Intrinsic::vastart:
1345 case Intrinsic::vacopy:
1346 case Intrinsic::vaend:
1347 case Intrinsic::returnaddress:
1348 case Intrinsic::frameaddress:
1349 // FIXME: should lower this ourselves
1350 // case Intrinsic::isunordered:
1351 // We directly implement these intrinsics
1353 case Intrinsic::readio: {
1354 // On PPC, memory operations are in-order. Lower this intrinsic
1355 // into a volatile load.
1356 Instruction *Before = CI->getPrev();
1357 LoadInst * LI = new LoadInst(CI->getOperand(1), "", true, CI);
1358 CI->replaceAllUsesWith(LI);
1359 BB->getInstList().erase(CI);
1362 case Intrinsic::writeio: {
1363 // On PPC, memory operations are in-order. Lower this intrinsic
1364 // into a volatile store.
1365 Instruction *Before = CI->getPrev();
1366 StoreInst *LI = new StoreInst(CI->getOperand(1),
1367 CI->getOperand(2), true, CI);
1368 CI->replaceAllUsesWith(LI);
1369 BB->getInstList().erase(CI);
1373 // All other intrinsic calls we must lower.
1374 Instruction *Before = CI->getPrev();
1375 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
1376 if (Before) { // Move iterator to instruction after call
1384 void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
1385 unsigned TmpReg1, TmpReg2, TmpReg3;
1387 case Intrinsic::vastart:
1388 // Get the address of the first vararg value...
1389 TmpReg1 = getReg(CI);
1390 addFrameReference(BuildMI(BB, PPC32::ADDI, 2, TmpReg1), VarArgsFrameIndex);
1393 case Intrinsic::vacopy:
1394 TmpReg1 = getReg(CI);
1395 TmpReg2 = getReg(CI.getOperand(1));
1396 BuildMI(BB, PPC32::OR, 2, TmpReg1).addReg(TmpReg2).addReg(TmpReg2);
1398 case Intrinsic::vaend: return;
1400 case Intrinsic::returnaddress:
1401 case Intrinsic::frameaddress:
1402 TmpReg1 = getReg(CI);
1403 if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
1404 if (ID == Intrinsic::returnaddress) {
1405 // Just load the return address
1406 addFrameReference(BuildMI(BB, PPC32::LWZ, 2, TmpReg1),
1407 ReturnAddressIndex);
1409 addFrameReference(BuildMI(BB, PPC32::ADDI, 2, TmpReg1),
1410 ReturnAddressIndex, -4, false);
1413 // Values other than zero are not implemented yet.
1414 BuildMI(BB, PPC32::ADDI, 2, TmpReg1).addReg(PPC32::R0).addImm(0);
1419 // This may be useful for supporting isunordered
1420 case Intrinsic::isnan:
1421 // If this is only used by 'isunordered' style comparisons, don't emit it.
1422 if (isOnlyUsedByUnorderedComparisons(&CI)) return;
1423 TmpReg1 = getReg(CI.getOperand(1));
1424 emitUCOM(BB, BB->end(), TmpReg1, TmpReg1);
1425 TmpReg2 = makeAnotherReg(Type::IntTy);
1426 BuildMI(BB, PPC32::MFCR, TmpReg2);
1427 TmpReg3 = getReg(CI);
1428 BuildMI(BB, PPC32::RLWINM, 4, TmpReg3).addReg(TmpReg2).addImm(4).addImm(31).addImm(31);
1432 default: assert(0 && "Error: unknown intrinsics should have been lowered!");
1436 /// visitSimpleBinary - Implement simple binary operators for integral types...
1437 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for
1440 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
1441 unsigned DestReg = getReg(B);
1442 MachineBasicBlock::iterator MI = BB->end();
1443 Value *Op0 = B.getOperand(0), *Op1 = B.getOperand(1);
1444 unsigned Class = getClassB(B.getType());
1446 emitSimpleBinaryOperation(BB, MI, Op0, Op1, OperatorClass, DestReg);
1449 /// emitBinaryFPOperation - This method handles emission of floating point
1450 /// Add (0), Sub (1), Mul (2), and Div (3) operations.
1451 void ISel::emitBinaryFPOperation(MachineBasicBlock *BB,
1452 MachineBasicBlock::iterator IP,
1453 Value *Op0, Value *Op1,
1454 unsigned OperatorClass, unsigned DestReg) {
1456 // Special case: op Reg, <const fp>
1457 if (ConstantFP *Op1C = dyn_cast<ConstantFP>(Op1)) {
1458 // Create a constant pool entry for this constant.
1459 MachineConstantPool *CP = F->getConstantPool();
1460 unsigned CPI = CP->getConstantPoolIndex(Op1C);
1461 const Type *Ty = Op1->getType();
1463 static const unsigned OpcodeTab[][4] = {
1464 { PPC32::FADDS, PPC32::FSUBS, PPC32::FMULS, PPC32::FDIVS }, // Float
1465 { PPC32::FADD, PPC32::FSUB, PPC32::FMUL, PPC32::FDIV }, // Double
1468 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
1469 unsigned TempReg = makeAnotherReg(Ty);
1470 unsigned LoadOpcode = Ty == Type::FloatTy ? PPC32::LFS : PPC32::LFD;
1471 addConstantPoolReference(BuildMI(*BB, IP, LoadOpcode, 2, TempReg), CPI);
1473 unsigned Opcode = OpcodeTab[Ty != Type::FloatTy][OperatorClass];
1474 unsigned Op0r = getReg(Op0, BB, IP);
1475 BuildMI(*BB, IP, Opcode, DestReg).addReg(Op0r).addReg(TempReg);
1479 // Special case: R1 = op <const fp>, R2
1480 if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op0))
1481 if (CFP->isExactlyValue(-0.0) && OperatorClass == 1) {
1483 unsigned op1Reg = getReg(Op1, BB, IP);
1484 BuildMI(*BB, IP, PPC32::FNEG, 1, DestReg).addReg(op1Reg);
1487 // R1 = op CST, R2 --> R1 = opr R2, CST
1489 // Create a constant pool entry for this constant.
1490 MachineConstantPool *CP = F->getConstantPool();
1491 unsigned CPI = CP->getConstantPoolIndex(CFP);
1492 const Type *Ty = CFP->getType();
1494 static const unsigned OpcodeTab[][4] = {
1495 { PPC32::FADDS, PPC32::FSUBS, PPC32::FMULS, PPC32::FDIVS }, // Float
1496 { PPC32::FADD, PPC32::FSUB, PPC32::FMUL, PPC32::FDIV }, // Double
1499 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
1500 unsigned TempReg = makeAnotherReg(Ty);
1501 unsigned LoadOpcode = Ty == Type::FloatTy ? PPC32::LFS : PPC32::LFD;
1502 addConstantPoolReference(BuildMI(*BB, IP, LoadOpcode, 2, TempReg), CPI);
1504 unsigned Opcode = OpcodeTab[Ty != Type::FloatTy][OperatorClass];
1505 unsigned Op1r = getReg(Op1, BB, IP);
1506 BuildMI(*BB, IP, Opcode, DestReg).addReg(TempReg).addReg(Op1r);
1511 static const unsigned OpcodeTab[4] = {
1512 PPC32::FADD, PPC32::FSUB, PPC32::FMUL, PPC32::FDIV
1515 unsigned Opcode = OpcodeTab[OperatorClass];
1516 unsigned Op0r = getReg(Op0, BB, IP);
1517 unsigned Op1r = getReg(Op1, BB, IP);
1518 BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
1521 /// emitSimpleBinaryOperation - Implement simple binary operators for integral
1522 /// types... OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for
1525 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
1526 /// and constant expression support.
1528 void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
1529 MachineBasicBlock::iterator IP,
1530 Value *Op0, Value *Op1,
1531 unsigned OperatorClass, unsigned DestReg) {
1532 unsigned Class = getClassB(Op0->getType());
1534 // Arithmetic and Bitwise operators
1535 static const unsigned OpcodeTab[5] = {
1536 PPC32::ADD, PPC32::SUB, PPC32::AND, PPC32::OR, PPC32::XOR
1538 // Otherwise, code generate the full operation with a constant.
1539 static const unsigned BottomTab[] = {
1540 PPC32::ADDC, PPC32::SUBC, PPC32::AND, PPC32::OR, PPC32::XOR
1542 static const unsigned TopTab[] = {
1543 PPC32::ADDE, PPC32::SUBFE, PPC32::AND, PPC32::OR, PPC32::XOR
1547 assert(OperatorClass < 2 && "No logical ops for FP!");
1548 emitBinaryFPOperation(MBB, IP, Op0, Op1, OperatorClass, DestReg);
1552 if (Op0->getType() == Type::BoolTy) {
1553 if (OperatorClass == 3)
1554 // If this is an or of two isnan's, emit an FP comparison directly instead
1555 // of or'ing two isnan's together.
1556 if (Value *LHS = dyncastIsNan(Op0))
1557 if (Value *RHS = dyncastIsNan(Op1)) {
1558 unsigned Op0Reg = getReg(RHS, MBB, IP), Op1Reg = getReg(LHS, MBB, IP);
1559 unsigned TmpReg = makeAnotherReg(Type::IntTy);
1560 emitUCOM(MBB, IP, Op0Reg, Op1Reg);
1561 BuildMI(*MBB, IP, PPC32::MFCR, TmpReg);
1562 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(TmpReg).addImm(4).addImm(31).addImm(31);
1567 // sub 0, X -> neg X
1568 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op0))
1569 if (OperatorClass == 1 && CI->isNullValue()) {
1570 unsigned op1Reg = getReg(Op1, MBB, IP);
1571 BuildMI(*MBB, IP, PPC32::NEG, 1, DestReg).addReg(op1Reg);
1573 if (Class == cLong) {
1574 unsigned zeroes = makeAnotherReg(Type::IntTy);
1575 unsigned overflow = makeAnotherReg(Type::IntTy);
1576 unsigned T = makeAnotherReg(Type::IntTy);
1577 BuildMI(*MBB, IP, PPC32::CNTLZW, 1, zeroes).addReg(op1Reg);
1578 BuildMI(*MBB, IP, PPC32::RLWINM, 4, overflow).addReg(zeroes).addImm(27).addImm(5).addImm(31);
1579 BuildMI(*MBB, IP, PPC32::ADD, 2, T).addReg(op1Reg+1).addReg(overflow);
1580 BuildMI(*MBB, IP, PPC32::NEG, 1, DestReg+1).addReg(T);
1585 // Special case: op Reg, <const int>
1586 if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
1587 unsigned Op0r = getReg(Op0, MBB, IP);
1589 // xor X, -1 -> not X
1590 if (OperatorClass == 4 && Op1C->isAllOnesValue()) {
1591 BuildMI(*MBB, IP, PPC32::NOR, 2, DestReg).addReg(Op0r).addReg(Op0r);
1592 if (Class == cLong) // Invert the top part too
1593 BuildMI(*MBB, IP, PPC32::NOR, 2, DestReg+1).addReg(Op0r+1).addReg(Op0r+1);
1597 unsigned Opcode = OpcodeTab[OperatorClass];
1598 unsigned Op1r = getReg(Op1, MBB, IP);
1600 if (Class != cLong) {
1601 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
1605 // If the constant is zero in the low 32-bits, just copy the low part
1606 // across and apply the normal 32-bit operation to the high parts. There
1607 // will be no carry or borrow into the top.
1608 if (cast<ConstantInt>(Op1C)->getRawValue() == 0) {
1609 if (OperatorClass != 2) // All but and...
1610 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(Op0r).addReg(Op0r);
1612 BuildMI(*MBB, IP, PPC32::ADDI, 2, DestReg).addReg(PPC32::R0).addImm(0);
1613 BuildMI(*MBB, IP, Opcode, 2, DestReg+1).addReg(Op0r+1).addReg(Op1r+1);
1617 // If this is a long value and the high or low bits have a special
1618 // property, emit some special cases.
1619 unsigned Op1h = cast<ConstantInt>(Op1C)->getRawValue() >> 32LL;
1621 // If this is a logical operation and the top 32-bits are zero, just
1622 // operate on the lower 32.
1623 if (Op1h == 0 && OperatorClass > 1) {
1624 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
1625 if (OperatorClass != 2) // All but and
1626 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg+1).addReg(Op0r+1).addReg(Op0r+1);
1628 BuildMI(*MBB, IP, PPC32::ADDI, 2, DestReg+1).addReg(PPC32::R0).addImm(0);
1632 // TODO: We could handle lots of other special cases here, such as AND'ing
1633 // with 0xFFFFFFFF00000000 -> noop, etc.
1635 BuildMI(*MBB, IP, BottomTab[OperatorClass], 2, DestReg).addReg(Op0r).addImm(Op1r);
1636 BuildMI(*MBB, IP, TopTab[OperatorClass], 2, DestReg+1).addReg(Op0r+1).addImm(Op1r+1);
1640 unsigned Op0r = getReg(Op0, MBB, IP);
1641 unsigned Op1r = getReg(Op1, MBB, IP);
1643 if (Class != cLong) {
1644 unsigned Opcode = OpcodeTab[OperatorClass];
1645 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
1647 BuildMI(*MBB, IP, BottomTab[OperatorClass], 2, DestReg).addReg(Op0r).addImm(Op1r);
1648 BuildMI(*MBB, IP, TopTab[OperatorClass], 2, DestReg+1).addReg(Op0r+1).addImm(Op1r+1);
1653 /// doMultiply - Emit appropriate instructions to multiply together the
1654 /// registers op0Reg and op1Reg, and put the result in DestReg. The type of the
1655 /// result should be given as DestTy.
1657 void ISel::doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
1658 unsigned DestReg, const Type *DestTy,
1659 unsigned op0Reg, unsigned op1Reg) {
1660 unsigned Class = getClass(DestTy);
1663 BuildMI(*MBB, MBBI, PPC32::MULHW, 2, DestReg+1).addReg(op0Reg+1).addReg(op1Reg+1);
1667 BuildMI(*MBB, MBBI, PPC32::MULLW, 2, DestReg).addReg(op0Reg).addReg(op1Reg);
1670 assert(0 && "doMultiply cannot operate on unknown type!");
1674 // ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
1675 // returns zero when the input is not exactly a power of two.
1676 static unsigned ExactLog2(unsigned Val) {
1677 if (Val == 0 || (Val & (Val-1))) return 0;
1687 /// doMultiplyConst - This function is specialized to efficiently codegen an 8,
1688 /// 16, or 32-bit integer multiply by a constant.
1689 void ISel::doMultiplyConst(MachineBasicBlock *MBB,
1690 MachineBasicBlock::iterator IP,
1691 unsigned DestReg, const Type *DestTy,
1692 unsigned op0Reg, unsigned ConstRHS) {
1693 unsigned Class = getClass(DestTy);
1694 // Handle special cases here.
1697 BuildMI(*MBB, IP, PPC32::ADDI, 2, DestReg).addReg(PPC32::R0).addImm(0);
1700 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(op0Reg).addReg(op0Reg);
1703 BuildMI(*MBB, IP, PPC32::ADD, 2,DestReg).addReg(op0Reg).addReg(op0Reg);
1707 // If the element size is exactly a power of 2, use a shift to get it.
1708 if (unsigned Shift = ExactLog2(ConstRHS)) {
1710 default: assert(0 && "Unknown class for this function!");
1714 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(op0Reg).addImm(Shift-1).addImm(0).addImm(31-Shift-1);
1719 // Most general case, emit a normal multiply...
1720 unsigned TmpReg1 = makeAnotherReg(Type::IntTy);
1721 unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
1722 BuildMI(*MBB, IP, PPC32::ADDIS, 2, TmpReg1).addReg(PPC32::R0).addImm(ConstRHS >> 16);
1723 BuildMI(*MBB, IP, PPC32::ORI, 2, TmpReg2).addReg(TmpReg1).addImm(ConstRHS);
1725 // Emit a MUL to multiply the register holding the index by
1726 // elementSize, putting the result in OffsetReg.
1727 doMultiply(MBB, IP, DestReg, DestTy, op0Reg, TmpReg2);
1730 void ISel::visitMul(BinaryOperator &I) {
1731 unsigned ResultReg = getReg(I);
1733 Value *Op0 = I.getOperand(0);
1734 Value *Op1 = I.getOperand(1);
1736 MachineBasicBlock::iterator IP = BB->end();
1737 emitMultiply(BB, IP, Op0, Op1, ResultReg);
1740 void ISel::emitMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
1741 Value *Op0, Value *Op1, unsigned DestReg) {
1742 MachineBasicBlock &BB = *MBB;
1743 TypeClass Class = getClass(Op0->getType());
1745 // Simple scalar multiply?
1746 unsigned Op0Reg = getReg(Op0, &BB, IP);
1751 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
1752 unsigned Val = (unsigned)CI->getRawValue(); // Isn't a 64-bit constant
1753 doMultiplyConst(&BB, IP, DestReg, Op0->getType(), Op0Reg, Val);
1755 unsigned Op1Reg = getReg(Op1, &BB, IP);
1756 doMultiply(&BB, IP, DestReg, Op1->getType(), Op0Reg, Op1Reg);
1760 emitBinaryFPOperation(MBB, IP, Op0, Op1, 2, DestReg);
1766 // Long value. We have to do things the hard way...
1767 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
1768 unsigned CLow = CI->getRawValue();
1769 unsigned CHi = CI->getRawValue() >> 32;
1772 // If the low part of the constant is all zeros, things are simple.
1773 BuildMI(BB, IP, PPC32::ADDI, 2, DestReg).addReg(PPC32::R0).addImm(0);
1774 doMultiplyConst(&BB, IP, DestReg+1, Type::UIntTy, Op0Reg, CHi);
1778 // Multiply the two low parts
1779 unsigned OverflowReg = 0;
1781 BuildMI(BB, IP, PPC32::OR, 2, DestReg).addReg(Op0Reg).addReg(Op0Reg);
1783 unsigned TmpRegL = makeAnotherReg(Type::UIntTy);
1784 unsigned Op1RegL = makeAnotherReg(Type::UIntTy);
1785 OverflowReg = makeAnotherReg(Type::UIntTy);
1786 BuildMI(BB, IP, PPC32::ADDIS, 2, TmpRegL).addReg(PPC32::R0).addImm(CLow >> 16);
1787 BuildMI(BB, IP, PPC32::ORI, 2, Op1RegL).addReg(TmpRegL).addImm(CLow);
1788 BuildMI(BB, IP, PPC32::MULLW, 2, DestReg).addReg(Op0Reg).addReg(Op1RegL);
1789 BuildMI(BB, IP, PPC32::MULHW, 2, OverflowReg).addReg(Op0Reg).addReg(Op1RegL);
1792 unsigned AHBLReg = makeAnotherReg(Type::UIntTy);
1793 doMultiplyConst(&BB, IP, AHBLReg, Type::UIntTy, Op0Reg+1, CLow);
1795 unsigned AHBLplusOverflowReg;
1797 AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
1798 BuildMI(BB, IP, PPC32::ADD, 2, // AH*BL+(AL*BL >> 32)
1799 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
1801 AHBLplusOverflowReg = AHBLReg;
1805 BuildMI(BB, IP, PPC32::OR, 2, DestReg+1).addReg(AHBLplusOverflowReg).addReg(AHBLplusOverflowReg);
1807 unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
1808 doMultiplyConst(&BB, IP, ALBHReg, Type::UIntTy, Op0Reg, CHi);
1810 BuildMI(BB, IP, PPC32::ADD, 2, // AL*BH + AH*BL + (AL*BL >> 32)
1811 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
1816 // General 64x64 multiply
1818 unsigned Op1Reg = getReg(Op1, &BB, IP);
1820 // Multiply the two low parts... capturing carry into EDX
1821 BuildMI(BB, IP, PPC32::MULLW, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg); // AL*BL
1823 unsigned OverflowReg = makeAnotherReg(Type::UIntTy);
1824 BuildMI(BB, IP, PPC32::MULHW, 2, OverflowReg).addReg(Op0Reg).addReg(Op1Reg); // AL*BL >> 32
1826 unsigned AHBLReg = makeAnotherReg(Type::UIntTy); // AH*BL
1827 BuildMI(BB, IP, PPC32::MULLW, 2, AHBLReg).addReg(Op0Reg+1).addReg(Op1Reg);
1829 unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
1830 BuildMI(BB, IP, PPC32::ADD, 2, // AH*BL+(AL*BL >> 32)
1831 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
1833 unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
1834 BuildMI(BB, IP, PPC32::MULLW, 2, ALBHReg).addReg(Op0Reg).addReg(Op1Reg+1);
1836 BuildMI(BB, IP, PPC32::ADD, 2, // AL*BH + AH*BL + (AL*BL >> 32)
1837 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
1841 /// visitDivRem - Handle division and remainder instructions... these
1842 /// instruction both require the same instructions to be generated, they just
1843 /// select the result from a different register. Note that both of these
1844 /// instructions work differently for signed and unsigned operands.
1846 void ISel::visitDivRem(BinaryOperator &I) {
1847 unsigned ResultReg = getReg(I);
1848 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
1850 MachineBasicBlock::iterator IP = BB->end();
1851 emitDivRemOperation(BB, IP, Op0, Op1, I.getOpcode() == Instruction::Div, ResultReg);
1854 void ISel::emitDivRemOperation(MachineBasicBlock *BB,
1855 MachineBasicBlock::iterator IP,
1856 Value *Op0, Value *Op1, bool isDiv,
1857 unsigned ResultReg) {
1858 const Type *Ty = Op0->getType();
1859 unsigned Class = getClass(Ty);
1861 case cFP: // Floating point divide
1863 emitBinaryFPOperation(BB, IP, Op0, Op1, 3, ResultReg);
1865 } else { // Floating point remainder...
1866 unsigned Op0Reg = getReg(Op0, BB, IP);
1867 unsigned Op1Reg = getReg(Op1, BB, IP);
1868 MachineInstr *TheCall =
1869 BuildMI(PPC32::CALLpcrel, 1).addExternalSymbol("fmod", true);
1870 std::vector<ValueRecord> Args;
1871 Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy));
1872 Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy));
1873 doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args);
1877 static const char *FnName[] =
1878 { "__moddi3", "__divdi3", "__umoddi3", "__udivdi3" };
1879 unsigned Op0Reg = getReg(Op0, BB, IP);
1880 unsigned Op1Reg = getReg(Op1, BB, IP);
1881 unsigned NameIdx = Ty->isUnsigned()*2 + isDiv;
1882 MachineInstr *TheCall =
1883 BuildMI(PPC32::CALLpcrel, 1).addExternalSymbol(FnName[NameIdx], true);
1885 std::vector<ValueRecord> Args;
1886 Args.push_back(ValueRecord(Op0Reg, Type::LongTy));
1887 Args.push_back(ValueRecord(Op1Reg, Type::LongTy));
1888 doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args);
1891 case cByte: case cShort: case cInt:
1892 break; // Small integrals, handled below...
1893 default: assert(0 && "Unknown class!");
1896 // Special case signed division by power of 2.
1898 if (ConstantSInt *CI = dyn_cast<ConstantSInt>(Op1)) {
1899 assert(Class != cLong && "This doesn't handle 64-bit divides!");
1900 int V = CI->getValue();
1902 if (V == 1) { // X /s 1 => X
1903 unsigned Op0Reg = getReg(Op0, BB, IP);
1904 BuildMI(*BB, IP, PPC32::OR, 2, ResultReg).addReg(Op0Reg).addReg(Op0Reg);
1908 if (V == -1) { // X /s -1 => -X
1909 unsigned Op0Reg = getReg(Op0, BB, IP);
1910 BuildMI(*BB, IP, PPC32::NEG, 1, ResultReg).addReg(Op0Reg);
1915 if (V < 0) { // Not a positive power of 2?
1917 isNeg = true; // Maybe it's a negative power of 2.
1919 if (unsigned Log = ExactLog2(V)) {
1921 unsigned Op0Reg = getReg(Op0, BB, IP);
1922 unsigned TmpReg = makeAnotherReg(Op0->getType());
1924 BuildMI(*BB, IP, PPC32::SRAWI, 2, TmpReg).addReg(Op0Reg).addImm(Log-1);
1926 BuildMI(*BB, IP, PPC32::OR, 2, TmpReg).addReg(Op0Reg).addReg(Op0Reg);
1928 unsigned TmpReg2 = makeAnotherReg(Op0->getType());
1929 BuildMI(*BB, IP, PPC32::RLWINM, 4, TmpReg2).addReg(TmpReg).addImm(Log).addImm(32-Log).addImm(31);
1931 unsigned TmpReg3 = makeAnotherReg(Op0->getType());
1932 BuildMI(*BB, IP, PPC32::ADD, 2, TmpReg3).addReg(Op0Reg).addReg(TmpReg2);
1934 unsigned TmpReg4 = isNeg ? makeAnotherReg(Op0->getType()) : ResultReg;
1935 BuildMI(*BB, IP, PPC32::SRAWI, 2, TmpReg4).addReg(Op0Reg).addImm(Log);
1938 BuildMI(*BB, IP, PPC32::NEG, 1, ResultReg).addReg(TmpReg4);
1943 unsigned Op0Reg = getReg(Op0, BB, IP);
1944 unsigned Op1Reg = getReg(Op1, BB, IP);
1947 if (Ty->isSigned()) {
1948 BuildMI(*BB, IP, PPC32::DIVW, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1950 BuildMI(*BB, IP, PPC32::DIVWU, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1952 } else { // Remainder
1953 unsigned TmpReg1 = makeAnotherReg(Op0->getType());
1954 unsigned TmpReg2 = makeAnotherReg(Op0->getType());
1956 if (Ty->isSigned()) {
1957 BuildMI(*BB, IP, PPC32::DIVW, 2, TmpReg1).addReg(Op0Reg).addReg(Op1Reg);
1959 BuildMI(*BB, IP, PPC32::DIVWU, 2, TmpReg1).addReg(Op0Reg).addReg(Op1Reg);
1961 BuildMI(*BB, IP, PPC32::MULLW, 2, TmpReg2).addReg(TmpReg1).addReg(Op1Reg);
1962 BuildMI(*BB, IP, PPC32::SUBF, 2, ResultReg).addReg(TmpReg2).addReg(Op0Reg);
1967 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
1968 /// for constant immediate shift values, and for constant immediate
1969 /// shift values equal to 1. Even the general case is sort of special,
1970 /// because the shift amount has to be in CL, not just any old register.
1972 void ISel::visitShiftInst(ShiftInst &I) {
1973 MachineBasicBlock::iterator IP = BB->end ();
1974 emitShiftOperation (BB, IP, I.getOperand (0), I.getOperand (1),
1975 I.getOpcode () == Instruction::Shl, I.getType (),
1979 /// emitShiftOperation - Common code shared between visitShiftInst and
1980 /// constant expression support.
1981 void ISel::emitShiftOperation(MachineBasicBlock *MBB,
1982 MachineBasicBlock::iterator IP,
1983 Value *Op, Value *ShiftAmount, bool isLeftShift,
1984 const Type *ResultTy, unsigned DestReg) {
1985 unsigned SrcReg = getReg (Op, MBB, IP);
1986 bool isSigned = ResultTy->isSigned ();
1987 unsigned Class = getClass (ResultTy);
1989 // Longs, as usual, are handled specially...
1990 if (Class == cLong) {
1991 // If we have a constant shift, we can generate much more efficient code
1992 // than otherwise...
1994 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
1995 unsigned Amount = CUI->getValue();
1998 // FIXME: RLWIMI is a use-and-def of DestReg+1, but that violates SSA
1999 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg+1).addReg(SrcReg+1).addImm(Amount).addImm(0).addImm(31-Amount);
2000 BuildMI(*MBB, IP, PPC32::RLWIMI, 5).addReg(DestReg+1).addReg(SrcReg).addImm(Amount).addImm(32-Amount).addImm(31);
2001 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg).addImm(Amount).addImm(0).addImm(31-Amount);
2003 // FIXME: RLWIMI is a use-and-def of DestReg, but that violates SSA
2004 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg).addImm(32-Amount).addImm(Amount).addImm(31);
2005 BuildMI(*MBB, IP, PPC32::RLWIMI, 5).addReg(DestReg).addReg(SrcReg+1).addImm(32-Amount).addImm(0).addImm(Amount-1);
2006 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg+1).addReg(SrcReg+1).addImm(32-Amount).addImm(Amount).addImm(31);
2008 } else { // Shifting more than 32 bits
2012 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg+1).addReg(SrcReg).addImm(Amount).addImm(0).addImm(31-Amount);
2014 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg+1).addReg(SrcReg).addReg(SrcReg);
2016 BuildMI(*MBB, IP, PPC32::ADDI, 2, DestReg).addReg(PPC32::R0).addImm(0);
2020 BuildMI(*MBB, IP, PPC32::SRAWI, 2, DestReg).addReg(SrcReg+1).addImm(Amount);
2022 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg+1).addImm(32-Amount).addImm(Amount).addImm(31);
2024 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg+1).addReg(SrcReg+1);
2026 BuildMI(*MBB, IP, PPC32::ADDI, 2, DestReg+1).addReg(PPC32::R0).addImm(0);
2030 unsigned TmpReg1 = makeAnotherReg(Type::IntTy);
2031 unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
2032 unsigned TmpReg3 = makeAnotherReg(Type::IntTy);
2033 unsigned TmpReg4 = makeAnotherReg(Type::IntTy);
2034 unsigned TmpReg5 = makeAnotherReg(Type::IntTy);
2035 unsigned TmpReg6 = makeAnotherReg(Type::IntTy);
2036 unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
2039 BuildMI(*MBB, IP, PPC32::SUBFIC, 2, TmpReg1).addReg(ShiftAmountReg).addImm(32);
2040 BuildMI(*MBB, IP, PPC32::SLW, 2, TmpReg2).addReg(SrcReg+1).addReg(ShiftAmountReg);
2041 BuildMI(*MBB, IP, PPC32::SRW, 2, TmpReg3).addReg(SrcReg).addReg(TmpReg1);
2042 BuildMI(*MBB, IP, PPC32::OR, 2, TmpReg4).addReg(TmpReg2).addReg(TmpReg3);
2043 BuildMI(*MBB, IP, PPC32::ADDI, 2, TmpReg5).addReg(ShiftAmountReg).addImm(-32);
2044 BuildMI(*MBB, IP, PPC32::SLW, 2, TmpReg6).addReg(SrcReg).addReg(TmpReg5);
2045 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg+1).addReg(TmpReg4).addReg(TmpReg6);
2046 BuildMI(*MBB, IP, PPC32::SLW, 2, DestReg).addReg(SrcReg).addReg(ShiftAmountReg);
2049 // FIXME: Unimplmented
2050 // Page C-3 of the PowerPC 32bit Programming Environments Manual
2052 BuildMI(*MBB, IP, PPC32::SUBFIC, 2, TmpReg1).addReg(ShiftAmountReg).addImm(32);
2053 BuildMI(*MBB, IP, PPC32::SRW, 2, TmpReg2).addReg(SrcReg).addReg(ShiftAmountReg);
2054 BuildMI(*MBB, IP, PPC32::SLW, 2, TmpReg3).addReg(SrcReg+1).addReg(TmpReg1);
2055 BuildMI(*MBB, IP, PPC32::OR, 2, TmpReg4).addReg(TmpReg2).addReg(TmpReg3);
2056 BuildMI(*MBB, IP, PPC32::ADDI, 2, TmpReg5).addReg(ShiftAmountReg).addImm(-32);
2057 BuildMI(*MBB, IP, PPC32::SRW, 2, TmpReg6).addReg(SrcReg+1).addReg(TmpReg5);
2058 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(TmpReg4).addReg(TmpReg6);
2059 BuildMI(*MBB, IP, PPC32::SRW, 2, DestReg+1).addReg(SrcReg+1).addReg(ShiftAmountReg);
2066 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
2067 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
2068 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
2069 unsigned Amount = CUI->getValue();
2072 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg).addImm(Amount).addImm(0).addImm(31-Amount);
2075 BuildMI(*MBB, IP, PPC32::SRAWI, 2, DestReg).addReg(SrcReg).addImm(Amount);
2077 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg).addImm(32-Amount).addImm(Amount).addImm(31);
2080 } else { // The shift amount is non-constant.
2081 unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
2084 BuildMI(*MBB, IP, PPC32::SLW, 2, DestReg).addReg(SrcReg).addReg(ShiftAmountReg);
2086 BuildMI(*MBB, IP, isSigned ? PPC32::SRAW : PPC32::SRW, 2, DestReg).addReg(SrcReg).addReg(ShiftAmountReg);
2092 /// visitLoadInst - Implement LLVM load instructions
2094 void ISel::visitLoadInst(LoadInst &I) {
2095 static const unsigned Opcodes[] = { PPC32::LBZ, PPC32::LHZ, PPC32::LWZ, PPC32::LFS };
2096 unsigned Class = getClassB(I.getType());
2097 unsigned Opcode = Opcodes[Class];
2098 if (I.getType() == Type::DoubleTy) Opcode = PPC32::LFD;
2100 unsigned DestReg = getReg(I);
2102 if (AllocaInst *AI = dyn_castFixedAlloca(I.getOperand(0))) {
2103 unsigned FI = getFixedSizedAllocaFI(AI);
2104 if (Class == cLong) {
2105 addFrameReference(BuildMI(BB, PPC32::LWZ, 2, DestReg), FI);
2106 addFrameReference(BuildMI(BB, PPC32::LWZ, 2, DestReg+1), FI, 4);
2108 addFrameReference(BuildMI(BB, Opcode, 2, DestReg), FI);
2111 unsigned SrcAddrReg = getReg(I.getOperand(0));
2113 if (Class == cLong) {
2114 BuildMI(BB, PPC32::LWZ, 2, DestReg).addImm(0).addReg(SrcAddrReg);
2115 BuildMI(BB, PPC32::LWZ, 2, DestReg+1).addImm(4).addReg(SrcAddrReg);
2117 BuildMI(BB, Opcode, 2, DestReg).addImm(0).addReg(SrcAddrReg);
2122 /// visitStoreInst - Implement LLVM store instructions
2124 void ISel::visitStoreInst(StoreInst &I) {
2125 unsigned ValReg = getReg(I.getOperand(0));
2126 unsigned AddressReg = getReg(I.getOperand(1));
2128 const Type *ValTy = I.getOperand(0)->getType();
2129 unsigned Class = getClassB(ValTy);
2131 if (Class == cLong) {
2132 BuildMI(BB, PPC32::STW, 3).addReg(ValReg).addImm(0).addReg(AddressReg);
2133 BuildMI(BB, PPC32::STW, 3).addReg(ValReg+1).addImm(4).addReg(AddressReg);
2137 static const unsigned Opcodes[] = {
2138 PPC32::STB, PPC32::STH, PPC32::STW, PPC32::STFS
2140 unsigned Opcode = Opcodes[Class];
2141 if (ValTy == Type::DoubleTy) Opcode = PPC32::STFD;
2142 BuildMI(BB, Opcode, 3).addReg(ValReg).addImm(0).addReg(AddressReg);
2146 /// visitCastInst - Here we have various kinds of copying with or without sign
2147 /// extension going on.
2149 void ISel::visitCastInst(CastInst &CI) {
2150 Value *Op = CI.getOperand(0);
2152 unsigned SrcClass = getClassB(Op->getType());
2153 unsigned DestClass = getClassB(CI.getType());
2154 // Noop casts are not emitted: getReg will return the source operand as the
2155 // register to use for any uses of the noop cast.
2156 if (DestClass == SrcClass)
2159 // If this is a cast from a 32-bit integer to a Long type, and the only uses
2160 // of the case are GEP instructions, then the cast does not need to be
2161 // generated explicitly, it will be folded into the GEP.
2162 if (DestClass == cLong && SrcClass == cInt) {
2163 bool AllUsesAreGEPs = true;
2164 for (Value::use_iterator I = CI.use_begin(), E = CI.use_end(); I != E; ++I)
2165 if (!isa<GetElementPtrInst>(*I)) {
2166 AllUsesAreGEPs = false;
2170 // No need to codegen this cast if all users are getelementptr instrs...
2171 if (AllUsesAreGEPs) return;
2174 unsigned DestReg = getReg(CI);
2175 MachineBasicBlock::iterator MI = BB->end();
2176 emitCastOperation(BB, MI, Op, CI.getType(), DestReg);
2179 /// emitCastOperation - Common code shared between visitCastInst and constant
2180 /// expression cast support.
2182 void ISel::emitCastOperation(MachineBasicBlock *BB,
2183 MachineBasicBlock::iterator IP,
2184 Value *Src, const Type *DestTy,
2186 const Type *SrcTy = Src->getType();
2187 unsigned SrcClass = getClassB(SrcTy);
2188 unsigned DestClass = getClassB(DestTy);
2189 unsigned SrcReg = getReg(Src, BB, IP);
2191 // Implement casts to bool by using compare on the operand followed by set if
2192 // not zero on the result.
2193 if (DestTy == Type::BoolTy) {
2198 unsigned TmpReg = makeAnotherReg(Type::IntTy);
2199 BuildMI(*BB, IP, PPC32::ADDIC, 2, TmpReg).addReg(SrcReg).addImm(-1);
2200 BuildMI(*BB, IP, PPC32::SUBFE, 2, DestReg).addReg(TmpReg).addReg(SrcReg);
2204 unsigned TmpReg = makeAnotherReg(Type::IntTy);
2205 unsigned SrcReg2 = makeAnotherReg(Type::IntTy);
2206 BuildMI(*BB, IP, PPC32::OR, 2, SrcReg2).addReg(SrcReg).addReg(SrcReg+1);
2207 BuildMI(*BB, IP, PPC32::ADDIC, 2, TmpReg).addReg(SrcReg2).addImm(-1);
2208 BuildMI(*BB, IP, PPC32::SUBFE, 2, DestReg).addReg(TmpReg).addReg(SrcReg2);
2227 // Implement casts between values of the same type class (as determined by
2228 // getClass) by using a register-to-register move.
2229 if (SrcClass == DestClass) {
2230 if (SrcClass <= cInt) {
2231 BuildMI(*BB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2232 } else if (SrcClass == cFP && SrcTy == DestTy) {
2233 BuildMI(*BB, IP, PPC32::FMR, 1, DestReg).addReg(SrcReg);
2234 } else if (SrcClass == cFP) {
2235 if (SrcTy == Type::FloatTy) { // float -> double
2236 assert(DestTy == Type::DoubleTy && "Unknown cFP member!");
2237 BuildMI(*BB, IP, PPC32::FMR, 1, DestReg).addReg(SrcReg);
2238 } else { // double -> float
2239 assert(SrcTy == Type::DoubleTy && DestTy == Type::FloatTy &&
2240 "Unknown cFP member!");
2241 BuildMI(*BB, IP, PPC32::FRSP, 1, DestReg).addReg(SrcReg);
2243 } else if (SrcClass == cLong) {
2244 BuildMI(*BB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2245 BuildMI(*BB, IP, PPC32::OR, 2, DestReg+1).addReg(SrcReg+1).addReg(SrcReg+1);
2247 assert(0 && "Cannot handle this type of cast instruction!");
2253 // Handle cast of SMALLER int to LARGER int using a move with sign extension
2254 // or zero extension, depending on whether the source type was signed.
2255 if (SrcClass <= cInt && (DestClass <= cInt || DestClass == cLong) &&
2256 SrcClass < DestClass) {
2257 bool isLong = DestClass == cLong;
2258 if (isLong) DestClass = cInt;
2260 bool isUnsigned = SrcTy->isUnsigned() || SrcTy == Type::BoolTy;
2261 if (SrcClass < cInt) {
2263 unsigned shift = (SrcClass == cByte) ? 24 : 16;
2264 BuildMI(*BB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg).addZImm(0).addImm(shift).addImm(31);
2266 BuildMI(*BB, IP, (SrcClass == cByte) ? PPC32::EXTSB : PPC32::EXTSH, 1, DestReg).addReg(SrcReg);
2269 BuildMI(*BB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2272 if (isLong) { // Handle upper 32 bits as appropriate...
2273 if (isUnsigned) // Zero out top bits...
2274 BuildMI(*BB, IP, PPC32::ADDI, 2, DestReg+1).addReg(PPC32::R0).addImm(0);
2275 else // Sign extend bottom half...
2276 BuildMI(*BB, IP, PPC32::SRAWI, 2, DestReg+1).addReg(DestReg).addImm(31);
2281 // Special case long -> int ...
2282 if (SrcClass == cLong && DestClass == cInt) {
2283 BuildMI(*BB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2287 // Handle cast of LARGER int to SMALLER int with a clear or sign extend
2288 if ((SrcClass <= cInt || SrcClass == cLong) && DestClass <= cInt
2289 && SrcClass > DestClass) {
2290 bool isUnsigned = SrcTy->isUnsigned() || SrcTy == Type::BoolTy;
2292 unsigned shift = (SrcClass == cByte) ? 24 : 16;
2293 BuildMI(*BB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg).addZImm(0).addImm(shift).addImm(31);
2295 BuildMI(*BB, IP, (SrcClass == cByte) ? PPC32::EXTSB : PPC32::EXTSH, 1, DestReg).addReg(SrcReg);
2300 // Handle casts from integer to floating point now...
2301 if (DestClass == cFP) {
2303 // Emit a library call for long to float conversion
2304 if (SrcClass == cLong) {
2305 std::vector<ValueRecord> Args;
2306 Args.push_back(ValueRecord(SrcReg, SrcTy));
2307 MachineInstr *TheCall = BuildMI(PPC32::CALLpcrel, 1).addExternalSymbol("__floatdidf", true);
2308 doCall(ValueRecord(DestReg, DestTy), TheCall, Args);
2312 unsigned TmpReg = makeAnotherReg(Type::IntTy);
2313 switch (SrcTy->getTypeID()) {
2314 case Type::BoolTyID:
2315 case Type::SByteTyID:
2316 BuildMI(*BB, IP, PPC32::EXTSB, 1, TmpReg).addReg(SrcReg);
2318 case Type::UByteTyID:
2319 BuildMI(*BB, IP, PPC32::RLWINM, 4, TmpReg).addReg(SrcReg).addZImm(0).addImm(24).addImm(31);
2321 case Type::ShortTyID:
2322 BuildMI(*BB, IP, PPC32::EXTSB, 1, TmpReg).addReg(SrcReg);
2324 case Type::UShortTyID:
2325 BuildMI(*BB, IP, PPC32::RLWINM, 4, TmpReg).addReg(SrcReg).addZImm(0).addImm(16).addImm(31);
2328 BuildMI(*BB, IP, PPC32::OR, 2, TmpReg).addReg(SrcReg).addReg(SrcReg);
2330 case Type::UIntTyID:
2331 BuildMI(*BB, IP, PPC32::OR, 2, TmpReg).addReg(SrcReg).addReg(SrcReg);
2333 default: // No promotion needed...
2339 // Spill the integer to memory and reload it from there.
2340 // Also spill room for a special conversion constant
2341 int ConstantFrameIndex =
2342 F->getFrameInfo()->CreateStackObject(Type::DoubleTy, TM.getTargetData());
2344 F->getFrameInfo()->CreateStackObject(Type::DoubleTy, TM.getTargetData());
2346 unsigned constantHi = makeAnotherReg(Type::IntTy);
2347 unsigned constantLo = makeAnotherReg(Type::IntTy);
2348 unsigned ConstF = makeAnotherReg(Type::DoubleTy);
2349 unsigned TempF = makeAnotherReg(Type::DoubleTy);
2351 if (!SrcTy->isSigned()) {
2352 BuildMI(*BB, IP, PPC32::ADDIS, 2, constantHi).addReg(PPC32::R0).addImm(0x4330);
2353 BuildMI(*BB, IP, PPC32::ADDI, 2, constantLo).addReg(PPC32::R0).addImm(0);
2354 addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantHi), ConstantFrameIndex);
2355 addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantLo), ConstantFrameIndex, 4);
2356 addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantHi), ValueFrameIdx);
2357 addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(SrcReg), ValueFrameIdx, 4);
2358 addFrameReference(BuildMI(*BB, IP, PPC32::LFD, 2, ConstF), ConstantFrameIndex);
2359 addFrameReference(BuildMI(*BB, IP, PPC32::LFD, 2, TempF), ValueFrameIdx);
2360 BuildMI(*BB, IP, PPC32::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF);
2362 unsigned TempLo = makeAnotherReg(Type::IntTy);
2363 BuildMI(*BB, IP, PPC32::ADDIS, 2, constantHi).addReg(PPC32::R0).addImm(0x4330);
2364 BuildMI(*BB, IP, PPC32::ADDIS, 2, constantLo).addReg(PPC32::R0).addImm(0x8000);
2365 addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantHi), ConstantFrameIndex);
2366 addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantLo), ConstantFrameIndex, 4);
2367 addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantHi), ValueFrameIdx);
2368 BuildMI(*BB, IP, PPC32::XORIS, 2, TempLo).addReg(SrcReg).addImm(0x8000);
2369 addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(TempLo), ValueFrameIdx, 4);
2370 addFrameReference(BuildMI(*BB, IP, PPC32::LFD, 2, ConstF), ConstantFrameIndex);
2371 addFrameReference(BuildMI(*BB, IP, PPC32::LFD, 2, TempF), ValueFrameIdx);
2372 BuildMI(*BB, IP, PPC32::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF);
2377 // Handle casts from floating point to integer now...
2378 if (SrcClass == cFP) {
2380 // emit library call
2381 if (DestClass == cLong) {
2382 std::vector<ValueRecord> Args;
2383 Args.push_back(ValueRecord(SrcReg, SrcTy));
2384 MachineInstr *TheCall = BuildMI(PPC32::CALLpcrel, 1).addExternalSymbol("__fixdfdi", true);
2385 doCall(ValueRecord(DestReg, DestTy), TheCall, Args);
2390 F->getFrameInfo()->CreateStackObject(Type::DoubleTy, TM.getTargetData());
2392 // load into 32 bit value, and then truncate as necessary
2393 // FIXME: This is wrong for unsigned dest types
2394 //if (DestTy->isSigned()) {
2395 unsigned TempReg = makeAnotherReg(Type::DoubleTy);
2396 BuildMI(*BB, IP, PPC32::FCTIWZ, 1, TempReg).addReg(SrcReg);
2397 addFrameReference(BuildMI(*BB, IP, PPC32::STFD, 3).addReg(TempReg), ValueFrameIdx);
2398 addFrameReference(BuildMI(*BB, IP, PPC32::LWZ, 2, DestReg), ValueFrameIdx+4);
2402 // FIXME: Truncate return value
2406 // Anything we haven't handled already, we can't (yet) handle at all.
2407 assert(0 && "Unhandled cast instruction!");
2411 /// visitVANextInst - Implement the va_next instruction...
2413 void ISel::visitVANextInst(VANextInst &I) {
2414 unsigned VAList = getReg(I.getOperand(0));
2415 unsigned DestReg = getReg(I);
2418 switch (I.getArgType()->getTypeID()) {
2421 assert(0 && "Error: bad type for va_next instruction!");
2423 case Type::PointerTyID:
2424 case Type::UIntTyID:
2428 case Type::ULongTyID:
2429 case Type::LongTyID:
2430 case Type::DoubleTyID:
2435 // Increment the VAList pointer...
2436 BuildMI(BB, PPC32::ADDI, 2, DestReg).addReg(VAList).addImm(Size);
2439 void ISel::visitVAArgInst(VAArgInst &I) {
2440 unsigned VAList = getReg(I.getOperand(0));
2441 unsigned DestReg = getReg(I);
2443 switch (I.getType()->getTypeID()) {
2446 assert(0 && "Error: bad type for va_next instruction!");
2448 case Type::PointerTyID:
2449 case Type::UIntTyID:
2451 BuildMI(BB, PPC32::LWZ, 2, DestReg).addImm(0).addReg(VAList);
2453 case Type::ULongTyID:
2454 case Type::LongTyID:
2455 BuildMI(BB, PPC32::LWZ, 2, DestReg).addImm(0).addReg(VAList);
2456 BuildMI(BB, PPC32::LWZ, 2, DestReg+1).addImm(4).addReg(VAList);
2458 case Type::DoubleTyID:
2459 BuildMI(BB, PPC32::LFD, 2, DestReg).addImm(0).addReg(VAList);
2464 /// visitGetElementPtrInst - instruction-select GEP instructions
2466 void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
2467 unsigned outputReg = getReg(I);
2468 emitGEPOperation(BB, BB->end(), I.getOperand(0),I.op_begin()+1, I.op_end(), outputReg);
2471 void ISel::emitGEPOperation(MachineBasicBlock *MBB,
2472 MachineBasicBlock::iterator IP,
2473 Value *Src, User::op_iterator IdxBegin,
2474 User::op_iterator IdxEnd, unsigned TargetReg) {
2475 const TargetData &TD = TM.getTargetData();
2476 if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(Src))
2477 Src = CPR->getValue();
2479 std::vector<Value*> GEPOps;
2480 GEPOps.resize(IdxEnd-IdxBegin+1);
2482 std::copy(IdxBegin, IdxEnd, GEPOps.begin()+1);
2484 std::vector<const Type*> GEPTypes;
2485 GEPTypes.assign(gep_type_begin(Src->getType(), IdxBegin, IdxEnd),
2486 gep_type_end(Src->getType(), IdxBegin, IdxEnd));
2488 // Keep emitting instructions until we consume the entire GEP instruction.
2489 while (!GEPOps.empty()) {
2490 // It's an array or pointer access: [ArraySize x ElementType].
2491 const SequentialType *SqTy = cast<SequentialType>(GEPTypes.back());
2492 Value *idx = GEPOps.back();
2493 GEPOps.pop_back(); // Consume a GEP operand
2494 GEPTypes.pop_back();
2496 // Many GEP instructions use a [cast (int/uint) to LongTy] as their
2497 // operand on X86. Handle this case directly now...
2498 if (CastInst *CI = dyn_cast<CastInst>(idx))
2499 if (CI->getOperand(0)->getType() == Type::IntTy ||
2500 CI->getOperand(0)->getType() == Type::UIntTy)
2501 idx = CI->getOperand(0);
2503 // We want to add BaseReg to(idxReg * sizeof ElementType). First, we
2504 // must find the size of the pointed-to type (Not coincidentally, the next
2505 // type is the type of the elements in the array).
2506 const Type *ElTy = SqTy->getElementType();
2507 unsigned elementSize = TD.getTypeSize(ElTy);
2509 if (elementSize == 1) {
2510 // If the element size is 1, we don't have to multiply, just add
2511 unsigned idxReg = getReg(idx, MBB, IP);
2512 unsigned Reg = makeAnotherReg(Type::UIntTy);
2513 BuildMI(*MBB, IP, PPC32::ADD, 2,TargetReg).addReg(Reg).addReg(idxReg);
2514 --IP; // Insert the next instruction before this one.
2515 TargetReg = Reg; // Codegen the rest of the GEP into this
2517 unsigned idxReg = getReg(idx, MBB, IP);
2518 unsigned OffsetReg = makeAnotherReg(Type::UIntTy);
2520 // Make sure we can back the iterator up to point to the first
2521 // instruction emitted.
2522 MachineBasicBlock::iterator BeforeIt = IP;
2523 if (IP == MBB->begin())
2524 BeforeIt = MBB->end();
2527 doMultiplyConst(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSize);
2529 // Emit an ADD to add OffsetReg to the basePtr.
2530 unsigned Reg = makeAnotherReg(Type::UIntTy);
2531 BuildMI(*MBB, IP, PPC32::ADD, 2, TargetReg).addReg(Reg).addReg(OffsetReg);
2533 // Step to the first instruction of the multiply.
2534 if (BeforeIt == MBB->end())
2539 TargetReg = Reg; // Codegen the rest of the GEP into this
2544 /// visitAllocaInst - If this is a fixed size alloca, allocate space from the
2545 /// frame manager, otherwise do it the hard way.
2547 void ISel::visitAllocaInst(AllocaInst &I) {
2548 // If this is a fixed size alloca in the entry block for the function, we
2549 // statically stack allocate the space, so we don't need to do anything here.
2551 if (dyn_castFixedAlloca(&I)) return;
2553 // Find the data size of the alloca inst's getAllocatedType.
2554 const Type *Ty = I.getAllocatedType();
2555 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
2557 // Create a register to hold the temporary result of multiplying the type size
2558 // constant by the variable amount.
2559 unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
2560 unsigned SrcReg1 = getReg(I.getArraySize());
2562 // TotalSizeReg = mul <numelements>, <TypeSize>
2563 MachineBasicBlock::iterator MBBI = BB->end();
2564 doMultiplyConst(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, TySize);
2566 // AddedSize = add <TotalSizeReg>, 15
2567 unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy);
2568 BuildMI(BB, PPC32::ADD, 2, AddedSizeReg).addReg(TotalSizeReg).addImm(15);
2570 // AlignedSize = and <AddedSize>, ~15
2571 unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
2572 BuildMI(BB, PPC32::RLWNM, 4, AlignedSize).addReg(AddedSizeReg).addImm(0).addImm(0).addImm(27);
2574 // Subtract size from stack pointer, thereby allocating some space.
2575 BuildMI(BB, PPC32::SUB, 2, PPC32::R1).addReg(PPC32::R1).addReg(AlignedSize);
2577 // Put a pointer to the space into the result register, by copying
2578 // the stack pointer.
2579 BuildMI(BB, PPC32::OR, 2, getReg(I)).addReg(PPC32::R1).addReg(PPC32::R1);
2581 // Inform the Frame Information that we have just allocated a variable-sized
2583 F->getFrameInfo()->CreateVariableSizedObject();
2586 /// visitMallocInst - Malloc instructions are code generated into direct calls
2587 /// to the library malloc.
2589 void ISel::visitMallocInst(MallocInst &I) {
2590 unsigned AllocSize = TM.getTargetData().getTypeSize(I.getAllocatedType());
2593 if (ConstantUInt *C = dyn_cast<ConstantUInt>(I.getOperand(0))) {
2594 Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize));
2596 Arg = makeAnotherReg(Type::UIntTy);
2597 unsigned Op0Reg = getReg(I.getOperand(0));
2598 MachineBasicBlock::iterator MBBI = BB->end();
2599 doMultiplyConst(BB, MBBI, Arg, Type::UIntTy, Op0Reg, AllocSize);
2602 std::vector<ValueRecord> Args;
2603 Args.push_back(ValueRecord(Arg, Type::UIntTy));
2604 MachineInstr *TheCall = BuildMI(PPC32::CALLpcrel, 1).addExternalSymbol("malloc", true);
2605 doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args);
2609 /// visitFreeInst - Free instructions are code gen'd to call the free libc
2612 void ISel::visitFreeInst(FreeInst &I) {
2613 std::vector<ValueRecord> Args;
2614 Args.push_back(ValueRecord(I.getOperand(0)));
2615 MachineInstr *TheCall = BuildMI(PPC32::CALLpcrel, 1).addExternalSymbol("free", true);
2616 doCall(ValueRecord(0, Type::VoidTy), TheCall, Args);
2619 /// createPPC32SimpleInstructionSelector - This pass converts an LLVM function
2620 /// into a machine code representation is a very simple peep-hole fashion. The
2621 /// generated code sucks but the implementation is nice and simple.
2623 FunctionPass *llvm::createPPCSimpleInstructionSelector(TargetMachine &TM) {
2624 return new ISel(TM);