1 //===- PPC32RegisterInfo.td - The PowerPC32 Register File --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 include "PowerPCRegisterInfo.td"
16 // Allocate volatiles first
17 // then nonvolatiles in reverse order since stmw/lmw save from rN to r31
18 def GPRC : RegisterClass<i32, 32,
19 [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
20 R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
21 R16, R15, R14, R13, R31, R0, R1, LR]>
24 iterator allocation_order_begin(MachineFunction &MF) const {
25 return begin() + (AIX ? 1 : 0);
27 iterator allocation_order_end(MachineFunction &MF) const {
36 def FPRC : RegisterClass<f64, 64, [F0, F1, F2, F3, F4, F5, F6, F7,
37 F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
38 F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
40 def CRRC : RegisterClass<i32, 32, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7]>;