1 //===-- PPC64ISelSimple.cpp - A simple instruction selector for PowerPC ---===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "isel"
12 #include "PowerPCInstrBuilder.h"
13 #include "PowerPCInstrInfo.h"
14 #include "PPC64TargetMachine.h"
15 #include "llvm/Constants.h"
16 #include "llvm/DerivedTypes.h"
17 #include "llvm/Function.h"
18 #include "llvm/Instructions.h"
19 #include "llvm/Pass.h"
20 #include "llvm/CodeGen/IntrinsicLowering.h"
21 #include "llvm/CodeGen/MachineConstantPool.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/SSARegMap.h"
25 #include "llvm/Target/MRegisterInfo.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Support/GetElementPtrTypeIterator.h"
28 #include "llvm/Support/InstVisitor.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/ADT/Statistic.h"
35 Statistic<> GEPFolds("ppc64-codegen", "Number of GEPs folded");
37 /// TypeClass - Used by the PowerPC backend to group LLVM types by their basic
38 /// PPC Representation.
41 cByte, cShort, cInt, cFP32, cFP64, cLong
45 /// getClass - Turn a primitive type into a "class" number which is based on the
46 /// size of the type, and whether or not it is floating point.
48 static inline TypeClass getClass(const Type *Ty) {
49 switch (Ty->getTypeID()) {
51 case Type::UByteTyID: return cByte; // Byte operands are class #0
53 case Type::UShortTyID: return cShort; // Short operands are class #1
55 case Type::UIntTyID: return cInt; // Ints are class #2
57 case Type::FloatTyID: return cFP32; // Single float is #3
58 case Type::DoubleTyID: return cFP64; // Double Point is #4
60 case Type::PointerTyID:
62 case Type::ULongTyID: return cLong; // Longs and pointers are class #5
64 assert(0 && "Invalid type to getClass!");
65 return cByte; // not reached
69 // getClassB - Just like getClass, but treat boolean values as ints.
70 static inline TypeClass getClassB(const Type *Ty) {
71 if (Ty == Type::BoolTy) return cInt;
76 struct PPC64ISel : public FunctionPass, InstVisitor<PPC64ISel> {
77 PPC64TargetMachine &TM;
78 MachineFunction *F; // The function we are compiling into
79 MachineBasicBlock *BB; // The current MBB we are compiling
80 int VarArgsFrameIndex; // FrameIndex for start of varargs area
82 std::map<Value*, unsigned> RegMap; // Mapping between Values and SSA Regs
84 // External functions used in the Module
85 Function *fmodfFn, *fmodFn, *__cmpdi2Fn, *__fixsfdiFn, *__fixdfdiFn,
86 *__fixunssfdiFn, *__fixunsdfdiFn, *mallocFn, *freeFn;
88 // MBBMap - Mapping between LLVM BB -> Machine BB
89 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
91 // AllocaMap - Mapping from fixed sized alloca instructions to the
92 // FrameIndex for the alloca.
93 std::map<AllocaInst*, unsigned> AllocaMap;
95 // Target configuration data
96 const unsigned ParameterSaveAreaOffset, MaxArgumentStackSpace;
98 PPC64ISel(TargetMachine &tm):TM(reinterpret_cast<PPC64TargetMachine&>(tm)),
99 F(0), BB(0), ParameterSaveAreaOffset(24), MaxArgumentStackSpace(32) {}
101 bool doInitialization(Module &M) {
102 // Add external functions that we may call
103 Type *i = Type::IntTy;
104 Type *d = Type::DoubleTy;
105 Type *f = Type::FloatTy;
106 Type *l = Type::LongTy;
107 Type *ul = Type::ULongTy;
108 Type *voidPtr = PointerType::get(Type::SByteTy);
109 // float fmodf(float, float);
110 fmodfFn = M.getOrInsertFunction("fmodf", f, f, f, 0);
111 // double fmod(double, double);
112 fmodFn = M.getOrInsertFunction("fmod", d, d, d, 0);
113 // int __cmpdi2(long, long);
114 __cmpdi2Fn = M.getOrInsertFunction("__cmpdi2", i, l, l, 0);
115 // long __fixsfdi(float)
116 __fixsfdiFn = M.getOrInsertFunction("__fixsfdi", l, f, 0);
117 // long __fixdfdi(double)
118 __fixdfdiFn = M.getOrInsertFunction("__fixdfdi", l, d, 0);
119 // unsigned long __fixunssfdi(float)
120 __fixunssfdiFn = M.getOrInsertFunction("__fixunssfdi", ul, f, 0);
121 // unsigned long __fixunsdfdi(double)
122 __fixunsdfdiFn = M.getOrInsertFunction("__fixunsdfdi", ul, d, 0);
123 // void* malloc(size_t)
124 mallocFn = M.getOrInsertFunction("malloc", voidPtr, Type::UIntTy, 0);
126 freeFn = M.getOrInsertFunction("free", Type::VoidTy, voidPtr, 0);
130 /// runOnFunction - Top level implementation of instruction selection for
131 /// the entire function.
133 bool runOnFunction(Function &Fn) {
134 // First pass over the function, lower any unknown intrinsic functions
135 // with the IntrinsicLowering class.
136 LowerUnknownIntrinsicFunctionCalls(Fn);
138 F = &MachineFunction::construct(&Fn, TM);
140 // Create all of the machine basic blocks for the function...
141 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
142 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
146 // Copy incoming arguments off of the stack...
147 LoadArgumentsToVirtualRegs(Fn);
149 // Instruction select everything except PHI nodes
152 // Select the PHI nodes
159 // We always build a machine code representation for the function
163 virtual const char *getPassName() const {
164 return "PowerPC Simple Instruction Selection";
167 /// visitBasicBlock - This method is called when we are visiting a new basic
168 /// block. This simply creates a new MachineBasicBlock to emit code into
169 /// and adds it to the current MachineFunction. Subsequent visit* for
170 /// instructions will be invoked for all instructions in the basic block.
172 void visitBasicBlock(BasicBlock &LLVM_BB) {
173 BB = MBBMap[&LLVM_BB];
176 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
177 /// function, lowering any calls to unknown intrinsic functions into the
178 /// equivalent LLVM code.
180 void LowerUnknownIntrinsicFunctionCalls(Function &F);
182 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function
183 /// from the stack into virtual registers.
185 void LoadArgumentsToVirtualRegs(Function &F);
187 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
188 /// because we have to generate our sources into the source basic blocks,
189 /// not the current one.
191 void SelectPHINodes();
193 // Visitation methods for various instructions. These methods simply emit
194 // fixed PowerPC code for each instruction.
196 // Control flow operators
197 void visitReturnInst(ReturnInst &RI);
198 void visitBranchInst(BranchInst &BI);
204 ValueRecord(unsigned R, const Type *T) : Val(0), Reg(R), Ty(T) {}
205 ValueRecord(Value *V) : Val(V), Reg(0), Ty(V->getType()) {}
208 // This struct is for recording the necessary operations to emit the GEP
209 struct CollapsedGepOp {
213 CollapsedGepOp(bool mul, Value *i, ConstantSInt *s) :
214 isMul(mul), index(i), size(s) {}
217 void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
218 const std::vector<ValueRecord> &Args, bool isVarArg);
219 void visitCallInst(CallInst &I);
220 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &I);
222 // Arithmetic operators
223 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
224 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
225 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
226 void visitMul(BinaryOperator &B);
228 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
229 void visitRem(BinaryOperator &B) { visitDivRem(B); }
230 void visitDivRem(BinaryOperator &B);
233 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
234 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
235 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
237 // Comparison operators...
238 void visitSetCondInst(SetCondInst &I);
239 unsigned EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
240 MachineBasicBlock *MBB,
241 MachineBasicBlock::iterator MBBI);
242 void visitSelectInst(SelectInst &SI);
245 // Memory Instructions
246 void visitLoadInst(LoadInst &I);
247 void visitStoreInst(StoreInst &I);
248 void visitGetElementPtrInst(GetElementPtrInst &I);
249 void visitAllocaInst(AllocaInst &I);
250 void visitMallocInst(MallocInst &I);
251 void visitFreeInst(FreeInst &I);
254 void visitShiftInst(ShiftInst &I);
255 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
256 void visitCastInst(CastInst &I);
257 void visitVANextInst(VANextInst &I);
258 void visitVAArgInst(VAArgInst &I);
260 void visitInstruction(Instruction &I) {
261 std::cerr << "Cannot instruction select: " << I;
265 /// promote32 - Make a value 32-bits wide, and put it somewhere.
267 void promote32(unsigned targetReg, const ValueRecord &VR);
269 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
270 /// constant expression GEP support.
272 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
273 Value *Src, User::op_iterator IdxBegin,
274 User::op_iterator IdxEnd, unsigned TargetReg,
275 bool CollapseRemainder, ConstantSInt **Remainder,
276 unsigned *PendingAddReg);
278 /// emitCastOperation - Common code shared between visitCastInst and
279 /// constant expression cast support.
281 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator IP,
282 Value *Src, const Type *DestTy, unsigned TargetReg);
284 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
285 /// and constant expression support.
287 void emitSimpleBinaryOperation(MachineBasicBlock *BB,
288 MachineBasicBlock::iterator IP,
289 Value *Op0, Value *Op1,
290 unsigned OperatorClass, unsigned TargetReg);
292 /// emitBinaryFPOperation - This method handles emission of floating point
293 /// Add (0), Sub (1), Mul (2), and Div (3) operations.
294 void emitBinaryFPOperation(MachineBasicBlock *BB,
295 MachineBasicBlock::iterator IP,
296 Value *Op0, Value *Op1,
297 unsigned OperatorClass, unsigned TargetReg);
299 void emitMultiply(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
300 Value *Op0, Value *Op1, unsigned TargetReg);
302 void doMultiply(MachineBasicBlock *MBB,
303 MachineBasicBlock::iterator IP,
304 unsigned DestReg, Value *Op0, Value *Op1);
306 /// doMultiplyConst - This method will multiply the value in Op0Reg by the
307 /// value of the ContantInt *CI
308 void doMultiplyConst(MachineBasicBlock *MBB,
309 MachineBasicBlock::iterator IP,
310 unsigned DestReg, Value *Op0, ConstantInt *CI);
312 void emitDivRemOperation(MachineBasicBlock *BB,
313 MachineBasicBlock::iterator IP,
314 Value *Op0, Value *Op1, bool isDiv,
317 /// emitSetCCOperation - Common code shared between visitSetCondInst and
318 /// constant expression support.
320 void emitSetCCOperation(MachineBasicBlock *BB,
321 MachineBasicBlock::iterator IP,
322 Value *Op0, Value *Op1, unsigned Opcode,
325 /// emitShiftOperation - Common code shared between visitShiftInst and
326 /// constant expression support.
328 void emitShiftOperation(MachineBasicBlock *MBB,
329 MachineBasicBlock::iterator IP,
330 Value *Op, Value *ShiftAmount, bool isLeftShift,
331 const Type *ResultTy, unsigned DestReg);
333 /// emitSelectOperation - Common code shared between visitSelectInst and the
334 /// constant expression support.
336 void emitSelectOperation(MachineBasicBlock *MBB,
337 MachineBasicBlock::iterator IP,
338 Value *Cond, Value *TrueVal, Value *FalseVal,
341 /// copyConstantToRegister - Output the instructions required to put the
342 /// specified constant into the specified register.
344 void copyConstantToRegister(MachineBasicBlock *MBB,
345 MachineBasicBlock::iterator MBBI,
346 Constant *C, unsigned Reg);
348 void emitUCOM(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
349 unsigned LHS, unsigned RHS);
351 /// makeAnotherReg - This method returns the next register number we haven't
354 unsigned makeAnotherReg(const Type *Ty) {
355 assert(dynamic_cast<const PPC64RegisterInfo*>(TM.getRegisterInfo()) &&
356 "Current target doesn't have PPC reg info??");
357 const PPC64RegisterInfo *PPCRI =
358 static_cast<const PPC64RegisterInfo*>(TM.getRegisterInfo());
359 // Add the mapping of regnumber => reg class to MachineFunction
360 const TargetRegisterClass *RC = PPCRI->getRegClassForType(Ty);
361 return F->getSSARegMap()->createVirtualRegister(RC);
364 /// getReg - This method turns an LLVM value into a register number.
366 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
367 unsigned getReg(Value *V) {
368 // Just append to the end of the current bb.
369 MachineBasicBlock::iterator It = BB->end();
370 return getReg(V, BB, It);
372 unsigned getReg(Value *V, MachineBasicBlock *MBB,
373 MachineBasicBlock::iterator IPt);
375 /// canUseAsImmediateForOpcode - This method returns whether a ConstantInt
376 /// is okay to use as an immediate argument to a certain binary operation
377 bool canUseAsImmediateForOpcode(ConstantInt *CI, unsigned Opcode);
379 /// getFixedSizedAllocaFI - Return the frame index for a fixed sized alloca
380 /// that is to be statically allocated with the initial stack frame
382 unsigned getFixedSizedAllocaFI(AllocaInst *AI);
386 /// dyn_castFixedAlloca - If the specified value is a fixed size alloca
387 /// instruction in the entry block, return it. Otherwise, return a null
389 static AllocaInst *dyn_castFixedAlloca(Value *V) {
390 if (AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
391 BasicBlock *BB = AI->getParent();
392 if (isa<ConstantUInt>(AI->getArraySize()) && BB ==&BB->getParent()->front())
398 /// getReg - This method turns an LLVM value into a register number.
400 unsigned PPC64ISel::getReg(Value *V, MachineBasicBlock *MBB,
401 MachineBasicBlock::iterator IPt) {
402 if (Constant *C = dyn_cast<Constant>(V)) {
403 unsigned Reg = makeAnotherReg(V->getType());
404 copyConstantToRegister(MBB, IPt, C, Reg);
406 } else if (AllocaInst *AI = dyn_castFixedAlloca(V)) {
407 unsigned Reg = makeAnotherReg(V->getType());
408 unsigned FI = getFixedSizedAllocaFI(AI);
409 addFrameReference(BuildMI(*MBB, IPt, PPC::ADDI, 2, Reg), FI, 0, false);
413 unsigned &Reg = RegMap[V];
415 Reg = makeAnotherReg(V->getType());
422 /// canUseAsImmediateForOpcode - This method returns whether a ConstantInt
423 /// is okay to use as an immediate argument to a certain binary operator.
425 /// Operator is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for Xor.
426 bool PPC64ISel::canUseAsImmediateForOpcode(ConstantInt *CI, unsigned Operator) {
430 // ADDI, Compare, and non-indexed Load take SIMM
431 bool cond1 = (Operator == 0)
432 && (Op1Cs = dyn_cast<ConstantSInt>(CI))
433 && (Op1Cs->getValue() <= 32767)
434 && (Op1Cs->getValue() >= -32768);
436 // SUBI takes -SIMM since it is a mnemonic for ADDI
437 bool cond2 = (Operator == 1)
438 && (Op1Cs = dyn_cast<ConstantSInt>(CI))
439 && (Op1Cs->getValue() <= 32768)
440 && (Op1Cs->getValue() >= -32767);
442 // ANDIo, ORI, and XORI take unsigned values
443 bool cond3 = (Operator >= 2)
444 && (Op1Cs = dyn_cast<ConstantSInt>(CI))
445 && (Op1Cs->getValue() >= 0)
446 && (Op1Cs->getValue() <= 32767);
448 // ADDI and SUBI take SIMMs, so we have to make sure the UInt would fit
449 bool cond4 = (Operator < 2)
450 && (Op1Cu = dyn_cast<ConstantUInt>(CI))
451 && (Op1Cu->getValue() <= 32767);
453 // ANDIo, ORI, and XORI take UIMMs, so they can be larger
454 bool cond5 = (Operator >= 2)
455 && (Op1Cu = dyn_cast<ConstantUInt>(CI))
456 && (Op1Cu->getValue() <= 65535);
458 if (cond1 || cond2 || cond3 || cond4 || cond5)
464 /// getFixedSizedAllocaFI - Return the frame index for a fixed sized alloca
465 /// that is to be statically allocated with the initial stack frame
467 unsigned PPC64ISel::getFixedSizedAllocaFI(AllocaInst *AI) {
468 // Already computed this?
469 std::map<AllocaInst*, unsigned>::iterator I = AllocaMap.lower_bound(AI);
470 if (I != AllocaMap.end() && I->first == AI) return I->second;
472 const Type *Ty = AI->getAllocatedType();
473 ConstantUInt *CUI = cast<ConstantUInt>(AI->getArraySize());
474 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
475 TySize *= CUI->getValue(); // Get total allocated size...
476 unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
478 // Create a new stack object using the frame manager...
479 int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
480 AllocaMap.insert(I, std::make_pair(AI, FrameIdx));
485 /// copyConstantToRegister - Output the instructions required to put the
486 /// specified constant into the specified register.
488 void PPC64ISel::copyConstantToRegister(MachineBasicBlock *MBB,
489 MachineBasicBlock::iterator IP,
490 Constant *C, unsigned R) {
491 if (C->getType()->isIntegral()) {
492 unsigned Class = getClassB(C->getType());
494 if (Class == cLong) {
495 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(C)) {
496 uint64_t uval = CUI->getValue();
497 if (uval < (1LL << 32)) {
498 ConstantUInt *CU = ConstantUInt::get(Type::UIntTy, uval);
499 copyConstantToRegister(MBB, IP, CU, R);
502 } else if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(C)) {
503 int64_t val = CUI->getValue();
504 if (val < (1LL << 31)) {
505 ConstantUInt *CU = ConstantUInt::get(Type::UIntTy, val);
506 copyConstantToRegister(MBB, IP, CU, R);
510 std::cerr << "Unhandled long constant type!\n";
513 // Spill long to the constant pool and load it
514 MachineConstantPool *CP = F->getConstantPool();
515 unsigned CPI = CP->getConstantPoolIndex(C);
516 BuildMI(*MBB, IP, PPC::LD, 1, R)
517 .addReg(PPC::R2).addConstantPoolIndex(CPI);
521 assert(Class <= cInt && "Type not handled yet!");
524 if (C->getType() == Type::BoolTy) {
525 BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(C == ConstantBool::True);
530 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(C)) {
531 unsigned uval = CUI->getValue();
533 BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(uval);
535 unsigned Temp = makeAnotherReg(Type::IntTy);
536 BuildMI(*MBB, IP, PPC::LIS, 1, Temp).addSImm(uval >> 16);
537 BuildMI(*MBB, IP, PPC::ORI, 2, R).addReg(Temp).addImm(uval);
540 } else if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(C)) {
541 int sval = CSI->getValue();
542 if (sval < 32768 && sval >= -32768) {
543 BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(sval);
545 unsigned Temp = makeAnotherReg(Type::IntTy);
546 BuildMI(*MBB, IP, PPC::LIS, 1, Temp).addSImm(sval >> 16);
547 BuildMI(*MBB, IP, PPC::ORI, 2, R).addReg(Temp).addImm(sval);
551 std::cerr << "Unhandled integer constant!\n";
553 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
554 // We need to spill the constant to memory...
555 MachineConstantPool *CP = F->getConstantPool();
556 unsigned CPI = CP->getConstantPoolIndex(CFP);
557 const Type *Ty = CFP->getType();
558 unsigned LoadOpcode = (Ty == Type::FloatTy) ? PPC::LFS : PPC::LFD;
559 BuildMI(*MBB,IP,LoadOpcode,2,R).addConstantPoolIndex(CPI).addReg(PPC::R2);
560 } else if (isa<ConstantPointerNull>(C)) {
561 // Copy zero (null pointer) to the register.
562 BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(0);
563 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
564 static unsigned OpcodeTable[] = {
565 PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LFS, PPC::LFD, PPC::LD
567 unsigned Opcode = OpcodeTable[getClassB(GV->getType())];
568 BuildMI(*MBB, IP, Opcode, 2, R).addGlobalAddress(GV).addReg(PPC::R2);
570 std::cerr << "Offending constant: " << *C << "\n";
571 assert(0 && "Type not handled yet!");
575 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function from
576 /// the stack into virtual registers.
577 void PPC64ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
578 unsigned ArgOffset = ParameterSaveAreaOffset;
579 unsigned GPR_remaining = 8;
580 unsigned FPR_remaining = 13;
581 unsigned GPR_idx = 0, FPR_idx = 0;
582 static const unsigned GPR[] = {
583 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
584 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
586 static const unsigned FPR[] = {
587 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
588 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
591 MachineFrameInfo *MFI = F->getFrameInfo();
593 for (Function::aiterator I = Fn.abegin(), E = Fn.aend(); I != E; ++I) {
594 bool ArgLive = !I->use_empty();
595 unsigned Reg = ArgLive ? getReg(*I) : 0;
596 int FI; // Frame object index
598 switch (getClassB(I->getType())) {
601 FI = MFI->CreateFixedObject(4, ArgOffset);
602 if (GPR_remaining > 0) {
603 BuildMI(BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
604 BuildMI(BB, PPC::OR, 2, Reg).addReg(GPR[GPR_idx])
605 .addReg(GPR[GPR_idx]);
607 addFrameReference(BuildMI(BB, PPC::LBZ, 2, Reg), FI);
613 FI = MFI->CreateFixedObject(4, ArgOffset);
614 if (GPR_remaining > 0) {
615 BuildMI(BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
616 BuildMI(BB, PPC::OR, 2, Reg).addReg(GPR[GPR_idx])
617 .addReg(GPR[GPR_idx]);
619 addFrameReference(BuildMI(BB, PPC::LHZ, 2, Reg), FI);
625 FI = MFI->CreateFixedObject(4, ArgOffset);
626 if (GPR_remaining > 0) {
627 BuildMI(BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
628 BuildMI(BB, PPC::OR, 2, Reg).addReg(GPR[GPR_idx])
629 .addReg(GPR[GPR_idx]);
631 addFrameReference(BuildMI(BB, PPC::LWZ, 2, Reg), FI);
637 FI = MFI->CreateFixedObject(8, ArgOffset);
638 if (GPR_remaining > 1) {
639 BuildMI(BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
640 BuildMI(BB, PPC::OR, 2, Reg).addReg(GPR[GPR_idx])
641 .addReg(GPR[GPR_idx]);
643 addFrameReference(BuildMI(BB, PPC::LD, 2, Reg), FI);
646 // longs require 4 additional bytes
651 FI = MFI->CreateFixedObject(4, ArgOffset);
653 if (FPR_remaining > 0) {
654 BuildMI(BB, PPC::IMPLICIT_DEF, 0, FPR[FPR_idx]);
655 BuildMI(BB, PPC::FMR, 1, Reg).addReg(FPR[FPR_idx]);
659 addFrameReference(BuildMI(BB, PPC::LFS, 2, Reg), FI);
665 FI = MFI->CreateFixedObject(8, ArgOffset);
667 if (FPR_remaining > 0) {
668 BuildMI(BB, PPC::IMPLICIT_DEF, 0, FPR[FPR_idx]);
669 BuildMI(BB, PPC::FMR, 1, Reg).addReg(FPR[FPR_idx]);
673 addFrameReference(BuildMI(BB, PPC::LFD, 2, Reg), FI);
677 // doubles require 4 additional bytes and use 2 GPRs of param space
679 if (GPR_remaining > 0) {
685 assert(0 && "Unhandled argument type!");
687 ArgOffset += 4; // Each argument takes at least 4 bytes on the stack...
688 if (GPR_remaining > 0) {
689 GPR_remaining--; // uses up 2 GPRs
694 // If the function takes variable number of arguments, add a frame offset for
695 // the start of the first vararg value... this is used to expand
697 if (Fn.getFunctionType()->isVarArg())
698 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
702 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
703 /// because we have to generate our sources into the source basic blocks, not
706 void PPC64ISel::SelectPHINodes() {
707 const TargetInstrInfo &TII = *TM.getInstrInfo();
708 const Function &LF = *F->getFunction(); // The LLVM function...
709 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
710 const BasicBlock *BB = I;
711 MachineBasicBlock &MBB = *MBBMap[I];
713 // Loop over all of the PHI nodes in the LLVM basic block...
714 MachineBasicBlock::iterator PHIInsertPoint = MBB.begin();
715 for (BasicBlock::const_iterator I = BB->begin();
716 PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
718 // Create a new machine instr PHI node, and insert it.
719 unsigned PHIReg = getReg(*PN);
720 MachineInstr *PhiMI = BuildMI(MBB, PHIInsertPoint,
721 PPC::PHI, PN->getNumOperands(), PHIReg);
723 // PHIValues - Map of blocks to incoming virtual registers. We use this
724 // so that we only initialize one incoming value for a particular block,
725 // even if the block has multiple entries in the PHI node.
727 std::map<MachineBasicBlock*, unsigned> PHIValues;
729 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
730 MachineBasicBlock *PredMBB = 0;
731 for (MachineBasicBlock::pred_iterator PI = MBB.pred_begin (),
732 PE = MBB.pred_end (); PI != PE; ++PI)
733 if (PN->getIncomingBlock(i) == (*PI)->getBasicBlock()) {
737 assert (PredMBB && "Couldn't find incoming machine-cfg edge for phi");
740 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
741 PHIValues.lower_bound(PredMBB);
743 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
744 // We already inserted an initialization of the register for this
745 // predecessor. Recycle it.
746 ValReg = EntryIt->second;
748 // Get the incoming value into a virtual register.
750 Value *Val = PN->getIncomingValue(i);
752 // If this is a constant or GlobalValue, we may have to insert code
753 // into the basic block to compute it into a virtual register.
754 if ((isa<Constant>(Val) && !isa<ConstantExpr>(Val)) ||
755 isa<GlobalValue>(Val)) {
756 // Simple constants get emitted at the end of the basic block,
757 // before any terminator instructions. We "know" that the code to
758 // move a constant into a register will never clobber any flags.
759 ValReg = getReg(Val, PredMBB, PredMBB->getFirstTerminator());
761 // Because we don't want to clobber any values which might be in
762 // physical registers with the computation of this constant (which
763 // might be arbitrarily complex if it is a constant expression),
764 // just insert the computation at the top of the basic block.
765 MachineBasicBlock::iterator PI = PredMBB->begin();
767 // Skip over any PHI nodes though!
768 while (PI != PredMBB->end() && PI->getOpcode() == PPC::PHI)
771 ValReg = getReg(Val, PredMBB, PI);
774 // Remember that we inserted a value for this PHI for this predecessor
775 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
778 PhiMI->addRegOperand(ValReg);
779 PhiMI->addMachineBasicBlockOperand(PredMBB);
782 // Now that we emitted all of the incoming values for the PHI node, make
783 // sure to reposition the InsertPoint after the PHI that we just added.
784 // This is needed because we might have inserted a constant into this
785 // block, right after the PHI's which is before the old insert point!
786 PHIInsertPoint = PhiMI;
793 // canFoldSetCCIntoBranchOrSelect - Return the setcc instruction if we can fold
794 // it into the conditional branch or select instruction which is the only user
795 // of the cc instruction. This is the case if the conditional branch is the
796 // only user of the setcc, and if the setcc is in the same basic block as the
797 // conditional branch.
799 static SetCondInst *canFoldSetCCIntoBranchOrSelect(Value *V) {
800 if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
801 if (SCI->hasOneUse()) {
802 Instruction *User = cast<Instruction>(SCI->use_back());
803 if ((isa<BranchInst>(User) || isa<SelectInst>(User)) &&
804 SCI->getParent() == User->getParent())
811 // canFoldGEPIntoLoadOrStore - Return the GEP instruction if we can fold it into
812 // the load or store instruction that is the only user of the GEP.
814 static GetElementPtrInst *canFoldGEPIntoLoadOrStore(Value *V) {
815 if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(V))
816 if (GEPI->hasOneUse()) {
817 Instruction *User = cast<Instruction>(GEPI->use_back());
818 if (isa<StoreInst>(User) &&
819 GEPI->getParent() == User->getParent() &&
820 User->getOperand(0) != GEPI &&
821 User->getOperand(1) == GEPI) {
825 if (isa<LoadInst>(User) &&
826 GEPI->getParent() == User->getParent() &&
827 User->getOperand(0) == GEPI) {
836 // Return a fixed numbering for setcc instructions which does not depend on the
837 // order of the opcodes.
839 static unsigned getSetCCNumber(unsigned Opcode) {
841 default: assert(0 && "Unknown setcc instruction!");
842 case Instruction::SetEQ: return 0;
843 case Instruction::SetNE: return 1;
844 case Instruction::SetLT: return 2;
845 case Instruction::SetGE: return 3;
846 case Instruction::SetGT: return 4;
847 case Instruction::SetLE: return 5;
851 static unsigned getPPCOpcodeForSetCCNumber(unsigned Opcode) {
853 default: assert(0 && "Unknown setcc instruction!");
854 case Instruction::SetEQ: return PPC::BEQ;
855 case Instruction::SetNE: return PPC::BNE;
856 case Instruction::SetLT: return PPC::BLT;
857 case Instruction::SetGE: return PPC::BGE;
858 case Instruction::SetGT: return PPC::BGT;
859 case Instruction::SetLE: return PPC::BLE;
863 /// emitUCOM - emits an unordered FP compare.
864 void PPC64ISel::emitUCOM(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
865 unsigned LHS, unsigned RHS) {
866 BuildMI(*MBB, IP, PPC::FCMPU, 2, PPC::CR0).addReg(LHS).addReg(RHS);
869 /// EmitComparison - emits a comparison of the two operands, returning the
870 /// extended setcc code to use. The result is in CR0.
872 unsigned PPC64ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
873 MachineBasicBlock *MBB,
874 MachineBasicBlock::iterator IP) {
875 // The arguments are already supposed to be of the same type.
876 const Type *CompTy = Op0->getType();
877 unsigned Class = getClassB(CompTy);
878 unsigned Op0r = getReg(Op0, MBB, IP);
880 // Before we do a comparison, we have to make sure that we're truncating our
881 // registers appropriately.
882 if (Class == cByte) {
883 unsigned TmpReg = makeAnotherReg(CompTy);
884 if (CompTy->isSigned())
885 BuildMI(*MBB, IP, PPC::EXTSB, 1, TmpReg).addReg(Op0r);
887 BuildMI(*MBB, IP, PPC::RLWINM, 4, TmpReg).addReg(Op0r).addImm(0)
888 .addImm(24).addImm(31);
890 } else if (Class == cShort) {
891 unsigned TmpReg = makeAnotherReg(CompTy);
892 if (CompTy->isSigned())
893 BuildMI(*MBB, IP, PPC::EXTSH, 1, TmpReg).addReg(Op0r);
895 BuildMI(*MBB, IP, PPC::RLWINM, 4, TmpReg).addReg(Op0r).addImm(0)
896 .addImm(16).addImm(31);
900 // Use crand for lt, gt and crandc for le, ge
901 unsigned CROpcode = (OpNum == 2 || OpNum == 4) ? PPC::CRAND : PPC::CRANDC;
902 unsigned Opcode = CompTy->isSigned() ? PPC::CMPW : PPC::CMPLW;
903 unsigned OpcodeImm = CompTy->isSigned() ? PPC::CMPWI : PPC::CMPLWI;
904 if (Class == cLong) {
905 Opcode = CompTy->isSigned() ? PPC::CMPD : PPC::CMPLD;
906 OpcodeImm = CompTy->isSigned() ? PPC::CMPDI : PPC::CMPLDI;
909 // Special case handling of: cmp R, i
910 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
911 unsigned Op1v = CI->getRawValue() & 0xFFFF;
913 // Treat compare like ADDI for the purposes of immediate suitability
914 if (canUseAsImmediateForOpcode(CI, 0)) {
915 BuildMI(*MBB, IP, OpcodeImm, 2, PPC::CR0).addReg(Op0r).addSImm(Op1v);
917 unsigned Op1r = getReg(Op1, MBB, IP);
918 BuildMI(*MBB, IP, Opcode, 2, PPC::CR0).addReg(Op0r).addReg(Op1r);
923 unsigned Op1r = getReg(Op1, MBB, IP);
926 default: assert(0 && "Unknown type class!");
931 BuildMI(*MBB, IP, Opcode, 2, PPC::CR0).addReg(Op0r).addReg(Op1r);
936 emitUCOM(MBB, IP, Op0r, Op1r);
943 /// visitSetCondInst - emit code to calculate the condition via
944 /// EmitComparison(), and possibly store a 0 or 1 to a register as a result
946 void PPC64ISel::visitSetCondInst(SetCondInst &I) {
947 if (canFoldSetCCIntoBranchOrSelect(&I))
950 unsigned DestReg = getReg(I);
951 unsigned OpNum = I.getOpcode();
952 const Type *Ty = I.getOperand (0)->getType();
954 EmitComparison(OpNum, I.getOperand(0), I.getOperand(1), BB, BB->end());
956 unsigned Opcode = getPPCOpcodeForSetCCNumber(OpNum);
957 MachineBasicBlock *thisMBB = BB;
958 const BasicBlock *LLVM_BB = BB->getBasicBlock();
959 ilist<MachineBasicBlock>::iterator It = BB;
968 // FIXME: we wouldn't need copy0MBB (we could fold it into thisMBB)
969 // if we could insert other, non-terminator instructions after the
970 // bCC. But MBB->getFirstTerminator() can't understand this.
971 MachineBasicBlock *copy1MBB = new MachineBasicBlock(LLVM_BB);
972 F->getBasicBlockList().insert(It, copy1MBB);
973 BuildMI(BB, Opcode, 2).addReg(PPC::CR0).addMBB(copy1MBB);
974 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
975 F->getBasicBlockList().insert(It, copy0MBB);
976 BuildMI(BB, PPC::B, 1).addMBB(copy0MBB);
977 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
978 F->getBasicBlockList().insert(It, sinkMBB);
979 // Update machine-CFG edges
980 BB->addSuccessor(copy1MBB);
981 BB->addSuccessor(copy0MBB);
987 unsigned TrueValue = makeAnotherReg(I.getType());
988 BuildMI(BB, PPC::LI, 1, TrueValue).addSImm(1);
989 BuildMI(BB, PPC::B, 1).addMBB(sinkMBB);
990 // Update machine-CFG edges
991 BB->addSuccessor(sinkMBB);
994 // %FalseValue = li 0
997 unsigned FalseValue = makeAnotherReg(I.getType());
998 BuildMI(BB, PPC::LI, 1, FalseValue).addSImm(0);
999 // Update machine-CFG edges
1000 BB->addSuccessor(sinkMBB);
1003 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, copy1MBB ]
1006 BuildMI(BB, PPC::PHI, 4, DestReg).addReg(FalseValue)
1007 .addMBB(copy0MBB).addReg(TrueValue).addMBB(copy1MBB);
1010 void PPC64ISel::visitSelectInst(SelectInst &SI) {
1011 unsigned DestReg = getReg(SI);
1012 MachineBasicBlock::iterator MII = BB->end();
1013 emitSelectOperation(BB, MII, SI.getCondition(), SI.getTrueValue(),
1014 SI.getFalseValue(), DestReg);
1017 /// emitSelect - Common code shared between visitSelectInst and the constant
1018 /// expression support.
1019 /// FIXME: this is most likely broken in one or more ways. Namely, PowerPC has
1020 /// no select instruction. FSEL only works for comparisons against zero.
1021 void PPC64ISel::emitSelectOperation(MachineBasicBlock *MBB,
1022 MachineBasicBlock::iterator IP,
1023 Value *Cond, Value *TrueVal,
1024 Value *FalseVal, unsigned DestReg) {
1025 unsigned SelectClass = getClassB(TrueVal->getType());
1028 // See if we can fold the setcc into the select instruction, or if we have
1029 // to get the register of the Cond value
1030 if (SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(Cond)) {
1031 // We successfully folded the setcc into the select instruction.
1032 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
1033 OpNum = EmitComparison(OpNum, SCI->getOperand(0),SCI->getOperand(1),MBB,IP);
1034 Opcode = getPPCOpcodeForSetCCNumber(SCI->getOpcode());
1036 unsigned CondReg = getReg(Cond, MBB, IP);
1037 BuildMI(*MBB, IP, PPC::CMPI, 2, PPC::CR0).addReg(CondReg).addSImm(0);
1038 Opcode = getPPCOpcodeForSetCCNumber(Instruction::SetNE);
1043 // cmpTY cr0, r1, r2
1047 MachineBasicBlock *thisMBB = BB;
1048 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1049 ilist<MachineBasicBlock>::iterator It = BB;
1052 // FIXME: we wouldn't need copy0MBB (we could fold it into thisMBB)
1053 // if we could insert other, non-terminator instructions after the
1054 // bCC. But MBB->getFirstTerminator() can't understand this.
1055 MachineBasicBlock *copy1MBB = new MachineBasicBlock(LLVM_BB);
1056 F->getBasicBlockList().insert(It, copy1MBB);
1057 BuildMI(BB, Opcode, 2).addReg(PPC::CR0).addMBB(copy1MBB);
1058 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
1059 F->getBasicBlockList().insert(It, copy0MBB);
1060 BuildMI(BB, PPC::B, 1).addMBB(copy0MBB);
1061 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
1062 F->getBasicBlockList().insert(It, sinkMBB);
1063 // Update machine-CFG edges
1064 BB->addSuccessor(copy1MBB);
1065 BB->addSuccessor(copy0MBB);
1071 unsigned TrueValue = getReg(TrueVal, BB, BB->begin());
1072 BuildMI(BB, PPC::B, 1).addMBB(sinkMBB);
1073 // Update machine-CFG edges
1074 BB->addSuccessor(sinkMBB);
1077 // %FalseValue = ...
1080 unsigned FalseValue = getReg(FalseVal, BB, BB->begin());
1081 // Update machine-CFG edges
1082 BB->addSuccessor(sinkMBB);
1085 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, copy1MBB ]
1088 BuildMI(BB, PPC::PHI, 4, DestReg).addReg(FalseValue)
1089 .addMBB(copy0MBB).addReg(TrueValue).addMBB(copy1MBB);
1095 /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
1096 /// operand, in the specified target register.
1098 void PPC64ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
1099 bool isUnsigned = VR.Ty->isUnsigned() || VR.Ty == Type::BoolTy;
1101 Value *Val = VR.Val;
1102 const Type *Ty = VR.Ty;
1104 if (Constant *C = dyn_cast<Constant>(Val)) {
1105 Val = ConstantExpr::getCast(C, Type::IntTy);
1106 if (isa<ConstantExpr>(Val)) // Could not fold
1109 Ty = Type::IntTy; // Folded!
1112 // If this is a simple constant, just emit a load directly to avoid the copy
1113 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
1114 int TheVal = CI->getRawValue() & 0xFFFFFFFF;
1116 if (TheVal < 32768 && TheVal >= -32768) {
1117 BuildMI(BB, PPC::LI, 1, targetReg).addSImm(TheVal);
1119 unsigned TmpReg = makeAnotherReg(Type::IntTy);
1120 BuildMI(BB, PPC::LIS, 1, TmpReg).addSImm(TheVal >> 16);
1121 BuildMI(BB, PPC::ORI, 2, targetReg).addReg(TmpReg)
1122 .addImm(TheVal & 0xFFFF);
1128 // Make sure we have the register number for this value...
1129 unsigned Reg = Val ? getReg(Val) : VR.Reg;
1130 switch (getClassB(Ty)) {
1132 // Extend value into target register (8->32)
1134 BuildMI(BB, PPC::RLWINM, 4, targetReg).addReg(Reg).addZImm(0)
1135 .addZImm(24).addZImm(31);
1137 BuildMI(BB, PPC::EXTSB, 1, targetReg).addReg(Reg);
1140 // Extend value into target register (16->32)
1142 BuildMI(BB, PPC::RLWINM, 4, targetReg).addReg(Reg).addZImm(0)
1143 .addZImm(16).addZImm(31);
1145 BuildMI(BB, PPC::EXTSH, 1, targetReg).addReg(Reg);
1149 // Move value into target register (32->32)
1150 BuildMI(BB, PPC::OR, 2, targetReg).addReg(Reg).addReg(Reg);
1153 assert(0 && "Unpromotable operand class in promote32");
1157 /// visitReturnInst - implemented with BLR
1159 void PPC64ISel::visitReturnInst(ReturnInst &I) {
1160 // Only do the processing if this is a non-void return
1161 if (I.getNumOperands() > 0) {
1162 Value *RetVal = I.getOperand(0);
1163 switch (getClassB(RetVal->getType())) {
1164 case cByte: // integral return values: extend or move into r3 and return
1168 promote32(PPC::R3, ValueRecord(RetVal));
1171 case cFP64: { // Floats & Doubles: Return in f1
1172 unsigned RetReg = getReg(RetVal);
1173 BuildMI(BB, PPC::FMR, 1, PPC::F1).addReg(RetReg);
1177 visitInstruction(I);
1180 BuildMI(BB, PPC::BLR, 1).addImm(1);
1183 // getBlockAfter - Return the basic block which occurs lexically after the
1185 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
1186 Function::iterator I = BB; ++I; // Get iterator to next block
1187 return I != BB->getParent()->end() ? &*I : 0;
1190 /// visitBranchInst - Handle conditional and unconditional branches here. Note
1191 /// that since code layout is frozen at this point, that if we are trying to
1192 /// jump to a block that is the immediate successor of the current block, we can
1193 /// just make a fall-through (but we don't currently).
1195 void PPC64ISel::visitBranchInst(BranchInst &BI) {
1196 // Update machine-CFG edges
1197 BB->addSuccessor(MBBMap[BI.getSuccessor(0)]);
1198 if (BI.isConditional())
1199 BB->addSuccessor(MBBMap[BI.getSuccessor(1)]);
1201 BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
1203 if (!BI.isConditional()) { // Unconditional branch?
1204 if (BI.getSuccessor(0) != NextBB)
1205 BuildMI(BB, PPC::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
1209 // See if we can fold the setcc into the branch itself...
1210 SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(BI.getCondition());
1212 // Nope, cannot fold setcc into this branch. Emit a branch on a condition
1213 // computed some other way...
1214 unsigned condReg = getReg(BI.getCondition());
1215 BuildMI(BB, PPC::CMPLI, 3, PPC::CR0).addImm(0).addReg(condReg)
1217 if (BI.getSuccessor(1) == NextBB) {
1218 if (BI.getSuccessor(0) != NextBB)
1219 BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(PPC::BNE)
1220 .addMBB(MBBMap[BI.getSuccessor(0)])
1221 .addMBB(MBBMap[BI.getSuccessor(1)]);
1223 BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(PPC::BEQ)
1224 .addMBB(MBBMap[BI.getSuccessor(1)])
1225 .addMBB(MBBMap[BI.getSuccessor(0)]);
1226 if (BI.getSuccessor(0) != NextBB)
1227 BuildMI(BB, PPC::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
1232 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
1233 unsigned Opcode = getPPCOpcodeForSetCCNumber(SCI->getOpcode());
1234 MachineBasicBlock::iterator MII = BB->end();
1235 OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
1237 if (BI.getSuccessor(0) != NextBB) {
1238 BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(Opcode)
1239 .addMBB(MBBMap[BI.getSuccessor(0)])
1240 .addMBB(MBBMap[BI.getSuccessor(1)]);
1241 if (BI.getSuccessor(1) != NextBB)
1242 BuildMI(BB, PPC::B, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
1244 // Change to the inverse condition...
1245 if (BI.getSuccessor(1) != NextBB) {
1246 Opcode = PPC64InstrInfo::invertPPCBranchOpcode(Opcode);
1247 BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(Opcode)
1248 .addMBB(MBBMap[BI.getSuccessor(1)])
1249 .addMBB(MBBMap[BI.getSuccessor(0)]);
1254 /// doCall - This emits an abstract call instruction, setting up the arguments
1255 /// and the return value as appropriate. For the actual function call itself,
1256 /// it inserts the specified CallMI instruction into the stream.
1258 void PPC64ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
1259 const std::vector<ValueRecord> &Args, bool isVarArg) {
1260 // Count how many bytes are to be pushed on the stack, including the linkage
1261 // area, and parameter passing area.
1262 unsigned NumBytes = ParameterSaveAreaOffset;
1263 unsigned ArgOffset = ParameterSaveAreaOffset;
1265 if (!Args.empty()) {
1266 for (unsigned i = 0, e = Args.size(); i != e; ++i)
1267 switch (getClassB(Args[i].Ty)) {
1268 case cByte: case cShort: case cInt:
1269 NumBytes += 4; break;
1271 NumBytes += 8; break;
1273 NumBytes += 4; break;
1275 NumBytes += 8; break;
1277 default: assert(0 && "Unknown class!");
1280 // Just to be safe, we'll always reserve the full argument passing space in
1281 // case any called code gets funky on us.
1282 if (NumBytes < ParameterSaveAreaOffset + MaxArgumentStackSpace)
1283 NumBytes = ParameterSaveAreaOffset + MaxArgumentStackSpace;
1285 // Adjust the stack pointer for the new arguments...
1286 // These functions are automatically eliminated by the prolog/epilog pass
1287 BuildMI(BB, PPC::ADJCALLSTACKDOWN, 1).addImm(NumBytes);
1289 // Arguments go on the stack in reverse order, as specified by the ABI.
1290 int GPR_remaining = 8, FPR_remaining = 13;
1291 unsigned GPR_idx = 0, FPR_idx = 0;
1292 static const unsigned GPR[] = {
1293 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1294 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1296 static const unsigned FPR[] = {
1297 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6,
1298 PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12,
1302 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
1304 switch (getClassB(Args[i].Ty)) {
1307 // Promote arg to 32 bits wide into a temporary register...
1308 ArgReg = makeAnotherReg(Type::UIntTy);
1309 promote32(ArgReg, Args[i]);
1312 if (GPR_remaining > 0) {
1313 BuildMI(BB, PPC::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
1315 CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
1317 if (GPR_remaining <= 0 || isVarArg) {
1318 BuildMI(BB, PPC::STW, 3).addReg(ArgReg).addSImm(ArgOffset)
1323 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1326 if (GPR_remaining > 0) {
1327 BuildMI(BB, PPC::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
1329 CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
1331 if (GPR_remaining <= 0 || isVarArg) {
1332 BuildMI(BB, PPC::STW, 3).addReg(ArgReg).addSImm(ArgOffset)
1337 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1340 if (GPR_remaining > 0) {
1341 BuildMI(BB, PPC::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
1343 CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
1345 if (GPR_remaining <= 0 || isVarArg) {
1346 BuildMI(BB, PPC::STD, 3).addReg(ArgReg).addSImm(ArgOffset)
1349 ArgOffset += 4; // 8 byte entry, not 4.
1352 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1354 if (FPR_remaining > 0) {
1355 BuildMI(BB, PPC::FMR, 1, FPR[FPR_idx]).addReg(ArgReg);
1356 CallMI->addRegOperand(FPR[FPR_idx], MachineOperand::Use);
1360 // If this is a vararg function, and there are GPRs left, also
1361 // pass the float in an int. Otherwise, put it on the stack.
1363 BuildMI(BB, PPC::STFS, 3).addReg(ArgReg).addSImm(ArgOffset)
1365 if (GPR_remaining > 0) {
1366 BuildMI(BB, PPC::LWZ, 2, GPR[GPR_idx])
1367 .addSImm(ArgOffset).addReg(ArgReg);
1368 CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
1372 BuildMI(BB, PPC::STFS, 3).addReg(ArgReg).addSImm(ArgOffset)
1377 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1379 if (FPR_remaining > 0) {
1380 BuildMI(BB, PPC::FMR, 1, FPR[FPR_idx]).addReg(ArgReg);
1381 CallMI->addRegOperand(FPR[FPR_idx], MachineOperand::Use);
1384 // For vararg functions, must pass doubles via int regs as well
1386 BuildMI(BB, PPC::STFD, 3).addReg(ArgReg).addSImm(ArgOffset)
1389 if (GPR_remaining > 0) {
1390 BuildMI(BB, PPC::LD, 2, GPR[GPR_idx]).addSImm(ArgOffset)
1392 CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
1396 BuildMI(BB, PPC::STFD, 3).addReg(ArgReg).addSImm(ArgOffset)
1399 // Doubles use 8 bytes
1403 default: assert(0 && "Unknown class!");
1410 BuildMI(BB, PPC::ADJCALLSTACKDOWN, 1).addImm(0);
1413 BuildMI(BB, PPC::IMPLICIT_DEF, 0, PPC::LR);
1414 BB->push_back(CallMI);
1415 BuildMI(BB, PPC::NOP, 0);
1417 // These functions are automatically eliminated by the prolog/epilog pass
1418 BuildMI(BB, PPC::ADJCALLSTACKUP, 1).addImm(NumBytes);
1420 // If there is a return value, scavenge the result from the location the call
1423 if (Ret.Ty != Type::VoidTy) {
1424 unsigned DestClass = getClassB(Ret.Ty);
1425 switch (DestClass) {
1430 // Integral results are in r3
1431 BuildMI(BB, PPC::OR, 2, Ret.Reg).addReg(PPC::R3).addReg(PPC::R3);
1433 case cFP32: // Floating-point return values live in f1
1435 BuildMI(BB, PPC::FMR, 1, Ret.Reg).addReg(PPC::F1);
1437 default: assert(0 && "Unknown class!");
1443 /// visitCallInst - Push args on stack and do a procedure call instruction.
1444 void PPC64ISel::visitCallInst(CallInst &CI) {
1445 MachineInstr *TheCall;
1446 Function *F = CI.getCalledFunction();
1448 // Is it an intrinsic function call?
1449 if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
1450 visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here
1453 // Emit a CALL instruction with PC-relative displacement.
1454 TheCall = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(F, true);
1455 } else { // Emit an indirect call through the CTR
1456 unsigned Reg = getReg(CI.getCalledValue());
1457 BuildMI(BB, PPC::MTCTR, 1).addReg(Reg);
1458 TheCall = BuildMI(PPC::CALLindirect, 2).addZImm(20).addZImm(0);
1461 std::vector<ValueRecord> Args;
1462 for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i)
1463 Args.push_back(ValueRecord(CI.getOperand(i)));
1465 unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
1466 bool isVarArg = F ? F->getFunctionType()->isVarArg() : true;
1467 doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args, isVarArg);
1471 /// dyncastIsNan - Return the operand of an isnan operation if this is an isnan.
1473 static Value *dyncastIsNan(Value *V) {
1474 if (CallInst *CI = dyn_cast<CallInst>(V))
1475 if (Function *F = CI->getCalledFunction())
1476 if (F->getIntrinsicID() == Intrinsic::isunordered)
1477 return CI->getOperand(1);
1481 /// isOnlyUsedByUnorderedComparisons - Return true if this value is only used by
1482 /// or's whos operands are all calls to the isnan predicate.
1483 static bool isOnlyUsedByUnorderedComparisons(Value *V) {
1484 assert(dyncastIsNan(V) && "The value isn't an isnan call!");
1486 // Check all uses, which will be or's of isnans if this predicate is true.
1487 for (Value::use_iterator UI = V->use_begin(), E = V->use_end(); UI != E;++UI){
1488 Instruction *I = cast<Instruction>(*UI);
1489 if (I->getOpcode() != Instruction::Or) return false;
1490 if (I->getOperand(0) != V && !dyncastIsNan(I->getOperand(0))) return false;
1491 if (I->getOperand(1) != V && !dyncastIsNan(I->getOperand(1))) return false;
1497 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
1498 /// function, lowering any calls to unknown intrinsic functions into the
1499 /// equivalent LLVM code.
1501 void PPC64ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
1502 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
1503 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
1504 if (CallInst *CI = dyn_cast<CallInst>(I++))
1505 if (Function *F = CI->getCalledFunction())
1506 switch (F->getIntrinsicID()) {
1507 case Intrinsic::not_intrinsic:
1508 case Intrinsic::vastart:
1509 case Intrinsic::vacopy:
1510 case Intrinsic::vaend:
1511 case Intrinsic::returnaddress:
1512 case Intrinsic::frameaddress:
1513 // FIXME: should lower these ourselves
1514 // case Intrinsic::isunordered:
1515 // case Intrinsic::memcpy: -> doCall(). system memcpy almost
1516 // guaranteed to be faster than anything we generate ourselves
1517 // We directly implement these intrinsics
1519 case Intrinsic::readio: {
1520 // On PPC, memory operations are in-order. Lower this intrinsic
1521 // into a volatile load.
1522 Instruction *Before = CI->getPrev();
1523 LoadInst * LI = new LoadInst(CI->getOperand(1), "", true, CI);
1524 CI->replaceAllUsesWith(LI);
1525 BB->getInstList().erase(CI);
1528 case Intrinsic::writeio: {
1529 // On PPC, memory operations are in-order. Lower this intrinsic
1530 // into a volatile store.
1531 Instruction *Before = CI->getPrev();
1532 StoreInst *SI = new StoreInst(CI->getOperand(1),
1533 CI->getOperand(2), true, CI);
1534 CI->replaceAllUsesWith(SI);
1535 BB->getInstList().erase(CI);
1539 // All other intrinsic calls we must lower.
1540 Instruction *Before = CI->getPrev();
1541 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
1542 if (Before) { // Move iterator to instruction after call
1550 void PPC64ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
1551 unsigned TmpReg1, TmpReg2, TmpReg3;
1553 case Intrinsic::vastart:
1554 // Get the address of the first vararg value...
1555 TmpReg1 = getReg(CI);
1556 addFrameReference(BuildMI(BB, PPC::ADDI, 2, TmpReg1), VarArgsFrameIndex,
1560 case Intrinsic::vacopy:
1561 TmpReg1 = getReg(CI);
1562 TmpReg2 = getReg(CI.getOperand(1));
1563 BuildMI(BB, PPC::OR, 2, TmpReg1).addReg(TmpReg2).addReg(TmpReg2);
1565 case Intrinsic::vaend: return;
1567 case Intrinsic::returnaddress:
1568 TmpReg1 = getReg(CI);
1569 if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
1570 MachineFrameInfo *MFI = F->getFrameInfo();
1571 unsigned NumBytes = MFI->getStackSize();
1573 BuildMI(BB, PPC::LWZ, 2, TmpReg1).addSImm(NumBytes+8)
1576 // Values other than zero are not implemented yet.
1577 BuildMI(BB, PPC::LI, 1, TmpReg1).addSImm(0);
1581 case Intrinsic::frameaddress:
1582 TmpReg1 = getReg(CI);
1583 if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
1584 BuildMI(BB, PPC::OR, 2, TmpReg1).addReg(PPC::R1).addReg(PPC::R1);
1586 // Values other than zero are not implemented yet.
1587 BuildMI(BB, PPC::LI, 1, TmpReg1).addSImm(0);
1592 // This may be useful for supporting isunordered
1593 case Intrinsic::isnan:
1594 // If this is only used by 'isunordered' style comparisons, don't emit it.
1595 if (isOnlyUsedByUnorderedComparisons(&CI)) return;
1596 TmpReg1 = getReg(CI.getOperand(1));
1597 emitUCOM(BB, BB->end(), TmpReg1, TmpReg1);
1598 TmpReg2 = makeAnotherReg(Type::IntTy);
1599 BuildMI(BB, PPC::MFCR, TmpReg2);
1600 TmpReg3 = getReg(CI);
1601 BuildMI(BB, PPC::RLWINM, 4, TmpReg3).addReg(TmpReg2).addImm(4).addImm(31).addImm(31);
1605 default: assert(0 && "Error: unknown intrinsics should have been lowered!");
1609 /// visitSimpleBinary - Implement simple binary operators for integral types...
1610 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for
1613 void PPC64ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
1614 unsigned DestReg = getReg(B);
1615 MachineBasicBlock::iterator MI = BB->end();
1616 Value *Op0 = B.getOperand(0), *Op1 = B.getOperand(1);
1617 unsigned Class = getClassB(B.getType());
1619 emitSimpleBinaryOperation(BB, MI, Op0, Op1, OperatorClass, DestReg);
1622 /// emitBinaryFPOperation - This method handles emission of floating point
1623 /// Add (0), Sub (1), Mul (2), and Div (3) operations.
1624 void PPC64ISel::emitBinaryFPOperation(MachineBasicBlock *BB,
1625 MachineBasicBlock::iterator IP,
1626 Value *Op0, Value *Op1,
1627 unsigned OperatorClass, unsigned DestReg){
1629 static const unsigned OpcodeTab[][4] = {
1630 { PPC::FADDS, PPC::FSUBS, PPC::FMULS, PPC::FDIVS }, // Float
1631 { PPC::FADD, PPC::FSUB, PPC::FMUL, PPC::FDIV }, // Double
1634 // Special case: R1 = op <const fp>, R2
1635 if (ConstantFP *Op0C = dyn_cast<ConstantFP>(Op0))
1636 if (Op0C->isExactlyValue(-0.0) && OperatorClass == 1) {
1638 unsigned op1Reg = getReg(Op1, BB, IP);
1639 BuildMI(*BB, IP, PPC::FNEG, 1, DestReg).addReg(op1Reg);
1643 unsigned Opcode = OpcodeTab[Op0->getType() == Type::DoubleTy][OperatorClass];
1644 unsigned Op0r = getReg(Op0, BB, IP);
1645 unsigned Op1r = getReg(Op1, BB, IP);
1646 BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
1649 /// emitSimpleBinaryOperation - Implement simple binary operators for integral
1650 /// types... OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for
1653 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
1654 /// and constant expression support.
1656 void PPC64ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
1657 MachineBasicBlock::iterator IP,
1658 Value *Op0, Value *Op1,
1659 unsigned OperatorClass,
1661 unsigned Class = getClassB(Op0->getType());
1663 // Arithmetic and Bitwise operators
1664 static const unsigned OpcodeTab[] = {
1665 PPC::ADD, PPC::SUB, PPC::AND, PPC::OR, PPC::XOR
1667 // FIXME: Convert this to the version from PPC32ISel
1668 static const unsigned ImmOpcodeTab[] = {
1669 PPC::ADDI, PPC::ADDI, PPC::ANDIo, PPC::ORI, PPC::XORI
1671 static const unsigned RImmOpcodeTab[] = {
1672 PPC::ADDI, PPC::SUBFIC, PPC::ANDIo, PPC::ORI, PPC::XORI
1675 if (Class == cFP32 || Class == cFP64) {
1676 assert(OperatorClass < 2 && "No logical ops for FP!");
1677 emitBinaryFPOperation(MBB, IP, Op0, Op1, OperatorClass, DestReg);
1681 if (Op0->getType() == Type::BoolTy) {
1682 if (OperatorClass == 3)
1683 // If this is an or of two isnan's, emit an FP comparison directly instead
1684 // of or'ing two isnan's together.
1685 if (Value *LHS = dyncastIsNan(Op0))
1686 if (Value *RHS = dyncastIsNan(Op1)) {
1687 unsigned Op0Reg = getReg(RHS, MBB, IP), Op1Reg = getReg(LHS, MBB, IP);
1688 unsigned TmpReg = makeAnotherReg(Type::IntTy);
1689 emitUCOM(MBB, IP, Op0Reg, Op1Reg);
1690 BuildMI(*MBB, IP, PPC::MFCR, TmpReg);
1691 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(TmpReg).addImm(4)
1692 .addImm(31).addImm(31);
1697 // Special case: op <const int>, Reg
1698 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op0)) {
1699 // sub 0, X -> subfic
1700 if (OperatorClass == 1 && canUseAsImmediateForOpcode(CI, 0)) {
1701 unsigned Op1r = getReg(Op1, MBB, IP);
1702 int imm = CI->getRawValue() & 0xFFFF;
1703 BuildMI(*MBB, IP, PPC::SUBFIC, 2, DestReg).addReg(Op1r).addSImm(imm);
1707 // If it is easy to do, swap the operands and emit an immediate op
1708 if (Class != cLong && OperatorClass != 1 &&
1709 canUseAsImmediateForOpcode(CI, OperatorClass)) {
1710 unsigned Op1r = getReg(Op1, MBB, IP);
1711 int imm = CI->getRawValue() & 0xFFFF;
1713 if (OperatorClass < 2)
1714 BuildMI(*MBB, IP, RImmOpcodeTab[OperatorClass], 2, DestReg).addReg(Op1r)
1717 BuildMI(*MBB, IP, RImmOpcodeTab[OperatorClass], 2, DestReg).addReg(Op1r)
1723 // Special case: op Reg, <const int>
1724 if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
1725 unsigned Op0r = getReg(Op0, MBB, IP);
1727 // xor X, -1 -> not X
1728 if (OperatorClass == 4 && Op1C->isAllOnesValue()) {
1729 BuildMI(*MBB, IP, PPC::NOR, 2, DestReg).addReg(Op0r).addReg(Op0r);
1733 if (canUseAsImmediateForOpcode(Op1C, OperatorClass)) {
1734 int immediate = Op1C->getRawValue() & 0xFFFF;
1736 if (OperatorClass < 2)
1737 BuildMI(*MBB, IP, ImmOpcodeTab[OperatorClass], 2,DestReg).addReg(Op0r)
1738 .addSImm(immediate);
1740 BuildMI(*MBB, IP, ImmOpcodeTab[OperatorClass], 2,DestReg).addReg(Op0r)
1741 .addZImm(immediate);
1743 unsigned Op1r = getReg(Op1, MBB, IP);
1744 BuildMI(*MBB, IP, OpcodeTab[OperatorClass], 2, DestReg).addReg(Op0r)
1750 // We couldn't generate an immediate variant of the op, load both halves into
1751 // registers and emit the appropriate opcode.
1752 unsigned Op0r = getReg(Op0, MBB, IP);
1753 unsigned Op1r = getReg(Op1, MBB, IP);
1754 unsigned Opcode = OpcodeTab[OperatorClass];
1755 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
1758 // ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
1759 // returns zero when the input is not exactly a power of two.
1760 static unsigned ExactLog2(unsigned Val) {
1761 if (Val == 0 || (Val & (Val-1))) return 0;
1770 /// doMultiply - Emit appropriate instructions to multiply together the
1771 /// Values Op0 and Op1, and put the result in DestReg.
1773 void PPC64ISel::doMultiply(MachineBasicBlock *MBB,
1774 MachineBasicBlock::iterator IP,
1775 unsigned DestReg, Value *Op0, Value *Op1) {
1776 unsigned Class0 = getClass(Op0->getType());
1777 unsigned Class1 = getClass(Op1->getType());
1779 unsigned Op0r = getReg(Op0, MBB, IP);
1780 unsigned Op1r = getReg(Op1, MBB, IP);
1783 if (Class0 == cLong && Class1 == cLong) {
1784 BuildMI(*MBB, IP, PPC::MULLD, 2, DestReg).addReg(Op0r).addReg(Op1r);
1788 // 64 x 32 or less, promote 32 to 64 and do a 64 x 64
1789 if (Class0 == cLong && Class1 <= cInt) {
1790 // FIXME: CLEAR or SIGN EXTEND Op1
1791 BuildMI(*MBB, IP, PPC::MULLD, 2, DestReg).addReg(Op0r).addReg(Op1r);
1796 if (Class0 <= cInt && Class1 <= cInt) {
1797 BuildMI(*MBB, IP, PPC::MULLW, 2, DestReg).addReg(Op0r).addReg(Op1r);
1801 assert(0 && "doMultiply cannot operate on unknown type!");
1804 /// doMultiplyConst - This method will multiply the value in Op0 by the
1805 /// value of the ContantInt *CI
1806 void PPC64ISel::doMultiplyConst(MachineBasicBlock *MBB,
1807 MachineBasicBlock::iterator IP,
1808 unsigned DestReg, Value *Op0, ConstantInt *CI) {
1809 unsigned Class = getClass(Op0->getType());
1812 if (CI->isNullValue()) {
1813 BuildMI(*MBB, IP, PPC::LI, 1, DestReg).addSImm(0);
1817 // Mul op0, 1 ==> op0
1818 if (CI->equalsInt(1)) {
1819 unsigned Op0r = getReg(Op0, MBB, IP);
1820 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(Op0r).addReg(Op0r);
1824 // If the element size is exactly a power of 2, use a shift to get it.
1825 if (unsigned Shift = ExactLog2(CI->getRawValue())) {
1826 ConstantUInt *ShiftCI = ConstantUInt::get(Type::UByteTy, Shift);
1827 emitShiftOperation(MBB, IP, Op0, ShiftCI, true, Op0->getType(), DestReg);
1831 // If 32 bits or less and immediate is in right range, emit mul by immediate
1832 if (Class == cByte || Class == cShort || Class == cInt) {
1833 if (canUseAsImmediateForOpcode(CI, 0)) {
1834 unsigned Op0r = getReg(Op0, MBB, IP);
1835 unsigned imm = CI->getRawValue() & 0xFFFF;
1836 BuildMI(*MBB, IP, PPC::MULLI, 2, DestReg).addReg(Op0r).addSImm(imm);
1841 doMultiply(MBB, IP, DestReg, Op0, CI);
1844 void PPC64ISel::visitMul(BinaryOperator &I) {
1845 unsigned ResultReg = getReg(I);
1847 Value *Op0 = I.getOperand(0);
1848 Value *Op1 = I.getOperand(1);
1850 MachineBasicBlock::iterator IP = BB->end();
1851 emitMultiply(BB, IP, Op0, Op1, ResultReg);
1854 void PPC64ISel::emitMultiply(MachineBasicBlock *MBB,
1855 MachineBasicBlock::iterator IP,
1856 Value *Op0, Value *Op1, unsigned DestReg) {
1857 TypeClass Class = getClass(Op0->getType());
1864 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
1865 doMultiplyConst(MBB, IP, DestReg, Op0, CI);
1867 doMultiply(MBB, IP, DestReg, Op0, Op1);
1872 emitBinaryFPOperation(MBB, IP, Op0, Op1, 2, DestReg);
1879 /// visitDivRem - Handle division and remainder instructions... these
1880 /// instruction both require the same instructions to be generated, they just
1881 /// select the result from a different register. Note that both of these
1882 /// instructions work differently for signed and unsigned operands.
1884 void PPC64ISel::visitDivRem(BinaryOperator &I) {
1885 unsigned ResultReg = getReg(I);
1886 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
1888 MachineBasicBlock::iterator IP = BB->end();
1889 emitDivRemOperation(BB, IP, Op0, Op1, I.getOpcode() == Instruction::Div,
1893 void PPC64ISel::emitDivRemOperation(MachineBasicBlock *BB,
1894 MachineBasicBlock::iterator IP,
1895 Value *Op0, Value *Op1, bool isDiv,
1896 unsigned ResultReg) {
1897 const Type *Ty = Op0->getType();
1898 unsigned Class = getClass(Ty);
1902 // Floating point divide...
1903 emitBinaryFPOperation(BB, IP, Op0, Op1, 3, ResultReg);
1906 // Floating point remainder via fmodf(float x, float y);
1907 unsigned Op0Reg = getReg(Op0, BB, IP);
1908 unsigned Op1Reg = getReg(Op1, BB, IP);
1909 MachineInstr *TheCall =
1910 BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(fmodfFn, true);
1911 std::vector<ValueRecord> Args;
1912 Args.push_back(ValueRecord(Op0Reg, Type::FloatTy));
1913 Args.push_back(ValueRecord(Op1Reg, Type::FloatTy));
1914 doCall(ValueRecord(ResultReg, Type::FloatTy), TheCall, Args, false);
1919 // Floating point divide...
1920 emitBinaryFPOperation(BB, IP, Op0, Op1, 3, ResultReg);
1923 // Floating point remainder via fmod(double x, double y);
1924 unsigned Op0Reg = getReg(Op0, BB, IP);
1925 unsigned Op1Reg = getReg(Op1, BB, IP);
1926 MachineInstr *TheCall =
1927 BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(fmodFn, true);
1928 std::vector<ValueRecord> Args;
1929 Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy));
1930 Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy));
1931 doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args, false);
1934 case cLong: case cByte: case cShort: case cInt:
1935 break; // Small integrals, handled below...
1936 default: assert(0 && "Unknown class!");
1939 // Special case signed division by power of 2.
1941 if (ConstantSInt *CI = dyn_cast<ConstantSInt>(Op1)) {
1942 assert(Class != cLong && "This doesn't handle 64-bit divides!");
1943 int V = CI->getValue();
1945 if (V == 1) { // X /s 1 => X
1946 unsigned Op0Reg = getReg(Op0, BB, IP);
1947 BuildMI(*BB, IP, PPC::OR, 2, ResultReg).addReg(Op0Reg).addReg(Op0Reg);
1951 if (V == -1) { // X /s -1 => -X
1952 unsigned Op0Reg = getReg(Op0, BB, IP);
1953 BuildMI(*BB, IP, PPC::NEG, 1, ResultReg).addReg(Op0Reg);
1957 unsigned log2V = ExactLog2(V);
1958 if (log2V != 0 && Ty->isSigned()) {
1959 unsigned Op0Reg = getReg(Op0, BB, IP);
1960 unsigned TmpReg = makeAnotherReg(Op0->getType());
1961 unsigned Opcode = Class == cLong ? PPC::SRADI : PPC::SRAWI;
1963 BuildMI(*BB, IP, Opcode, 2, TmpReg).addReg(Op0Reg).addImm(log2V);
1964 BuildMI(*BB, IP, PPC::ADDZE, 1, ResultReg).addReg(TmpReg);
1969 static const unsigned DivOpcodes[] =
1970 { PPC::DIVWU, PPC::DIVW, PPC::DIVDU, PPC::DIVD };
1972 unsigned Op0Reg = getReg(Op0, BB, IP);
1973 unsigned Op1Reg = getReg(Op1, BB, IP);
1974 unsigned Opcode = DivOpcodes[2*(Class == cLong) + Ty->isSigned()];
1977 BuildMI(*BB, IP, Opcode, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1978 } else { // Remainder
1979 unsigned TmpReg1 = makeAnotherReg(Op0->getType());
1980 unsigned TmpReg2 = makeAnotherReg(Op0->getType());
1981 unsigned MulOpcode = Class == cLong ? PPC::MULLD : PPC::MULLW;
1983 BuildMI(*BB, IP, Opcode, 2, TmpReg1).addReg(Op0Reg).addReg(Op1Reg);
1984 BuildMI(*BB, IP, MulOpcode, 2, TmpReg2).addReg(TmpReg1).addReg(Op1Reg);
1985 BuildMI(*BB, IP, PPC::SUBF, 2, ResultReg).addReg(TmpReg2).addReg(Op0Reg);
1990 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
1991 /// for constant immediate shift values, and for constant immediate
1992 /// shift values equal to 1. Even the general case is sort of special,
1993 /// because the shift amount has to be in CL, not just any old register.
1995 void PPC64ISel::visitShiftInst(ShiftInst &I) {
1996 MachineBasicBlock::iterator IP = BB->end();
1997 emitShiftOperation(BB, IP, I.getOperand(0), I.getOperand(1),
1998 I.getOpcode() == Instruction::Shl, I.getType(),
2002 /// emitShiftOperation - Common code shared between visitShiftInst and
2003 /// constant expression support.
2005 void PPC64ISel::emitShiftOperation(MachineBasicBlock *MBB,
2006 MachineBasicBlock::iterator IP,
2007 Value *Op, Value *ShiftAmount,
2008 bool isLeftShift, const Type *ResultTy,
2010 unsigned SrcReg = getReg (Op, MBB, IP);
2011 bool isSigned = ResultTy->isSigned ();
2012 unsigned Class = getClass (ResultTy);
2014 // Longs, as usual, are handled specially...
2015 if (Class == cLong) {
2016 // If we have a constant shift, we can generate much more efficient code
2017 // than otherwise...
2019 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
2020 unsigned Amount = CUI->getValue();
2021 assert(Amount < 64 && "Invalid immediate shift amount!");
2023 BuildMI(*MBB, IP, PPC::RLDICR, 3, DestReg).addReg(SrcReg).addImm(Amount)
2027 BuildMI(*MBB, IP, PPC::SRADI, 2, DestReg).addReg(SrcReg)
2030 BuildMI(*MBB, IP, PPC::RLDICL, 3, DestReg).addReg(SrcReg)
2031 .addImm(64-Amount).addImm(Amount);
2035 unsigned ShiftReg = getReg (ShiftAmount, MBB, IP);
2038 BuildMI(*MBB, IP, PPC::SLD, 2, DestReg).addReg(SrcReg).addReg(ShiftReg);
2040 unsigned Opcode = (isSigned) ? PPC::SRAD : PPC::SRD;
2041 BuildMI(*MBB, IP, Opcode, DestReg).addReg(SrcReg).addReg(ShiftReg);
2047 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
2048 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
2049 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
2050 unsigned Amount = CUI->getValue();
2053 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
2054 .addImm(Amount).addImm(0).addImm(31-Amount);
2057 BuildMI(*MBB, IP, PPC::SRAWI,2,DestReg).addReg(SrcReg).addImm(Amount);
2059 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
2060 .addImm(32-Amount).addImm(Amount).addImm(31);
2063 } else { // The shift amount is non-constant.
2064 unsigned ShiftAmountReg = getReg(ShiftAmount, MBB, IP);
2067 BuildMI(*MBB, IP, PPC::SLW, 2, DestReg).addReg(SrcReg)
2068 .addReg(ShiftAmountReg);
2070 BuildMI(*MBB, IP, isSigned ? PPC::SRAW : PPC::SRW, 2, DestReg)
2071 .addReg(SrcReg).addReg(ShiftAmountReg);
2077 /// visitLoadInst - Implement LLVM load instructions. Pretty straightforward
2078 /// mapping of LLVM classes to PPC load instructions, with the exception of
2079 /// signed byte loads, which need a sign extension following them.
2081 void PPC64ISel::visitLoadInst(LoadInst &I) {
2082 // Immediate opcodes, for reg+imm addressing
2083 static const unsigned ImmOpcodes[] = {
2084 PPC::LBZ, PPC::LHZ, PPC::LWZ,
2085 PPC::LFS, PPC::LFD, PPC::LWZ
2087 // Indexed opcodes, for reg+reg addressing
2088 static const unsigned IdxOpcodes[] = {
2089 PPC::LBZX, PPC::LHZX, PPC::LWZX,
2090 PPC::LFSX, PPC::LFDX, PPC::LWZX
2093 unsigned Class = getClassB(I.getType());
2094 unsigned ImmOpcode = ImmOpcodes[Class];
2095 unsigned IdxOpcode = IdxOpcodes[Class];
2096 unsigned DestReg = getReg(I);
2097 Value *SourceAddr = I.getOperand(0);
2099 if (Class == cShort && I.getType()->isSigned()) ImmOpcode = PPC::LHA;
2100 if (Class == cShort && I.getType()->isSigned()) IdxOpcode = PPC::LHAX;
2102 if (AllocaInst *AI = dyn_castFixedAlloca(SourceAddr)) {
2103 unsigned FI = getFixedSizedAllocaFI(AI);
2104 if (Class == cByte && I.getType()->isSigned()) {
2105 unsigned TmpReg = makeAnotherReg(I.getType());
2106 addFrameReference(BuildMI(BB, ImmOpcode, 2, TmpReg), FI);
2107 BuildMI(BB, PPC::EXTSB, 1, DestReg).addReg(TmpReg);
2109 addFrameReference(BuildMI(BB, ImmOpcode, 2, DestReg), FI);
2114 // If this load is the only use of the GEP instruction that is its address,
2115 // then we can fold the GEP directly into the load instruction.
2116 // emitGEPOperation with a second to last arg of 'true' will place the
2117 // base register for the GEP into baseReg, and the constant offset from that
2118 // into offset. If the offset fits in 16 bits, we can emit a reg+imm store
2119 // otherwise, we copy the offset into another reg, and use reg+reg addressing.
2120 if (GetElementPtrInst *GEPI = canFoldGEPIntoLoadOrStore(SourceAddr)) {
2121 unsigned baseReg = getReg(GEPI);
2122 unsigned pendingAdd;
2123 ConstantSInt *offset;
2125 emitGEPOperation(BB, BB->end(), GEPI->getOperand(0), GEPI->op_begin()+1,
2126 GEPI->op_end(), baseReg, true, &offset, &pendingAdd);
2128 if (pendingAdd == 0 && Class != cLong &&
2129 canUseAsImmediateForOpcode(offset, 0)) {
2130 if (Class == cByte && I.getType()->isSigned()) {
2131 unsigned TmpReg = makeAnotherReg(I.getType());
2132 BuildMI(BB, ImmOpcode, 2, TmpReg).addSImm(offset->getValue())
2134 BuildMI(BB, PPC::EXTSB, 1, DestReg).addReg(TmpReg);
2136 BuildMI(BB, ImmOpcode, 2, DestReg).addSImm(offset->getValue())
2142 unsigned indexReg = (pendingAdd != 0) ? pendingAdd : getReg(offset);
2144 if (Class == cByte && I.getType()->isSigned()) {
2145 unsigned TmpReg = makeAnotherReg(I.getType());
2146 BuildMI(BB, IdxOpcode, 2, TmpReg).addReg(indexReg).addReg(baseReg);
2147 BuildMI(BB, PPC::EXTSB, 1, DestReg).addReg(TmpReg);
2149 BuildMI(BB, IdxOpcode, 2, DestReg).addReg(indexReg).addReg(baseReg);
2154 // The fallback case, where the load was from a source that could not be
2155 // folded into the load instruction.
2156 unsigned SrcAddrReg = getReg(SourceAddr);
2158 if (Class == cByte && I.getType()->isSigned()) {
2159 unsigned TmpReg = makeAnotherReg(I.getType());
2160 BuildMI(BB, ImmOpcode, 2, TmpReg).addSImm(0).addReg(SrcAddrReg);
2161 BuildMI(BB, PPC::EXTSB, 1, DestReg).addReg(TmpReg);
2163 BuildMI(BB, ImmOpcode, 2, DestReg).addSImm(0).addReg(SrcAddrReg);
2167 /// visitStoreInst - Implement LLVM store instructions
2169 void PPC64ISel::visitStoreInst(StoreInst &I) {
2170 // Immediate opcodes, for reg+imm addressing
2171 static const unsigned ImmOpcodes[] = {
2172 PPC::STB, PPC::STH, PPC::STW,
2173 PPC::STFS, PPC::STFD, PPC::STW
2175 // Indexed opcodes, for reg+reg addressing
2176 static const unsigned IdxOpcodes[] = {
2177 PPC::STBX, PPC::STHX, PPC::STWX,
2178 PPC::STFSX, PPC::STFDX, PPC::STWX
2181 Value *SourceAddr = I.getOperand(1);
2182 const Type *ValTy = I.getOperand(0)->getType();
2183 unsigned Class = getClassB(ValTy);
2184 unsigned ImmOpcode = ImmOpcodes[Class];
2185 unsigned IdxOpcode = IdxOpcodes[Class];
2186 unsigned ValReg = getReg(I.getOperand(0));
2188 // If this store is the only use of the GEP instruction that is its address,
2189 // then we can fold the GEP directly into the store instruction.
2190 // emitGEPOperation with a second to last arg of 'true' will place the
2191 // base register for the GEP into baseReg, and the constant offset from that
2192 // into offset. If the offset fits in 16 bits, we can emit a reg+imm store
2193 // otherwise, we copy the offset into another reg, and use reg+reg addressing.
2194 if (GetElementPtrInst *GEPI = canFoldGEPIntoLoadOrStore(SourceAddr)) {
2195 unsigned baseReg = getReg(GEPI);
2196 unsigned pendingAdd;
2197 ConstantSInt *offset;
2199 emitGEPOperation(BB, BB->end(), GEPI->getOperand(0), GEPI->op_begin()+1,
2200 GEPI->op_end(), baseReg, true, &offset, &pendingAdd);
2202 if (0 == pendingAdd && Class != cLong &&
2203 canUseAsImmediateForOpcode(offset, 0)) {
2204 BuildMI(BB, ImmOpcode, 3).addReg(ValReg).addSImm(offset->getValue())
2209 unsigned indexReg = (pendingAdd != 0) ? pendingAdd : getReg(offset);
2210 BuildMI(BB, IdxOpcode, 3).addReg(ValReg).addReg(indexReg).addReg(baseReg);
2214 // If the store address wasn't the only use of a GEP, we fall back to the
2215 // standard path: store the ValReg at the value in AddressReg.
2216 unsigned AddressReg = getReg(I.getOperand(1));
2217 BuildMI(BB, ImmOpcode, 3).addReg(ValReg).addSImm(0).addReg(AddressReg);
2221 /// visitCastInst - Here we have various kinds of copying with or without sign
2222 /// extension going on.
2224 void PPC64ISel::visitCastInst(CastInst &CI) {
2225 Value *Op = CI.getOperand(0);
2227 unsigned SrcClass = getClassB(Op->getType());
2228 unsigned DestClass = getClassB(CI.getType());
2230 // If this is a cast from a 32-bit integer to a Long type, and the only uses
2231 // of the case are GEP instructions, then the cast does not need to be
2232 // generated explicitly, it will be folded into the GEP.
2233 if (DestClass == cLong && SrcClass == cInt) {
2234 bool AllUsesAreGEPs = true;
2235 for (Value::use_iterator I = CI.use_begin(), E = CI.use_end(); I != E; ++I)
2236 if (!isa<GetElementPtrInst>(*I)) {
2237 AllUsesAreGEPs = false;
2241 // No need to codegen this cast if all users are getelementptr instrs...
2242 if (AllUsesAreGEPs) return;
2245 unsigned DestReg = getReg(CI);
2246 MachineBasicBlock::iterator MI = BB->end();
2247 emitCastOperation(BB, MI, Op, CI.getType(), DestReg);
2250 /// emitCastOperation - Common code shared between visitCastInst and constant
2251 /// expression cast support.
2253 void PPC64ISel::emitCastOperation(MachineBasicBlock *MBB,
2254 MachineBasicBlock::iterator IP,
2255 Value *Src, const Type *DestTy,
2257 const Type *SrcTy = Src->getType();
2258 unsigned SrcClass = getClassB(SrcTy);
2259 unsigned DestClass = getClassB(DestTy);
2260 unsigned SrcReg = getReg(Src, MBB, IP);
2262 // Implement casts to bool by using compare on the operand followed by set if
2263 // not zero on the result.
2264 if (DestTy == Type::BoolTy) {
2270 unsigned TmpReg = makeAnotherReg(Type::IntTy);
2271 BuildMI(*MBB, IP, PPC::ADDIC, 2, TmpReg).addReg(SrcReg).addSImm(-1);
2272 BuildMI(*MBB, IP, PPC::SUBFE, 2, DestReg).addReg(TmpReg).addReg(SrcReg);
2278 std::cerr << "ERROR: Cast fp-to-bool not implemented!\n";
2284 // Handle cast of Float -> Double
2285 if (SrcClass == cFP32 && DestClass == cFP64) {
2286 BuildMI(*MBB, IP, PPC::FMR, 1, DestReg).addReg(SrcReg);
2290 // Handle cast of Double -> Float
2291 if (SrcClass == cFP64 && DestClass == cFP32) {
2292 BuildMI(*MBB, IP, PPC::FRSP, 1, DestReg).addReg(SrcReg);
2296 // Handle casts from integer to floating point now...
2297 if (DestClass == cFP32 || DestClass == cFP64) {
2299 // Spill the integer to memory and reload it from there.
2300 unsigned TmpReg = makeAnotherReg(Type::DoubleTy);
2302 F->getFrameInfo()->CreateStackObject(Type::DoubleTy, TM.getTargetData());
2304 if (SrcClass == cLong) {
2305 if (SrcTy->isSigned()) {
2306 addFrameReference(BuildMI(*MBB, IP, PPC::STD, 3).addReg(SrcReg),
2308 addFrameReference(BuildMI(*MBB, IP, PPC::LFD, 2, TmpReg),
2310 BuildMI(*MBB, IP, PPC::FCFID, 1, DestReg).addReg(TmpReg);
2312 unsigned Scale = getReg(ConstantFP::get(Type::DoubleTy, 0x1p32));
2313 unsigned TmpHi = makeAnotherReg(Type::IntTy);
2314 unsigned TmpLo = makeAnotherReg(Type::IntTy);
2315 unsigned FPLow = makeAnotherReg(Type::DoubleTy);
2316 unsigned FPTmpHi = makeAnotherReg(Type::DoubleTy);
2317 unsigned FPTmpLo = makeAnotherReg(Type::DoubleTy);
2318 int OtherFrameIdx = F->getFrameInfo()->CreateStackObject(Type::DoubleTy,
2319 TM.getTargetData());
2320 BuildMI(*MBB, IP, PPC::RLDICL, 3, TmpHi).addReg(SrcReg).addImm(32)
2322 BuildMI(*MBB, IP, PPC::RLDICL, 3, TmpLo).addReg(SrcReg).addImm(0)
2324 addFrameReference(BuildMI(*MBB, IP, PPC::STD, 3).addReg(TmpHi),
2326 addFrameReference(BuildMI(*MBB, IP, PPC::STD, 3).addReg(TmpLo),
2328 addFrameReference(BuildMI(*MBB, IP, PPC::LFD, 2, TmpReg),
2330 addFrameReference(BuildMI(*MBB, IP, PPC::LFD, 2, FPLow),
2332 BuildMI(*MBB, IP, PPC::FCFID, 1, FPTmpHi).addReg(TmpReg);
2333 BuildMI(*MBB, IP, PPC::FCFID, 1, FPTmpLo).addReg(FPLow);
2334 BuildMI(*MBB, IP, PPC::FMADD, 3, DestReg).addReg(Scale).addReg(FPTmpHi)
2340 // FIXME: really want a promote64
2341 unsigned IntTmp = makeAnotherReg(Type::IntTy);
2343 if (SrcTy->isSigned())
2344 BuildMI(*MBB, IP, PPC::EXTSW, 1, IntTmp).addReg(SrcReg);
2346 BuildMI(*MBB, IP, PPC::RLDICL, 3, IntTmp).addReg(SrcReg).addImm(0)
2348 addFrameReference(BuildMI(*MBB, IP, PPC::STD, 3).addReg(IntTmp),
2350 addFrameReference(BuildMI(*MBB, IP, PPC::LFD, 2, TmpReg),
2352 BuildMI(*MBB, IP, PPC::FCFID, 1, DestReg).addReg(TmpReg);
2356 // Handle casts from floating point to integer now...
2357 if (SrcClass == cFP32 || SrcClass == cFP64) {
2358 static Function* const Funcs[] =
2359 { __fixsfdiFn, __fixdfdiFn, __fixunssfdiFn, __fixunsdfdiFn };
2360 // emit library call
2361 if (DestClass == cLong) {
2362 bool isDouble = SrcClass == cFP64;
2363 unsigned nameIndex = 2 * DestTy->isSigned() + isDouble;
2364 std::vector<ValueRecord> Args;
2365 Args.push_back(ValueRecord(SrcReg, SrcTy));
2366 Function *floatFn = Funcs[nameIndex];
2367 MachineInstr *TheCall =
2368 BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(floatFn, true);
2369 doCall(ValueRecord(DestReg, DestTy), TheCall, Args, false);
2374 F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
2376 if (DestTy->isSigned()) {
2377 unsigned TempReg = makeAnotherReg(Type::DoubleTy);
2379 // Convert to integer in the FP reg and store it to a stack slot
2380 BuildMI(*BB, IP, PPC::FCTIWZ, 1, TempReg).addReg(SrcReg);
2381 addFrameReference(BuildMI(*BB, IP, PPC::STFD, 3)
2382 .addReg(TempReg), ValueFrameIdx);
2384 // There is no load signed byte opcode, so we must emit a sign extend for
2385 // that particular size. Make sure to source the new integer from the
2387 if (DestClass == cByte) {
2388 unsigned TempReg2 = makeAnotherReg(DestTy);
2389 addFrameReference(BuildMI(*BB, IP, PPC::LBZ, 2, TempReg2),
2391 BuildMI(*MBB, IP, PPC::EXTSB, DestReg).addReg(TempReg2);
2393 int offset = (DestClass == cShort) ? 6 : 4;
2394 unsigned LoadOp = (DestClass == cShort) ? PPC::LHA : PPC::LWZ;
2395 addFrameReference(BuildMI(*BB, IP, LoadOp, 2, DestReg),
2396 ValueFrameIdx, offset);
2399 unsigned Zero = getReg(ConstantFP::get(Type::DoubleTy, 0.0f));
2400 double maxInt = (1LL << 32) - 1;
2401 unsigned MaxInt = getReg(ConstantFP::get(Type::DoubleTy, maxInt));
2402 double border = 1LL << 31;
2403 unsigned Border = getReg(ConstantFP::get(Type::DoubleTy, border));
2404 unsigned UseZero = makeAnotherReg(Type::DoubleTy);
2405 unsigned UseMaxInt = makeAnotherReg(Type::DoubleTy);
2406 unsigned UseChoice = makeAnotherReg(Type::DoubleTy);
2407 unsigned TmpReg = makeAnotherReg(Type::DoubleTy);
2408 unsigned TmpReg2 = makeAnotherReg(Type::DoubleTy);
2409 unsigned ConvReg = makeAnotherReg(Type::DoubleTy);
2410 unsigned IntTmp = makeAnotherReg(Type::IntTy);
2411 unsigned XorReg = makeAnotherReg(Type::IntTy);
2413 F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
2414 // Update machine-CFG edges
2415 MachineBasicBlock *XorMBB = new MachineBasicBlock(BB->getBasicBlock());
2416 MachineBasicBlock *PhiMBB = new MachineBasicBlock(BB->getBasicBlock());
2417 MachineBasicBlock *OldMBB = BB;
2418 ilist<MachineBasicBlock>::iterator It = BB; ++It;
2419 F->getBasicBlockList().insert(It, XorMBB);
2420 F->getBasicBlockList().insert(It, PhiMBB);
2421 BB->addSuccessor(XorMBB);
2422 BB->addSuccessor(PhiMBB);
2424 // Convert from floating point to unsigned 32-bit value
2425 // Use 0 if incoming value is < 0.0
2426 BuildMI(*BB, IP, PPC::FSEL, 3, UseZero).addReg(SrcReg).addReg(SrcReg)
2428 // Use 2**32 - 1 if incoming value is >= 2**32
2429 BuildMI(*BB, IP, PPC::FSUB, 2, UseMaxInt).addReg(MaxInt).addReg(SrcReg);
2430 BuildMI(*BB, IP, PPC::FSEL, 3, UseChoice).addReg(UseMaxInt)
2431 .addReg(UseZero).addReg(MaxInt);
2433 BuildMI(*BB, IP, PPC::FSUB, 2, TmpReg).addReg(UseChoice).addReg(Border);
2434 // Use difference if >= 2**31
2435 BuildMI(*BB, IP, PPC::FCMPU, 2, PPC::CR0).addReg(UseChoice)
2437 BuildMI(*BB, IP, PPC::FSEL, 3, TmpReg2).addReg(TmpReg).addReg(TmpReg)
2439 // Convert to integer
2440 BuildMI(*BB, IP, PPC::FCTIWZ, 1, ConvReg).addReg(TmpReg2);
2441 addFrameReference(BuildMI(*BB, IP, PPC::STFD, 3).addReg(ConvReg),
2443 if (DestClass == cByte) {
2444 addFrameReference(BuildMI(*BB, IP, PPC::LBZ, 2, DestReg),
2446 } else if (DestClass == cShort) {
2447 addFrameReference(BuildMI(*BB, IP, PPC::LHZ, 2, DestReg),
2449 } if (DestClass == cInt) {
2450 addFrameReference(BuildMI(*BB, IP, PPC::LWZ, 2, IntTmp),
2452 BuildMI(*BB, IP, PPC::BLT, 2).addReg(PPC::CR0).addMBB(PhiMBB);
2453 BuildMI(*BB, IP, PPC::B, 1).addMBB(XorMBB);
2456 // add 2**31 if input was >= 2**31
2458 BuildMI(BB, PPC::XORIS, 2, XorReg).addReg(IntTmp).addImm(0x8000);
2459 XorMBB->addSuccessor(PhiMBB);
2462 // DestReg = phi [ IntTmp, OldMBB ], [ XorReg, XorMBB ]
2464 BuildMI(BB, PPC::PHI, 4, DestReg).addReg(IntTmp).addMBB(OldMBB)
2465 .addReg(XorReg).addMBB(XorMBB);
2471 // Check our invariants
2472 assert((SrcClass <= cInt || SrcClass == cLong) &&
2473 "Unhandled source class for cast operation!");
2474 assert((DestClass <= cInt || DestClass == cLong) &&
2475 "Unhandled destination class for cast operation!");
2477 bool sourceUnsigned = SrcTy->isUnsigned() || SrcTy == Type::BoolTy;
2478 bool destUnsigned = DestTy->isUnsigned();
2480 // Unsigned -> Unsigned, clear if larger
2481 if (sourceUnsigned && destUnsigned) {
2482 // handle long dest class now to keep switch clean
2483 if (DestClass == cLong) {
2484 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2488 // handle u{ byte, short, int } x u{ byte, short, int }
2489 unsigned clearBits = (SrcClass == cByte || DestClass == cByte) ? 24 : 16;
2493 if (SrcClass == DestClass)
2494 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2496 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
2497 .addImm(0).addImm(clearBits).addImm(31);
2501 if (DestClass == cInt)
2502 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2504 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
2505 .addImm(0).addImm(clearBits).addImm(31);
2512 if (!sourceUnsigned && !destUnsigned) {
2513 // handle long dest class now to keep switch clean
2514 if (DestClass == cLong) {
2515 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2519 // handle { byte, short, int } x { byte, short, int }
2522 if (DestClass == cByte)
2523 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2525 BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
2528 if (DestClass == cByte)
2529 BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
2530 else if (DestClass == cShort)
2531 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2533 BuildMI(*MBB, IP, PPC::EXTSH, 1, DestReg).addReg(SrcReg);
2537 if (DestClass == cByte)
2538 BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
2539 else if (DestClass == cShort)
2540 BuildMI(*MBB, IP, PPC::EXTSH, 1, DestReg).addReg(SrcReg);
2542 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2548 // Unsigned -> Signed
2549 if (sourceUnsigned && !destUnsigned) {
2550 // handle long dest class now to keep switch clean
2551 if (DestClass == cLong) {
2552 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2556 // handle u{ byte, short, int } -> { byte, short, int }
2559 if (DestClass == cByte)
2560 // uByte 255 -> signed byte == -1
2561 BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
2563 // uByte 255 -> signed short/int == 255
2564 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg).addImm(0)
2565 .addImm(24).addImm(31);
2568 if (DestClass == cByte)
2569 BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
2570 else if (DestClass == cShort)
2571 BuildMI(*MBB, IP, PPC::EXTSH, 1, DestReg).addReg(SrcReg);
2573 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg).addImm(0)
2574 .addImm(16).addImm(31);
2578 if (DestClass == cByte)
2579 BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
2580 else if (DestClass == cShort)
2581 BuildMI(*MBB, IP, PPC::EXTSH, 1, DestReg).addReg(SrcReg);
2583 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2589 // Signed -> Unsigned
2590 if (!sourceUnsigned && destUnsigned) {
2591 // handle long dest class now to keep switch clean
2592 if (DestClass == cLong) {
2593 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2597 // handle { byte, short, int } -> u{ byte, short, int }
2598 unsigned clearBits = (DestClass == cByte) ? 24 : 16;
2602 if (DestClass == cByte || DestClass == cShort)
2603 // sbyte -1 -> ubyte 0x000000FF
2604 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
2605 .addImm(0).addImm(clearBits).addImm(31);
2607 // sbyte -1 -> ubyte 0xFFFFFFFF
2608 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2612 if (DestClass == cInt)
2613 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2615 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
2616 .addImm(0).addImm(clearBits).addImm(31);
2622 // Anything we haven't handled already, we can't (yet) handle at all.
2623 std::cerr << "Unhandled cast from " << SrcTy->getDescription()
2624 << "to " << DestTy->getDescription() << '\n';
2628 /// visitVANextInst - Implement the va_next instruction...
2630 void PPC64ISel::visitVANextInst(VANextInst &I) {
2631 unsigned VAList = getReg(I.getOperand(0));
2632 unsigned DestReg = getReg(I);
2635 switch (I.getArgType()->getTypeID()) {
2638 assert(0 && "Error: bad type for va_next instruction!");
2640 case Type::PointerTyID:
2641 case Type::UIntTyID:
2645 case Type::ULongTyID:
2646 case Type::LongTyID:
2647 case Type::DoubleTyID:
2652 // Increment the VAList pointer...
2653 BuildMI(BB, PPC::ADDI, 2, DestReg).addReg(VAList).addSImm(Size);
2656 void PPC64ISel::visitVAArgInst(VAArgInst &I) {
2657 unsigned VAList = getReg(I.getOperand(0));
2658 unsigned DestReg = getReg(I);
2660 switch (I.getType()->getTypeID()) {
2663 assert(0 && "Error: bad type for va_next instruction!");
2665 case Type::PointerTyID:
2666 case Type::UIntTyID:
2668 BuildMI(BB, PPC::LWZ, 2, DestReg).addSImm(0).addReg(VAList);
2670 case Type::ULongTyID:
2671 case Type::LongTyID:
2672 BuildMI(BB, PPC::LD, 2, DestReg).addSImm(0).addReg(VAList);
2674 case Type::FloatTyID:
2675 BuildMI(BB, PPC::LFS, 2, DestReg).addSImm(0).addReg(VAList);
2677 case Type::DoubleTyID:
2678 BuildMI(BB, PPC::LFD, 2, DestReg).addSImm(0).addReg(VAList);
2683 /// visitGetElementPtrInst - instruction-select GEP instructions
2685 void PPC64ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
2686 if (canFoldGEPIntoLoadOrStore(&I))
2689 unsigned outputReg = getReg(I);
2690 emitGEPOperation(BB, BB->end(), I.getOperand(0), I.op_begin()+1, I.op_end(),
2691 outputReg, false, 0, 0);
2694 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
2695 /// constant expression GEP support.
2697 void PPC64ISel::emitGEPOperation(MachineBasicBlock *MBB,
2698 MachineBasicBlock::iterator IP,
2699 Value *Src, User::op_iterator IdxBegin,
2700 User::op_iterator IdxEnd, unsigned TargetReg,
2701 bool GEPIsFolded, ConstantSInt **RemainderPtr,
2702 unsigned *PendingAddReg) {
2703 const TargetData &TD = TM.getTargetData();
2704 const Type *Ty = Src->getType();
2705 unsigned basePtrReg = getReg(Src, MBB, IP);
2706 int64_t constValue = 0;
2708 // Record the operations to emit the GEP in a vector so that we can emit them
2709 // after having analyzed the entire instruction.
2710 std::vector<CollapsedGepOp> ops;
2712 // GEPs have zero or more indices; we must perform a struct access
2713 // or array access for each one.
2714 for (GetElementPtrInst::op_iterator oi = IdxBegin, oe = IdxEnd; oi != oe;
2717 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2718 // It's a struct access. idx is the index into the structure,
2719 // which names the field. Use the TargetData structure to
2720 // pick out what the layout of the structure is in memory.
2721 // Use the (constant) structure index's value to find the
2722 // right byte offset from the StructLayout class's list of
2723 // structure member offsets.
2724 unsigned fieldIndex = cast<ConstantUInt>(idx)->getValue();
2725 unsigned memberOffset =
2726 TD.getStructLayout(StTy)->MemberOffsets[fieldIndex];
2728 // StructType member offsets are always constant values. Add it to the
2730 constValue += memberOffset;
2732 // The next type is the member of the structure selected by the
2734 Ty = StTy->getElementType (fieldIndex);
2735 } else if (const SequentialType *SqTy = dyn_cast<SequentialType> (Ty)) {
2736 // Many GEP instructions use a [cast (int/uint) to LongTy] as their
2737 // operand. Handle this case directly now...
2738 if (CastInst *CI = dyn_cast<CastInst>(idx))
2739 if (CI->getOperand(0)->getType() == Type::IntTy ||
2740 CI->getOperand(0)->getType() == Type::UIntTy)
2741 idx = CI->getOperand(0);
2743 // It's an array or pointer access: [ArraySize x ElementType].
2744 // We want to add basePtrReg to (idxReg * sizeof ElementType). First, we
2745 // must find the size of the pointed-to type (Not coincidentally, the next
2746 // type is the type of the elements in the array).
2747 Ty = SqTy->getElementType();
2748 unsigned elementSize = TD.getTypeSize(Ty);
2750 if (ConstantInt *C = dyn_cast<ConstantInt>(idx)) {
2751 if (ConstantSInt *CS = dyn_cast<ConstantSInt>(C))
2752 constValue += CS->getValue() * elementSize;
2753 else if (ConstantUInt *CU = dyn_cast<ConstantUInt>(C))
2754 constValue += CU->getValue() * elementSize;
2756 assert(0 && "Invalid ConstantInt GEP index type!");
2758 // Push current gep state to this point as an add
2759 ops.push_back(CollapsedGepOp(false, 0,
2760 ConstantSInt::get(Type::IntTy,constValue)));
2762 // Push multiply gep op and reset constant value
2763 ops.push_back(CollapsedGepOp(true, idx,
2764 ConstantSInt::get(Type::IntTy, elementSize)));
2770 // Emit instructions for all the collapsed ops
2771 bool pendingAdd = false;
2772 unsigned pendingAddReg = 0;
2774 for(std::vector<CollapsedGepOp>::iterator cgo_i = ops.begin(),
2775 cgo_e = ops.end(); cgo_i != cgo_e; ++cgo_i) {
2776 CollapsedGepOp& cgo = *cgo_i;
2777 unsigned nextBasePtrReg = makeAnotherReg(Type::IntTy);
2779 // If we didn't emit an add last time through the loop, we need to now so
2780 // that the base reg is updated appropriately.
2782 assert(pendingAddReg != 0 && "Uninitialized register in pending add!");
2783 BuildMI(*MBB, IP, PPC::ADD, 2, nextBasePtrReg).addReg(basePtrReg)
2784 .addReg(pendingAddReg);
2785 basePtrReg = nextBasePtrReg;
2786 nextBasePtrReg = makeAnotherReg(Type::IntTy);
2792 // We know the elementSize is a constant, so we can emit a constant mul
2793 unsigned TmpReg = makeAnotherReg(Type::IntTy);
2794 doMultiplyConst(MBB, IP, nextBasePtrReg, cgo.index, cgo.size);
2795 pendingAddReg = basePtrReg;
2798 // Try and generate an immediate addition if possible
2799 if (cgo.size->isNullValue()) {
2800 BuildMI(*MBB, IP, PPC::OR, 2, nextBasePtrReg).addReg(basePtrReg)
2801 .addReg(basePtrReg);
2802 } else if (canUseAsImmediateForOpcode(cgo.size, 0)) {
2803 BuildMI(*MBB, IP, PPC::ADDI, 2, nextBasePtrReg).addReg(basePtrReg)
2804 .addSImm(cgo.size->getValue());
2806 unsigned Op1r = getReg(cgo.size, MBB, IP);
2807 BuildMI(*MBB, IP, PPC::ADD, 2, nextBasePtrReg).addReg(basePtrReg)
2812 basePtrReg = nextBasePtrReg;
2814 // Add the current base register plus any accumulated constant value
2815 ConstantSInt *remainder = ConstantSInt::get(Type::IntTy, constValue);
2817 // If we are emitting this during a fold, copy the current base register to
2818 // the target, and save the current constant offset so the folding load or
2819 // store can try and use it as an immediate.
2821 // If this is a folded GEP and the last element was an index, then we need
2822 // to do some extra work to turn a shift/add/stw into a shift/stwx
2823 if (pendingAdd && 0 == remainder->getValue()) {
2824 assert(pendingAddReg != 0 && "Uninitialized register in pending add!");
2825 *PendingAddReg = pendingAddReg;
2829 unsigned nextBasePtrReg = makeAnotherReg(Type::IntTy);
2830 assert(pendingAddReg != 0 && "Uninitialized register in pending add!");
2831 BuildMI(*MBB, IP, PPC::ADD, 2, nextBasePtrReg).addReg(basePtrReg)
2832 .addReg(pendingAddReg);
2833 basePtrReg = nextBasePtrReg;
2836 BuildMI (*MBB, IP, PPC::OR, 2, TargetReg).addReg(basePtrReg)
2837 .addReg(basePtrReg);
2838 *RemainderPtr = remainder;
2842 // If we still have a pending add at this point, emit it now
2844 unsigned TmpReg = makeAnotherReg(Type::IntTy);
2845 BuildMI(*MBB, IP, PPC::ADD, 2, TmpReg).addReg(pendingAddReg)
2846 .addReg(basePtrReg);
2847 basePtrReg = TmpReg;
2850 // After we have processed all the indices, the result is left in
2851 // basePtrReg. Move it to the register where we were expected to
2853 if (remainder->isNullValue()) {
2854 BuildMI (*MBB, IP, PPC::OR, 2, TargetReg).addReg(basePtrReg)
2855 .addReg(basePtrReg);
2856 } else if (canUseAsImmediateForOpcode(remainder, 0)) {
2857 BuildMI(*MBB, IP, PPC::ADDI, 2, TargetReg).addReg(basePtrReg)
2858 .addSImm(remainder->getValue());
2860 unsigned Op1r = getReg(remainder, MBB, IP);
2861 BuildMI(*MBB, IP, PPC::ADD, 2, TargetReg).addReg(basePtrReg).addReg(Op1r);
2865 /// visitAllocaInst - If this is a fixed size alloca, allocate space from the
2866 /// frame manager, otherwise do it the hard way.
2868 void PPC64ISel::visitAllocaInst(AllocaInst &I) {
2869 // If this is a fixed size alloca in the entry block for the function, we
2870 // statically stack allocate the space, so we don't need to do anything here.
2872 if (dyn_castFixedAlloca(&I)) return;
2874 // Find the data size of the alloca inst's getAllocatedType.
2875 const Type *Ty = I.getAllocatedType();
2876 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
2878 // Create a register to hold the temporary result of multiplying the type size
2879 // constant by the variable amount.
2880 unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
2882 // TotalSizeReg = mul <numelements>, <TypeSize>
2883 MachineBasicBlock::iterator MBBI = BB->end();
2884 ConstantUInt *CUI = ConstantUInt::get(Type::UIntTy, TySize);
2885 doMultiplyConst(BB, MBBI, TotalSizeReg, I.getArraySize(), CUI);
2887 // AddedSize = add <TotalSizeReg>, 15
2888 unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy);
2889 BuildMI(BB, PPC::ADDI, 2, AddedSizeReg).addReg(TotalSizeReg).addSImm(15);
2891 // AlignedSize = and <AddedSize>, ~15
2892 unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
2893 BuildMI(BB, PPC::RLWINM, 4, AlignedSize).addReg(AddedSizeReg).addImm(0)
2894 .addImm(0).addImm(27);
2896 // Subtract size from stack pointer, thereby allocating some space.
2897 BuildMI(BB, PPC::SUB, 2, PPC::R1).addReg(PPC::R1).addReg(AlignedSize);
2899 // Put a pointer to the space into the result register, by copying
2900 // the stack pointer.
2901 BuildMI(BB, PPC::OR, 2, getReg(I)).addReg(PPC::R1).addReg(PPC::R1);
2903 // Inform the Frame Information that we have just allocated a variable-sized
2905 F->getFrameInfo()->CreateVariableSizedObject();
2908 /// visitMallocInst - Malloc instructions are code generated into direct calls
2909 /// to the library malloc.
2911 void PPC64ISel::visitMallocInst(MallocInst &I) {
2912 unsigned AllocSize = TM.getTargetData().getTypeSize(I.getAllocatedType());
2915 if (ConstantUInt *C = dyn_cast<ConstantUInt>(I.getOperand(0))) {
2916 Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize));
2918 Arg = makeAnotherReg(Type::UIntTy);
2919 MachineBasicBlock::iterator MBBI = BB->end();
2920 ConstantUInt *CUI = ConstantUInt::get(Type::UIntTy, AllocSize);
2921 doMultiplyConst(BB, MBBI, Arg, I.getOperand(0), CUI);
2924 std::vector<ValueRecord> Args;
2925 Args.push_back(ValueRecord(Arg, Type::UIntTy));
2926 MachineInstr *TheCall =
2927 BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(mallocFn, true);
2928 doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args, false);
2932 /// visitFreeInst - Free instructions are code gen'd to call the free libc
2935 void PPC64ISel::visitFreeInst(FreeInst &I) {
2936 std::vector<ValueRecord> Args;
2937 Args.push_back(ValueRecord(I.getOperand(0)));
2938 MachineInstr *TheCall =
2939 BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(freeFn, true);
2940 doCall(ValueRecord(0, Type::VoidTy), TheCall, Args, false);
2943 /// createPPC64ISelSimple - This pass converts an LLVM function into a machine
2944 /// code representation is a very simple peep-hole fashion.
2946 FunctionPass *llvm::createPPC64ISelSimple(TargetMachine &TM) {
2947 return new PPC64ISel(TM);