1 //===-- PPC64ISelSimple.cpp - A simple instruction selector for PowerPC ---===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "isel"
12 #include "PowerPCInstrBuilder.h"
13 #include "PowerPCInstrInfo.h"
14 #include "PPC64TargetMachine.h"
15 #include "llvm/Constants.h"
16 #include "llvm/DerivedTypes.h"
17 #include "llvm/Function.h"
18 #include "llvm/Instructions.h"
19 #include "llvm/Pass.h"
20 #include "llvm/CodeGen/IntrinsicLowering.h"
21 #include "llvm/CodeGen/MachineConstantPool.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/SSARegMap.h"
25 #include "llvm/Target/MRegisterInfo.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Support/GetElementPtrTypeIterator.h"
28 #include "llvm/Support/InstVisitor.h"
29 #include "Support/Debug.h"
30 #include "Support/Statistic.h"
35 Statistic<> GEPFolds("ppc64-codegen", "Number of GEPs folded");
37 /// TypeClass - Used by the PowerPC backend to group LLVM types by their basic
38 /// PPC Representation.
41 cByte, cShort, cInt, cFP32, cFP64, cLong
45 /// getClass - Turn a primitive type into a "class" number which is based on the
46 /// size of the type, and whether or not it is floating point.
48 static inline TypeClass getClass(const Type *Ty) {
49 switch (Ty->getTypeID()) {
51 case Type::UByteTyID: return cByte; // Byte operands are class #0
53 case Type::UShortTyID: return cShort; // Short operands are class #1
55 case Type::UIntTyID: return cInt; // Ints are class #2
57 case Type::FloatTyID: return cFP32; // Single float is #3
58 case Type::DoubleTyID: return cFP64; // Double Point is #4
60 case Type::PointerTyID:
62 case Type::ULongTyID: return cLong; // Longs and pointers are class #5
64 assert(0 && "Invalid type to getClass!");
65 return cByte; // not reached
69 // getClassB - Just like getClass, but treat boolean values as ints.
70 static inline TypeClass getClassB(const Type *Ty) {
71 if (Ty == Type::BoolTy) return cInt;
76 struct ISel : public FunctionPass, InstVisitor<ISel> {
77 PPC64TargetMachine &TM;
78 MachineFunction *F; // The function we are compiling into
79 MachineBasicBlock *BB; // The current MBB we are compiling
80 int VarArgsFrameIndex; // FrameIndex for start of varargs area
82 std::map<Value*, unsigned> RegMap; // Mapping between Values and SSA Regs
84 // External functions used in the Module
85 Function *fmodfFn, *fmodFn, *__cmpdi2Fn, *__moddi3Fn, *__divdi3Fn,
86 *__umoddi3Fn, *__udivdi3Fn, *__fixsfdiFn, *__fixdfdiFn, *__fixunssfdiFn,
87 *__fixunsdfdiFn, *__floatdisfFn, *__floatdidfFn, *mallocFn, *freeFn;
89 // MBBMap - Mapping between LLVM BB -> Machine BB
90 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
92 // AllocaMap - Mapping from fixed sized alloca instructions to the
93 // FrameIndex for the alloca.
94 std::map<AllocaInst*, unsigned> AllocaMap;
96 // Target configuration data
97 const unsigned ParameterSaveAreaOffset, MaxArgumentStackSpace;
99 ISel(TargetMachine &tm) : TM(reinterpret_cast<PPC64TargetMachine&>(tm)),
100 F(0), BB(0), ParameterSaveAreaOffset(24), MaxArgumentStackSpace(32) {}
102 bool doInitialization(Module &M) {
103 // Add external functions that we may call
104 Type *i = Type::IntTy;
105 Type *d = Type::DoubleTy;
106 Type *f = Type::FloatTy;
107 Type *l = Type::LongTy;
108 Type *ul = Type::ULongTy;
109 Type *voidPtr = PointerType::get(Type::SByteTy);
110 // float fmodf(float, float);
111 fmodfFn = M.getOrInsertFunction("fmodf", f, f, f, 0);
112 // double fmod(double, double);
113 fmodFn = M.getOrInsertFunction("fmod", d, d, d, 0);
114 // int __cmpdi2(long, long);
115 __cmpdi2Fn = M.getOrInsertFunction("__cmpdi2", i, l, l, 0);
116 // long __moddi3(long, long);
117 __moddi3Fn = M.getOrInsertFunction("__moddi3", l, l, l, 0);
118 // long __divdi3(long, long);
119 __divdi3Fn = M.getOrInsertFunction("__divdi3", l, l, l, 0);
120 // unsigned long __umoddi3(unsigned long, unsigned long);
121 __umoddi3Fn = M.getOrInsertFunction("__umoddi3", ul, ul, ul, 0);
122 // unsigned long __udivdi3(unsigned long, unsigned long);
123 __udivdi3Fn = M.getOrInsertFunction("__udivdi3", ul, ul, ul, 0);
124 // long __fixsfdi(float)
125 __fixsfdiFn = M.getOrInsertFunction("__fixsfdi", l, f, 0);
126 // long __fixdfdi(double)
127 __fixdfdiFn = M.getOrInsertFunction("__fixdfdi", l, d, 0);
128 // unsigned long __fixunssfdi(float)
129 __fixunssfdiFn = M.getOrInsertFunction("__fixunssfdi", ul, f, 0);
130 // unsigned long __fixunsdfdi(double)
131 __fixunsdfdiFn = M.getOrInsertFunction("__fixunsdfdi", ul, d, 0);
132 // float __floatdisf(long)
133 __floatdisfFn = M.getOrInsertFunction("__floatdisf", f, l, 0);
134 // double __floatdidf(long)
135 __floatdidfFn = M.getOrInsertFunction("__floatdidf", d, l, 0);
136 // void* malloc(size_t)
137 mallocFn = M.getOrInsertFunction("malloc", voidPtr, Type::UIntTy, 0);
139 freeFn = M.getOrInsertFunction("free", Type::VoidTy, voidPtr, 0);
143 /// runOnFunction - Top level implementation of instruction selection for
144 /// the entire function.
146 bool runOnFunction(Function &Fn) {
147 // First pass over the function, lower any unknown intrinsic functions
148 // with the IntrinsicLowering class.
149 LowerUnknownIntrinsicFunctionCalls(Fn);
151 F = &MachineFunction::construct(&Fn, TM);
153 // Create all of the machine basic blocks for the function...
154 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
155 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
159 // Copy incoming arguments off of the stack...
160 LoadArgumentsToVirtualRegs(Fn);
162 // Instruction select everything except PHI nodes
165 // Select the PHI nodes
172 // We always build a machine code representation for the function
176 virtual const char *getPassName() const {
177 return "PowerPC Simple Instruction Selection";
180 /// visitBasicBlock - This method is called when we are visiting a new basic
181 /// block. This simply creates a new MachineBasicBlock to emit code into
182 /// and adds it to the current MachineFunction. Subsequent visit* for
183 /// instructions will be invoked for all instructions in the basic block.
185 void visitBasicBlock(BasicBlock &LLVM_BB) {
186 BB = MBBMap[&LLVM_BB];
189 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
190 /// function, lowering any calls to unknown intrinsic functions into the
191 /// equivalent LLVM code.
193 void LowerUnknownIntrinsicFunctionCalls(Function &F);
195 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function
196 /// from the stack into virtual registers.
198 void LoadArgumentsToVirtualRegs(Function &F);
200 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
201 /// because we have to generate our sources into the source basic blocks,
202 /// not the current one.
204 void SelectPHINodes();
206 // Visitation methods for various instructions. These methods simply emit
207 // fixed PowerPC code for each instruction.
209 // Control flow operators
210 void visitReturnInst(ReturnInst &RI);
211 void visitBranchInst(BranchInst &BI);
217 ValueRecord(unsigned R, const Type *T) : Val(0), Reg(R), Ty(T) {}
218 ValueRecord(Value *V) : Val(V), Reg(0), Ty(V->getType()) {}
221 // This struct is for recording the necessary operations to emit the GEP
222 struct CollapsedGepOp {
226 CollapsedGepOp(bool mul, Value *i, ConstantSInt *s) :
227 isMul(mul), index(i), size(s) {}
230 void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
231 const std::vector<ValueRecord> &Args, bool isVarArg);
232 void visitCallInst(CallInst &I);
233 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &I);
235 // Arithmetic operators
236 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
237 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
238 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
239 void visitMul(BinaryOperator &B);
241 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
242 void visitRem(BinaryOperator &B) { visitDivRem(B); }
243 void visitDivRem(BinaryOperator &B);
246 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
247 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
248 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
250 // Comparison operators...
251 void visitSetCondInst(SetCondInst &I);
252 unsigned EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
253 MachineBasicBlock *MBB,
254 MachineBasicBlock::iterator MBBI);
255 void visitSelectInst(SelectInst &SI);
258 // Memory Instructions
259 void visitLoadInst(LoadInst &I);
260 void visitStoreInst(StoreInst &I);
261 void visitGetElementPtrInst(GetElementPtrInst &I);
262 void visitAllocaInst(AllocaInst &I);
263 void visitMallocInst(MallocInst &I);
264 void visitFreeInst(FreeInst &I);
267 void visitShiftInst(ShiftInst &I);
268 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
269 void visitCastInst(CastInst &I);
270 void visitVANextInst(VANextInst &I);
271 void visitVAArgInst(VAArgInst &I);
273 void visitInstruction(Instruction &I) {
274 std::cerr << "Cannot instruction select: " << I;
278 /// promote32 - Make a value 32-bits wide, and put it somewhere.
280 void promote32(unsigned targetReg, const ValueRecord &VR);
282 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
283 /// constant expression GEP support.
285 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
286 Value *Src, User::op_iterator IdxBegin,
287 User::op_iterator IdxEnd, unsigned TargetReg,
288 bool CollapseRemainder, ConstantSInt **Remainder,
289 unsigned *PendingAddReg);
291 /// emitCastOperation - Common code shared between visitCastInst and
292 /// constant expression cast support.
294 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator IP,
295 Value *Src, const Type *DestTy, unsigned TargetReg);
297 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
298 /// and constant expression support.
300 void emitSimpleBinaryOperation(MachineBasicBlock *BB,
301 MachineBasicBlock::iterator IP,
302 Value *Op0, Value *Op1,
303 unsigned OperatorClass, unsigned TargetReg);
305 /// emitBinaryFPOperation - This method handles emission of floating point
306 /// Add (0), Sub (1), Mul (2), and Div (3) operations.
307 void emitBinaryFPOperation(MachineBasicBlock *BB,
308 MachineBasicBlock::iterator IP,
309 Value *Op0, Value *Op1,
310 unsigned OperatorClass, unsigned TargetReg);
312 void emitMultiply(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
313 Value *Op0, Value *Op1, unsigned TargetReg);
315 void doMultiply(MachineBasicBlock *MBB,
316 MachineBasicBlock::iterator IP,
317 unsigned DestReg, Value *Op0, Value *Op1);
319 /// doMultiplyConst - This method will multiply the value in Op0Reg by the
320 /// value of the ContantInt *CI
321 void doMultiplyConst(MachineBasicBlock *MBB,
322 MachineBasicBlock::iterator IP,
323 unsigned DestReg, Value *Op0, ConstantInt *CI);
325 void emitDivRemOperation(MachineBasicBlock *BB,
326 MachineBasicBlock::iterator IP,
327 Value *Op0, Value *Op1, bool isDiv,
330 /// emitSetCCOperation - Common code shared between visitSetCondInst and
331 /// constant expression support.
333 void emitSetCCOperation(MachineBasicBlock *BB,
334 MachineBasicBlock::iterator IP,
335 Value *Op0, Value *Op1, unsigned Opcode,
338 /// emitShiftOperation - Common code shared between visitShiftInst and
339 /// constant expression support.
341 void emitShiftOperation(MachineBasicBlock *MBB,
342 MachineBasicBlock::iterator IP,
343 Value *Op, Value *ShiftAmount, bool isLeftShift,
344 const Type *ResultTy, unsigned DestReg);
346 /// emitSelectOperation - Common code shared between visitSelectInst and the
347 /// constant expression support.
349 void emitSelectOperation(MachineBasicBlock *MBB,
350 MachineBasicBlock::iterator IP,
351 Value *Cond, Value *TrueVal, Value *FalseVal,
354 /// copyConstantToRegister - Output the instructions required to put the
355 /// specified constant into the specified register.
357 void copyConstantToRegister(MachineBasicBlock *MBB,
358 MachineBasicBlock::iterator MBBI,
359 Constant *C, unsigned Reg);
361 void emitUCOM(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
362 unsigned LHS, unsigned RHS);
364 /// makeAnotherReg - This method returns the next register number we haven't
367 unsigned makeAnotherReg(const Type *Ty) {
368 assert(dynamic_cast<const PPC64RegisterInfo*>(TM.getRegisterInfo()) &&
369 "Current target doesn't have PPC reg info??");
370 const PPC64RegisterInfo *PPCRI =
371 static_cast<const PPC64RegisterInfo*>(TM.getRegisterInfo());
372 // Add the mapping of regnumber => reg class to MachineFunction
373 const TargetRegisterClass *RC = PPCRI->getRegClassForType(Ty);
374 return F->getSSARegMap()->createVirtualRegister(RC);
377 /// getReg - This method turns an LLVM value into a register number.
379 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
380 unsigned getReg(Value *V) {
381 // Just append to the end of the current bb.
382 MachineBasicBlock::iterator It = BB->end();
383 return getReg(V, BB, It);
385 unsigned getReg(Value *V, MachineBasicBlock *MBB,
386 MachineBasicBlock::iterator IPt);
388 /// canUseAsImmediateForOpcode - This method returns whether a ConstantInt
389 /// is okay to use as an immediate argument to a certain binary operation
390 bool canUseAsImmediateForOpcode(ConstantInt *CI, unsigned Opcode);
392 /// getFixedSizedAllocaFI - Return the frame index for a fixed sized alloca
393 /// that is to be statically allocated with the initial stack frame
395 unsigned getFixedSizedAllocaFI(AllocaInst *AI);
399 /// dyn_castFixedAlloca - If the specified value is a fixed size alloca
400 /// instruction in the entry block, return it. Otherwise, return a null
402 static AllocaInst *dyn_castFixedAlloca(Value *V) {
403 if (AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
404 BasicBlock *BB = AI->getParent();
405 if (isa<ConstantUInt>(AI->getArraySize()) && BB ==&BB->getParent()->front())
411 /// getReg - This method turns an LLVM value into a register number.
413 unsigned ISel::getReg(Value *V, MachineBasicBlock *MBB,
414 MachineBasicBlock::iterator IPt) {
415 if (Constant *C = dyn_cast<Constant>(V)) {
416 unsigned Reg = makeAnotherReg(V->getType());
417 copyConstantToRegister(MBB, IPt, C, Reg);
419 } else if (AllocaInst *AI = dyn_castFixedAlloca(V)) {
420 unsigned Reg = makeAnotherReg(V->getType());
421 unsigned FI = getFixedSizedAllocaFI(AI);
422 addFrameReference(BuildMI(*MBB, IPt, PPC::ADDI, 2, Reg), FI, 0, false);
426 unsigned &Reg = RegMap[V];
428 Reg = makeAnotherReg(V->getType());
435 /// canUseAsImmediateForOpcode - This method returns whether a ConstantInt
436 /// is okay to use as an immediate argument to a certain binary operator.
438 /// Operator is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for Xor.
439 bool ISel::canUseAsImmediateForOpcode(ConstantInt *CI, unsigned Operator) {
443 // ADDI, Compare, and non-indexed Load take SIMM
444 bool cond1 = (Operator == 0)
445 && (Op1Cs = dyn_cast<ConstantSInt>(CI))
446 && (Op1Cs->getValue() <= 32767)
447 && (Op1Cs->getValue() >= -32768);
449 // SUBI takes -SIMM since it is a mnemonic for ADDI
450 bool cond2 = (Operator == 1)
451 && (Op1Cs = dyn_cast<ConstantSInt>(CI))
452 && (Op1Cs->getValue() <= 32768)
453 && (Op1Cs->getValue() >= -32767);
455 // ANDIo, ORI, and XORI take unsigned values
456 bool cond3 = (Operator >= 2)
457 && (Op1Cs = dyn_cast<ConstantSInt>(CI))
458 && (Op1Cs->getValue() >= 0)
459 && (Op1Cs->getValue() <= 32767);
461 // ADDI and SUBI take SIMMs, so we have to make sure the UInt would fit
462 bool cond4 = (Operator < 2)
463 && (Op1Cu = dyn_cast<ConstantUInt>(CI))
464 && (Op1Cu->getValue() <= 32767);
466 // ANDIo, ORI, and XORI take UIMMs, so they can be larger
467 bool cond5 = (Operator >= 2)
468 && (Op1Cu = dyn_cast<ConstantUInt>(CI))
469 && (Op1Cu->getValue() <= 65535);
471 if (cond1 || cond2 || cond3 || cond4 || cond5)
477 /// getFixedSizedAllocaFI - Return the frame index for a fixed sized alloca
478 /// that is to be statically allocated with the initial stack frame
480 unsigned ISel::getFixedSizedAllocaFI(AllocaInst *AI) {
481 // Already computed this?
482 std::map<AllocaInst*, unsigned>::iterator I = AllocaMap.lower_bound(AI);
483 if (I != AllocaMap.end() && I->first == AI) return I->second;
485 const Type *Ty = AI->getAllocatedType();
486 ConstantUInt *CUI = cast<ConstantUInt>(AI->getArraySize());
487 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
488 TySize *= CUI->getValue(); // Get total allocated size...
489 unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
491 // Create a new stack object using the frame manager...
492 int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
493 AllocaMap.insert(I, std::make_pair(AI, FrameIdx));
498 /// copyConstantToRegister - Output the instructions required to put the
499 /// specified constant into the specified register.
501 void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
502 MachineBasicBlock::iterator IP,
503 Constant *C, unsigned R) {
504 if (C->getType()->isIntegral()) {
505 unsigned Class = getClassB(C->getType());
507 if (Class == cLong) {
508 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(C)) {
509 uint64_t uval = CUI->getValue();
510 if (uval < (1LL << 32)) {
511 ConstantUInt *CU = ConstantUInt::get(Type::UIntTy, uval);
512 copyConstantToRegister(MBB, IP, CU, R);
515 } else if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(C)) {
516 int64_t val = CUI->getValue();
517 if (val < (1LL << 31)) {
518 ConstantUInt *CU = ConstantUInt::get(Type::UIntTy, val);
519 copyConstantToRegister(MBB, IP, CU, R);
523 std::cerr << "Unhandled long constant type!\n";
526 // Spill long to the constant pool and load it
527 MachineConstantPool *CP = F->getConstantPool();
528 unsigned CPI = CP->getConstantPoolIndex(C);
529 BuildMI(*MBB, IP, PPC::LD, 1, R)
530 .addReg(PPC::R2).addConstantPoolIndex(CPI);
534 assert(Class <= cInt && "Type not handled yet!");
537 if (C->getType() == Type::BoolTy) {
538 BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(C == ConstantBool::True);
543 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(C)) {
544 unsigned uval = CUI->getValue();
546 BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(uval);
548 unsigned Temp = makeAnotherReg(Type::IntTy);
549 BuildMI(*MBB, IP, PPC::LIS, 1, Temp).addSImm(uval >> 16);
550 BuildMI(*MBB, IP, PPC::ORI, 2, R).addReg(Temp).addImm(uval);
553 } else if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(C)) {
554 int sval = CSI->getValue();
555 if (sval < 32768 && sval >= -32768) {
556 BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(sval);
558 unsigned Temp = makeAnotherReg(Type::IntTy);
559 BuildMI(*MBB, IP, PPC::LIS, 1, Temp).addSImm(sval >> 16);
560 BuildMI(*MBB, IP, PPC::ORI, 2, R).addReg(Temp).addImm(sval);
564 std::cerr << "Unhandled integer constant!\n";
566 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
567 // We need to spill the constant to memory...
568 MachineConstantPool *CP = F->getConstantPool();
569 unsigned CPI = CP->getConstantPoolIndex(CFP);
570 const Type *Ty = CFP->getType();
571 unsigned LoadOpcode = (Ty == Type::FloatTy) ? PPC::LFS : PPC::LFD;
572 BuildMI(*MBB,IP,LoadOpcode,2,R).addConstantPoolIndex(CPI).addReg(PPC::R2);
573 } else if (isa<ConstantPointerNull>(C)) {
574 // Copy zero (null pointer) to the register.
575 BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(0);
576 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
577 static unsigned OpcodeTable[] = {
578 PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LFS, PPC::LFD, PPC::LD
580 unsigned Opcode = OpcodeTable[getClassB(GV->getType())];
581 BuildMI(*MBB, IP, Opcode, 2, R).addGlobalAddress(GV).addReg(PPC::R2);
583 std::cerr << "Offending constant: " << *C << "\n";
584 assert(0 && "Type not handled yet!");
588 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function from
589 /// the stack into virtual registers.
590 void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
591 unsigned ArgOffset = ParameterSaveAreaOffset;
592 unsigned GPR_remaining = 8;
593 unsigned FPR_remaining = 13;
594 unsigned GPR_idx = 0, FPR_idx = 0;
595 static const unsigned GPR[] = {
596 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
597 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
599 static const unsigned FPR[] = {
600 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
601 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
604 MachineFrameInfo *MFI = F->getFrameInfo();
606 for (Function::aiterator I = Fn.abegin(), E = Fn.aend(); I != E; ++I) {
607 bool ArgLive = !I->use_empty();
608 unsigned Reg = ArgLive ? getReg(*I) : 0;
609 int FI; // Frame object index
611 switch (getClassB(I->getType())) {
614 FI = MFI->CreateFixedObject(4, ArgOffset);
615 if (GPR_remaining > 0) {
616 BuildMI(BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
617 BuildMI(BB, PPC::OR, 2, Reg).addReg(GPR[GPR_idx])
618 .addReg(GPR[GPR_idx]);
620 addFrameReference(BuildMI(BB, PPC::LBZ, 2, Reg), FI);
626 FI = MFI->CreateFixedObject(4, ArgOffset);
627 if (GPR_remaining > 0) {
628 BuildMI(BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
629 BuildMI(BB, PPC::OR, 2, Reg).addReg(GPR[GPR_idx])
630 .addReg(GPR[GPR_idx]);
632 addFrameReference(BuildMI(BB, PPC::LHZ, 2, Reg), FI);
638 FI = MFI->CreateFixedObject(4, ArgOffset);
639 if (GPR_remaining > 0) {
640 BuildMI(BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
641 BuildMI(BB, PPC::OR, 2, Reg).addReg(GPR[GPR_idx])
642 .addReg(GPR[GPR_idx]);
644 addFrameReference(BuildMI(BB, PPC::LWZ, 2, Reg), FI);
650 FI = MFI->CreateFixedObject(8, ArgOffset);
651 if (GPR_remaining > 1) {
652 BuildMI(BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
653 BuildMI(BB, PPC::OR, 2, Reg).addReg(GPR[GPR_idx])
654 .addReg(GPR[GPR_idx]);
656 addFrameReference(BuildMI(BB, PPC::LD, 2, Reg), FI);
659 // longs require 4 additional bytes
664 FI = MFI->CreateFixedObject(4, ArgOffset);
666 if (FPR_remaining > 0) {
667 BuildMI(BB, PPC::IMPLICIT_DEF, 0, FPR[FPR_idx]);
668 BuildMI(BB, PPC::FMR, 1, Reg).addReg(FPR[FPR_idx]);
672 addFrameReference(BuildMI(BB, PPC::LFS, 2, Reg), FI);
678 FI = MFI->CreateFixedObject(8, ArgOffset);
680 if (FPR_remaining > 0) {
681 BuildMI(BB, PPC::IMPLICIT_DEF, 0, FPR[FPR_idx]);
682 BuildMI(BB, PPC::FMR, 1, Reg).addReg(FPR[FPR_idx]);
686 addFrameReference(BuildMI(BB, PPC::LFD, 2, Reg), FI);
690 // doubles require 4 additional bytes and use 2 GPRs of param space
692 if (GPR_remaining > 0) {
698 assert(0 && "Unhandled argument type!");
700 ArgOffset += 4; // Each argument takes at least 4 bytes on the stack...
701 if (GPR_remaining > 0) {
702 GPR_remaining--; // uses up 2 GPRs
707 // If the function takes variable number of arguments, add a frame offset for
708 // the start of the first vararg value... this is used to expand
710 if (Fn.getFunctionType()->isVarArg())
711 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
715 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
716 /// because we have to generate our sources into the source basic blocks, not
719 void ISel::SelectPHINodes() {
720 const TargetInstrInfo &TII = *TM.getInstrInfo();
721 const Function &LF = *F->getFunction(); // The LLVM function...
722 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
723 const BasicBlock *BB = I;
724 MachineBasicBlock &MBB = *MBBMap[I];
726 // Loop over all of the PHI nodes in the LLVM basic block...
727 MachineBasicBlock::iterator PHIInsertPoint = MBB.begin();
728 for (BasicBlock::const_iterator I = BB->begin();
729 PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
731 // Create a new machine instr PHI node, and insert it.
732 unsigned PHIReg = getReg(*PN);
733 MachineInstr *PhiMI = BuildMI(MBB, PHIInsertPoint,
734 PPC::PHI, PN->getNumOperands(), PHIReg);
736 // PHIValues - Map of blocks to incoming virtual registers. We use this
737 // so that we only initialize one incoming value for a particular block,
738 // even if the block has multiple entries in the PHI node.
740 std::map<MachineBasicBlock*, unsigned> PHIValues;
742 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
743 MachineBasicBlock *PredMBB = 0;
744 for (MachineBasicBlock::pred_iterator PI = MBB.pred_begin (),
745 PE = MBB.pred_end (); PI != PE; ++PI)
746 if (PN->getIncomingBlock(i) == (*PI)->getBasicBlock()) {
750 assert (PredMBB && "Couldn't find incoming machine-cfg edge for phi");
753 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
754 PHIValues.lower_bound(PredMBB);
756 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
757 // We already inserted an initialization of the register for this
758 // predecessor. Recycle it.
759 ValReg = EntryIt->second;
761 // Get the incoming value into a virtual register.
763 Value *Val = PN->getIncomingValue(i);
765 // If this is a constant or GlobalValue, we may have to insert code
766 // into the basic block to compute it into a virtual register.
767 if ((isa<Constant>(Val) && !isa<ConstantExpr>(Val)) ||
768 isa<GlobalValue>(Val)) {
769 // Simple constants get emitted at the end of the basic block,
770 // before any terminator instructions. We "know" that the code to
771 // move a constant into a register will never clobber any flags.
772 ValReg = getReg(Val, PredMBB, PredMBB->getFirstTerminator());
774 // Because we don't want to clobber any values which might be in
775 // physical registers with the computation of this constant (which
776 // might be arbitrarily complex if it is a constant expression),
777 // just insert the computation at the top of the basic block.
778 MachineBasicBlock::iterator PI = PredMBB->begin();
780 // Skip over any PHI nodes though!
781 while (PI != PredMBB->end() && PI->getOpcode() == PPC::PHI)
784 ValReg = getReg(Val, PredMBB, PI);
787 // Remember that we inserted a value for this PHI for this predecessor
788 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
791 PhiMI->addRegOperand(ValReg);
792 PhiMI->addMachineBasicBlockOperand(PredMBB);
795 // Now that we emitted all of the incoming values for the PHI node, make
796 // sure to reposition the InsertPoint after the PHI that we just added.
797 // This is needed because we might have inserted a constant into this
798 // block, right after the PHI's which is before the old insert point!
799 PHIInsertPoint = PhiMI;
806 // canFoldSetCCIntoBranchOrSelect - Return the setcc instruction if we can fold
807 // it into the conditional branch or select instruction which is the only user
808 // of the cc instruction. This is the case if the conditional branch is the
809 // only user of the setcc, and if the setcc is in the same basic block as the
810 // conditional branch.
812 static SetCondInst *canFoldSetCCIntoBranchOrSelect(Value *V) {
813 if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
814 if (SCI->hasOneUse()) {
815 Instruction *User = cast<Instruction>(SCI->use_back());
816 if ((isa<BranchInst>(User) || isa<SelectInst>(User)) &&
817 SCI->getParent() == User->getParent())
824 // canFoldGEPIntoLoadOrStore - Return the GEP instruction if we can fold it into
825 // the load or store instruction that is the only user of the GEP.
827 static GetElementPtrInst *canFoldGEPIntoLoadOrStore(Value *V) {
828 if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(V))
829 if (GEPI->hasOneUse()) {
830 Instruction *User = cast<Instruction>(GEPI->use_back());
831 if (isa<StoreInst>(User) &&
832 GEPI->getParent() == User->getParent() &&
833 User->getOperand(0) != GEPI &&
834 User->getOperand(1) == GEPI) {
838 if (isa<LoadInst>(User) &&
839 GEPI->getParent() == User->getParent() &&
840 User->getOperand(0) == GEPI) {
849 // Return a fixed numbering for setcc instructions which does not depend on the
850 // order of the opcodes.
852 static unsigned getSetCCNumber(unsigned Opcode) {
854 default: assert(0 && "Unknown setcc instruction!");
855 case Instruction::SetEQ: return 0;
856 case Instruction::SetNE: return 1;
857 case Instruction::SetLT: return 2;
858 case Instruction::SetGE: return 3;
859 case Instruction::SetGT: return 4;
860 case Instruction::SetLE: return 5;
864 static unsigned getPPCOpcodeForSetCCNumber(unsigned Opcode) {
866 default: assert(0 && "Unknown setcc instruction!");
867 case Instruction::SetEQ: return PPC::BEQ;
868 case Instruction::SetNE: return PPC::BNE;
869 case Instruction::SetLT: return PPC::BLT;
870 case Instruction::SetGE: return PPC::BGE;
871 case Instruction::SetGT: return PPC::BGT;
872 case Instruction::SetLE: return PPC::BLE;
876 /// emitUCOM - emits an unordered FP compare.
877 void ISel::emitUCOM(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
878 unsigned LHS, unsigned RHS) {
879 BuildMI(*MBB, IP, PPC::FCMPU, 2, PPC::CR0).addReg(LHS).addReg(RHS);
882 /// EmitComparison - emits a comparison of the two operands, returning the
883 /// extended setcc code to use. The result is in CR0.
885 unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
886 MachineBasicBlock *MBB,
887 MachineBasicBlock::iterator IP) {
888 // The arguments are already supposed to be of the same type.
889 const Type *CompTy = Op0->getType();
890 unsigned Class = getClassB(CompTy);
891 unsigned Op0r = getReg(Op0, MBB, IP);
893 // Before we do a comparison, we have to make sure that we're truncating our
894 // registers appropriately.
895 if (Class == cByte) {
896 unsigned TmpReg = makeAnotherReg(CompTy);
897 if (CompTy->isSigned())
898 BuildMI(*MBB, IP, PPC::EXTSB, 1, TmpReg).addReg(Op0r);
900 BuildMI(*MBB, IP, PPC::RLWINM, 4, TmpReg).addReg(Op0r).addImm(0)
901 .addImm(24).addImm(31);
903 } else if (Class == cShort) {
904 unsigned TmpReg = makeAnotherReg(CompTy);
905 if (CompTy->isSigned())
906 BuildMI(*MBB, IP, PPC::EXTSH, 1, TmpReg).addReg(Op0r);
908 BuildMI(*MBB, IP, PPC::RLWINM, 4, TmpReg).addReg(Op0r).addImm(0)
909 .addImm(16).addImm(31);
913 // Use crand for lt, gt and crandc for le, ge
914 unsigned CROpcode = (OpNum == 2 || OpNum == 4) ? PPC::CRAND : PPC::CRANDC;
915 unsigned Opcode = CompTy->isSigned() ? PPC::CMPW : PPC::CMPLW;
916 unsigned OpcodeImm = CompTy->isSigned() ? PPC::CMPWI : PPC::CMPLWI;
917 if (Class == cLong) {
918 Opcode = CompTy->isSigned() ? PPC::CMPD : PPC::CMPLD;
919 OpcodeImm = CompTy->isSigned() ? PPC::CMPDI : PPC::CMPLDI;
922 // Special case handling of: cmp R, i
923 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
924 unsigned Op1v = CI->getRawValue() & 0xFFFF;
926 // Treat compare like ADDI for the purposes of immediate suitability
927 if (canUseAsImmediateForOpcode(CI, 0)) {
928 BuildMI(*MBB, IP, OpcodeImm, 2, PPC::CR0).addReg(Op0r).addSImm(Op1v);
930 unsigned Op1r = getReg(Op1, MBB, IP);
931 BuildMI(*MBB, IP, Opcode, 2, PPC::CR0).addReg(Op0r).addReg(Op1r);
936 unsigned Op1r = getReg(Op1, MBB, IP);
939 default: assert(0 && "Unknown type class!");
944 BuildMI(*MBB, IP, Opcode, 2, PPC::CR0).addReg(Op0r).addReg(Op1r);
949 emitUCOM(MBB, IP, Op0r, Op1r);
956 /// visitSetCondInst - emit code to calculate the condition via
957 /// EmitComparison(), and possibly store a 0 or 1 to a register as a result
959 void ISel::visitSetCondInst(SetCondInst &I) {
960 if (canFoldSetCCIntoBranchOrSelect(&I))
963 unsigned DestReg = getReg(I);
964 unsigned OpNum = I.getOpcode();
965 const Type *Ty = I.getOperand (0)->getType();
967 EmitComparison(OpNum, I.getOperand(0), I.getOperand(1), BB, BB->end());
969 unsigned Opcode = getPPCOpcodeForSetCCNumber(OpNum);
970 MachineBasicBlock *thisMBB = BB;
971 const BasicBlock *LLVM_BB = BB->getBasicBlock();
972 ilist<MachineBasicBlock>::iterator It = BB;
981 // FIXME: we wouldn't need copy0MBB (we could fold it into thisMBB)
982 // if we could insert other, non-terminator instructions after the
983 // bCC. But MBB->getFirstTerminator() can't understand this.
984 MachineBasicBlock *copy1MBB = new MachineBasicBlock(LLVM_BB);
985 F->getBasicBlockList().insert(It, copy1MBB);
986 BuildMI(BB, Opcode, 2).addReg(PPC::CR0).addMBB(copy1MBB);
987 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
988 F->getBasicBlockList().insert(It, copy0MBB);
989 BuildMI(BB, PPC::B, 1).addMBB(copy0MBB);
990 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
991 F->getBasicBlockList().insert(It, sinkMBB);
992 // Update machine-CFG edges
993 BB->addSuccessor(copy1MBB);
994 BB->addSuccessor(copy0MBB);
1000 unsigned TrueValue = makeAnotherReg(I.getType());
1001 BuildMI(BB, PPC::LI, 1, TrueValue).addSImm(1);
1002 BuildMI(BB, PPC::B, 1).addMBB(sinkMBB);
1003 // Update machine-CFG edges
1004 BB->addSuccessor(sinkMBB);
1007 // %FalseValue = li 0
1010 unsigned FalseValue = makeAnotherReg(I.getType());
1011 BuildMI(BB, PPC::LI, 1, FalseValue).addSImm(0);
1012 // Update machine-CFG edges
1013 BB->addSuccessor(sinkMBB);
1016 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, copy1MBB ]
1019 BuildMI(BB, PPC::PHI, 4, DestReg).addReg(FalseValue)
1020 .addMBB(copy0MBB).addReg(TrueValue).addMBB(copy1MBB);
1023 void ISel::visitSelectInst(SelectInst &SI) {
1024 unsigned DestReg = getReg(SI);
1025 MachineBasicBlock::iterator MII = BB->end();
1026 emitSelectOperation(BB, MII, SI.getCondition(), SI.getTrueValue(),
1027 SI.getFalseValue(), DestReg);
1030 /// emitSelect - Common code shared between visitSelectInst and the constant
1031 /// expression support.
1032 /// FIXME: this is most likely broken in one or more ways. Namely, PowerPC has
1033 /// no select instruction. FSEL only works for comparisons against zero.
1034 void ISel::emitSelectOperation(MachineBasicBlock *MBB,
1035 MachineBasicBlock::iterator IP,
1036 Value *Cond, Value *TrueVal, Value *FalseVal,
1038 unsigned SelectClass = getClassB(TrueVal->getType());
1041 // See if we can fold the setcc into the select instruction, or if we have
1042 // to get the register of the Cond value
1043 if (SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(Cond)) {
1044 // We successfully folded the setcc into the select instruction.
1045 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
1046 OpNum = EmitComparison(OpNum, SCI->getOperand(0),SCI->getOperand(1),MBB,IP);
1047 Opcode = getPPCOpcodeForSetCCNumber(SCI->getOpcode());
1049 unsigned CondReg = getReg(Cond, MBB, IP);
1050 BuildMI(*MBB, IP, PPC::CMPI, 2, PPC::CR0).addReg(CondReg).addSImm(0);
1051 Opcode = getPPCOpcodeForSetCCNumber(Instruction::SetNE);
1056 // cmpTY cr0, r1, r2
1060 MachineBasicBlock *thisMBB = BB;
1061 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1062 ilist<MachineBasicBlock>::iterator It = BB;
1065 // FIXME: we wouldn't need copy0MBB (we could fold it into thisMBB)
1066 // if we could insert other, non-terminator instructions after the
1067 // bCC. But MBB->getFirstTerminator() can't understand this.
1068 MachineBasicBlock *copy1MBB = new MachineBasicBlock(LLVM_BB);
1069 F->getBasicBlockList().insert(It, copy1MBB);
1070 BuildMI(BB, Opcode, 2).addReg(PPC::CR0).addMBB(copy1MBB);
1071 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
1072 F->getBasicBlockList().insert(It, copy0MBB);
1073 BuildMI(BB, PPC::B, 1).addMBB(copy0MBB);
1074 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
1075 F->getBasicBlockList().insert(It, sinkMBB);
1076 // Update machine-CFG edges
1077 BB->addSuccessor(copy1MBB);
1078 BB->addSuccessor(copy0MBB);
1084 unsigned TrueValue = getReg(TrueVal, BB, BB->begin());
1085 BuildMI(BB, PPC::B, 1).addMBB(sinkMBB);
1086 // Update machine-CFG edges
1087 BB->addSuccessor(sinkMBB);
1090 // %FalseValue = ...
1093 unsigned FalseValue = getReg(FalseVal, BB, BB->begin());
1094 // Update machine-CFG edges
1095 BB->addSuccessor(sinkMBB);
1098 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, copy1MBB ]
1101 BuildMI(BB, PPC::PHI, 4, DestReg).addReg(FalseValue)
1102 .addMBB(copy0MBB).addReg(TrueValue).addMBB(copy1MBB);
1108 /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
1109 /// operand, in the specified target register.
1111 void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
1112 bool isUnsigned = VR.Ty->isUnsigned() || VR.Ty == Type::BoolTy;
1114 Value *Val = VR.Val;
1115 const Type *Ty = VR.Ty;
1117 if (Constant *C = dyn_cast<Constant>(Val)) {
1118 Val = ConstantExpr::getCast(C, Type::IntTy);
1119 if (isa<ConstantExpr>(Val)) // Could not fold
1122 Ty = Type::IntTy; // Folded!
1125 // If this is a simple constant, just emit a load directly to avoid the copy
1126 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
1127 int TheVal = CI->getRawValue() & 0xFFFFFFFF;
1129 if (TheVal < 32768 && TheVal >= -32768) {
1130 BuildMI(BB, PPC::LI, 1, targetReg).addSImm(TheVal);
1132 unsigned TmpReg = makeAnotherReg(Type::IntTy);
1133 BuildMI(BB, PPC::LIS, 1, TmpReg).addSImm(TheVal >> 16);
1134 BuildMI(BB, PPC::ORI, 2, targetReg).addReg(TmpReg)
1135 .addImm(TheVal & 0xFFFF);
1141 // Make sure we have the register number for this value...
1142 unsigned Reg = Val ? getReg(Val) : VR.Reg;
1143 switch (getClassB(Ty)) {
1145 // Extend value into target register (8->32)
1147 BuildMI(BB, PPC::RLWINM, 4, targetReg).addReg(Reg).addZImm(0)
1148 .addZImm(24).addZImm(31);
1150 BuildMI(BB, PPC::EXTSB, 1, targetReg).addReg(Reg);
1153 // Extend value into target register (16->32)
1155 BuildMI(BB, PPC::RLWINM, 4, targetReg).addReg(Reg).addZImm(0)
1156 .addZImm(16).addZImm(31);
1158 BuildMI(BB, PPC::EXTSH, 1, targetReg).addReg(Reg);
1162 // Move value into target register (32->32)
1163 BuildMI(BB, PPC::OR, 2, targetReg).addReg(Reg).addReg(Reg);
1166 assert(0 && "Unpromotable operand class in promote32");
1170 /// visitReturnInst - implemented with BLR
1172 void ISel::visitReturnInst(ReturnInst &I) {
1173 // Only do the processing if this is a non-void return
1174 if (I.getNumOperands() > 0) {
1175 Value *RetVal = I.getOperand(0);
1176 switch (getClassB(RetVal->getType())) {
1177 case cByte: // integral return values: extend or move into r3 and return
1181 promote32(PPC::R3, ValueRecord(RetVal));
1184 case cFP64: { // Floats & Doubles: Return in f1
1185 unsigned RetReg = getReg(RetVal);
1186 BuildMI(BB, PPC::FMR, 1, PPC::F1).addReg(RetReg);
1190 visitInstruction(I);
1193 BuildMI(BB, PPC::BLR, 1).addImm(1);
1196 // getBlockAfter - Return the basic block which occurs lexically after the
1198 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
1199 Function::iterator I = BB; ++I; // Get iterator to next block
1200 return I != BB->getParent()->end() ? &*I : 0;
1203 /// visitBranchInst - Handle conditional and unconditional branches here. Note
1204 /// that since code layout is frozen at this point, that if we are trying to
1205 /// jump to a block that is the immediate successor of the current block, we can
1206 /// just make a fall-through (but we don't currently).
1208 void ISel::visitBranchInst(BranchInst &BI) {
1209 // Update machine-CFG edges
1210 BB->addSuccessor(MBBMap[BI.getSuccessor(0)]);
1211 if (BI.isConditional())
1212 BB->addSuccessor(MBBMap[BI.getSuccessor(1)]);
1214 BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
1216 if (!BI.isConditional()) { // Unconditional branch?
1217 if (BI.getSuccessor(0) != NextBB)
1218 BuildMI(BB, PPC::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
1222 // See if we can fold the setcc into the branch itself...
1223 SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(BI.getCondition());
1225 // Nope, cannot fold setcc into this branch. Emit a branch on a condition
1226 // computed some other way...
1227 unsigned condReg = getReg(BI.getCondition());
1228 BuildMI(BB, PPC::CMPLI, 3, PPC::CR0).addImm(0).addReg(condReg)
1230 if (BI.getSuccessor(1) == NextBB) {
1231 if (BI.getSuccessor(0) != NextBB)
1232 BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(PPC::BNE)
1233 .addMBB(MBBMap[BI.getSuccessor(0)])
1234 .addMBB(MBBMap[BI.getSuccessor(1)]);
1236 BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(PPC::BEQ)
1237 .addMBB(MBBMap[BI.getSuccessor(1)])
1238 .addMBB(MBBMap[BI.getSuccessor(0)]);
1239 if (BI.getSuccessor(0) != NextBB)
1240 BuildMI(BB, PPC::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
1245 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
1246 unsigned Opcode = getPPCOpcodeForSetCCNumber(SCI->getOpcode());
1247 MachineBasicBlock::iterator MII = BB->end();
1248 OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
1250 if (BI.getSuccessor(0) != NextBB) {
1251 BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(Opcode)
1252 .addMBB(MBBMap[BI.getSuccessor(0)])
1253 .addMBB(MBBMap[BI.getSuccessor(1)]);
1254 if (BI.getSuccessor(1) != NextBB)
1255 BuildMI(BB, PPC::B, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
1257 // Change to the inverse condition...
1258 if (BI.getSuccessor(1) != NextBB) {
1259 Opcode = PPC64InstrInfo::invertPPCBranchOpcode(Opcode);
1260 BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(Opcode)
1261 .addMBB(MBBMap[BI.getSuccessor(1)])
1262 .addMBB(MBBMap[BI.getSuccessor(0)]);
1267 /// doCall - This emits an abstract call instruction, setting up the arguments
1268 /// and the return value as appropriate. For the actual function call itself,
1269 /// it inserts the specified CallMI instruction into the stream.
1271 void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
1272 const std::vector<ValueRecord> &Args, bool isVarArg) {
1273 // Count how many bytes are to be pushed on the stack, including the linkage
1274 // area, and parameter passing area.
1275 unsigned NumBytes = ParameterSaveAreaOffset;
1276 unsigned ArgOffset = ParameterSaveAreaOffset;
1278 if (!Args.empty()) {
1279 for (unsigned i = 0, e = Args.size(); i != e; ++i)
1280 switch (getClassB(Args[i].Ty)) {
1281 case cByte: case cShort: case cInt:
1282 NumBytes += 4; break;
1284 NumBytes += 8; break;
1286 NumBytes += 4; break;
1288 NumBytes += 8; break;
1290 default: assert(0 && "Unknown class!");
1293 // Just to be safe, we'll always reserve the full argument passing space in
1294 // case any called code gets funky on us.
1295 if (NumBytes < ParameterSaveAreaOffset + MaxArgumentStackSpace)
1296 NumBytes = ParameterSaveAreaOffset + MaxArgumentStackSpace;
1298 // Adjust the stack pointer for the new arguments...
1299 // These functions are automatically eliminated by the prolog/epilog pass
1300 BuildMI(BB, PPC::ADJCALLSTACKDOWN, 1).addImm(NumBytes);
1302 // Arguments go on the stack in reverse order, as specified by the ABI.
1303 int GPR_remaining = 8, FPR_remaining = 13;
1304 unsigned GPR_idx = 0, FPR_idx = 0;
1305 static const unsigned GPR[] = {
1306 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1307 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1309 static const unsigned FPR[] = {
1310 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6,
1311 PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12,
1315 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
1317 switch (getClassB(Args[i].Ty)) {
1320 // Promote arg to 32 bits wide into a temporary register...
1321 ArgReg = makeAnotherReg(Type::UIntTy);
1322 promote32(ArgReg, Args[i]);
1325 if (GPR_remaining > 0) {
1326 BuildMI(BB, PPC::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
1328 CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
1330 if (GPR_remaining <= 0 || isVarArg) {
1331 BuildMI(BB, PPC::STW, 3).addReg(ArgReg).addSImm(ArgOffset)
1336 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1339 if (GPR_remaining > 0) {
1340 BuildMI(BB, PPC::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
1342 CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
1344 if (GPR_remaining <= 0 || isVarArg) {
1345 BuildMI(BB, PPC::STW, 3).addReg(ArgReg).addSImm(ArgOffset)
1350 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1353 if (GPR_remaining > 0) {
1354 BuildMI(BB, PPC::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
1356 CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
1358 if (GPR_remaining <= 0 || isVarArg) {
1359 BuildMI(BB, PPC::STD, 3).addReg(ArgReg).addSImm(ArgOffset)
1362 ArgOffset += 4; // 8 byte entry, not 4.
1365 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1367 if (FPR_remaining > 0) {
1368 BuildMI(BB, PPC::FMR, 1, FPR[FPR_idx]).addReg(ArgReg);
1369 CallMI->addRegOperand(FPR[FPR_idx], MachineOperand::Use);
1373 // If this is a vararg function, and there are GPRs left, also
1374 // pass the float in an int. Otherwise, put it on the stack.
1376 BuildMI(BB, PPC::STFS, 3).addReg(ArgReg).addSImm(ArgOffset)
1378 if (GPR_remaining > 0) {
1379 BuildMI(BB, PPC::LWZ, 2, GPR[GPR_idx])
1380 .addSImm(ArgOffset).addReg(ArgReg);
1381 CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
1385 BuildMI(BB, PPC::STFS, 3).addReg(ArgReg).addSImm(ArgOffset)
1390 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1392 if (FPR_remaining > 0) {
1393 BuildMI(BB, PPC::FMR, 1, FPR[FPR_idx]).addReg(ArgReg);
1394 CallMI->addRegOperand(FPR[FPR_idx], MachineOperand::Use);
1397 // For vararg functions, must pass doubles via int regs as well
1399 BuildMI(BB, PPC::STFD, 3).addReg(ArgReg).addSImm(ArgOffset)
1402 if (GPR_remaining > 0) {
1403 BuildMI(BB, PPC::LD, 2, GPR[GPR_idx]).addSImm(ArgOffset)
1405 CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
1409 BuildMI(BB, PPC::STFD, 3).addReg(ArgReg).addSImm(ArgOffset)
1412 // Doubles use 8 bytes
1416 default: assert(0 && "Unknown class!");
1423 BuildMI(BB, PPC::ADJCALLSTACKDOWN, 1).addImm(0);
1426 BuildMI(BB, PPC::IMPLICIT_DEF, 0, PPC::LR);
1427 BB->push_back(CallMI);
1428 BuildMI(BB, PPC::NOP, 0);
1430 // These functions are automatically eliminated by the prolog/epilog pass
1431 BuildMI(BB, PPC::ADJCALLSTACKUP, 1).addImm(NumBytes);
1433 // If there is a return value, scavenge the result from the location the call
1436 if (Ret.Ty != Type::VoidTy) {
1437 unsigned DestClass = getClassB(Ret.Ty);
1438 switch (DestClass) {
1443 // Integral results are in r3
1444 BuildMI(BB, PPC::OR, 2, Ret.Reg).addReg(PPC::R3).addReg(PPC::R3);
1446 case cFP32: // Floating-point return values live in f1
1448 BuildMI(BB, PPC::FMR, 1, Ret.Reg).addReg(PPC::F1);
1450 default: assert(0 && "Unknown class!");
1456 /// visitCallInst - Push args on stack and do a procedure call instruction.
1457 void ISel::visitCallInst(CallInst &CI) {
1458 MachineInstr *TheCall;
1459 Function *F = CI.getCalledFunction();
1461 // Is it an intrinsic function call?
1462 if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
1463 visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here
1466 // Emit a CALL instruction with PC-relative displacement.
1467 TheCall = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(F, true);
1468 } else { // Emit an indirect call through the CTR
1469 unsigned Reg = getReg(CI.getCalledValue());
1470 BuildMI(BB, PPC::MTCTR, 1).addReg(Reg);
1471 TheCall = BuildMI(PPC::CALLindirect, 2).addZImm(20).addZImm(0);
1474 std::vector<ValueRecord> Args;
1475 for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i)
1476 Args.push_back(ValueRecord(CI.getOperand(i)));
1478 unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
1479 bool isVarArg = F ? F->getFunctionType()->isVarArg() : true;
1480 doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args, isVarArg);
1484 /// dyncastIsNan - Return the operand of an isnan operation if this is an isnan.
1486 static Value *dyncastIsNan(Value *V) {
1487 if (CallInst *CI = dyn_cast<CallInst>(V))
1488 if (Function *F = CI->getCalledFunction())
1489 if (F->getIntrinsicID() == Intrinsic::isunordered)
1490 return CI->getOperand(1);
1494 /// isOnlyUsedByUnorderedComparisons - Return true if this value is only used by
1495 /// or's whos operands are all calls to the isnan predicate.
1496 static bool isOnlyUsedByUnorderedComparisons(Value *V) {
1497 assert(dyncastIsNan(V) && "The value isn't an isnan call!");
1499 // Check all uses, which will be or's of isnans if this predicate is true.
1500 for (Value::use_iterator UI = V->use_begin(), E = V->use_end(); UI != E;++UI){
1501 Instruction *I = cast<Instruction>(*UI);
1502 if (I->getOpcode() != Instruction::Or) return false;
1503 if (I->getOperand(0) != V && !dyncastIsNan(I->getOperand(0))) return false;
1504 if (I->getOperand(1) != V && !dyncastIsNan(I->getOperand(1))) return false;
1510 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
1511 /// function, lowering any calls to unknown intrinsic functions into the
1512 /// equivalent LLVM code.
1514 void ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
1515 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
1516 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
1517 if (CallInst *CI = dyn_cast<CallInst>(I++))
1518 if (Function *F = CI->getCalledFunction())
1519 switch (F->getIntrinsicID()) {
1520 case Intrinsic::not_intrinsic:
1521 case Intrinsic::vastart:
1522 case Intrinsic::vacopy:
1523 case Intrinsic::vaend:
1524 case Intrinsic::returnaddress:
1525 case Intrinsic::frameaddress:
1526 // FIXME: should lower these ourselves
1527 // case Intrinsic::isunordered:
1528 // case Intrinsic::memcpy: -> doCall(). system memcpy almost
1529 // guaranteed to be faster than anything we generate ourselves
1530 // We directly implement these intrinsics
1532 case Intrinsic::readio: {
1533 // On PPC, memory operations are in-order. Lower this intrinsic
1534 // into a volatile load.
1535 Instruction *Before = CI->getPrev();
1536 LoadInst * LI = new LoadInst(CI->getOperand(1), "", true, CI);
1537 CI->replaceAllUsesWith(LI);
1538 BB->getInstList().erase(CI);
1541 case Intrinsic::writeio: {
1542 // On PPC, memory operations are in-order. Lower this intrinsic
1543 // into a volatile store.
1544 Instruction *Before = CI->getPrev();
1545 StoreInst *SI = new StoreInst(CI->getOperand(1),
1546 CI->getOperand(2), true, CI);
1547 CI->replaceAllUsesWith(SI);
1548 BB->getInstList().erase(CI);
1552 // All other intrinsic calls we must lower.
1553 Instruction *Before = CI->getPrev();
1554 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
1555 if (Before) { // Move iterator to instruction after call
1563 void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
1564 unsigned TmpReg1, TmpReg2, TmpReg3;
1566 case Intrinsic::vastart:
1567 // Get the address of the first vararg value...
1568 TmpReg1 = getReg(CI);
1569 addFrameReference(BuildMI(BB, PPC::ADDI, 2, TmpReg1), VarArgsFrameIndex,
1573 case Intrinsic::vacopy:
1574 TmpReg1 = getReg(CI);
1575 TmpReg2 = getReg(CI.getOperand(1));
1576 BuildMI(BB, PPC::OR, 2, TmpReg1).addReg(TmpReg2).addReg(TmpReg2);
1578 case Intrinsic::vaend: return;
1580 case Intrinsic::returnaddress:
1581 TmpReg1 = getReg(CI);
1582 if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
1583 MachineFrameInfo *MFI = F->getFrameInfo();
1584 unsigned NumBytes = MFI->getStackSize();
1586 BuildMI(BB, PPC::LWZ, 2, TmpReg1).addSImm(NumBytes+8)
1589 // Values other than zero are not implemented yet.
1590 BuildMI(BB, PPC::LI, 1, TmpReg1).addSImm(0);
1594 case Intrinsic::frameaddress:
1595 TmpReg1 = getReg(CI);
1596 if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
1597 BuildMI(BB, PPC::OR, 2, TmpReg1).addReg(PPC::R1).addReg(PPC::R1);
1599 // Values other than zero are not implemented yet.
1600 BuildMI(BB, PPC::LI, 1, TmpReg1).addSImm(0);
1605 // This may be useful for supporting isunordered
1606 case Intrinsic::isnan:
1607 // If this is only used by 'isunordered' style comparisons, don't emit it.
1608 if (isOnlyUsedByUnorderedComparisons(&CI)) return;
1609 TmpReg1 = getReg(CI.getOperand(1));
1610 emitUCOM(BB, BB->end(), TmpReg1, TmpReg1);
1611 TmpReg2 = makeAnotherReg(Type::IntTy);
1612 BuildMI(BB, PPC::MFCR, TmpReg2);
1613 TmpReg3 = getReg(CI);
1614 BuildMI(BB, PPC::RLWINM, 4, TmpReg3).addReg(TmpReg2).addImm(4).addImm(31).addImm(31);
1618 default: assert(0 && "Error: unknown intrinsics should have been lowered!");
1622 /// visitSimpleBinary - Implement simple binary operators for integral types...
1623 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for
1626 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
1627 unsigned DestReg = getReg(B);
1628 MachineBasicBlock::iterator MI = BB->end();
1629 Value *Op0 = B.getOperand(0), *Op1 = B.getOperand(1);
1630 unsigned Class = getClassB(B.getType());
1632 emitSimpleBinaryOperation(BB, MI, Op0, Op1, OperatorClass, DestReg);
1635 /// emitBinaryFPOperation - This method handles emission of floating point
1636 /// Add (0), Sub (1), Mul (2), and Div (3) operations.
1637 void ISel::emitBinaryFPOperation(MachineBasicBlock *BB,
1638 MachineBasicBlock::iterator IP,
1639 Value *Op0, Value *Op1,
1640 unsigned OperatorClass, unsigned DestReg) {
1642 static const unsigned OpcodeTab[][4] = {
1643 { PPC::FADDS, PPC::FSUBS, PPC::FMULS, PPC::FDIVS }, // Float
1644 { PPC::FADD, PPC::FSUB, PPC::FMUL, PPC::FDIV }, // Double
1647 // Special case: R1 = op <const fp>, R2
1648 if (ConstantFP *Op0C = dyn_cast<ConstantFP>(Op0))
1649 if (Op0C->isExactlyValue(-0.0) && OperatorClass == 1) {
1651 unsigned op1Reg = getReg(Op1, BB, IP);
1652 BuildMI(*BB, IP, PPC::FNEG, 1, DestReg).addReg(op1Reg);
1656 unsigned Opcode = OpcodeTab[Op0->getType() == Type::DoubleTy][OperatorClass];
1657 unsigned Op0r = getReg(Op0, BB, IP);
1658 unsigned Op1r = getReg(Op1, BB, IP);
1659 BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
1662 /// emitSimpleBinaryOperation - Implement simple binary operators for integral
1663 /// types... OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for
1666 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
1667 /// and constant expression support.
1669 void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
1670 MachineBasicBlock::iterator IP,
1671 Value *Op0, Value *Op1,
1672 unsigned OperatorClass, unsigned DestReg) {
1673 unsigned Class = getClassB(Op0->getType());
1675 // Arithmetic and Bitwise operators
1676 static const unsigned OpcodeTab[] = {
1677 PPC::ADD, PPC::SUB, PPC::AND, PPC::OR, PPC::XOR
1679 static const unsigned ImmOpcodeTab[] = {
1680 PPC::ADDI, PPC::SUBI, PPC::ANDIo, PPC::ORI, PPC::XORI
1682 static const unsigned RImmOpcodeTab[] = {
1683 PPC::ADDI, PPC::SUBFIC, PPC::ANDIo, PPC::ORI, PPC::XORI
1686 if (Class == cFP32 || Class == cFP64) {
1687 assert(OperatorClass < 2 && "No logical ops for FP!");
1688 emitBinaryFPOperation(MBB, IP, Op0, Op1, OperatorClass, DestReg);
1692 if (Op0->getType() == Type::BoolTy) {
1693 if (OperatorClass == 3)
1694 // If this is an or of two isnan's, emit an FP comparison directly instead
1695 // of or'ing two isnan's together.
1696 if (Value *LHS = dyncastIsNan(Op0))
1697 if (Value *RHS = dyncastIsNan(Op1)) {
1698 unsigned Op0Reg = getReg(RHS, MBB, IP), Op1Reg = getReg(LHS, MBB, IP);
1699 unsigned TmpReg = makeAnotherReg(Type::IntTy);
1700 emitUCOM(MBB, IP, Op0Reg, Op1Reg);
1701 BuildMI(*MBB, IP, PPC::MFCR, TmpReg);
1702 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(TmpReg).addImm(4)
1703 .addImm(31).addImm(31);
1708 // Special case: op <const int>, Reg
1709 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op0)) {
1710 // sub 0, X -> subfic
1711 if (OperatorClass == 1 && canUseAsImmediateForOpcode(CI, 0)) {
1712 unsigned Op1r = getReg(Op1, MBB, IP);
1713 int imm = CI->getRawValue() & 0xFFFF;
1714 BuildMI(*MBB, IP, PPC::SUBFIC, 2, DestReg).addReg(Op1r).addSImm(imm);
1718 // If it is easy to do, swap the operands and emit an immediate op
1719 if (Class != cLong && OperatorClass != 1 &&
1720 canUseAsImmediateForOpcode(CI, OperatorClass)) {
1721 unsigned Op1r = getReg(Op1, MBB, IP);
1722 int imm = CI->getRawValue() & 0xFFFF;
1724 if (OperatorClass < 2)
1725 BuildMI(*MBB, IP, RImmOpcodeTab[OperatorClass], 2, DestReg).addReg(Op1r)
1728 BuildMI(*MBB, IP, RImmOpcodeTab[OperatorClass], 2, DestReg).addReg(Op1r)
1734 // Special case: op Reg, <const int>
1735 if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
1736 unsigned Op0r = getReg(Op0, MBB, IP);
1738 // xor X, -1 -> not X
1739 if (OperatorClass == 4 && Op1C->isAllOnesValue()) {
1740 BuildMI(*MBB, IP, PPC::NOR, 2, DestReg).addReg(Op0r).addReg(Op0r);
1744 if (canUseAsImmediateForOpcode(Op1C, OperatorClass)) {
1745 int immediate = Op1C->getRawValue() & 0xFFFF;
1747 if (OperatorClass < 2)
1748 BuildMI(*MBB, IP, ImmOpcodeTab[OperatorClass], 2,DestReg).addReg(Op0r)
1749 .addSImm(immediate);
1751 BuildMI(*MBB, IP, ImmOpcodeTab[OperatorClass], 2,DestReg).addReg(Op0r)
1752 .addZImm(immediate);
1754 unsigned Op1r = getReg(Op1, MBB, IP);
1755 BuildMI(*MBB, IP, OpcodeTab[OperatorClass], 2, DestReg).addReg(Op0r)
1761 // We couldn't generate an immediate variant of the op, load both halves into
1762 // registers and emit the appropriate opcode.
1763 unsigned Op0r = getReg(Op0, MBB, IP);
1764 unsigned Op1r = getReg(Op1, MBB, IP);
1765 unsigned Opcode = OpcodeTab[OperatorClass];
1766 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
1769 // ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
1770 // returns zero when the input is not exactly a power of two.
1771 static unsigned ExactLog2(unsigned Val) {
1772 if (Val == 0 || (Val & (Val-1))) return 0;
1781 /// doMultiply - Emit appropriate instructions to multiply together the
1782 /// Values Op0 and Op1, and put the result in DestReg.
1784 void ISel::doMultiply(MachineBasicBlock *MBB,
1785 MachineBasicBlock::iterator IP,
1786 unsigned DestReg, Value *Op0, Value *Op1) {
1787 unsigned Class0 = getClass(Op0->getType());
1788 unsigned Class1 = getClass(Op1->getType());
1790 unsigned Op0r = getReg(Op0, MBB, IP);
1791 unsigned Op1r = getReg(Op1, MBB, IP);
1794 if (Class0 == cLong && Class1 == cLong) {
1795 BuildMI(*MBB, IP, PPC::MULLD, 2, DestReg).addReg(Op0r).addReg(Op1r);
1799 // 64 x 32 or less, promote 32 to 64 and do a 64 x 64
1800 if (Class0 == cLong && Class1 <= cInt) {
1801 // FIXME: CLEAR or SIGN EXTEND Op1
1802 BuildMI(*MBB, IP, PPC::MULLD, 2, DestReg).addReg(Op0r).addReg(Op1r);
1807 if (Class0 <= cInt && Class1 <= cInt) {
1808 BuildMI(*MBB, IP, PPC::MULLW, 2, DestReg).addReg(Op0r).addReg(Op1r);
1812 assert(0 && "doMultiply cannot operate on unknown type!");
1815 /// doMultiplyConst - This method will multiply the value in Op0 by the
1816 /// value of the ContantInt *CI
1817 void ISel::doMultiplyConst(MachineBasicBlock *MBB,
1818 MachineBasicBlock::iterator IP,
1819 unsigned DestReg, Value *Op0, ConstantInt *CI) {
1820 unsigned Class = getClass(Op0->getType());
1823 if (CI->isNullValue()) {
1824 BuildMI(*MBB, IP, PPC::LI, 1, DestReg).addSImm(0);
1828 // Mul op0, 1 ==> op0
1829 if (CI->equalsInt(1)) {
1830 unsigned Op0r = getReg(Op0, MBB, IP);
1831 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(Op0r).addReg(Op0r);
1835 // If the element size is exactly a power of 2, use a shift to get it.
1836 if (unsigned Shift = ExactLog2(CI->getRawValue())) {
1837 ConstantUInt *ShiftCI = ConstantUInt::get(Type::UByteTy, Shift);
1838 emitShiftOperation(MBB, IP, Op0, ShiftCI, true, Op0->getType(), DestReg);
1842 // If 32 bits or less and immediate is in right range, emit mul by immediate
1843 if (Class == cByte || Class == cShort || Class == cInt) {
1844 if (canUseAsImmediateForOpcode(CI, 0)) {
1845 unsigned Op0r = getReg(Op0, MBB, IP);
1846 unsigned imm = CI->getRawValue() & 0xFFFF;
1847 BuildMI(*MBB, IP, PPC::MULLI, 2, DestReg).addReg(Op0r).addSImm(imm);
1852 doMultiply(MBB, IP, DestReg, Op0, CI);
1855 void ISel::visitMul(BinaryOperator &I) {
1856 unsigned ResultReg = getReg(I);
1858 Value *Op0 = I.getOperand(0);
1859 Value *Op1 = I.getOperand(1);
1861 MachineBasicBlock::iterator IP = BB->end();
1862 emitMultiply(BB, IP, Op0, Op1, ResultReg);
1865 void ISel::emitMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
1866 Value *Op0, Value *Op1, unsigned DestReg) {
1867 TypeClass Class = getClass(Op0->getType());
1874 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
1875 doMultiplyConst(MBB, IP, DestReg, Op0, CI);
1877 doMultiply(MBB, IP, DestReg, Op0, Op1);
1882 emitBinaryFPOperation(MBB, IP, Op0, Op1, 2, DestReg);
1889 /// visitDivRem - Handle division and remainder instructions... these
1890 /// instruction both require the same instructions to be generated, they just
1891 /// select the result from a different register. Note that both of these
1892 /// instructions work differently for signed and unsigned operands.
1894 void ISel::visitDivRem(BinaryOperator &I) {
1895 unsigned ResultReg = getReg(I);
1896 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
1898 MachineBasicBlock::iterator IP = BB->end();
1899 emitDivRemOperation(BB, IP, Op0, Op1, I.getOpcode() == Instruction::Div,
1903 void ISel::emitDivRemOperation(MachineBasicBlock *BB,
1904 MachineBasicBlock::iterator IP,
1905 Value *Op0, Value *Op1, bool isDiv,
1906 unsigned ResultReg) {
1907 const Type *Ty = Op0->getType();
1908 unsigned Class = getClass(Ty);
1912 // Floating point divide...
1913 emitBinaryFPOperation(BB, IP, Op0, Op1, 3, ResultReg);
1916 // Floating point remainder via fmodf(float x, float y);
1917 unsigned Op0Reg = getReg(Op0, BB, IP);
1918 unsigned Op1Reg = getReg(Op1, BB, IP);
1919 MachineInstr *TheCall =
1920 BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(fmodfFn, true);
1921 std::vector<ValueRecord> Args;
1922 Args.push_back(ValueRecord(Op0Reg, Type::FloatTy));
1923 Args.push_back(ValueRecord(Op1Reg, Type::FloatTy));
1924 doCall(ValueRecord(ResultReg, Type::FloatTy), TheCall, Args, false);
1929 // Floating point divide...
1930 emitBinaryFPOperation(BB, IP, Op0, Op1, 3, ResultReg);
1933 // Floating point remainder via fmod(double x, double y);
1934 unsigned Op0Reg = getReg(Op0, BB, IP);
1935 unsigned Op1Reg = getReg(Op1, BB, IP);
1936 MachineInstr *TheCall =
1937 BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(fmodFn, true);
1938 std::vector<ValueRecord> Args;
1939 Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy));
1940 Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy));
1941 doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args, false);
1945 static Function* const Funcs[] =
1946 { __moddi3Fn, __divdi3Fn, __umoddi3Fn, __udivdi3Fn };
1947 unsigned Op0Reg = getReg(Op0, BB, IP);
1948 unsigned Op1Reg = getReg(Op1, BB, IP);
1949 unsigned NameIdx = Ty->isUnsigned()*2 + isDiv;
1950 MachineInstr *TheCall =
1951 BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(Funcs[NameIdx], true);
1953 std::vector<ValueRecord> Args;
1954 Args.push_back(ValueRecord(Op0Reg, Type::LongTy));
1955 Args.push_back(ValueRecord(Op1Reg, Type::LongTy));
1956 doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args, false);
1959 case cByte: case cShort: case cInt:
1960 break; // Small integrals, handled below...
1961 default: assert(0 && "Unknown class!");
1964 // Special case signed division by power of 2.
1966 if (ConstantSInt *CI = dyn_cast<ConstantSInt>(Op1)) {
1967 assert(Class != cLong && "This doesn't handle 64-bit divides!");
1968 int V = CI->getValue();
1970 if (V == 1) { // X /s 1 => X
1971 unsigned Op0Reg = getReg(Op0, BB, IP);
1972 BuildMI(*BB, IP, PPC::OR, 2, ResultReg).addReg(Op0Reg).addReg(Op0Reg);
1976 if (V == -1) { // X /s -1 => -X
1977 unsigned Op0Reg = getReg(Op0, BB, IP);
1978 BuildMI(*BB, IP, PPC::NEG, 1, ResultReg).addReg(Op0Reg);
1982 unsigned log2V = ExactLog2(V);
1983 if (log2V != 0 && Ty->isSigned()) {
1984 unsigned Op0Reg = getReg(Op0, BB, IP);
1985 unsigned TmpReg = makeAnotherReg(Op0->getType());
1987 BuildMI(*BB, IP, PPC::SRAWI, 2, TmpReg).addReg(Op0Reg).addImm(log2V);
1988 BuildMI(*BB, IP, PPC::ADDZE, 1, ResultReg).addReg(TmpReg);
1993 unsigned Op0Reg = getReg(Op0, BB, IP);
1994 unsigned Op1Reg = getReg(Op1, BB, IP);
1995 unsigned Opcode = Ty->isSigned() ? PPC::DIVW : PPC::DIVWU;
1998 BuildMI(*BB, IP, Opcode, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1999 } else { // Remainder
2000 unsigned TmpReg1 = makeAnotherReg(Op0->getType());
2001 unsigned TmpReg2 = makeAnotherReg(Op0->getType());
2003 BuildMI(*BB, IP, Opcode, 2, TmpReg1).addReg(Op0Reg).addReg(Op1Reg);
2004 BuildMI(*BB, IP, PPC::MULLW, 2, TmpReg2).addReg(TmpReg1).addReg(Op1Reg);
2005 BuildMI(*BB, IP, PPC::SUBF, 2, ResultReg).addReg(TmpReg2).addReg(Op0Reg);
2010 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
2011 /// for constant immediate shift values, and for constant immediate
2012 /// shift values equal to 1. Even the general case is sort of special,
2013 /// because the shift amount has to be in CL, not just any old register.
2015 void ISel::visitShiftInst(ShiftInst &I) {
2016 MachineBasicBlock::iterator IP = BB->end();
2017 emitShiftOperation(BB, IP, I.getOperand(0), I.getOperand(1),
2018 I.getOpcode() == Instruction::Shl, I.getType(),
2022 /// emitShiftOperation - Common code shared between visitShiftInst and
2023 /// constant expression support.
2025 void ISel::emitShiftOperation(MachineBasicBlock *MBB,
2026 MachineBasicBlock::iterator IP,
2027 Value *Op, Value *ShiftAmount, bool isLeftShift,
2028 const Type *ResultTy, unsigned DestReg) {
2029 unsigned SrcReg = getReg (Op, MBB, IP);
2030 bool isSigned = ResultTy->isSigned ();
2031 unsigned Class = getClass (ResultTy);
2033 // Longs, as usual, are handled specially...
2034 if (Class == cLong) {
2035 // If we have a constant shift, we can generate much more efficient code
2036 // than otherwise...
2038 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
2039 unsigned Amount = CUI->getValue();
2040 assert(Amount < 64 && "Invalid immediate shift amount!");
2042 BuildMI(*MBB, IP, PPC::RLDICR, 3, DestReg).addReg(SrcReg).addImm(Amount)
2046 BuildMI(*MBB, IP, PPC::SRADI, 2, DestReg).addReg(SrcReg)
2049 BuildMI(*MBB, IP, PPC::RLDICL, 3, DestReg).addReg(SrcReg)
2050 .addImm(64-Amount).addImm(Amount);
2054 unsigned ShiftReg = getReg (ShiftAmount, MBB, IP);
2057 BuildMI(*MBB, IP, PPC::SLD, 2, DestReg).addReg(SrcReg).addReg(ShiftReg);
2059 unsigned Opcode = (isSigned) ? PPC::SRAD : PPC::SRD;
2060 BuildMI(*MBB, IP, Opcode, DestReg).addReg(SrcReg).addReg(ShiftReg);
2066 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
2067 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
2068 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
2069 unsigned Amount = CUI->getValue();
2072 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
2073 .addImm(Amount).addImm(0).addImm(31-Amount);
2076 BuildMI(*MBB, IP, PPC::SRAWI,2,DestReg).addReg(SrcReg).addImm(Amount);
2078 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
2079 .addImm(32-Amount).addImm(Amount).addImm(31);
2082 } else { // The shift amount is non-constant.
2083 unsigned ShiftAmountReg = getReg(ShiftAmount, MBB, IP);
2086 BuildMI(*MBB, IP, PPC::SLW, 2, DestReg).addReg(SrcReg)
2087 .addReg(ShiftAmountReg);
2089 BuildMI(*MBB, IP, isSigned ? PPC::SRAW : PPC::SRW, 2, DestReg)
2090 .addReg(SrcReg).addReg(ShiftAmountReg);
2096 /// visitLoadInst - Implement LLVM load instructions. Pretty straightforward
2097 /// mapping of LLVM classes to PPC load instructions, with the exception of
2098 /// signed byte loads, which need a sign extension following them.
2100 void ISel::visitLoadInst(LoadInst &I) {
2101 // Immediate opcodes, for reg+imm addressing
2102 static const unsigned ImmOpcodes[] = {
2103 PPC::LBZ, PPC::LHZ, PPC::LWZ,
2104 PPC::LFS, PPC::LFD, PPC::LWZ
2106 // Indexed opcodes, for reg+reg addressing
2107 static const unsigned IdxOpcodes[] = {
2108 PPC::LBZX, PPC::LHZX, PPC::LWZX,
2109 PPC::LFSX, PPC::LFDX, PPC::LWZX
2112 unsigned Class = getClassB(I.getType());
2113 unsigned ImmOpcode = ImmOpcodes[Class];
2114 unsigned IdxOpcode = IdxOpcodes[Class];
2115 unsigned DestReg = getReg(I);
2116 Value *SourceAddr = I.getOperand(0);
2118 if (Class == cShort && I.getType()->isSigned()) ImmOpcode = PPC::LHA;
2119 if (Class == cShort && I.getType()->isSigned()) IdxOpcode = PPC::LHAX;
2121 if (AllocaInst *AI = dyn_castFixedAlloca(SourceAddr)) {
2122 unsigned FI = getFixedSizedAllocaFI(AI);
2123 if (Class == cByte && I.getType()->isSigned()) {
2124 unsigned TmpReg = makeAnotherReg(I.getType());
2125 addFrameReference(BuildMI(BB, ImmOpcode, 2, TmpReg), FI);
2126 BuildMI(BB, PPC::EXTSB, 1, DestReg).addReg(TmpReg);
2128 addFrameReference(BuildMI(BB, ImmOpcode, 2, DestReg), FI);
2133 // If this load is the only use of the GEP instruction that is its address,
2134 // then we can fold the GEP directly into the load instruction.
2135 // emitGEPOperation with a second to last arg of 'true' will place the
2136 // base register for the GEP into baseReg, and the constant offset from that
2137 // into offset. If the offset fits in 16 bits, we can emit a reg+imm store
2138 // otherwise, we copy the offset into another reg, and use reg+reg addressing.
2139 if (GetElementPtrInst *GEPI = canFoldGEPIntoLoadOrStore(SourceAddr)) {
2140 unsigned baseReg = getReg(GEPI);
2141 unsigned pendingAdd;
2142 ConstantSInt *offset;
2144 emitGEPOperation(BB, BB->end(), GEPI->getOperand(0), GEPI->op_begin()+1,
2145 GEPI->op_end(), baseReg, true, &offset, &pendingAdd);
2147 if (pendingAdd == 0 && Class != cLong &&
2148 canUseAsImmediateForOpcode(offset, 0)) {
2149 if (Class == cByte && I.getType()->isSigned()) {
2150 unsigned TmpReg = makeAnotherReg(I.getType());
2151 BuildMI(BB, ImmOpcode, 2, TmpReg).addSImm(offset->getValue())
2153 BuildMI(BB, PPC::EXTSB, 1, DestReg).addReg(TmpReg);
2155 BuildMI(BB, ImmOpcode, 2, DestReg).addSImm(offset->getValue())
2161 unsigned indexReg = (pendingAdd != 0) ? pendingAdd : getReg(offset);
2163 if (Class == cByte && I.getType()->isSigned()) {
2164 unsigned TmpReg = makeAnotherReg(I.getType());
2165 BuildMI(BB, IdxOpcode, 2, TmpReg).addReg(indexReg).addReg(baseReg);
2166 BuildMI(BB, PPC::EXTSB, 1, DestReg).addReg(TmpReg);
2168 BuildMI(BB, IdxOpcode, 2, DestReg).addReg(indexReg).addReg(baseReg);
2173 // The fallback case, where the load was from a source that could not be
2174 // folded into the load instruction.
2175 unsigned SrcAddrReg = getReg(SourceAddr);
2177 if (Class == cByte && I.getType()->isSigned()) {
2178 unsigned TmpReg = makeAnotherReg(I.getType());
2179 BuildMI(BB, ImmOpcode, 2, TmpReg).addSImm(0).addReg(SrcAddrReg);
2180 BuildMI(BB, PPC::EXTSB, 1, DestReg).addReg(TmpReg);
2182 BuildMI(BB, ImmOpcode, 2, DestReg).addSImm(0).addReg(SrcAddrReg);
2186 /// visitStoreInst - Implement LLVM store instructions
2188 void ISel::visitStoreInst(StoreInst &I) {
2189 // Immediate opcodes, for reg+imm addressing
2190 static const unsigned ImmOpcodes[] = {
2191 PPC::STB, PPC::STH, PPC::STW,
2192 PPC::STFS, PPC::STFD, PPC::STW
2194 // Indexed opcodes, for reg+reg addressing
2195 static const unsigned IdxOpcodes[] = {
2196 PPC::STBX, PPC::STHX, PPC::STWX,
2197 PPC::STFSX, PPC::STFDX, PPC::STWX
2200 Value *SourceAddr = I.getOperand(1);
2201 const Type *ValTy = I.getOperand(0)->getType();
2202 unsigned Class = getClassB(ValTy);
2203 unsigned ImmOpcode = ImmOpcodes[Class];
2204 unsigned IdxOpcode = IdxOpcodes[Class];
2205 unsigned ValReg = getReg(I.getOperand(0));
2207 // If this store is the only use of the GEP instruction that is its address,
2208 // then we can fold the GEP directly into the store instruction.
2209 // emitGEPOperation with a second to last arg of 'true' will place the
2210 // base register for the GEP into baseReg, and the constant offset from that
2211 // into offset. If the offset fits in 16 bits, we can emit a reg+imm store
2212 // otherwise, we copy the offset into another reg, and use reg+reg addressing.
2213 if (GetElementPtrInst *GEPI = canFoldGEPIntoLoadOrStore(SourceAddr)) {
2214 unsigned baseReg = getReg(GEPI);
2215 unsigned pendingAdd;
2216 ConstantSInt *offset;
2218 emitGEPOperation(BB, BB->end(), GEPI->getOperand(0), GEPI->op_begin()+1,
2219 GEPI->op_end(), baseReg, true, &offset, &pendingAdd);
2221 if (0 == pendingAdd && Class != cLong &&
2222 canUseAsImmediateForOpcode(offset, 0)) {
2223 BuildMI(BB, ImmOpcode, 3).addReg(ValReg).addSImm(offset->getValue())
2228 unsigned indexReg = (pendingAdd != 0) ? pendingAdd : getReg(offset);
2229 BuildMI(BB, IdxOpcode, 3).addReg(ValReg).addReg(indexReg).addReg(baseReg);
2233 // If the store address wasn't the only use of a GEP, we fall back to the
2234 // standard path: store the ValReg at the value in AddressReg.
2235 unsigned AddressReg = getReg(I.getOperand(1));
2236 BuildMI(BB, ImmOpcode, 3).addReg(ValReg).addSImm(0).addReg(AddressReg);
2240 /// visitCastInst - Here we have various kinds of copying with or without sign
2241 /// extension going on.
2243 void ISel::visitCastInst(CastInst &CI) {
2244 Value *Op = CI.getOperand(0);
2246 unsigned SrcClass = getClassB(Op->getType());
2247 unsigned DestClass = getClassB(CI.getType());
2249 // If this is a cast from a 32-bit integer to a Long type, and the only uses
2250 // of the case are GEP instructions, then the cast does not need to be
2251 // generated explicitly, it will be folded into the GEP.
2252 if (DestClass == cLong && SrcClass == cInt) {
2253 bool AllUsesAreGEPs = true;
2254 for (Value::use_iterator I = CI.use_begin(), E = CI.use_end(); I != E; ++I)
2255 if (!isa<GetElementPtrInst>(*I)) {
2256 AllUsesAreGEPs = false;
2260 // No need to codegen this cast if all users are getelementptr instrs...
2261 if (AllUsesAreGEPs) return;
2264 unsigned DestReg = getReg(CI);
2265 MachineBasicBlock::iterator MI = BB->end();
2266 emitCastOperation(BB, MI, Op, CI.getType(), DestReg);
2269 /// emitCastOperation - Common code shared between visitCastInst and constant
2270 /// expression cast support.
2272 void ISel::emitCastOperation(MachineBasicBlock *MBB,
2273 MachineBasicBlock::iterator IP,
2274 Value *Src, const Type *DestTy,
2276 const Type *SrcTy = Src->getType();
2277 unsigned SrcClass = getClassB(SrcTy);
2278 unsigned DestClass = getClassB(DestTy);
2279 unsigned SrcReg = getReg(Src, MBB, IP);
2281 // Implement casts to bool by using compare on the operand followed by set if
2282 // not zero on the result.
2283 if (DestTy == Type::BoolTy) {
2289 unsigned TmpReg = makeAnotherReg(Type::IntTy);
2290 BuildMI(*MBB, IP, PPC::ADDIC, 2, TmpReg).addReg(SrcReg).addSImm(-1);
2291 BuildMI(*MBB, IP, PPC::SUBFE, 2, DestReg).addReg(TmpReg).addReg(SrcReg);
2297 std::cerr << "ERROR: Cast fp-to-bool not implemented!\n";
2303 // Handle cast of Float -> Double
2304 if (SrcClass == cFP32 && DestClass == cFP64) {
2305 BuildMI(*MBB, IP, PPC::FMR, 1, DestReg).addReg(SrcReg);
2309 // Handle cast of Double -> Float
2310 if (SrcClass == cFP64 && DestClass == cFP32) {
2311 BuildMI(*MBB, IP, PPC::FRSP, 1, DestReg).addReg(SrcReg);
2315 // Handle casts from integer to floating point now...
2316 if (DestClass == cFP32 || DestClass == cFP64) {
2318 // Emit a library call for long to float conversion
2319 if (SrcClass == cLong) {
2320 std::vector<ValueRecord> Args;
2321 Args.push_back(ValueRecord(SrcReg, SrcTy));
2322 Function *floatFn = (DestClass == cFP32) ? __floatdisfFn : __floatdidfFn;
2323 MachineInstr *TheCall =
2324 BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(floatFn, true);
2325 doCall(ValueRecord(DestReg, DestTy), TheCall, Args, false);
2329 // Make sure we're dealing with a full 32 bits
2330 unsigned TmpReg = makeAnotherReg(Type::IntTy);
2331 promote32(TmpReg, ValueRecord(SrcReg, SrcTy));
2335 // Spill the integer to memory and reload it from there.
2336 // Also spill room for a special conversion constant
2337 int ConstantFrameIndex =
2338 F->getFrameInfo()->CreateStackObject(Type::DoubleTy, TM.getTargetData());
2340 F->getFrameInfo()->CreateStackObject(Type::DoubleTy, TM.getTargetData());
2342 unsigned constantHi = makeAnotherReg(Type::IntTy);
2343 unsigned constantLo = makeAnotherReg(Type::IntTy);
2344 unsigned ConstF = makeAnotherReg(Type::DoubleTy);
2345 unsigned TempF = makeAnotherReg(Type::DoubleTy);
2347 if (!SrcTy->isSigned()) {
2348 BuildMI(*BB, IP, PPC::LIS, 1, constantHi).addSImm(0x4330);
2349 BuildMI(*BB, IP, PPC::LI, 1, constantLo).addSImm(0);
2350 addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(constantHi),
2351 ConstantFrameIndex);
2352 addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(constantLo),
2353 ConstantFrameIndex, 4);
2354 addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(constantHi),
2356 addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(SrcReg),
2358 addFrameReference(BuildMI(*BB, IP, PPC::LFD, 2, ConstF),
2359 ConstantFrameIndex);
2360 addFrameReference(BuildMI(*BB, IP, PPC::LFD, 2, TempF), ValueFrameIdx);
2361 BuildMI(*BB, IP, PPC::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF);
2363 unsigned TempLo = makeAnotherReg(Type::IntTy);
2364 BuildMI(*BB, IP, PPC::LIS, 1, constantHi).addSImm(0x4330);
2365 BuildMI(*BB, IP, PPC::LIS, 1, constantLo).addSImm(0x8000);
2366 addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(constantHi),
2367 ConstantFrameIndex);
2368 addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(constantLo),
2369 ConstantFrameIndex, 4);
2370 addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(constantHi),
2372 BuildMI(*BB, IP, PPC::XORIS, 2, TempLo).addReg(SrcReg).addImm(0x8000);
2373 addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(TempLo),
2375 addFrameReference(BuildMI(*BB, IP, PPC::LFD, 2, ConstF),
2376 ConstantFrameIndex);
2377 addFrameReference(BuildMI(*BB, IP, PPC::LFD, 2, TempF), ValueFrameIdx);
2378 BuildMI(*BB, IP, PPC::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF);
2383 // Handle casts from floating point to integer now...
2384 if (SrcClass == cFP32 || SrcClass == cFP64) {
2385 static Function* const Funcs[] =
2386 { __fixsfdiFn, __fixdfdiFn, __fixunssfdiFn, __fixunsdfdiFn };
2387 // emit library call
2388 if (DestClass == cLong) {
2389 bool isDouble = SrcClass == cFP64;
2390 unsigned nameIndex = 2 * DestTy->isSigned() + isDouble;
2391 std::vector<ValueRecord> Args;
2392 Args.push_back(ValueRecord(SrcReg, SrcTy));
2393 Function *floatFn = Funcs[nameIndex];
2394 MachineInstr *TheCall =
2395 BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(floatFn, true);
2396 doCall(ValueRecord(DestReg, DestTy), TheCall, Args, false);
2401 F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
2403 if (DestTy->isSigned()) {
2404 unsigned TempReg = makeAnotherReg(Type::DoubleTy);
2406 // Convert to integer in the FP reg and store it to a stack slot
2407 BuildMI(*BB, IP, PPC::FCTIWZ, 1, TempReg).addReg(SrcReg);
2408 addFrameReference(BuildMI(*BB, IP, PPC::STFD, 3)
2409 .addReg(TempReg), ValueFrameIdx);
2411 // There is no load signed byte opcode, so we must emit a sign extend for
2412 // that particular size. Make sure to source the new integer from the
2414 if (DestClass == cByte) {
2415 unsigned TempReg2 = makeAnotherReg(DestTy);
2416 addFrameReference(BuildMI(*BB, IP, PPC::LBZ, 2, TempReg2),
2418 BuildMI(*MBB, IP, PPC::EXTSB, DestReg).addReg(TempReg2);
2420 int offset = (DestClass == cShort) ? 6 : 4;
2421 unsigned LoadOp = (DestClass == cShort) ? PPC::LHA : PPC::LWZ;
2422 addFrameReference(BuildMI(*BB, IP, LoadOp, 2, DestReg),
2423 ValueFrameIdx, offset);
2426 unsigned Zero = getReg(ConstantFP::get(Type::DoubleTy, 0.0f));
2427 double maxInt = (1LL << 32) - 1;
2428 unsigned MaxInt = getReg(ConstantFP::get(Type::DoubleTy, maxInt));
2429 double border = 1LL << 31;
2430 unsigned Border = getReg(ConstantFP::get(Type::DoubleTy, border));
2431 unsigned UseZero = makeAnotherReg(Type::DoubleTy);
2432 unsigned UseMaxInt = makeAnotherReg(Type::DoubleTy);
2433 unsigned UseChoice = makeAnotherReg(Type::DoubleTy);
2434 unsigned TmpReg = makeAnotherReg(Type::DoubleTy);
2435 unsigned TmpReg2 = makeAnotherReg(Type::DoubleTy);
2436 unsigned ConvReg = makeAnotherReg(Type::DoubleTy);
2437 unsigned IntTmp = makeAnotherReg(Type::IntTy);
2438 unsigned XorReg = makeAnotherReg(Type::IntTy);
2440 F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
2441 // Update machine-CFG edges
2442 MachineBasicBlock *XorMBB = new MachineBasicBlock(BB->getBasicBlock());
2443 MachineBasicBlock *PhiMBB = new MachineBasicBlock(BB->getBasicBlock());
2444 MachineBasicBlock *OldMBB = BB;
2445 ilist<MachineBasicBlock>::iterator It = BB; ++It;
2446 F->getBasicBlockList().insert(It, XorMBB);
2447 F->getBasicBlockList().insert(It, PhiMBB);
2448 BB->addSuccessor(XorMBB);
2449 BB->addSuccessor(PhiMBB);
2451 // Convert from floating point to unsigned 32-bit value
2452 // Use 0 if incoming value is < 0.0
2453 BuildMI(*BB, IP, PPC::FSEL, 3, UseZero).addReg(SrcReg).addReg(SrcReg)
2455 // Use 2**32 - 1 if incoming value is >= 2**32
2456 BuildMI(*BB, IP, PPC::FSUB, 2, UseMaxInt).addReg(MaxInt).addReg(SrcReg);
2457 BuildMI(*BB, IP, PPC::FSEL, 3, UseChoice).addReg(UseMaxInt)
2458 .addReg(UseZero).addReg(MaxInt);
2460 BuildMI(*BB, IP, PPC::FSUB, 2, TmpReg).addReg(UseChoice).addReg(Border);
2461 // Use difference if >= 2**31
2462 BuildMI(*BB, IP, PPC::FCMPU, 2, PPC::CR0).addReg(UseChoice)
2464 BuildMI(*BB, IP, PPC::FSEL, 3, TmpReg2).addReg(TmpReg).addReg(TmpReg)
2466 // Convert to integer
2467 BuildMI(*BB, IP, PPC::FCTIWZ, 1, ConvReg).addReg(TmpReg2);
2468 addFrameReference(BuildMI(*BB, IP, PPC::STFD, 3).addReg(ConvReg),
2470 if (DestClass == cByte) {
2471 addFrameReference(BuildMI(*BB, IP, PPC::LBZ, 2, DestReg),
2473 } else if (DestClass == cShort) {
2474 addFrameReference(BuildMI(*BB, IP, PPC::LHZ, 2, DestReg),
2476 } if (DestClass == cInt) {
2477 addFrameReference(BuildMI(*BB, IP, PPC::LWZ, 2, IntTmp),
2479 BuildMI(*BB, IP, PPC::BLT, 2).addReg(PPC::CR0).addMBB(PhiMBB);
2480 BuildMI(*BB, IP, PPC::B, 1).addMBB(XorMBB);
2483 // add 2**31 if input was >= 2**31
2485 BuildMI(BB, PPC::XORIS, 2, XorReg).addReg(IntTmp).addImm(0x8000);
2486 XorMBB->addSuccessor(PhiMBB);
2489 // DestReg = phi [ IntTmp, OldMBB ], [ XorReg, XorMBB ]
2491 BuildMI(BB, PPC::PHI, 4, DestReg).addReg(IntTmp).addMBB(OldMBB)
2492 .addReg(XorReg).addMBB(XorMBB);
2498 // Check our invariants
2499 assert((SrcClass <= cInt || SrcClass == cLong) &&
2500 "Unhandled source class for cast operation!");
2501 assert((DestClass <= cInt || DestClass == cLong) &&
2502 "Unhandled destination class for cast operation!");
2504 bool sourceUnsigned = SrcTy->isUnsigned() || SrcTy == Type::BoolTy;
2505 bool destUnsigned = DestTy->isUnsigned();
2507 // Unsigned -> Unsigned, clear if larger
2508 if (sourceUnsigned && destUnsigned) {
2509 // handle long dest class now to keep switch clean
2510 if (DestClass == cLong) {
2511 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2515 // handle u{ byte, short, int } x u{ byte, short, int }
2516 unsigned clearBits = (SrcClass == cByte || DestClass == cByte) ? 24 : 16;
2520 if (SrcClass == DestClass)
2521 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2523 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
2524 .addImm(0).addImm(clearBits).addImm(31);
2528 if (DestClass == cInt)
2529 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2531 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
2532 .addImm(0).addImm(clearBits).addImm(31);
2539 if (!sourceUnsigned && !destUnsigned) {
2540 // handle long dest class now to keep switch clean
2541 if (DestClass == cLong) {
2542 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2546 // handle { byte, short, int } x { byte, short, int }
2549 if (DestClass == cByte)
2550 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2552 BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
2555 if (DestClass == cByte)
2556 BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
2557 else if (DestClass == cShort)
2558 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2560 BuildMI(*MBB, IP, PPC::EXTSH, 1, DestReg).addReg(SrcReg);
2564 if (DestClass == cByte)
2565 BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
2566 else if (DestClass == cShort)
2567 BuildMI(*MBB, IP, PPC::EXTSH, 1, DestReg).addReg(SrcReg);
2569 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2575 // Unsigned -> Signed
2576 if (sourceUnsigned && !destUnsigned) {
2577 // handle long dest class now to keep switch clean
2578 if (DestClass == cLong) {
2579 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2583 // handle u{ byte, short, int } -> { byte, short, int }
2586 if (DestClass == cByte)
2587 // uByte 255 -> signed byte == -1
2588 BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
2590 // uByte 255 -> signed short/int == 255
2591 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg).addImm(0)
2592 .addImm(24).addImm(31);
2595 if (DestClass == cByte)
2596 BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
2597 else if (DestClass == cShort)
2598 BuildMI(*MBB, IP, PPC::EXTSH, 1, DestReg).addReg(SrcReg);
2600 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg).addImm(0)
2601 .addImm(16).addImm(31);
2605 if (DestClass == cByte)
2606 BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
2607 else if (DestClass == cShort)
2608 BuildMI(*MBB, IP, PPC::EXTSH, 1, DestReg).addReg(SrcReg);
2610 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2616 // Signed -> Unsigned
2617 if (!sourceUnsigned && destUnsigned) {
2618 // handle long dest class now to keep switch clean
2619 if (DestClass == cLong) {
2620 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2624 // handle { byte, short, int } -> u{ byte, short, int }
2625 unsigned clearBits = (DestClass == cByte) ? 24 : 16;
2629 if (DestClass == cByte || DestClass == cShort)
2630 // sbyte -1 -> ubyte 0x000000FF
2631 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
2632 .addImm(0).addImm(clearBits).addImm(31);
2634 // sbyte -1 -> ubyte 0xFFFFFFFF
2635 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2639 if (DestClass == cInt)
2640 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2642 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
2643 .addImm(0).addImm(clearBits).addImm(31);
2649 // Anything we haven't handled already, we can't (yet) handle at all.
2650 std::cerr << "Unhandled cast from " << SrcTy->getDescription()
2651 << "to " << DestTy->getDescription() << '\n';
2655 /// visitVANextInst - Implement the va_next instruction...
2657 void ISel::visitVANextInst(VANextInst &I) {
2658 unsigned VAList = getReg(I.getOperand(0));
2659 unsigned DestReg = getReg(I);
2662 switch (I.getArgType()->getTypeID()) {
2665 assert(0 && "Error: bad type for va_next instruction!");
2667 case Type::PointerTyID:
2668 case Type::UIntTyID:
2672 case Type::ULongTyID:
2673 case Type::LongTyID:
2674 case Type::DoubleTyID:
2679 // Increment the VAList pointer...
2680 BuildMI(BB, PPC::ADDI, 2, DestReg).addReg(VAList).addSImm(Size);
2683 void ISel::visitVAArgInst(VAArgInst &I) {
2684 unsigned VAList = getReg(I.getOperand(0));
2685 unsigned DestReg = getReg(I);
2687 switch (I.getType()->getTypeID()) {
2690 assert(0 && "Error: bad type for va_next instruction!");
2692 case Type::PointerTyID:
2693 case Type::UIntTyID:
2695 BuildMI(BB, PPC::LWZ, 2, DestReg).addSImm(0).addReg(VAList);
2697 case Type::ULongTyID:
2698 case Type::LongTyID:
2699 BuildMI(BB, PPC::LD, 2, DestReg).addSImm(0).addReg(VAList);
2701 case Type::FloatTyID:
2702 BuildMI(BB, PPC::LFS, 2, DestReg).addSImm(0).addReg(VAList);
2704 case Type::DoubleTyID:
2705 BuildMI(BB, PPC::LFD, 2, DestReg).addSImm(0).addReg(VAList);
2710 /// visitGetElementPtrInst - instruction-select GEP instructions
2712 void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
2713 if (canFoldGEPIntoLoadOrStore(&I))
2716 unsigned outputReg = getReg(I);
2717 emitGEPOperation(BB, BB->end(), I.getOperand(0), I.op_begin()+1, I.op_end(),
2718 outputReg, false, 0, 0);
2721 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
2722 /// constant expression GEP support.
2724 void ISel::emitGEPOperation(MachineBasicBlock *MBB,
2725 MachineBasicBlock::iterator IP,
2726 Value *Src, User::op_iterator IdxBegin,
2727 User::op_iterator IdxEnd, unsigned TargetReg,
2728 bool GEPIsFolded, ConstantSInt **RemainderPtr,
2729 unsigned *PendingAddReg) {
2730 const TargetData &TD = TM.getTargetData();
2731 const Type *Ty = Src->getType();
2732 unsigned basePtrReg = getReg(Src, MBB, IP);
2733 int64_t constValue = 0;
2735 // Record the operations to emit the GEP in a vector so that we can emit them
2736 // after having analyzed the entire instruction.
2737 std::vector<CollapsedGepOp> ops;
2739 // GEPs have zero or more indices; we must perform a struct access
2740 // or array access for each one.
2741 for (GetElementPtrInst::op_iterator oi = IdxBegin, oe = IdxEnd; oi != oe;
2744 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2745 // It's a struct access. idx is the index into the structure,
2746 // which names the field. Use the TargetData structure to
2747 // pick out what the layout of the structure is in memory.
2748 // Use the (constant) structure index's value to find the
2749 // right byte offset from the StructLayout class's list of
2750 // structure member offsets.
2751 unsigned fieldIndex = cast<ConstantUInt>(idx)->getValue();
2752 unsigned memberOffset =
2753 TD.getStructLayout(StTy)->MemberOffsets[fieldIndex];
2755 // StructType member offsets are always constant values. Add it to the
2757 constValue += memberOffset;
2759 // The next type is the member of the structure selected by the
2761 Ty = StTy->getElementType (fieldIndex);
2762 } else if (const SequentialType *SqTy = dyn_cast<SequentialType> (Ty)) {
2763 // Many GEP instructions use a [cast (int/uint) to LongTy] as their
2764 // operand. Handle this case directly now...
2765 if (CastInst *CI = dyn_cast<CastInst>(idx))
2766 if (CI->getOperand(0)->getType() == Type::IntTy ||
2767 CI->getOperand(0)->getType() == Type::UIntTy)
2768 idx = CI->getOperand(0);
2770 // It's an array or pointer access: [ArraySize x ElementType].
2771 // We want to add basePtrReg to (idxReg * sizeof ElementType). First, we
2772 // must find the size of the pointed-to type (Not coincidentally, the next
2773 // type is the type of the elements in the array).
2774 Ty = SqTy->getElementType();
2775 unsigned elementSize = TD.getTypeSize(Ty);
2777 if (ConstantInt *C = dyn_cast<ConstantInt>(idx)) {
2778 if (ConstantSInt *CS = dyn_cast<ConstantSInt>(C))
2779 constValue += CS->getValue() * elementSize;
2780 else if (ConstantUInt *CU = dyn_cast<ConstantUInt>(C))
2781 constValue += CU->getValue() * elementSize;
2783 assert(0 && "Invalid ConstantInt GEP index type!");
2785 // Push current gep state to this point as an add
2786 ops.push_back(CollapsedGepOp(false, 0,
2787 ConstantSInt::get(Type::IntTy,constValue)));
2789 // Push multiply gep op and reset constant value
2790 ops.push_back(CollapsedGepOp(true, idx,
2791 ConstantSInt::get(Type::IntTy, elementSize)));
2797 // Emit instructions for all the collapsed ops
2798 bool pendingAdd = false;
2799 unsigned pendingAddReg = 0;
2801 for(std::vector<CollapsedGepOp>::iterator cgo_i = ops.begin(),
2802 cgo_e = ops.end(); cgo_i != cgo_e; ++cgo_i) {
2803 CollapsedGepOp& cgo = *cgo_i;
2804 unsigned nextBasePtrReg = makeAnotherReg(Type::IntTy);
2806 // If we didn't emit an add last time through the loop, we need to now so
2807 // that the base reg is updated appropriately.
2809 assert(pendingAddReg != 0 && "Uninitialized register in pending add!");
2810 BuildMI(*MBB, IP, PPC::ADD, 2, nextBasePtrReg).addReg(basePtrReg)
2811 .addReg(pendingAddReg);
2812 basePtrReg = nextBasePtrReg;
2813 nextBasePtrReg = makeAnotherReg(Type::IntTy);
2819 // We know the elementSize is a constant, so we can emit a constant mul
2820 unsigned TmpReg = makeAnotherReg(Type::IntTy);
2821 doMultiplyConst(MBB, IP, nextBasePtrReg, cgo.index, cgo.size);
2822 pendingAddReg = basePtrReg;
2825 // Try and generate an immediate addition if possible
2826 if (cgo.size->isNullValue()) {
2827 BuildMI(*MBB, IP, PPC::OR, 2, nextBasePtrReg).addReg(basePtrReg)
2828 .addReg(basePtrReg);
2829 } else if (canUseAsImmediateForOpcode(cgo.size, 0)) {
2830 BuildMI(*MBB, IP, PPC::ADDI, 2, nextBasePtrReg).addReg(basePtrReg)
2831 .addSImm(cgo.size->getValue());
2833 unsigned Op1r = getReg(cgo.size, MBB, IP);
2834 BuildMI(*MBB, IP, PPC::ADD, 2, nextBasePtrReg).addReg(basePtrReg)
2839 basePtrReg = nextBasePtrReg;
2841 // Add the current base register plus any accumulated constant value
2842 ConstantSInt *remainder = ConstantSInt::get(Type::IntTy, constValue);
2844 // If we are emitting this during a fold, copy the current base register to
2845 // the target, and save the current constant offset so the folding load or
2846 // store can try and use it as an immediate.
2848 // If this is a folded GEP and the last element was an index, then we need
2849 // to do some extra work to turn a shift/add/stw into a shift/stwx
2850 if (pendingAdd && 0 == remainder->getValue()) {
2851 assert(pendingAddReg != 0 && "Uninitialized register in pending add!");
2852 *PendingAddReg = pendingAddReg;
2856 unsigned nextBasePtrReg = makeAnotherReg(Type::IntTy);
2857 assert(pendingAddReg != 0 && "Uninitialized register in pending add!");
2858 BuildMI(*MBB, IP, PPC::ADD, 2, nextBasePtrReg).addReg(basePtrReg)
2859 .addReg(pendingAddReg);
2860 basePtrReg = nextBasePtrReg;
2863 BuildMI (*MBB, IP, PPC::OR, 2, TargetReg).addReg(basePtrReg)
2864 .addReg(basePtrReg);
2865 *RemainderPtr = remainder;
2869 // If we still have a pending add at this point, emit it now
2871 unsigned TmpReg = makeAnotherReg(Type::IntTy);
2872 BuildMI(*MBB, IP, PPC::ADD, 2, TmpReg).addReg(pendingAddReg)
2873 .addReg(basePtrReg);
2874 basePtrReg = TmpReg;
2877 // After we have processed all the indices, the result is left in
2878 // basePtrReg. Move it to the register where we were expected to
2880 if (remainder->isNullValue()) {
2881 BuildMI (*MBB, IP, PPC::OR, 2, TargetReg).addReg(basePtrReg)
2882 .addReg(basePtrReg);
2883 } else if (canUseAsImmediateForOpcode(remainder, 0)) {
2884 BuildMI(*MBB, IP, PPC::ADDI, 2, TargetReg).addReg(basePtrReg)
2885 .addSImm(remainder->getValue());
2887 unsigned Op1r = getReg(remainder, MBB, IP);
2888 BuildMI(*MBB, IP, PPC::ADD, 2, TargetReg).addReg(basePtrReg).addReg(Op1r);
2892 /// visitAllocaInst - If this is a fixed size alloca, allocate space from the
2893 /// frame manager, otherwise do it the hard way.
2895 void ISel::visitAllocaInst(AllocaInst &I) {
2896 // If this is a fixed size alloca in the entry block for the function, we
2897 // statically stack allocate the space, so we don't need to do anything here.
2899 if (dyn_castFixedAlloca(&I)) return;
2901 // Find the data size of the alloca inst's getAllocatedType.
2902 const Type *Ty = I.getAllocatedType();
2903 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
2905 // Create a register to hold the temporary result of multiplying the type size
2906 // constant by the variable amount.
2907 unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
2909 // TotalSizeReg = mul <numelements>, <TypeSize>
2910 MachineBasicBlock::iterator MBBI = BB->end();
2911 ConstantUInt *CUI = ConstantUInt::get(Type::UIntTy, TySize);
2912 doMultiplyConst(BB, MBBI, TotalSizeReg, I.getArraySize(), CUI);
2914 // AddedSize = add <TotalSizeReg>, 15
2915 unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy);
2916 BuildMI(BB, PPC::ADDI, 2, AddedSizeReg).addReg(TotalSizeReg).addSImm(15);
2918 // AlignedSize = and <AddedSize>, ~15
2919 unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
2920 BuildMI(BB, PPC::RLWINM, 4, AlignedSize).addReg(AddedSizeReg).addImm(0)
2921 .addImm(0).addImm(27);
2923 // Subtract size from stack pointer, thereby allocating some space.
2924 BuildMI(BB, PPC::SUB, 2, PPC::R1).addReg(PPC::R1).addReg(AlignedSize);
2926 // Put a pointer to the space into the result register, by copying
2927 // the stack pointer.
2928 BuildMI(BB, PPC::OR, 2, getReg(I)).addReg(PPC::R1).addReg(PPC::R1);
2930 // Inform the Frame Information that we have just allocated a variable-sized
2932 F->getFrameInfo()->CreateVariableSizedObject();
2935 /// visitMallocInst - Malloc instructions are code generated into direct calls
2936 /// to the library malloc.
2938 void ISel::visitMallocInst(MallocInst &I) {
2939 unsigned AllocSize = TM.getTargetData().getTypeSize(I.getAllocatedType());
2942 if (ConstantUInt *C = dyn_cast<ConstantUInt>(I.getOperand(0))) {
2943 Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize));
2945 Arg = makeAnotherReg(Type::UIntTy);
2946 MachineBasicBlock::iterator MBBI = BB->end();
2947 ConstantUInt *CUI = ConstantUInt::get(Type::UIntTy, AllocSize);
2948 doMultiplyConst(BB, MBBI, Arg, I.getOperand(0), CUI);
2951 std::vector<ValueRecord> Args;
2952 Args.push_back(ValueRecord(Arg, Type::UIntTy));
2953 MachineInstr *TheCall =
2954 BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(mallocFn, true);
2955 doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args, false);
2959 /// visitFreeInst - Free instructions are code gen'd to call the free libc
2962 void ISel::visitFreeInst(FreeInst &I) {
2963 std::vector<ValueRecord> Args;
2964 Args.push_back(ValueRecord(I.getOperand(0)));
2965 MachineInstr *TheCall =
2966 BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(freeFn, true);
2967 doCall(ValueRecord(0, Type::VoidTy), TheCall, Args, false);
2970 /// createPPC64ISelSimple - This pass converts an LLVM function into a machine
2971 /// code representation is a very simple peep-hole fashion.
2973 FunctionPass *llvm::createPPC64ISelSimple(TargetMachine &TM) {
2974 return new ISel(TM);