1 //===-- PPC64ISelSimple.cpp - A simple instruction selector for PowerPC ---===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "isel"
12 #include "PowerPCInstrBuilder.h"
13 #include "PowerPCInstrInfo.h"
14 #include "PPC64TargetMachine.h"
15 #include "llvm/Constants.h"
16 #include "llvm/DerivedTypes.h"
17 #include "llvm/Function.h"
18 #include "llvm/Instructions.h"
19 #include "llvm/Pass.h"
20 #include "llvm/CodeGen/IntrinsicLowering.h"
21 #include "llvm/CodeGen/MachineConstantPool.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/SSARegMap.h"
25 #include "llvm/Target/MRegisterInfo.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Support/GetElementPtrTypeIterator.h"
28 #include "llvm/Support/InstVisitor.h"
29 #include "Support/Debug.h"
30 #include "Support/Statistic.h"
35 Statistic<> GEPFolds("ppc64-codegen", "Number of GEPs folded");
37 /// TypeClass - Used by the PowerPC backend to group LLVM types by their basic
38 /// PPC Representation.
41 cByte, cShort, cInt, cFP32, cFP64, cLong
45 /// getClass - Turn a primitive type into a "class" number which is based on the
46 /// size of the type, and whether or not it is floating point.
48 static inline TypeClass getClass(const Type *Ty) {
49 switch (Ty->getTypeID()) {
51 case Type::UByteTyID: return cByte; // Byte operands are class #0
53 case Type::UShortTyID: return cShort; // Short operands are class #1
55 case Type::UIntTyID: return cInt; // Ints are class #2
57 case Type::FloatTyID: return cFP32; // Single float is #3
58 case Type::DoubleTyID: return cFP64; // Double Point is #4
60 case Type::PointerTyID:
62 case Type::ULongTyID: return cLong; // Longs and pointers are class #5
64 assert(0 && "Invalid type to getClass!");
65 return cByte; // not reached
69 // getClassB - Just like getClass, but treat boolean values as ints.
70 static inline TypeClass getClassB(const Type *Ty) {
71 if (Ty == Type::BoolTy) return cInt;
76 struct ISel : public FunctionPass, InstVisitor<ISel> {
77 PPC64TargetMachine &TM;
78 MachineFunction *F; // The function we are compiling into
79 MachineBasicBlock *BB; // The current MBB we are compiling
80 int VarArgsFrameIndex; // FrameIndex for start of varargs area
82 std::map<Value*, unsigned> RegMap; // Mapping between Values and SSA Regs
84 // External functions used in the Module
85 Function *fmodfFn, *fmodFn, *__cmpdi2Fn, *__moddi3Fn, *__divdi3Fn,
86 *__umoddi3Fn, *__udivdi3Fn, *__fixsfdiFn, *__fixdfdiFn, *__fixunssfdiFn,
87 *__fixunsdfdiFn, *__floatdisfFn, *__floatdidfFn, *mallocFn, *freeFn;
89 // MBBMap - Mapping between LLVM BB -> Machine BB
90 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
92 // AllocaMap - Mapping from fixed sized alloca instructions to the
93 // FrameIndex for the alloca.
94 std::map<AllocaInst*, unsigned> AllocaMap;
96 ISel(TargetMachine &tm) : TM(reinterpret_cast<PPC64TargetMachine&>(tm)),
99 bool doInitialization(Module &M) {
100 // Add external functions that we may call
101 Type *i = Type::IntTy;
102 Type *d = Type::DoubleTy;
103 Type *f = Type::FloatTy;
104 Type *l = Type::LongTy;
105 Type *ul = Type::ULongTy;
106 Type *voidPtr = PointerType::get(Type::SByteTy);
107 // float fmodf(float, float);
108 fmodfFn = M.getOrInsertFunction("fmodf", f, f, f, 0);
109 // double fmod(double, double);
110 fmodFn = M.getOrInsertFunction("fmod", d, d, d, 0);
111 // int __cmpdi2(long, long);
112 __cmpdi2Fn = M.getOrInsertFunction("__cmpdi2", i, l, l, 0);
113 // long __moddi3(long, long);
114 __moddi3Fn = M.getOrInsertFunction("__moddi3", l, l, l, 0);
115 // long __divdi3(long, long);
116 __divdi3Fn = M.getOrInsertFunction("__divdi3", l, l, l, 0);
117 // unsigned long __umoddi3(unsigned long, unsigned long);
118 __umoddi3Fn = M.getOrInsertFunction("__umoddi3", ul, ul, ul, 0);
119 // unsigned long __udivdi3(unsigned long, unsigned long);
120 __udivdi3Fn = M.getOrInsertFunction("__udivdi3", ul, ul, ul, 0);
121 // long __fixsfdi(float)
122 __fixsfdiFn = M.getOrInsertFunction("__fixsfdi", l, f, 0);
123 // long __fixdfdi(double)
124 __fixdfdiFn = M.getOrInsertFunction("__fixdfdi", l, d, 0);
125 // unsigned long __fixunssfdi(float)
126 __fixunssfdiFn = M.getOrInsertFunction("__fixunssfdi", ul, f, 0);
127 // unsigned long __fixunsdfdi(double)
128 __fixunsdfdiFn = M.getOrInsertFunction("__fixunsdfdi", ul, d, 0);
129 // float __floatdisf(long)
130 __floatdisfFn = M.getOrInsertFunction("__floatdisf", f, l, 0);
131 // double __floatdidf(long)
132 __floatdidfFn = M.getOrInsertFunction("__floatdidf", d, l, 0);
133 // void* malloc(size_t)
134 mallocFn = M.getOrInsertFunction("malloc", voidPtr, Type::UIntTy, 0);
136 freeFn = M.getOrInsertFunction("free", Type::VoidTy, voidPtr, 0);
140 /// runOnFunction - Top level implementation of instruction selection for
141 /// the entire function.
143 bool runOnFunction(Function &Fn) {
144 // First pass over the function, lower any unknown intrinsic functions
145 // with the IntrinsicLowering class.
146 LowerUnknownIntrinsicFunctionCalls(Fn);
148 F = &MachineFunction::construct(&Fn, TM);
150 // Create all of the machine basic blocks for the function...
151 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
152 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
156 // Copy incoming arguments off of the stack...
157 LoadArgumentsToVirtualRegs(Fn);
159 // Instruction select everything except PHI nodes
162 // Select the PHI nodes
169 // We always build a machine code representation for the function
173 virtual const char *getPassName() const {
174 return "PowerPC Simple Instruction Selection";
177 /// visitBasicBlock - This method is called when we are visiting a new basic
178 /// block. This simply creates a new MachineBasicBlock to emit code into
179 /// and adds it to the current MachineFunction. Subsequent visit* for
180 /// instructions will be invoked for all instructions in the basic block.
182 void visitBasicBlock(BasicBlock &LLVM_BB) {
183 BB = MBBMap[&LLVM_BB];
186 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
187 /// function, lowering any calls to unknown intrinsic functions into the
188 /// equivalent LLVM code.
190 void LowerUnknownIntrinsicFunctionCalls(Function &F);
192 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function
193 /// from the stack into virtual registers.
195 void LoadArgumentsToVirtualRegs(Function &F);
197 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
198 /// because we have to generate our sources into the source basic blocks,
199 /// not the current one.
201 void SelectPHINodes();
203 // Visitation methods for various instructions. These methods simply emit
204 // fixed PowerPC code for each instruction.
206 // Control flow operators
207 void visitReturnInst(ReturnInst &RI);
208 void visitBranchInst(BranchInst &BI);
214 ValueRecord(unsigned R, const Type *T) : Val(0), Reg(R), Ty(T) {}
215 ValueRecord(Value *V) : Val(V), Reg(0), Ty(V->getType()) {}
218 // This struct is for recording the necessary operations to emit the GEP
219 struct CollapsedGepOp {
223 CollapsedGepOp(bool mul, Value *i, ConstantSInt *s) :
224 isMul(mul), index(i), size(s) {}
227 void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
228 const std::vector<ValueRecord> &Args, bool isVarArg);
229 void visitCallInst(CallInst &I);
230 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &I);
232 // Arithmetic operators
233 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
234 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
235 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
236 void visitMul(BinaryOperator &B);
238 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
239 void visitRem(BinaryOperator &B) { visitDivRem(B); }
240 void visitDivRem(BinaryOperator &B);
243 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
244 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
245 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
247 // Comparison operators...
248 void visitSetCondInst(SetCondInst &I);
249 unsigned EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
250 MachineBasicBlock *MBB,
251 MachineBasicBlock::iterator MBBI);
252 void visitSelectInst(SelectInst &SI);
255 // Memory Instructions
256 void visitLoadInst(LoadInst &I);
257 void visitStoreInst(StoreInst &I);
258 void visitGetElementPtrInst(GetElementPtrInst &I);
259 void visitAllocaInst(AllocaInst &I);
260 void visitMallocInst(MallocInst &I);
261 void visitFreeInst(FreeInst &I);
264 void visitShiftInst(ShiftInst &I);
265 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
266 void visitCastInst(CastInst &I);
267 void visitVANextInst(VANextInst &I);
268 void visitVAArgInst(VAArgInst &I);
270 void visitInstruction(Instruction &I) {
271 std::cerr << "Cannot instruction select: " << I;
275 /// promote32 - Make a value 32-bits wide, and put it somewhere.
277 void promote32(unsigned targetReg, const ValueRecord &VR);
279 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
280 /// constant expression GEP support.
282 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
283 Value *Src, User::op_iterator IdxBegin,
284 User::op_iterator IdxEnd, unsigned TargetReg,
285 bool CollapseRemainder, ConstantSInt **Remainder,
286 unsigned *PendingAddReg);
288 /// emitCastOperation - Common code shared between visitCastInst and
289 /// constant expression cast support.
291 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator IP,
292 Value *Src, const Type *DestTy, unsigned TargetReg);
294 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
295 /// and constant expression support.
297 void emitSimpleBinaryOperation(MachineBasicBlock *BB,
298 MachineBasicBlock::iterator IP,
299 Value *Op0, Value *Op1,
300 unsigned OperatorClass, unsigned TargetReg);
302 /// emitBinaryFPOperation - This method handles emission of floating point
303 /// Add (0), Sub (1), Mul (2), and Div (3) operations.
304 void emitBinaryFPOperation(MachineBasicBlock *BB,
305 MachineBasicBlock::iterator IP,
306 Value *Op0, Value *Op1,
307 unsigned OperatorClass, unsigned TargetReg);
309 void emitMultiply(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
310 Value *Op0, Value *Op1, unsigned TargetReg);
312 void doMultiply(MachineBasicBlock *MBB,
313 MachineBasicBlock::iterator IP,
314 unsigned DestReg, Value *Op0, Value *Op1);
316 /// doMultiplyConst - This method will multiply the value in Op0Reg by the
317 /// value of the ContantInt *CI
318 void doMultiplyConst(MachineBasicBlock *MBB,
319 MachineBasicBlock::iterator IP,
320 unsigned DestReg, Value *Op0, ConstantInt *CI);
322 void emitDivRemOperation(MachineBasicBlock *BB,
323 MachineBasicBlock::iterator IP,
324 Value *Op0, Value *Op1, bool isDiv,
327 /// emitSetCCOperation - Common code shared between visitSetCondInst and
328 /// constant expression support.
330 void emitSetCCOperation(MachineBasicBlock *BB,
331 MachineBasicBlock::iterator IP,
332 Value *Op0, Value *Op1, unsigned Opcode,
335 /// emitShiftOperation - Common code shared between visitShiftInst and
336 /// constant expression support.
338 void emitShiftOperation(MachineBasicBlock *MBB,
339 MachineBasicBlock::iterator IP,
340 Value *Op, Value *ShiftAmount, bool isLeftShift,
341 const Type *ResultTy, unsigned DestReg);
343 /// emitSelectOperation - Common code shared between visitSelectInst and the
344 /// constant expression support.
346 void emitSelectOperation(MachineBasicBlock *MBB,
347 MachineBasicBlock::iterator IP,
348 Value *Cond, Value *TrueVal, Value *FalseVal,
351 /// copyConstantToRegister - Output the instructions required to put the
352 /// specified constant into the specified register.
354 void copyConstantToRegister(MachineBasicBlock *MBB,
355 MachineBasicBlock::iterator MBBI,
356 Constant *C, unsigned Reg);
358 void emitUCOM(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
359 unsigned LHS, unsigned RHS);
361 /// makeAnotherReg - This method returns the next register number we haven't
364 unsigned makeAnotherReg(const Type *Ty) {
365 assert(dynamic_cast<const PPC64RegisterInfo*>(TM.getRegisterInfo()) &&
366 "Current target doesn't have PPC reg info??");
367 const PPC64RegisterInfo *PPCRI =
368 static_cast<const PPC64RegisterInfo*>(TM.getRegisterInfo());
369 // Add the mapping of regnumber => reg class to MachineFunction
370 const TargetRegisterClass *RC = PPCRI->getRegClassForType(Ty);
371 return F->getSSARegMap()->createVirtualRegister(RC);
374 /// getReg - This method turns an LLVM value into a register number.
376 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
377 unsigned getReg(Value *V) {
378 // Just append to the end of the current bb.
379 MachineBasicBlock::iterator It = BB->end();
380 return getReg(V, BB, It);
382 unsigned getReg(Value *V, MachineBasicBlock *MBB,
383 MachineBasicBlock::iterator IPt);
385 /// canUseAsImmediateForOpcode - This method returns whether a ConstantInt
386 /// is okay to use as an immediate argument to a certain binary operation
387 bool canUseAsImmediateForOpcode(ConstantInt *CI, unsigned Opcode);
389 /// getFixedSizedAllocaFI - Return the frame index for a fixed sized alloca
390 /// that is to be statically allocated with the initial stack frame
392 unsigned getFixedSizedAllocaFI(AllocaInst *AI);
396 /// dyn_castFixedAlloca - If the specified value is a fixed size alloca
397 /// instruction in the entry block, return it. Otherwise, return a null
399 static AllocaInst *dyn_castFixedAlloca(Value *V) {
400 if (AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
401 BasicBlock *BB = AI->getParent();
402 if (isa<ConstantUInt>(AI->getArraySize()) && BB ==&BB->getParent()->front())
408 /// getReg - This method turns an LLVM value into a register number.
410 unsigned ISel::getReg(Value *V, MachineBasicBlock *MBB,
411 MachineBasicBlock::iterator IPt) {
412 if (Constant *C = dyn_cast<Constant>(V)) {
413 unsigned Reg = makeAnotherReg(V->getType());
414 copyConstantToRegister(MBB, IPt, C, Reg);
416 } else if (AllocaInst *AI = dyn_castFixedAlloca(V)) {
417 unsigned Reg = makeAnotherReg(V->getType());
418 unsigned FI = getFixedSizedAllocaFI(AI);
419 addFrameReference(BuildMI(*MBB, IPt, PPC::ADDI, 2, Reg), FI, 0, false);
423 unsigned &Reg = RegMap[V];
425 Reg = makeAnotherReg(V->getType());
432 /// canUseAsImmediateForOpcode - This method returns whether a ConstantInt
433 /// is okay to use as an immediate argument to a certain binary operator.
435 /// Operator is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for Xor.
436 bool ISel::canUseAsImmediateForOpcode(ConstantInt *CI, unsigned Operator) {
440 // ADDI, Compare, and non-indexed Load take SIMM
441 bool cond1 = (Operator == 0)
442 && (Op1Cs = dyn_cast<ConstantSInt>(CI))
443 && (Op1Cs->getValue() <= 32767)
444 && (Op1Cs->getValue() >= -32768);
446 // SUBI takes -SIMM since it is a mnemonic for ADDI
447 bool cond2 = (Operator == 1)
448 && (Op1Cs = dyn_cast<ConstantSInt>(CI))
449 && (Op1Cs->getValue() <= 32768)
450 && (Op1Cs->getValue() >= -32767);
452 // ANDIo, ORI, and XORI take unsigned values
453 bool cond3 = (Operator >= 2)
454 && (Op1Cs = dyn_cast<ConstantSInt>(CI))
455 && (Op1Cs->getValue() >= 0)
456 && (Op1Cs->getValue() <= 32767);
458 // ADDI and SUBI take SIMMs, so we have to make sure the UInt would fit
459 bool cond4 = (Operator < 2)
460 && (Op1Cu = dyn_cast<ConstantUInt>(CI))
461 && (Op1Cu->getValue() <= 32767);
463 // ANDIo, ORI, and XORI take UIMMs, so they can be larger
464 bool cond5 = (Operator >= 2)
465 && (Op1Cu = dyn_cast<ConstantUInt>(CI))
466 && (Op1Cu->getValue() <= 65535);
468 if (cond1 || cond2 || cond3 || cond4 || cond5)
474 /// getFixedSizedAllocaFI - Return the frame index for a fixed sized alloca
475 /// that is to be statically allocated with the initial stack frame
477 unsigned ISel::getFixedSizedAllocaFI(AllocaInst *AI) {
478 // Already computed this?
479 std::map<AllocaInst*, unsigned>::iterator I = AllocaMap.lower_bound(AI);
480 if (I != AllocaMap.end() && I->first == AI) return I->second;
482 const Type *Ty = AI->getAllocatedType();
483 ConstantUInt *CUI = cast<ConstantUInt>(AI->getArraySize());
484 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
485 TySize *= CUI->getValue(); // Get total allocated size...
486 unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
488 // Create a new stack object using the frame manager...
489 int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
490 AllocaMap.insert(I, std::make_pair(AI, FrameIdx));
495 /// copyConstantToRegister - Output the instructions required to put the
496 /// specified constant into the specified register.
498 void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
499 MachineBasicBlock::iterator IP,
500 Constant *C, unsigned R) {
501 if (C->getType()->isIntegral()) {
502 unsigned Class = getClassB(C->getType());
504 if (Class == cLong) {
505 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(C)) {
506 uint64_t uval = CUI->getValue();
507 if (uval < (1LL << 32)) {
508 ConstantUInt *CU = ConstantUInt::get(Type::UIntTy, uval);
509 copyConstantToRegister(MBB, IP, CU, R);
512 } else if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(C)) {
513 int64_t val = CUI->getValue();
514 if (val < (1LL << 31)) {
515 ConstantUInt *CU = ConstantUInt::get(Type::UIntTy, val);
516 copyConstantToRegister(MBB, IP, CU, R);
520 std::cerr << "Unhandled long constant type!\n";
523 // Spill long to the constant pool and load it
524 MachineConstantPool *CP = F->getConstantPool();
525 unsigned CPI = CP->getConstantPoolIndex(C);
526 BuildMI(*MBB, IP, PPC::LD, 1, R)
527 .addReg(PPC::R2).addConstantPoolIndex(CPI);
531 assert(Class <= cInt && "Type not handled yet!");
534 if (C->getType() == Type::BoolTy) {
535 BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(C == ConstantBool::True);
540 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(C)) {
541 unsigned uval = CUI->getValue();
543 BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(uval);
545 unsigned Temp = makeAnotherReg(Type::IntTy);
546 BuildMI(*MBB, IP, PPC::LIS, 1, Temp).addSImm(uval >> 16);
547 BuildMI(*MBB, IP, PPC::ORI, 2, R).addReg(Temp).addImm(uval);
550 } else if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(C)) {
551 int sval = CSI->getValue();
552 if (sval < 32768 && sval >= -32768) {
553 BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(sval);
555 unsigned Temp = makeAnotherReg(Type::IntTy);
556 BuildMI(*MBB, IP, PPC::LIS, 1, Temp).addSImm(sval >> 16);
557 BuildMI(*MBB, IP, PPC::ORI, 2, R).addReg(Temp).addImm(sval);
561 std::cerr << "Unhandled integer constant!\n";
563 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
564 // We need to spill the constant to memory...
565 MachineConstantPool *CP = F->getConstantPool();
566 unsigned CPI = CP->getConstantPoolIndex(CFP);
567 const Type *Ty = CFP->getType();
568 unsigned LoadOpcode = (Ty == Type::FloatTy) ? PPC::LFS : PPC::LFD;
569 BuildMI(*MBB,IP,LoadOpcode,2,R).addConstantPoolIndex(CPI).addReg(PPC::R2);
570 } else if (isa<ConstantPointerNull>(C)) {
571 // Copy zero (null pointer) to the register.
572 BuildMI(*MBB, IP, PPC::LI, 1, R).addSImm(0);
573 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
574 static unsigned OpcodeTable[] = {
575 PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LFS, PPC::LFD, PPC::LD
577 unsigned Opcode = OpcodeTable[getClassB(GV->getType())];
578 BuildMI(*MBB, IP, Opcode, 2, R).addGlobalAddress(GV).addReg(PPC::R2);
580 std::cerr << "Offending constant: " << *C << "\n";
581 assert(0 && "Type not handled yet!");
585 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function from
586 /// the stack into virtual registers.
587 void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
588 unsigned ArgOffset = 24;
589 unsigned GPR_remaining = 8;
590 unsigned FPR_remaining = 13;
591 unsigned GPR_idx = 0, FPR_idx = 0;
592 static const unsigned GPR[] = {
593 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
594 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
596 static const unsigned FPR[] = {
597 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
598 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
601 MachineFrameInfo *MFI = F->getFrameInfo();
603 for (Function::aiterator I = Fn.abegin(), E = Fn.aend(); I != E; ++I) {
604 bool ArgLive = !I->use_empty();
605 unsigned Reg = ArgLive ? getReg(*I) : 0;
606 int FI; // Frame object index
608 switch (getClassB(I->getType())) {
611 FI = MFI->CreateFixedObject(4, ArgOffset);
612 if (GPR_remaining > 0) {
613 BuildMI(BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
614 BuildMI(BB, PPC::OR, 2, Reg).addReg(GPR[GPR_idx])
615 .addReg(GPR[GPR_idx]);
617 addFrameReference(BuildMI(BB, PPC::LBZ, 2, Reg), FI);
623 FI = MFI->CreateFixedObject(4, ArgOffset);
624 if (GPR_remaining > 0) {
625 BuildMI(BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
626 BuildMI(BB, PPC::OR, 2, Reg).addReg(GPR[GPR_idx])
627 .addReg(GPR[GPR_idx]);
629 addFrameReference(BuildMI(BB, PPC::LHZ, 2, Reg), FI);
635 FI = MFI->CreateFixedObject(4, ArgOffset);
636 if (GPR_remaining > 0) {
637 BuildMI(BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
638 BuildMI(BB, PPC::OR, 2, Reg).addReg(GPR[GPR_idx])
639 .addReg(GPR[GPR_idx]);
641 addFrameReference(BuildMI(BB, PPC::LWZ, 2, Reg), FI);
647 FI = MFI->CreateFixedObject(8, ArgOffset);
648 if (GPR_remaining > 1) {
649 BuildMI(BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
650 BuildMI(BB, PPC::OR, 2, Reg).addReg(GPR[GPR_idx])
651 .addReg(GPR[GPR_idx]);
653 addFrameReference(BuildMI(BB, PPC::LD, 2, Reg), FI);
656 // longs require 4 additional bytes
661 FI = MFI->CreateFixedObject(4, ArgOffset);
663 if (FPR_remaining > 0) {
664 BuildMI(BB, PPC::IMPLICIT_DEF, 0, FPR[FPR_idx]);
665 BuildMI(BB, PPC::FMR, 1, Reg).addReg(FPR[FPR_idx]);
669 addFrameReference(BuildMI(BB, PPC::LFS, 2, Reg), FI);
675 FI = MFI->CreateFixedObject(8, ArgOffset);
677 if (FPR_remaining > 0) {
678 BuildMI(BB, PPC::IMPLICIT_DEF, 0, FPR[FPR_idx]);
679 BuildMI(BB, PPC::FMR, 1, Reg).addReg(FPR[FPR_idx]);
683 addFrameReference(BuildMI(BB, PPC::LFD, 2, Reg), FI);
687 // doubles require 4 additional bytes and use 2 GPRs of param space
689 if (GPR_remaining > 0) {
695 assert(0 && "Unhandled argument type!");
697 ArgOffset += 4; // Each argument takes at least 4 bytes on the stack...
698 if (GPR_remaining > 0) {
699 GPR_remaining--; // uses up 2 GPRs
704 // If the function takes variable number of arguments, add a frame offset for
705 // the start of the first vararg value... this is used to expand
707 if (Fn.getFunctionType()->isVarArg())
708 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
712 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
713 /// because we have to generate our sources into the source basic blocks, not
716 void ISel::SelectPHINodes() {
717 const TargetInstrInfo &TII = *TM.getInstrInfo();
718 const Function &LF = *F->getFunction(); // The LLVM function...
719 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
720 const BasicBlock *BB = I;
721 MachineBasicBlock &MBB = *MBBMap[I];
723 // Loop over all of the PHI nodes in the LLVM basic block...
724 MachineBasicBlock::iterator PHIInsertPoint = MBB.begin();
725 for (BasicBlock::const_iterator I = BB->begin();
726 PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
728 // Create a new machine instr PHI node, and insert it.
729 unsigned PHIReg = getReg(*PN);
730 MachineInstr *PhiMI = BuildMI(MBB, PHIInsertPoint,
731 PPC::PHI, PN->getNumOperands(), PHIReg);
733 // PHIValues - Map of blocks to incoming virtual registers. We use this
734 // so that we only initialize one incoming value for a particular block,
735 // even if the block has multiple entries in the PHI node.
737 std::map<MachineBasicBlock*, unsigned> PHIValues;
739 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
740 MachineBasicBlock *PredMBB = 0;
741 for (MachineBasicBlock::pred_iterator PI = MBB.pred_begin (),
742 PE = MBB.pred_end (); PI != PE; ++PI)
743 if (PN->getIncomingBlock(i) == (*PI)->getBasicBlock()) {
747 assert (PredMBB && "Couldn't find incoming machine-cfg edge for phi");
750 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
751 PHIValues.lower_bound(PredMBB);
753 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
754 // We already inserted an initialization of the register for this
755 // predecessor. Recycle it.
756 ValReg = EntryIt->second;
758 // Get the incoming value into a virtual register.
760 Value *Val = PN->getIncomingValue(i);
762 // If this is a constant or GlobalValue, we may have to insert code
763 // into the basic block to compute it into a virtual register.
764 if ((isa<Constant>(Val) && !isa<ConstantExpr>(Val)) ||
765 isa<GlobalValue>(Val)) {
766 // Simple constants get emitted at the end of the basic block,
767 // before any terminator instructions. We "know" that the code to
768 // move a constant into a register will never clobber any flags.
769 ValReg = getReg(Val, PredMBB, PredMBB->getFirstTerminator());
771 // Because we don't want to clobber any values which might be in
772 // physical registers with the computation of this constant (which
773 // might be arbitrarily complex if it is a constant expression),
774 // just insert the computation at the top of the basic block.
775 MachineBasicBlock::iterator PI = PredMBB->begin();
777 // Skip over any PHI nodes though!
778 while (PI != PredMBB->end() && PI->getOpcode() == PPC::PHI)
781 ValReg = getReg(Val, PredMBB, PI);
784 // Remember that we inserted a value for this PHI for this predecessor
785 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
788 PhiMI->addRegOperand(ValReg);
789 PhiMI->addMachineBasicBlockOperand(PredMBB);
792 // Now that we emitted all of the incoming values for the PHI node, make
793 // sure to reposition the InsertPoint after the PHI that we just added.
794 // This is needed because we might have inserted a constant into this
795 // block, right after the PHI's which is before the old insert point!
796 PHIInsertPoint = PhiMI;
803 // canFoldSetCCIntoBranchOrSelect - Return the setcc instruction if we can fold
804 // it into the conditional branch or select instruction which is the only user
805 // of the cc instruction. This is the case if the conditional branch is the
806 // only user of the setcc, and if the setcc is in the same basic block as the
807 // conditional branch.
809 static SetCondInst *canFoldSetCCIntoBranchOrSelect(Value *V) {
810 if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
811 if (SCI->hasOneUse()) {
812 Instruction *User = cast<Instruction>(SCI->use_back());
813 if ((isa<BranchInst>(User) || isa<SelectInst>(User)) &&
814 SCI->getParent() == User->getParent())
821 // canFoldGEPIntoLoadOrStore - Return the GEP instruction if we can fold it into
822 // the load or store instruction that is the only user of the GEP.
824 static GetElementPtrInst *canFoldGEPIntoLoadOrStore(Value *V) {
825 if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(V))
826 if (GEPI->hasOneUse()) {
827 Instruction *User = cast<Instruction>(GEPI->use_back());
828 if (isa<StoreInst>(User) &&
829 GEPI->getParent() == User->getParent() &&
830 User->getOperand(0) != GEPI &&
831 User->getOperand(1) == GEPI) {
835 if (isa<LoadInst>(User) &&
836 GEPI->getParent() == User->getParent() &&
837 User->getOperand(0) == GEPI) {
846 // Return a fixed numbering for setcc instructions which does not depend on the
847 // order of the opcodes.
849 static unsigned getSetCCNumber(unsigned Opcode) {
851 default: assert(0 && "Unknown setcc instruction!");
852 case Instruction::SetEQ: return 0;
853 case Instruction::SetNE: return 1;
854 case Instruction::SetLT: return 2;
855 case Instruction::SetGE: return 3;
856 case Instruction::SetGT: return 4;
857 case Instruction::SetLE: return 5;
861 static unsigned getPPCOpcodeForSetCCNumber(unsigned Opcode) {
863 default: assert(0 && "Unknown setcc instruction!");
864 case Instruction::SetEQ: return PPC::BEQ;
865 case Instruction::SetNE: return PPC::BNE;
866 case Instruction::SetLT: return PPC::BLT;
867 case Instruction::SetGE: return PPC::BGE;
868 case Instruction::SetGT: return PPC::BGT;
869 case Instruction::SetLE: return PPC::BLE;
873 /// emitUCOM - emits an unordered FP compare.
874 void ISel::emitUCOM(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
875 unsigned LHS, unsigned RHS) {
876 BuildMI(*MBB, IP, PPC::FCMPU, 2, PPC::CR0).addReg(LHS).addReg(RHS);
879 /// EmitComparison - emits a comparison of the two operands, returning the
880 /// extended setcc code to use. The result is in CR0.
882 unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
883 MachineBasicBlock *MBB,
884 MachineBasicBlock::iterator IP) {
885 // The arguments are already supposed to be of the same type.
886 const Type *CompTy = Op0->getType();
887 unsigned Class = getClassB(CompTy);
888 unsigned Op0r = getReg(Op0, MBB, IP);
890 // Before we do a comparison, we have to make sure that we're truncating our
891 // registers appropriately.
892 if (Class == cByte) {
893 unsigned TmpReg = makeAnotherReg(CompTy);
894 if (CompTy->isSigned())
895 BuildMI(*MBB, IP, PPC::EXTSB, 1, TmpReg).addReg(Op0r);
897 BuildMI(*MBB, IP, PPC::RLWINM, 4, TmpReg).addReg(Op0r).addImm(0)
898 .addImm(24).addImm(31);
900 } else if (Class == cShort) {
901 unsigned TmpReg = makeAnotherReg(CompTy);
902 if (CompTy->isSigned())
903 BuildMI(*MBB, IP, PPC::EXTSH, 1, TmpReg).addReg(Op0r);
905 BuildMI(*MBB, IP, PPC::RLWINM, 4, TmpReg).addReg(Op0r).addImm(0)
906 .addImm(16).addImm(31);
910 // Use crand for lt, gt and crandc for le, ge
911 unsigned CROpcode = (OpNum == 2 || OpNum == 4) ? PPC::CRAND : PPC::CRANDC;
912 unsigned Opcode = CompTy->isSigned() ? PPC::CMPW : PPC::CMPLW;
913 unsigned OpcodeImm = CompTy->isSigned() ? PPC::CMPWI : PPC::CMPLWI;
914 if (Class == cLong) {
915 Opcode = CompTy->isSigned() ? PPC::CMPD : PPC::CMPLD;
916 OpcodeImm = CompTy->isSigned() ? PPC::CMPDI : PPC::CMPLDI;
919 // Special case handling of: cmp R, i
920 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
921 unsigned Op1v = CI->getRawValue() & 0xFFFF;
923 // Treat compare like ADDI for the purposes of immediate suitability
924 if (canUseAsImmediateForOpcode(CI, 0)) {
925 BuildMI(*MBB, IP, OpcodeImm, 2, PPC::CR0).addReg(Op0r).addSImm(Op1v);
927 unsigned Op1r = getReg(Op1, MBB, IP);
928 BuildMI(*MBB, IP, Opcode, 2, PPC::CR0).addReg(Op0r).addReg(Op1r);
933 unsigned Op1r = getReg(Op1, MBB, IP);
936 default: assert(0 && "Unknown type class!");
941 BuildMI(*MBB, IP, Opcode, 2, PPC::CR0).addReg(Op0r).addReg(Op1r);
946 emitUCOM(MBB, IP, Op0r, Op1r);
953 /// visitSetCondInst - emit code to calculate the condition via
954 /// EmitComparison(), and possibly store a 0 or 1 to a register as a result
956 void ISel::visitSetCondInst(SetCondInst &I) {
957 if (canFoldSetCCIntoBranchOrSelect(&I))
960 unsigned DestReg = getReg(I);
961 unsigned OpNum = I.getOpcode();
962 const Type *Ty = I.getOperand (0)->getType();
964 EmitComparison(OpNum, I.getOperand(0), I.getOperand(1), BB, BB->end());
966 unsigned Opcode = getPPCOpcodeForSetCCNumber(OpNum);
967 MachineBasicBlock *thisMBB = BB;
968 const BasicBlock *LLVM_BB = BB->getBasicBlock();
969 ilist<MachineBasicBlock>::iterator It = BB;
978 // FIXME: we wouldn't need copy0MBB (we could fold it into thisMBB)
979 // if we could insert other, non-terminator instructions after the
980 // bCC. But MBB->getFirstTerminator() can't understand this.
981 MachineBasicBlock *copy1MBB = new MachineBasicBlock(LLVM_BB);
982 F->getBasicBlockList().insert(It, copy1MBB);
983 BuildMI(BB, Opcode, 2).addReg(PPC::CR0).addMBB(copy1MBB);
984 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
985 F->getBasicBlockList().insert(It, copy0MBB);
986 BuildMI(BB, PPC::B, 1).addMBB(copy0MBB);
987 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
988 F->getBasicBlockList().insert(It, sinkMBB);
989 // Update machine-CFG edges
990 BB->addSuccessor(copy1MBB);
991 BB->addSuccessor(copy0MBB);
997 unsigned TrueValue = makeAnotherReg(I.getType());
998 BuildMI(BB, PPC::LI, 1, TrueValue).addSImm(1);
999 BuildMI(BB, PPC::B, 1).addMBB(sinkMBB);
1000 // Update machine-CFG edges
1001 BB->addSuccessor(sinkMBB);
1004 // %FalseValue = li 0
1007 unsigned FalseValue = makeAnotherReg(I.getType());
1008 BuildMI(BB, PPC::LI, 1, FalseValue).addSImm(0);
1009 // Update machine-CFG edges
1010 BB->addSuccessor(sinkMBB);
1013 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, copy1MBB ]
1016 BuildMI(BB, PPC::PHI, 4, DestReg).addReg(FalseValue)
1017 .addMBB(copy0MBB).addReg(TrueValue).addMBB(copy1MBB);
1020 void ISel::visitSelectInst(SelectInst &SI) {
1021 unsigned DestReg = getReg(SI);
1022 MachineBasicBlock::iterator MII = BB->end();
1023 emitSelectOperation(BB, MII, SI.getCondition(), SI.getTrueValue(),
1024 SI.getFalseValue(), DestReg);
1027 /// emitSelect - Common code shared between visitSelectInst and the constant
1028 /// expression support.
1029 /// FIXME: this is most likely broken in one or more ways. Namely, PowerPC has
1030 /// no select instruction. FSEL only works for comparisons against zero.
1031 void ISel::emitSelectOperation(MachineBasicBlock *MBB,
1032 MachineBasicBlock::iterator IP,
1033 Value *Cond, Value *TrueVal, Value *FalseVal,
1035 unsigned SelectClass = getClassB(TrueVal->getType());
1038 // See if we can fold the setcc into the select instruction, or if we have
1039 // to get the register of the Cond value
1040 if (SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(Cond)) {
1041 // We successfully folded the setcc into the select instruction.
1042 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
1043 OpNum = EmitComparison(OpNum, SCI->getOperand(0),SCI->getOperand(1),MBB,IP);
1044 Opcode = getPPCOpcodeForSetCCNumber(SCI->getOpcode());
1046 unsigned CondReg = getReg(Cond, MBB, IP);
1047 BuildMI(*MBB, IP, PPC::CMPI, 2, PPC::CR0).addReg(CondReg).addSImm(0);
1048 Opcode = getPPCOpcodeForSetCCNumber(Instruction::SetNE);
1053 // cmpTY cr0, r1, r2
1057 MachineBasicBlock *thisMBB = BB;
1058 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1059 ilist<MachineBasicBlock>::iterator It = BB;
1062 // FIXME: we wouldn't need copy0MBB (we could fold it into thisMBB)
1063 // if we could insert other, non-terminator instructions after the
1064 // bCC. But MBB->getFirstTerminator() can't understand this.
1065 MachineBasicBlock *copy1MBB = new MachineBasicBlock(LLVM_BB);
1066 F->getBasicBlockList().insert(It, copy1MBB);
1067 BuildMI(BB, Opcode, 2).addReg(PPC::CR0).addMBB(copy1MBB);
1068 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
1069 F->getBasicBlockList().insert(It, copy0MBB);
1070 BuildMI(BB, PPC::B, 1).addMBB(copy0MBB);
1071 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
1072 F->getBasicBlockList().insert(It, sinkMBB);
1073 // Update machine-CFG edges
1074 BB->addSuccessor(copy1MBB);
1075 BB->addSuccessor(copy0MBB);
1081 unsigned TrueValue = getReg(TrueVal, BB, BB->begin());
1082 BuildMI(BB, PPC::B, 1).addMBB(sinkMBB);
1083 // Update machine-CFG edges
1084 BB->addSuccessor(sinkMBB);
1087 // %FalseValue = ...
1090 unsigned FalseValue = getReg(FalseVal, BB, BB->begin());
1091 // Update machine-CFG edges
1092 BB->addSuccessor(sinkMBB);
1095 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, copy1MBB ]
1098 BuildMI(BB, PPC::PHI, 4, DestReg).addReg(FalseValue)
1099 .addMBB(copy0MBB).addReg(TrueValue).addMBB(copy1MBB);
1105 /// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
1106 /// operand, in the specified target register.
1108 void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
1109 bool isUnsigned = VR.Ty->isUnsigned() || VR.Ty == Type::BoolTy;
1111 Value *Val = VR.Val;
1112 const Type *Ty = VR.Ty;
1114 if (Constant *C = dyn_cast<Constant>(Val)) {
1115 Val = ConstantExpr::getCast(C, Type::IntTy);
1116 if (isa<ConstantExpr>(Val)) // Could not fold
1119 Ty = Type::IntTy; // Folded!
1122 // If this is a simple constant, just emit a load directly to avoid the copy
1123 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
1124 int TheVal = CI->getRawValue() & 0xFFFFFFFF;
1126 if (TheVal < 32768 && TheVal >= -32768) {
1127 BuildMI(BB, PPC::LI, 1, targetReg).addSImm(TheVal);
1129 unsigned TmpReg = makeAnotherReg(Type::IntTy);
1130 BuildMI(BB, PPC::LIS, 1, TmpReg).addSImm(TheVal >> 16);
1131 BuildMI(BB, PPC::ORI, 2, targetReg).addReg(TmpReg)
1132 .addImm(TheVal & 0xFFFF);
1138 // Make sure we have the register number for this value...
1139 unsigned Reg = Val ? getReg(Val) : VR.Reg;
1140 switch (getClassB(Ty)) {
1142 // Extend value into target register (8->32)
1144 BuildMI(BB, PPC::RLWINM, 4, targetReg).addReg(Reg).addZImm(0)
1145 .addZImm(24).addZImm(31);
1147 BuildMI(BB, PPC::EXTSB, 1, targetReg).addReg(Reg);
1150 // Extend value into target register (16->32)
1152 BuildMI(BB, PPC::RLWINM, 4, targetReg).addReg(Reg).addZImm(0)
1153 .addZImm(16).addZImm(31);
1155 BuildMI(BB, PPC::EXTSH, 1, targetReg).addReg(Reg);
1159 // Move value into target register (32->32)
1160 BuildMI(BB, PPC::OR, 2, targetReg).addReg(Reg).addReg(Reg);
1163 assert(0 && "Unpromotable operand class in promote32");
1167 /// visitReturnInst - implemented with BLR
1169 void ISel::visitReturnInst(ReturnInst &I) {
1170 // Only do the processing if this is a non-void return
1171 if (I.getNumOperands() > 0) {
1172 Value *RetVal = I.getOperand(0);
1173 switch (getClassB(RetVal->getType())) {
1174 case cByte: // integral return values: extend or move into r3 and return
1178 promote32(PPC::R3, ValueRecord(RetVal));
1181 case cFP64: { // Floats & Doubles: Return in f1
1182 unsigned RetReg = getReg(RetVal);
1183 BuildMI(BB, PPC::FMR, 1, PPC::F1).addReg(RetReg);
1187 visitInstruction(I);
1190 BuildMI(BB, PPC::BLR, 1).addImm(1);
1193 // getBlockAfter - Return the basic block which occurs lexically after the
1195 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
1196 Function::iterator I = BB; ++I; // Get iterator to next block
1197 return I != BB->getParent()->end() ? &*I : 0;
1200 /// visitBranchInst - Handle conditional and unconditional branches here. Note
1201 /// that since code layout is frozen at this point, that if we are trying to
1202 /// jump to a block that is the immediate successor of the current block, we can
1203 /// just make a fall-through (but we don't currently).
1205 void ISel::visitBranchInst(BranchInst &BI) {
1206 // Update machine-CFG edges
1207 BB->addSuccessor(MBBMap[BI.getSuccessor(0)]);
1208 if (BI.isConditional())
1209 BB->addSuccessor(MBBMap[BI.getSuccessor(1)]);
1211 BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
1213 if (!BI.isConditional()) { // Unconditional branch?
1214 if (BI.getSuccessor(0) != NextBB)
1215 BuildMI(BB, PPC::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
1219 // See if we can fold the setcc into the branch itself...
1220 SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(BI.getCondition());
1222 // Nope, cannot fold setcc into this branch. Emit a branch on a condition
1223 // computed some other way...
1224 unsigned condReg = getReg(BI.getCondition());
1225 BuildMI(BB, PPC::CMPLI, 3, PPC::CR0).addImm(0).addReg(condReg)
1227 if (BI.getSuccessor(1) == NextBB) {
1228 if (BI.getSuccessor(0) != NextBB)
1229 BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(PPC::BNE)
1230 .addMBB(MBBMap[BI.getSuccessor(0)])
1231 .addMBB(MBBMap[BI.getSuccessor(1)]);
1233 BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(PPC::BEQ)
1234 .addMBB(MBBMap[BI.getSuccessor(1)])
1235 .addMBB(MBBMap[BI.getSuccessor(0)]);
1236 if (BI.getSuccessor(0) != NextBB)
1237 BuildMI(BB, PPC::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
1242 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
1243 unsigned Opcode = getPPCOpcodeForSetCCNumber(SCI->getOpcode());
1244 MachineBasicBlock::iterator MII = BB->end();
1245 OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
1247 if (BI.getSuccessor(0) != NextBB) {
1248 BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(Opcode)
1249 .addMBB(MBBMap[BI.getSuccessor(0)])
1250 .addMBB(MBBMap[BI.getSuccessor(1)]);
1251 if (BI.getSuccessor(1) != NextBB)
1252 BuildMI(BB, PPC::B, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
1254 // Change to the inverse condition...
1255 if (BI.getSuccessor(1) != NextBB) {
1256 Opcode = PPC64InstrInfo::invertPPCBranchOpcode(Opcode);
1257 BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(Opcode)
1258 .addMBB(MBBMap[BI.getSuccessor(1)])
1259 .addMBB(MBBMap[BI.getSuccessor(0)]);
1264 /// doCall - This emits an abstract call instruction, setting up the arguments
1265 /// and the return value as appropriate. For the actual function call itself,
1266 /// it inserts the specified CallMI instruction into the stream.
1268 void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
1269 const std::vector<ValueRecord> &Args, bool isVarArg) {
1270 // Count how many bytes are to be pushed on the stack, including the linkage
1271 // area, and parameter passing area.
1272 unsigned NumBytes = 24;
1273 unsigned ArgOffset = 24;
1275 if (!Args.empty()) {
1276 for (unsigned i = 0, e = Args.size(); i != e; ++i)
1277 switch (getClassB(Args[i].Ty)) {
1278 case cByte: case cShort: case cInt:
1279 NumBytes += 4; break;
1281 NumBytes += 8; break;
1283 NumBytes += 4; break;
1285 NumBytes += 8; break;
1287 default: assert(0 && "Unknown class!");
1290 // Just to be safe, we'll always reserve the full 32 bytes worth of
1291 // argument passing space in case any called code gets funky on us.
1292 if (NumBytes < 24 + 32) NumBytes = 24 + 32;
1294 // Adjust the stack pointer for the new arguments...
1295 // These functions are automatically eliminated by the prolog/epilog pass
1296 BuildMI(BB, PPC::ADJCALLSTACKDOWN, 1).addImm(NumBytes);
1298 // Arguments go on the stack in reverse order, as specified by the ABI.
1299 // Offset to the paramater area on the stack is 24.
1300 int GPR_remaining = 8, FPR_remaining = 13;
1301 unsigned GPR_idx = 0, FPR_idx = 0;
1302 static const unsigned GPR[] = {
1303 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1304 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1306 static const unsigned FPR[] = {
1307 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6,
1308 PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12,
1312 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
1314 switch (getClassB(Args[i].Ty)) {
1317 // Promote arg to 32 bits wide into a temporary register...
1318 ArgReg = makeAnotherReg(Type::UIntTy);
1319 promote32(ArgReg, Args[i]);
1322 if (GPR_remaining > 0) {
1323 BuildMI(BB, PPC::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
1325 CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
1327 if (GPR_remaining <= 0 || isVarArg) {
1328 BuildMI(BB, PPC::STW, 3).addReg(ArgReg).addSImm(ArgOffset)
1333 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1336 if (GPR_remaining > 0) {
1337 BuildMI(BB, PPC::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
1339 CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
1341 if (GPR_remaining <= 0 || isVarArg) {
1342 BuildMI(BB, PPC::STW, 3).addReg(ArgReg).addSImm(ArgOffset)
1347 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1350 if (GPR_remaining > 0) {
1351 BuildMI(BB, PPC::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
1353 CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
1355 if (GPR_remaining <= 0 || isVarArg) {
1356 BuildMI(BB, PPC::STD, 3).addReg(ArgReg).addSImm(ArgOffset)
1359 ArgOffset += 4; // 8 byte entry, not 4.
1362 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1364 if (FPR_remaining > 0) {
1365 BuildMI(BB, PPC::FMR, 1, FPR[FPR_idx]).addReg(ArgReg);
1366 CallMI->addRegOperand(FPR[FPR_idx], MachineOperand::Use);
1370 // If this is a vararg function, and there are GPRs left, also
1371 // pass the float in an int. Otherwise, put it on the stack.
1373 BuildMI(BB, PPC::STFS, 3).addReg(ArgReg).addSImm(ArgOffset)
1375 if (GPR_remaining > 0) {
1376 BuildMI(BB, PPC::LWZ, 2, GPR[GPR_idx])
1377 .addSImm(ArgOffset).addReg(ArgReg);
1378 CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
1382 BuildMI(BB, PPC::STFS, 3).addReg(ArgReg).addSImm(ArgOffset)
1387 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1389 if (FPR_remaining > 0) {
1390 BuildMI(BB, PPC::FMR, 1, FPR[FPR_idx]).addReg(ArgReg);
1391 CallMI->addRegOperand(FPR[FPR_idx], MachineOperand::Use);
1394 // For vararg functions, must pass doubles via int regs as well
1396 BuildMI(BB, PPC::STFD, 3).addReg(ArgReg).addSImm(ArgOffset)
1399 if (GPR_remaining > 0) {
1400 BuildMI(BB, PPC::LD, 2, GPR[GPR_idx]).addSImm(ArgOffset)
1402 CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
1406 BuildMI(BB, PPC::STFD, 3).addReg(ArgReg).addSImm(ArgOffset)
1409 // Doubles use 8 bytes
1413 default: assert(0 && "Unknown class!");
1420 BuildMI(BB, PPC::ADJCALLSTACKDOWN, 1).addImm(0);
1423 BuildMI(BB, PPC::IMPLICIT_DEF, 0, PPC::LR);
1424 BB->push_back(CallMI);
1425 BuildMI(BB, PPC::NOP, 0);
1427 // These functions are automatically eliminated by the prolog/epilog pass
1428 BuildMI(BB, PPC::ADJCALLSTACKUP, 1).addImm(NumBytes);
1430 // If there is a return value, scavenge the result from the location the call
1433 if (Ret.Ty != Type::VoidTy) {
1434 unsigned DestClass = getClassB(Ret.Ty);
1435 switch (DestClass) {
1440 // Integral results are in r3
1441 BuildMI(BB, PPC::OR, 2, Ret.Reg).addReg(PPC::R3).addReg(PPC::R3);
1443 case cFP32: // Floating-point return values live in f1
1445 BuildMI(BB, PPC::FMR, 1, Ret.Reg).addReg(PPC::F1);
1447 default: assert(0 && "Unknown class!");
1453 /// visitCallInst - Push args on stack and do a procedure call instruction.
1454 void ISel::visitCallInst(CallInst &CI) {
1455 MachineInstr *TheCall;
1456 Function *F = CI.getCalledFunction();
1458 // Is it an intrinsic function call?
1459 if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
1460 visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here
1463 // Emit a CALL instruction with PC-relative displacement.
1464 TheCall = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(F, true);
1465 } else { // Emit an indirect call through the CTR
1466 unsigned Reg = getReg(CI.getCalledValue());
1467 BuildMI(BB, PPC::MTCTR, 1).addReg(Reg);
1468 TheCall = BuildMI(PPC::CALLindirect, 2).addZImm(20).addZImm(0);
1471 std::vector<ValueRecord> Args;
1472 for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i)
1473 Args.push_back(ValueRecord(CI.getOperand(i)));
1475 unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
1476 bool isVarArg = F ? F->getFunctionType()->isVarArg() : true;
1477 doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args, isVarArg);
1481 /// dyncastIsNan - Return the operand of an isnan operation if this is an isnan.
1483 static Value *dyncastIsNan(Value *V) {
1484 if (CallInst *CI = dyn_cast<CallInst>(V))
1485 if (Function *F = CI->getCalledFunction())
1486 if (F->getIntrinsicID() == Intrinsic::isunordered)
1487 return CI->getOperand(1);
1491 /// isOnlyUsedByUnorderedComparisons - Return true if this value is only used by
1492 /// or's whos operands are all calls to the isnan predicate.
1493 static bool isOnlyUsedByUnorderedComparisons(Value *V) {
1494 assert(dyncastIsNan(V) && "The value isn't an isnan call!");
1496 // Check all uses, which will be or's of isnans if this predicate is true.
1497 for (Value::use_iterator UI = V->use_begin(), E = V->use_end(); UI != E;++UI){
1498 Instruction *I = cast<Instruction>(*UI);
1499 if (I->getOpcode() != Instruction::Or) return false;
1500 if (I->getOperand(0) != V && !dyncastIsNan(I->getOperand(0))) return false;
1501 if (I->getOperand(1) != V && !dyncastIsNan(I->getOperand(1))) return false;
1507 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
1508 /// function, lowering any calls to unknown intrinsic functions into the
1509 /// equivalent LLVM code.
1511 void ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
1512 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
1513 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
1514 if (CallInst *CI = dyn_cast<CallInst>(I++))
1515 if (Function *F = CI->getCalledFunction())
1516 switch (F->getIntrinsicID()) {
1517 case Intrinsic::not_intrinsic:
1518 case Intrinsic::vastart:
1519 case Intrinsic::vacopy:
1520 case Intrinsic::vaend:
1521 case Intrinsic::returnaddress:
1522 case Intrinsic::frameaddress:
1523 // FIXME: should lower these ourselves
1524 // case Intrinsic::isunordered:
1525 // case Intrinsic::memcpy: -> doCall(). system memcpy almost
1526 // guaranteed to be faster than anything we generate ourselves
1527 // We directly implement these intrinsics
1529 case Intrinsic::readio: {
1530 // On PPC, memory operations are in-order. Lower this intrinsic
1531 // into a volatile load.
1532 Instruction *Before = CI->getPrev();
1533 LoadInst * LI = new LoadInst(CI->getOperand(1), "", true, CI);
1534 CI->replaceAllUsesWith(LI);
1535 BB->getInstList().erase(CI);
1538 case Intrinsic::writeio: {
1539 // On PPC, memory operations are in-order. Lower this intrinsic
1540 // into a volatile store.
1541 Instruction *Before = CI->getPrev();
1542 StoreInst *SI = new StoreInst(CI->getOperand(1),
1543 CI->getOperand(2), true, CI);
1544 CI->replaceAllUsesWith(SI);
1545 BB->getInstList().erase(CI);
1549 // All other intrinsic calls we must lower.
1550 Instruction *Before = CI->getPrev();
1551 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
1552 if (Before) { // Move iterator to instruction after call
1560 void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
1561 unsigned TmpReg1, TmpReg2, TmpReg3;
1563 case Intrinsic::vastart:
1564 // Get the address of the first vararg value...
1565 TmpReg1 = getReg(CI);
1566 addFrameReference(BuildMI(BB, PPC::ADDI, 2, TmpReg1), VarArgsFrameIndex,
1570 case Intrinsic::vacopy:
1571 TmpReg1 = getReg(CI);
1572 TmpReg2 = getReg(CI.getOperand(1));
1573 BuildMI(BB, PPC::OR, 2, TmpReg1).addReg(TmpReg2).addReg(TmpReg2);
1575 case Intrinsic::vaend: return;
1577 case Intrinsic::returnaddress:
1578 TmpReg1 = getReg(CI);
1579 if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
1580 MachineFrameInfo *MFI = F->getFrameInfo();
1581 unsigned NumBytes = MFI->getStackSize();
1583 BuildMI(BB, PPC::LWZ, 2, TmpReg1).addSImm(NumBytes+8)
1586 // Values other than zero are not implemented yet.
1587 BuildMI(BB, PPC::LI, 1, TmpReg1).addSImm(0);
1591 case Intrinsic::frameaddress:
1592 TmpReg1 = getReg(CI);
1593 if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
1594 BuildMI(BB, PPC::OR, 2, TmpReg1).addReg(PPC::R1).addReg(PPC::R1);
1596 // Values other than zero are not implemented yet.
1597 BuildMI(BB, PPC::LI, 1, TmpReg1).addSImm(0);
1602 // This may be useful for supporting isunordered
1603 case Intrinsic::isnan:
1604 // If this is only used by 'isunordered' style comparisons, don't emit it.
1605 if (isOnlyUsedByUnorderedComparisons(&CI)) return;
1606 TmpReg1 = getReg(CI.getOperand(1));
1607 emitUCOM(BB, BB->end(), TmpReg1, TmpReg1);
1608 TmpReg2 = makeAnotherReg(Type::IntTy);
1609 BuildMI(BB, PPC::MFCR, TmpReg2);
1610 TmpReg3 = getReg(CI);
1611 BuildMI(BB, PPC::RLWINM, 4, TmpReg3).addReg(TmpReg2).addImm(4).addImm(31).addImm(31);
1615 default: assert(0 && "Error: unknown intrinsics should have been lowered!");
1619 /// visitSimpleBinary - Implement simple binary operators for integral types...
1620 /// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for
1623 void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
1624 unsigned DestReg = getReg(B);
1625 MachineBasicBlock::iterator MI = BB->end();
1626 Value *Op0 = B.getOperand(0), *Op1 = B.getOperand(1);
1627 unsigned Class = getClassB(B.getType());
1629 emitSimpleBinaryOperation(BB, MI, Op0, Op1, OperatorClass, DestReg);
1632 /// emitBinaryFPOperation - This method handles emission of floating point
1633 /// Add (0), Sub (1), Mul (2), and Div (3) operations.
1634 void ISel::emitBinaryFPOperation(MachineBasicBlock *BB,
1635 MachineBasicBlock::iterator IP,
1636 Value *Op0, Value *Op1,
1637 unsigned OperatorClass, unsigned DestReg) {
1639 static const unsigned OpcodeTab[][4] = {
1640 { PPC::FADDS, PPC::FSUBS, PPC::FMULS, PPC::FDIVS }, // Float
1641 { PPC::FADD, PPC::FSUB, PPC::FMUL, PPC::FDIV }, // Double
1644 // Special case: R1 = op <const fp>, R2
1645 if (ConstantFP *Op0C = dyn_cast<ConstantFP>(Op0))
1646 if (Op0C->isExactlyValue(-0.0) && OperatorClass == 1) {
1648 unsigned op1Reg = getReg(Op1, BB, IP);
1649 BuildMI(*BB, IP, PPC::FNEG, 1, DestReg).addReg(op1Reg);
1653 unsigned Opcode = OpcodeTab[Op0->getType() == Type::DoubleTy][OperatorClass];
1654 unsigned Op0r = getReg(Op0, BB, IP);
1655 unsigned Op1r = getReg(Op1, BB, IP);
1656 BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
1659 /// emitSimpleBinaryOperation - Implement simple binary operators for integral
1660 /// types... OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for
1663 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
1664 /// and constant expression support.
1666 void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
1667 MachineBasicBlock::iterator IP,
1668 Value *Op0, Value *Op1,
1669 unsigned OperatorClass, unsigned DestReg) {
1670 unsigned Class = getClassB(Op0->getType());
1672 // Arithmetic and Bitwise operators
1673 static const unsigned OpcodeTab[] = {
1674 PPC::ADD, PPC::SUB, PPC::AND, PPC::OR, PPC::XOR
1676 static const unsigned ImmOpcodeTab[] = {
1677 PPC::ADDI, PPC::SUBI, PPC::ANDIo, PPC::ORI, PPC::XORI
1679 static const unsigned RImmOpcodeTab[] = {
1680 PPC::ADDI, PPC::SUBFIC, PPC::ANDIo, PPC::ORI, PPC::XORI
1683 if (Class == cFP32 || Class == cFP64) {
1684 assert(OperatorClass < 2 && "No logical ops for FP!");
1685 emitBinaryFPOperation(MBB, IP, Op0, Op1, OperatorClass, DestReg);
1689 if (Op0->getType() == Type::BoolTy) {
1690 if (OperatorClass == 3)
1691 // If this is an or of two isnan's, emit an FP comparison directly instead
1692 // of or'ing two isnan's together.
1693 if (Value *LHS = dyncastIsNan(Op0))
1694 if (Value *RHS = dyncastIsNan(Op1)) {
1695 unsigned Op0Reg = getReg(RHS, MBB, IP), Op1Reg = getReg(LHS, MBB, IP);
1696 unsigned TmpReg = makeAnotherReg(Type::IntTy);
1697 emitUCOM(MBB, IP, Op0Reg, Op1Reg);
1698 BuildMI(*MBB, IP, PPC::MFCR, TmpReg);
1699 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(TmpReg).addImm(4)
1700 .addImm(31).addImm(31);
1705 // Special case: op <const int>, Reg
1706 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op0)) {
1707 // sub 0, X -> subfic
1708 if (OperatorClass == 1 && canUseAsImmediateForOpcode(CI, 0)) {
1709 unsigned Op1r = getReg(Op1, MBB, IP);
1710 int imm = CI->getRawValue() & 0xFFFF;
1711 BuildMI(*MBB, IP, PPC::SUBFIC, 2, DestReg).addReg(Op1r).addSImm(imm);
1715 // If it is easy to do, swap the operands and emit an immediate op
1716 if (Class != cLong && OperatorClass != 1 &&
1717 canUseAsImmediateForOpcode(CI, OperatorClass)) {
1718 unsigned Op1r = getReg(Op1, MBB, IP);
1719 int imm = CI->getRawValue() & 0xFFFF;
1721 if (OperatorClass < 2)
1722 BuildMI(*MBB, IP, RImmOpcodeTab[OperatorClass], 2, DestReg).addReg(Op1r)
1725 BuildMI(*MBB, IP, RImmOpcodeTab[OperatorClass], 2, DestReg).addReg(Op1r)
1731 // Special case: op Reg, <const int>
1732 if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
1733 unsigned Op0r = getReg(Op0, MBB, IP);
1735 // xor X, -1 -> not X
1736 if (OperatorClass == 4 && Op1C->isAllOnesValue()) {
1737 BuildMI(*MBB, IP, PPC::NOR, 2, DestReg).addReg(Op0r).addReg(Op0r);
1741 if (canUseAsImmediateForOpcode(Op1C, OperatorClass)) {
1742 int immediate = Op1C->getRawValue() & 0xFFFF;
1744 if (OperatorClass < 2)
1745 BuildMI(*MBB, IP, ImmOpcodeTab[OperatorClass], 2,DestReg).addReg(Op0r)
1746 .addSImm(immediate);
1748 BuildMI(*MBB, IP, ImmOpcodeTab[OperatorClass], 2,DestReg).addReg(Op0r)
1749 .addZImm(immediate);
1751 unsigned Op1r = getReg(Op1, MBB, IP);
1752 BuildMI(*MBB, IP, OpcodeTab[OperatorClass], 2, DestReg).addReg(Op0r)
1758 // We couldn't generate an immediate variant of the op, load both halves into
1759 // registers and emit the appropriate opcode.
1760 unsigned Op0r = getReg(Op0, MBB, IP);
1761 unsigned Op1r = getReg(Op1, MBB, IP);
1762 unsigned Opcode = OpcodeTab[OperatorClass];
1763 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
1766 // ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
1767 // returns zero when the input is not exactly a power of two.
1768 static unsigned ExactLog2(unsigned Val) {
1769 if (Val == 0 || (Val & (Val-1))) return 0;
1778 /// doMultiply - Emit appropriate instructions to multiply together the
1779 /// Values Op0 and Op1, and put the result in DestReg.
1781 void ISel::doMultiply(MachineBasicBlock *MBB,
1782 MachineBasicBlock::iterator IP,
1783 unsigned DestReg, Value *Op0, Value *Op1) {
1784 unsigned Class0 = getClass(Op0->getType());
1785 unsigned Class1 = getClass(Op1->getType());
1787 unsigned Op0r = getReg(Op0, MBB, IP);
1788 unsigned Op1r = getReg(Op1, MBB, IP);
1791 if (Class0 == cLong && Class1 == cLong) {
1792 BuildMI(*MBB, IP, PPC::MULLD, 2, DestReg).addReg(Op0r).addReg(Op1r);
1796 // 64 x 32 or less, promote 32 to 64 and do a 64 x 64
1797 if (Class0 == cLong && Class1 <= cInt) {
1798 // FIXME: CLEAR or SIGN EXTEND Op1
1799 BuildMI(*MBB, IP, PPC::MULLD, 2, DestReg).addReg(Op0r).addReg(Op1r);
1804 if (Class0 <= cInt && Class1 <= cInt) {
1805 BuildMI(*MBB, IP, PPC::MULLW, 2, DestReg).addReg(Op0r).addReg(Op1r);
1809 assert(0 && "doMultiply cannot operate on unknown type!");
1812 /// doMultiplyConst - This method will multiply the value in Op0 by the
1813 /// value of the ContantInt *CI
1814 void ISel::doMultiplyConst(MachineBasicBlock *MBB,
1815 MachineBasicBlock::iterator IP,
1816 unsigned DestReg, Value *Op0, ConstantInt *CI) {
1817 unsigned Class = getClass(Op0->getType());
1820 if (CI->isNullValue()) {
1821 BuildMI(*MBB, IP, PPC::LI, 1, DestReg).addSImm(0);
1825 // Mul op0, 1 ==> op0
1826 if (CI->equalsInt(1)) {
1827 unsigned Op0r = getReg(Op0, MBB, IP);
1828 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(Op0r).addReg(Op0r);
1832 // If the element size is exactly a power of 2, use a shift to get it.
1833 if (unsigned Shift = ExactLog2(CI->getRawValue())) {
1834 ConstantUInt *ShiftCI = ConstantUInt::get(Type::UByteTy, Shift);
1835 emitShiftOperation(MBB, IP, Op0, ShiftCI, true, Op0->getType(), DestReg);
1839 // If 32 bits or less and immediate is in right range, emit mul by immediate
1840 if (Class == cByte || Class == cShort || Class == cInt) {
1841 if (canUseAsImmediateForOpcode(CI, 0)) {
1842 unsigned Op0r = getReg(Op0, MBB, IP);
1843 unsigned imm = CI->getRawValue() & 0xFFFF;
1844 BuildMI(*MBB, IP, PPC::MULLI, 2, DestReg).addReg(Op0r).addSImm(imm);
1849 doMultiply(MBB, IP, DestReg, Op0, CI);
1852 void ISel::visitMul(BinaryOperator &I) {
1853 unsigned ResultReg = getReg(I);
1855 Value *Op0 = I.getOperand(0);
1856 Value *Op1 = I.getOperand(1);
1858 MachineBasicBlock::iterator IP = BB->end();
1859 emitMultiply(BB, IP, Op0, Op1, ResultReg);
1862 void ISel::emitMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
1863 Value *Op0, Value *Op1, unsigned DestReg) {
1864 TypeClass Class = getClass(Op0->getType());
1871 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
1872 doMultiplyConst(MBB, IP, DestReg, Op0, CI);
1874 doMultiply(MBB, IP, DestReg, Op0, Op1);
1879 emitBinaryFPOperation(MBB, IP, Op0, Op1, 2, DestReg);
1886 /// visitDivRem - Handle division and remainder instructions... these
1887 /// instruction both require the same instructions to be generated, they just
1888 /// select the result from a different register. Note that both of these
1889 /// instructions work differently for signed and unsigned operands.
1891 void ISel::visitDivRem(BinaryOperator &I) {
1892 unsigned ResultReg = getReg(I);
1893 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
1895 MachineBasicBlock::iterator IP = BB->end();
1896 emitDivRemOperation(BB, IP, Op0, Op1, I.getOpcode() == Instruction::Div,
1900 void ISel::emitDivRemOperation(MachineBasicBlock *BB,
1901 MachineBasicBlock::iterator IP,
1902 Value *Op0, Value *Op1, bool isDiv,
1903 unsigned ResultReg) {
1904 const Type *Ty = Op0->getType();
1905 unsigned Class = getClass(Ty);
1909 // Floating point divide...
1910 emitBinaryFPOperation(BB, IP, Op0, Op1, 3, ResultReg);
1913 // Floating point remainder via fmodf(float x, float y);
1914 unsigned Op0Reg = getReg(Op0, BB, IP);
1915 unsigned Op1Reg = getReg(Op1, BB, IP);
1916 MachineInstr *TheCall =
1917 BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(fmodfFn, true);
1918 std::vector<ValueRecord> Args;
1919 Args.push_back(ValueRecord(Op0Reg, Type::FloatTy));
1920 Args.push_back(ValueRecord(Op1Reg, Type::FloatTy));
1921 doCall(ValueRecord(ResultReg, Type::FloatTy), TheCall, Args, false);
1926 // Floating point divide...
1927 emitBinaryFPOperation(BB, IP, Op0, Op1, 3, ResultReg);
1930 // Floating point remainder via fmod(double x, double y);
1931 unsigned Op0Reg = getReg(Op0, BB, IP);
1932 unsigned Op1Reg = getReg(Op1, BB, IP);
1933 MachineInstr *TheCall =
1934 BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(fmodFn, true);
1935 std::vector<ValueRecord> Args;
1936 Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy));
1937 Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy));
1938 doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args, false);
1942 static Function* const Funcs[] =
1943 { __moddi3Fn, __divdi3Fn, __umoddi3Fn, __udivdi3Fn };
1944 unsigned Op0Reg = getReg(Op0, BB, IP);
1945 unsigned Op1Reg = getReg(Op1, BB, IP);
1946 unsigned NameIdx = Ty->isUnsigned()*2 + isDiv;
1947 MachineInstr *TheCall =
1948 BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(Funcs[NameIdx], true);
1950 std::vector<ValueRecord> Args;
1951 Args.push_back(ValueRecord(Op0Reg, Type::LongTy));
1952 Args.push_back(ValueRecord(Op1Reg, Type::LongTy));
1953 doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args, false);
1956 case cByte: case cShort: case cInt:
1957 break; // Small integrals, handled below...
1958 default: assert(0 && "Unknown class!");
1961 // Special case signed division by power of 2.
1963 if (ConstantSInt *CI = dyn_cast<ConstantSInt>(Op1)) {
1964 assert(Class != cLong && "This doesn't handle 64-bit divides!");
1965 int V = CI->getValue();
1967 if (V == 1) { // X /s 1 => X
1968 unsigned Op0Reg = getReg(Op0, BB, IP);
1969 BuildMI(*BB, IP, PPC::OR, 2, ResultReg).addReg(Op0Reg).addReg(Op0Reg);
1973 if (V == -1) { // X /s -1 => -X
1974 unsigned Op0Reg = getReg(Op0, BB, IP);
1975 BuildMI(*BB, IP, PPC::NEG, 1, ResultReg).addReg(Op0Reg);
1979 unsigned log2V = ExactLog2(V);
1980 if (log2V != 0 && Ty->isSigned()) {
1981 unsigned Op0Reg = getReg(Op0, BB, IP);
1982 unsigned TmpReg = makeAnotherReg(Op0->getType());
1984 BuildMI(*BB, IP, PPC::SRAWI, 2, TmpReg).addReg(Op0Reg).addImm(log2V);
1985 BuildMI(*BB, IP, PPC::ADDZE, 1, ResultReg).addReg(TmpReg);
1990 unsigned Op0Reg = getReg(Op0, BB, IP);
1991 unsigned Op1Reg = getReg(Op1, BB, IP);
1992 unsigned Opcode = Ty->isSigned() ? PPC::DIVW : PPC::DIVWU;
1995 BuildMI(*BB, IP, Opcode, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1996 } else { // Remainder
1997 unsigned TmpReg1 = makeAnotherReg(Op0->getType());
1998 unsigned TmpReg2 = makeAnotherReg(Op0->getType());
2000 BuildMI(*BB, IP, Opcode, 2, TmpReg1).addReg(Op0Reg).addReg(Op1Reg);
2001 BuildMI(*BB, IP, PPC::MULLW, 2, TmpReg2).addReg(TmpReg1).addReg(Op1Reg);
2002 BuildMI(*BB, IP, PPC::SUBF, 2, ResultReg).addReg(TmpReg2).addReg(Op0Reg);
2007 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
2008 /// for constant immediate shift values, and for constant immediate
2009 /// shift values equal to 1. Even the general case is sort of special,
2010 /// because the shift amount has to be in CL, not just any old register.
2012 void ISel::visitShiftInst(ShiftInst &I) {
2013 MachineBasicBlock::iterator IP = BB->end();
2014 emitShiftOperation(BB, IP, I.getOperand(0), I.getOperand(1),
2015 I.getOpcode() == Instruction::Shl, I.getType(),
2019 /// emitShiftOperation - Common code shared between visitShiftInst and
2020 /// constant expression support.
2022 void ISel::emitShiftOperation(MachineBasicBlock *MBB,
2023 MachineBasicBlock::iterator IP,
2024 Value *Op, Value *ShiftAmount, bool isLeftShift,
2025 const Type *ResultTy, unsigned DestReg) {
2026 unsigned SrcReg = getReg (Op, MBB, IP);
2027 bool isSigned = ResultTy->isSigned ();
2028 unsigned Class = getClass (ResultTy);
2030 // Longs, as usual, are handled specially...
2031 if (Class == cLong) {
2032 // If we have a constant shift, we can generate much more efficient code
2033 // than otherwise...
2035 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
2036 unsigned Amount = CUI->getValue();
2037 assert(Amount < 64 && "Invalid immediate shift amount!");
2039 BuildMI(*MBB, IP, PPC::RLDICR, 3, DestReg).addReg(SrcReg).addImm(Amount)
2043 BuildMI(*MBB, IP, PPC::SRADI, 2, DestReg).addReg(SrcReg)
2046 BuildMI(*MBB, IP, PPC::RLDICL, 3, DestReg).addReg(SrcReg)
2047 .addImm(64-Amount).addImm(Amount);
2051 unsigned ShiftReg = getReg (ShiftAmount, MBB, IP);
2054 BuildMI(*MBB, IP, PPC::SLD, 2, DestReg).addReg(SrcReg).addReg(ShiftReg);
2056 unsigned Opcode = (isSigned) ? PPC::SRAD : PPC::SRD;
2057 BuildMI(*MBB, IP, Opcode, DestReg).addReg(SrcReg).addReg(ShiftReg);
2063 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
2064 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
2065 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
2066 unsigned Amount = CUI->getValue();
2069 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
2070 .addImm(Amount).addImm(0).addImm(31-Amount);
2073 BuildMI(*MBB, IP, PPC::SRAWI,2,DestReg).addReg(SrcReg).addImm(Amount);
2075 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
2076 .addImm(32-Amount).addImm(Amount).addImm(31);
2079 } else { // The shift amount is non-constant.
2080 unsigned ShiftAmountReg = getReg(ShiftAmount, MBB, IP);
2083 BuildMI(*MBB, IP, PPC::SLW, 2, DestReg).addReg(SrcReg)
2084 .addReg(ShiftAmountReg);
2086 BuildMI(*MBB, IP, isSigned ? PPC::SRAW : PPC::SRW, 2, DestReg)
2087 .addReg(SrcReg).addReg(ShiftAmountReg);
2093 /// visitLoadInst - Implement LLVM load instructions. Pretty straightforward
2094 /// mapping of LLVM classes to PPC load instructions, with the exception of
2095 /// signed byte loads, which need a sign extension following them.
2097 void ISel::visitLoadInst(LoadInst &I) {
2098 // Immediate opcodes, for reg+imm addressing
2099 static const unsigned ImmOpcodes[] = {
2100 PPC::LBZ, PPC::LHZ, PPC::LWZ,
2101 PPC::LFS, PPC::LFD, PPC::LWZ
2103 // Indexed opcodes, for reg+reg addressing
2104 static const unsigned IdxOpcodes[] = {
2105 PPC::LBZX, PPC::LHZX, PPC::LWZX,
2106 PPC::LFSX, PPC::LFDX, PPC::LWZX
2109 unsigned Class = getClassB(I.getType());
2110 unsigned ImmOpcode = ImmOpcodes[Class];
2111 unsigned IdxOpcode = IdxOpcodes[Class];
2112 unsigned DestReg = getReg(I);
2113 Value *SourceAddr = I.getOperand(0);
2115 if (Class == cShort && I.getType()->isSigned()) ImmOpcode = PPC::LHA;
2116 if (Class == cShort && I.getType()->isSigned()) IdxOpcode = PPC::LHAX;
2118 if (AllocaInst *AI = dyn_castFixedAlloca(SourceAddr)) {
2119 unsigned FI = getFixedSizedAllocaFI(AI);
2120 if (Class == cByte && I.getType()->isSigned()) {
2121 unsigned TmpReg = makeAnotherReg(I.getType());
2122 addFrameReference(BuildMI(BB, ImmOpcode, 2, TmpReg), FI);
2123 BuildMI(BB, PPC::EXTSB, 1, DestReg).addReg(TmpReg);
2125 addFrameReference(BuildMI(BB, ImmOpcode, 2, DestReg), FI);
2130 // If this load is the only use of the GEP instruction that is its address,
2131 // then we can fold the GEP directly into the load instruction.
2132 // emitGEPOperation with a second to last arg of 'true' will place the
2133 // base register for the GEP into baseReg, and the constant offset from that
2134 // into offset. If the offset fits in 16 bits, we can emit a reg+imm store
2135 // otherwise, we copy the offset into another reg, and use reg+reg addressing.
2136 if (GetElementPtrInst *GEPI = canFoldGEPIntoLoadOrStore(SourceAddr)) {
2137 unsigned baseReg = getReg(GEPI);
2138 unsigned pendingAdd;
2139 ConstantSInt *offset;
2141 emitGEPOperation(BB, BB->end(), GEPI->getOperand(0), GEPI->op_begin()+1,
2142 GEPI->op_end(), baseReg, true, &offset, &pendingAdd);
2144 if (pendingAdd == 0 && Class != cLong &&
2145 canUseAsImmediateForOpcode(offset, 0)) {
2146 if (Class == cByte && I.getType()->isSigned()) {
2147 unsigned TmpReg = makeAnotherReg(I.getType());
2148 BuildMI(BB, ImmOpcode, 2, TmpReg).addSImm(offset->getValue())
2150 BuildMI(BB, PPC::EXTSB, 1, DestReg).addReg(TmpReg);
2152 BuildMI(BB, ImmOpcode, 2, DestReg).addSImm(offset->getValue())
2158 unsigned indexReg = (pendingAdd != 0) ? pendingAdd : getReg(offset);
2160 if (Class == cByte && I.getType()->isSigned()) {
2161 unsigned TmpReg = makeAnotherReg(I.getType());
2162 BuildMI(BB, IdxOpcode, 2, TmpReg).addReg(indexReg).addReg(baseReg);
2163 BuildMI(BB, PPC::EXTSB, 1, DestReg).addReg(TmpReg);
2165 BuildMI(BB, IdxOpcode, 2, DestReg).addReg(indexReg).addReg(baseReg);
2170 // The fallback case, where the load was from a source that could not be
2171 // folded into the load instruction.
2172 unsigned SrcAddrReg = getReg(SourceAddr);
2174 if (Class == cByte && I.getType()->isSigned()) {
2175 unsigned TmpReg = makeAnotherReg(I.getType());
2176 BuildMI(BB, ImmOpcode, 2, TmpReg).addSImm(0).addReg(SrcAddrReg);
2177 BuildMI(BB, PPC::EXTSB, 1, DestReg).addReg(TmpReg);
2179 BuildMI(BB, ImmOpcode, 2, DestReg).addSImm(0).addReg(SrcAddrReg);
2183 /// visitStoreInst - Implement LLVM store instructions
2185 void ISel::visitStoreInst(StoreInst &I) {
2186 // Immediate opcodes, for reg+imm addressing
2187 static const unsigned ImmOpcodes[] = {
2188 PPC::STB, PPC::STH, PPC::STW,
2189 PPC::STFS, PPC::STFD, PPC::STW
2191 // Indexed opcodes, for reg+reg addressing
2192 static const unsigned IdxOpcodes[] = {
2193 PPC::STBX, PPC::STHX, PPC::STWX,
2194 PPC::STFSX, PPC::STFDX, PPC::STWX
2197 Value *SourceAddr = I.getOperand(1);
2198 const Type *ValTy = I.getOperand(0)->getType();
2199 unsigned Class = getClassB(ValTy);
2200 unsigned ImmOpcode = ImmOpcodes[Class];
2201 unsigned IdxOpcode = IdxOpcodes[Class];
2202 unsigned ValReg = getReg(I.getOperand(0));
2204 // If this store is the only use of the GEP instruction that is its address,
2205 // then we can fold the GEP directly into the store instruction.
2206 // emitGEPOperation with a second to last arg of 'true' will place the
2207 // base register for the GEP into baseReg, and the constant offset from that
2208 // into offset. If the offset fits in 16 bits, we can emit a reg+imm store
2209 // otherwise, we copy the offset into another reg, and use reg+reg addressing.
2210 if (GetElementPtrInst *GEPI = canFoldGEPIntoLoadOrStore(SourceAddr)) {
2211 unsigned baseReg = getReg(GEPI);
2212 unsigned pendingAdd;
2213 ConstantSInt *offset;
2215 emitGEPOperation(BB, BB->end(), GEPI->getOperand(0), GEPI->op_begin()+1,
2216 GEPI->op_end(), baseReg, true, &offset, &pendingAdd);
2218 if (0 == pendingAdd && Class != cLong &&
2219 canUseAsImmediateForOpcode(offset, 0)) {
2220 BuildMI(BB, ImmOpcode, 3).addReg(ValReg).addSImm(offset->getValue())
2225 unsigned indexReg = (pendingAdd != 0) ? pendingAdd : getReg(offset);
2226 BuildMI(BB, IdxOpcode, 3).addReg(ValReg).addReg(indexReg).addReg(baseReg);
2230 // If the store address wasn't the only use of a GEP, we fall back to the
2231 // standard path: store the ValReg at the value in AddressReg.
2232 unsigned AddressReg = getReg(I.getOperand(1));
2233 BuildMI(BB, ImmOpcode, 3).addReg(ValReg).addSImm(0).addReg(AddressReg);
2237 /// visitCastInst - Here we have various kinds of copying with or without sign
2238 /// extension going on.
2240 void ISel::visitCastInst(CastInst &CI) {
2241 Value *Op = CI.getOperand(0);
2243 unsigned SrcClass = getClassB(Op->getType());
2244 unsigned DestClass = getClassB(CI.getType());
2246 // If this is a cast from a 32-bit integer to a Long type, and the only uses
2247 // of the case are GEP instructions, then the cast does not need to be
2248 // generated explicitly, it will be folded into the GEP.
2249 if (DestClass == cLong && SrcClass == cInt) {
2250 bool AllUsesAreGEPs = true;
2251 for (Value::use_iterator I = CI.use_begin(), E = CI.use_end(); I != E; ++I)
2252 if (!isa<GetElementPtrInst>(*I)) {
2253 AllUsesAreGEPs = false;
2257 // No need to codegen this cast if all users are getelementptr instrs...
2258 if (AllUsesAreGEPs) return;
2261 unsigned DestReg = getReg(CI);
2262 MachineBasicBlock::iterator MI = BB->end();
2263 emitCastOperation(BB, MI, Op, CI.getType(), DestReg);
2266 /// emitCastOperation - Common code shared between visitCastInst and constant
2267 /// expression cast support.
2269 void ISel::emitCastOperation(MachineBasicBlock *MBB,
2270 MachineBasicBlock::iterator IP,
2271 Value *Src, const Type *DestTy,
2273 const Type *SrcTy = Src->getType();
2274 unsigned SrcClass = getClassB(SrcTy);
2275 unsigned DestClass = getClassB(DestTy);
2276 unsigned SrcReg = getReg(Src, MBB, IP);
2278 // Implement casts to bool by using compare on the operand followed by set if
2279 // not zero on the result.
2280 if (DestTy == Type::BoolTy) {
2286 unsigned TmpReg = makeAnotherReg(Type::IntTy);
2287 BuildMI(*MBB, IP, PPC::ADDIC, 2, TmpReg).addReg(SrcReg).addSImm(-1);
2288 BuildMI(*MBB, IP, PPC::SUBFE, 2, DestReg).addReg(TmpReg).addReg(SrcReg);
2294 std::cerr << "ERROR: Cast fp-to-bool not implemented!\n";
2300 // Handle cast of Float -> Double
2301 if (SrcClass == cFP32 && DestClass == cFP64) {
2302 BuildMI(*MBB, IP, PPC::FMR, 1, DestReg).addReg(SrcReg);
2306 // Handle cast of Double -> Float
2307 if (SrcClass == cFP64 && DestClass == cFP32) {
2308 BuildMI(*MBB, IP, PPC::FRSP, 1, DestReg).addReg(SrcReg);
2312 // Handle casts from integer to floating point now...
2313 if (DestClass == cFP32 || DestClass == cFP64) {
2315 // Emit a library call for long to float conversion
2316 if (SrcClass == cLong) {
2317 std::vector<ValueRecord> Args;
2318 Args.push_back(ValueRecord(SrcReg, SrcTy));
2319 Function *floatFn = (DestClass == cFP32) ? __floatdisfFn : __floatdidfFn;
2320 MachineInstr *TheCall =
2321 BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(floatFn, true);
2322 doCall(ValueRecord(DestReg, DestTy), TheCall, Args, false);
2326 // Make sure we're dealing with a full 32 bits
2327 unsigned TmpReg = makeAnotherReg(Type::IntTy);
2328 promote32(TmpReg, ValueRecord(SrcReg, SrcTy));
2332 // Spill the integer to memory and reload it from there.
2333 // Also spill room for a special conversion constant
2334 int ConstantFrameIndex =
2335 F->getFrameInfo()->CreateStackObject(Type::DoubleTy, TM.getTargetData());
2337 F->getFrameInfo()->CreateStackObject(Type::DoubleTy, TM.getTargetData());
2339 unsigned constantHi = makeAnotherReg(Type::IntTy);
2340 unsigned constantLo = makeAnotherReg(Type::IntTy);
2341 unsigned ConstF = makeAnotherReg(Type::DoubleTy);
2342 unsigned TempF = makeAnotherReg(Type::DoubleTy);
2344 if (!SrcTy->isSigned()) {
2345 BuildMI(*BB, IP, PPC::LIS, 1, constantHi).addSImm(0x4330);
2346 BuildMI(*BB, IP, PPC::LI, 1, constantLo).addSImm(0);
2347 addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(constantHi),
2348 ConstantFrameIndex);
2349 addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(constantLo),
2350 ConstantFrameIndex, 4);
2351 addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(constantHi),
2353 addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(SrcReg),
2355 addFrameReference(BuildMI(*BB, IP, PPC::LFD, 2, ConstF),
2356 ConstantFrameIndex);
2357 addFrameReference(BuildMI(*BB, IP, PPC::LFD, 2, TempF), ValueFrameIdx);
2358 BuildMI(*BB, IP, PPC::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF);
2360 unsigned TempLo = makeAnotherReg(Type::IntTy);
2361 BuildMI(*BB, IP, PPC::LIS, 1, constantHi).addSImm(0x4330);
2362 BuildMI(*BB, IP, PPC::LIS, 1, constantLo).addSImm(0x8000);
2363 addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(constantHi),
2364 ConstantFrameIndex);
2365 addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(constantLo),
2366 ConstantFrameIndex, 4);
2367 addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(constantHi),
2369 BuildMI(*BB, IP, PPC::XORIS, 2, TempLo).addReg(SrcReg).addImm(0x8000);
2370 addFrameReference(BuildMI(*BB, IP, PPC::STW, 3).addReg(TempLo),
2372 addFrameReference(BuildMI(*BB, IP, PPC::LFD, 2, ConstF),
2373 ConstantFrameIndex);
2374 addFrameReference(BuildMI(*BB, IP, PPC::LFD, 2, TempF), ValueFrameIdx);
2375 BuildMI(*BB, IP, PPC::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF);
2380 // Handle casts from floating point to integer now...
2381 if (SrcClass == cFP32 || SrcClass == cFP64) {
2382 static Function* const Funcs[] =
2383 { __fixsfdiFn, __fixdfdiFn, __fixunssfdiFn, __fixunsdfdiFn };
2384 // emit library call
2385 if (DestClass == cLong) {
2386 bool isDouble = SrcClass == cFP64;
2387 unsigned nameIndex = 2 * DestTy->isSigned() + isDouble;
2388 std::vector<ValueRecord> Args;
2389 Args.push_back(ValueRecord(SrcReg, SrcTy));
2390 Function *floatFn = Funcs[nameIndex];
2391 MachineInstr *TheCall =
2392 BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(floatFn, true);
2393 doCall(ValueRecord(DestReg, DestTy), TheCall, Args, false);
2398 F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
2400 if (DestTy->isSigned()) {
2401 unsigned TempReg = makeAnotherReg(Type::DoubleTy);
2403 // Convert to integer in the FP reg and store it to a stack slot
2404 BuildMI(*BB, IP, PPC::FCTIWZ, 1, TempReg).addReg(SrcReg);
2405 addFrameReference(BuildMI(*BB, IP, PPC::STFD, 3)
2406 .addReg(TempReg), ValueFrameIdx);
2408 // There is no load signed byte opcode, so we must emit a sign extend for
2409 // that particular size. Make sure to source the new integer from the
2411 if (DestClass == cByte) {
2412 unsigned TempReg2 = makeAnotherReg(DestTy);
2413 addFrameReference(BuildMI(*BB, IP, PPC::LBZ, 2, TempReg2),
2415 BuildMI(*MBB, IP, PPC::EXTSB, DestReg).addReg(TempReg2);
2417 int offset = (DestClass == cShort) ? 6 : 4;
2418 unsigned LoadOp = (DestClass == cShort) ? PPC::LHA : PPC::LWZ;
2419 addFrameReference(BuildMI(*BB, IP, LoadOp, 2, DestReg),
2420 ValueFrameIdx, offset);
2423 unsigned Zero = getReg(ConstantFP::get(Type::DoubleTy, 0.0f));
2424 double maxInt = (1LL << 32) - 1;
2425 unsigned MaxInt = getReg(ConstantFP::get(Type::DoubleTy, maxInt));
2426 double border = 1LL << 31;
2427 unsigned Border = getReg(ConstantFP::get(Type::DoubleTy, border));
2428 unsigned UseZero = makeAnotherReg(Type::DoubleTy);
2429 unsigned UseMaxInt = makeAnotherReg(Type::DoubleTy);
2430 unsigned UseChoice = makeAnotherReg(Type::DoubleTy);
2431 unsigned TmpReg = makeAnotherReg(Type::DoubleTy);
2432 unsigned TmpReg2 = makeAnotherReg(Type::DoubleTy);
2433 unsigned ConvReg = makeAnotherReg(Type::DoubleTy);
2434 unsigned IntTmp = makeAnotherReg(Type::IntTy);
2435 unsigned XorReg = makeAnotherReg(Type::IntTy);
2437 F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
2438 // Update machine-CFG edges
2439 MachineBasicBlock *XorMBB = new MachineBasicBlock(BB->getBasicBlock());
2440 MachineBasicBlock *PhiMBB = new MachineBasicBlock(BB->getBasicBlock());
2441 MachineBasicBlock *OldMBB = BB;
2442 ilist<MachineBasicBlock>::iterator It = BB; ++It;
2443 F->getBasicBlockList().insert(It, XorMBB);
2444 F->getBasicBlockList().insert(It, PhiMBB);
2445 BB->addSuccessor(XorMBB);
2446 BB->addSuccessor(PhiMBB);
2448 // Convert from floating point to unsigned 32-bit value
2449 // Use 0 if incoming value is < 0.0
2450 BuildMI(*BB, IP, PPC::FSEL, 3, UseZero).addReg(SrcReg).addReg(SrcReg)
2452 // Use 2**32 - 1 if incoming value is >= 2**32
2453 BuildMI(*BB, IP, PPC::FSUB, 2, UseMaxInt).addReg(MaxInt).addReg(SrcReg);
2454 BuildMI(*BB, IP, PPC::FSEL, 3, UseChoice).addReg(UseMaxInt)
2455 .addReg(UseZero).addReg(MaxInt);
2457 BuildMI(*BB, IP, PPC::FSUB, 2, TmpReg).addReg(UseChoice).addReg(Border);
2458 // Use difference if >= 2**31
2459 BuildMI(*BB, IP, PPC::FCMPU, 2, PPC::CR0).addReg(UseChoice)
2461 BuildMI(*BB, IP, PPC::FSEL, 3, TmpReg2).addReg(TmpReg).addReg(TmpReg)
2463 // Convert to integer
2464 BuildMI(*BB, IP, PPC::FCTIWZ, 1, ConvReg).addReg(TmpReg2);
2465 addFrameReference(BuildMI(*BB, IP, PPC::STFD, 3).addReg(ConvReg),
2467 if (DestClass == cByte) {
2468 addFrameReference(BuildMI(*BB, IP, PPC::LBZ, 2, DestReg),
2470 } else if (DestClass == cShort) {
2471 addFrameReference(BuildMI(*BB, IP, PPC::LHZ, 2, DestReg),
2473 } if (DestClass == cInt) {
2474 addFrameReference(BuildMI(*BB, IP, PPC::LWZ, 2, IntTmp),
2476 BuildMI(*BB, IP, PPC::BLT, 2).addReg(PPC::CR0).addMBB(PhiMBB);
2477 BuildMI(*BB, IP, PPC::B, 1).addMBB(XorMBB);
2480 // add 2**31 if input was >= 2**31
2482 BuildMI(BB, PPC::XORIS, 2, XorReg).addReg(IntTmp).addImm(0x8000);
2483 XorMBB->addSuccessor(PhiMBB);
2486 // DestReg = phi [ IntTmp, OldMBB ], [ XorReg, XorMBB ]
2488 BuildMI(BB, PPC::PHI, 4, DestReg).addReg(IntTmp).addMBB(OldMBB)
2489 .addReg(XorReg).addMBB(XorMBB);
2495 // Check our invariants
2496 assert((SrcClass <= cInt || SrcClass == cLong) &&
2497 "Unhandled source class for cast operation!");
2498 assert((DestClass <= cInt || DestClass == cLong) &&
2499 "Unhandled destination class for cast operation!");
2501 bool sourceUnsigned = SrcTy->isUnsigned() || SrcTy == Type::BoolTy;
2502 bool destUnsigned = DestTy->isUnsigned();
2504 // Unsigned -> Unsigned, clear if larger
2505 if (sourceUnsigned && destUnsigned) {
2506 // handle long dest class now to keep switch clean
2507 if (DestClass == cLong) {
2508 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2512 // handle u{ byte, short, int } x u{ byte, short, int }
2513 unsigned clearBits = (SrcClass == cByte || DestClass == cByte) ? 24 : 16;
2517 if (SrcClass == DestClass)
2518 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2520 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
2521 .addImm(0).addImm(clearBits).addImm(31);
2527 if (DestClass == cInt)
2528 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2530 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
2531 .addImm(0).addImm(clearBits).addImm(31);
2538 if (!sourceUnsigned && !destUnsigned) {
2539 // handle long dest class now to keep switch clean
2540 if (DestClass == cLong) {
2541 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2545 // handle { byte, short, int } x { byte, short, int }
2548 if (DestClass == cByte)
2549 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2551 BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
2554 if (DestClass == cByte)
2555 BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
2556 else if (DestClass == cShort)
2557 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2559 BuildMI(*MBB, IP, PPC::EXTSH, 1, DestReg).addReg(SrcReg);
2565 if (DestClass == cByte)
2566 BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
2567 else if (DestClass == cShort)
2568 BuildMI(*MBB, IP, PPC::EXTSH, 1, DestReg).addReg(SrcReg);
2570 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2576 // Unsigned -> Signed
2577 if (sourceUnsigned && !destUnsigned) {
2578 // handle long dest class now to keep switch clean
2579 if (DestClass == cLong) {
2580 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2584 // handle u{ byte, short, int } -> { byte, short, int }
2587 if (DestClass == cByte)
2588 // uByte 255 -> signed byte == -1
2589 BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
2591 // uByte 255 -> signed short/int == 255
2592 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg).addImm(0)
2593 .addImm(24).addImm(31);
2596 if (DestClass == cByte)
2597 BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
2598 else if (DestClass == cShort)
2599 BuildMI(*MBB, IP, PPC::EXTSH, 1, DestReg).addReg(SrcReg);
2601 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg).addImm(0)
2602 .addImm(16).addImm(31);
2608 if (DestClass == cByte)
2609 BuildMI(*MBB, IP, PPC::EXTSB, 1, DestReg).addReg(SrcReg);
2610 else if (DestClass == cShort)
2611 BuildMI(*MBB, IP, PPC::EXTSH, 1, DestReg).addReg(SrcReg);
2613 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2619 // Signed -> Unsigned
2620 if (!sourceUnsigned && destUnsigned) {
2621 // handle long dest class now to keep switch clean
2622 if (DestClass == cLong) {
2623 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2627 // handle { byte, short, int } -> u{ byte, short, int }
2628 unsigned clearBits = (DestClass == cByte) ? 24 : 16;
2632 if (DestClass == cByte || DestClass == cShort)
2633 // sbyte -1 -> ubyte 0x000000FF
2634 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
2635 .addImm(0).addImm(clearBits).addImm(31);
2637 // sbyte -1 -> ubyte 0xFFFFFFFF
2638 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2642 if (DestClass == cInt)
2643 BuildMI(*MBB, IP, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2645 BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg)
2646 .addImm(0).addImm(clearBits).addImm(31);
2652 // Anything we haven't handled already, we can't (yet) handle at all.
2653 std::cerr << "Unhandled cast from " << SrcTy->getDescription()
2654 << "to " << DestTy->getDescription() << '\n';
2658 /// visitVANextInst - Implement the va_next instruction...
2660 void ISel::visitVANextInst(VANextInst &I) {
2661 unsigned VAList = getReg(I.getOperand(0));
2662 unsigned DestReg = getReg(I);
2665 switch (I.getArgType()->getTypeID()) {
2668 assert(0 && "Error: bad type for va_next instruction!");
2670 case Type::PointerTyID:
2671 case Type::UIntTyID:
2675 case Type::ULongTyID:
2676 case Type::LongTyID:
2677 case Type::DoubleTyID:
2682 // Increment the VAList pointer...
2683 BuildMI(BB, PPC::ADDI, 2, DestReg).addReg(VAList).addSImm(Size);
2686 void ISel::visitVAArgInst(VAArgInst &I) {
2687 unsigned VAList = getReg(I.getOperand(0));
2688 unsigned DestReg = getReg(I);
2690 switch (I.getType()->getTypeID()) {
2693 assert(0 && "Error: bad type for va_next instruction!");
2695 case Type::PointerTyID:
2696 case Type::UIntTyID:
2698 BuildMI(BB, PPC::LWZ, 2, DestReg).addSImm(0).addReg(VAList);
2700 case Type::ULongTyID:
2701 case Type::LongTyID:
2702 BuildMI(BB, PPC::LD, 2, DestReg).addSImm(0).addReg(VAList);
2704 case Type::FloatTyID:
2705 BuildMI(BB, PPC::LFS, 2, DestReg).addSImm(0).addReg(VAList);
2707 case Type::DoubleTyID:
2708 BuildMI(BB, PPC::LFD, 2, DestReg).addSImm(0).addReg(VAList);
2713 /// visitGetElementPtrInst - instruction-select GEP instructions
2715 void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
2716 if (canFoldGEPIntoLoadOrStore(&I))
2719 unsigned outputReg = getReg(I);
2720 emitGEPOperation(BB, BB->end(), I.getOperand(0), I.op_begin()+1, I.op_end(),
2721 outputReg, false, 0, 0);
2724 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
2725 /// constant expression GEP support.
2727 void ISel::emitGEPOperation(MachineBasicBlock *MBB,
2728 MachineBasicBlock::iterator IP,
2729 Value *Src, User::op_iterator IdxBegin,
2730 User::op_iterator IdxEnd, unsigned TargetReg,
2731 bool GEPIsFolded, ConstantSInt **RemainderPtr,
2732 unsigned *PendingAddReg) {
2733 const TargetData &TD = TM.getTargetData();
2734 const Type *Ty = Src->getType();
2735 unsigned basePtrReg = getReg(Src, MBB, IP);
2736 int64_t constValue = 0;
2738 // Record the operations to emit the GEP in a vector so that we can emit them
2739 // after having analyzed the entire instruction.
2740 std::vector<CollapsedGepOp> ops;
2742 // GEPs have zero or more indices; we must perform a struct access
2743 // or array access for each one.
2744 for (GetElementPtrInst::op_iterator oi = IdxBegin, oe = IdxEnd; oi != oe;
2747 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2748 // It's a struct access. idx is the index into the structure,
2749 // which names the field. Use the TargetData structure to
2750 // pick out what the layout of the structure is in memory.
2751 // Use the (constant) structure index's value to find the
2752 // right byte offset from the StructLayout class's list of
2753 // structure member offsets.
2754 unsigned fieldIndex = cast<ConstantUInt>(idx)->getValue();
2755 unsigned memberOffset =
2756 TD.getStructLayout(StTy)->MemberOffsets[fieldIndex];
2758 // StructType member offsets are always constant values. Add it to the
2760 constValue += memberOffset;
2762 // The next type is the member of the structure selected by the
2764 Ty = StTy->getElementType (fieldIndex);
2765 } else if (const SequentialType *SqTy = dyn_cast<SequentialType> (Ty)) {
2766 // Many GEP instructions use a [cast (int/uint) to LongTy] as their
2767 // operand. Handle this case directly now...
2768 if (CastInst *CI = dyn_cast<CastInst>(idx))
2769 if (CI->getOperand(0)->getType() == Type::IntTy ||
2770 CI->getOperand(0)->getType() == Type::UIntTy)
2771 idx = CI->getOperand(0);
2773 // It's an array or pointer access: [ArraySize x ElementType].
2774 // We want to add basePtrReg to (idxReg * sizeof ElementType). First, we
2775 // must find the size of the pointed-to type (Not coincidentally, the next
2776 // type is the type of the elements in the array).
2777 Ty = SqTy->getElementType();
2778 unsigned elementSize = TD.getTypeSize(Ty);
2780 if (ConstantInt *C = dyn_cast<ConstantInt>(idx)) {
2781 if (ConstantSInt *CS = dyn_cast<ConstantSInt>(C))
2782 constValue += CS->getValue() * elementSize;
2783 else if (ConstantUInt *CU = dyn_cast<ConstantUInt>(C))
2784 constValue += CU->getValue() * elementSize;
2786 assert(0 && "Invalid ConstantInt GEP index type!");
2788 // Push current gep state to this point as an add
2789 ops.push_back(CollapsedGepOp(false, 0,
2790 ConstantSInt::get(Type::IntTy,constValue)));
2792 // Push multiply gep op and reset constant value
2793 ops.push_back(CollapsedGepOp(true, idx,
2794 ConstantSInt::get(Type::IntTy, elementSize)));
2800 // Emit instructions for all the collapsed ops
2801 bool pendingAdd = false;
2802 unsigned pendingAddReg = 0;
2804 for(std::vector<CollapsedGepOp>::iterator cgo_i = ops.begin(),
2805 cgo_e = ops.end(); cgo_i != cgo_e; ++cgo_i) {
2806 CollapsedGepOp& cgo = *cgo_i;
2807 unsigned nextBasePtrReg = makeAnotherReg(Type::IntTy);
2809 // If we didn't emit an add last time through the loop, we need to now so
2810 // that the base reg is updated appropriately.
2812 assert(pendingAddReg != 0 && "Uninitialized register in pending add!");
2813 BuildMI(*MBB, IP, PPC::ADD, 2, nextBasePtrReg).addReg(basePtrReg)
2814 .addReg(pendingAddReg);
2815 basePtrReg = nextBasePtrReg;
2816 nextBasePtrReg = makeAnotherReg(Type::IntTy);
2822 // We know the elementSize is a constant, so we can emit a constant mul
2823 unsigned TmpReg = makeAnotherReg(Type::IntTy);
2824 doMultiplyConst(MBB, IP, nextBasePtrReg, cgo.index, cgo.size);
2825 pendingAddReg = basePtrReg;
2828 // Try and generate an immediate addition if possible
2829 if (cgo.size->isNullValue()) {
2830 BuildMI(*MBB, IP, PPC::OR, 2, nextBasePtrReg).addReg(basePtrReg)
2831 .addReg(basePtrReg);
2832 } else if (canUseAsImmediateForOpcode(cgo.size, 0)) {
2833 BuildMI(*MBB, IP, PPC::ADDI, 2, nextBasePtrReg).addReg(basePtrReg)
2834 .addSImm(cgo.size->getValue());
2836 unsigned Op1r = getReg(cgo.size, MBB, IP);
2837 BuildMI(*MBB, IP, PPC::ADD, 2, nextBasePtrReg).addReg(basePtrReg)
2842 basePtrReg = nextBasePtrReg;
2844 // Add the current base register plus any accumulated constant value
2845 ConstantSInt *remainder = ConstantSInt::get(Type::IntTy, constValue);
2847 // If we are emitting this during a fold, copy the current base register to
2848 // the target, and save the current constant offset so the folding load or
2849 // store can try and use it as an immediate.
2851 // If this is a folded GEP and the last element was an index, then we need
2852 // to do some extra work to turn a shift/add/stw into a shift/stwx
2853 if (pendingAdd && 0 == remainder->getValue()) {
2854 assert(pendingAddReg != 0 && "Uninitialized register in pending add!");
2855 *PendingAddReg = pendingAddReg;
2859 unsigned nextBasePtrReg = makeAnotherReg(Type::IntTy);
2860 assert(pendingAddReg != 0 && "Uninitialized register in pending add!");
2861 BuildMI(*MBB, IP, PPC::ADD, 2, nextBasePtrReg).addReg(basePtrReg)
2862 .addReg(pendingAddReg);
2863 basePtrReg = nextBasePtrReg;
2866 BuildMI (*MBB, IP, PPC::OR, 2, TargetReg).addReg(basePtrReg)
2867 .addReg(basePtrReg);
2868 *RemainderPtr = remainder;
2872 // If we still have a pending add at this point, emit it now
2874 unsigned TmpReg = makeAnotherReg(Type::IntTy);
2875 BuildMI(*MBB, IP, PPC::ADD, 2, TmpReg).addReg(pendingAddReg)
2876 .addReg(basePtrReg);
2877 basePtrReg = TmpReg;
2880 // After we have processed all the indices, the result is left in
2881 // basePtrReg. Move it to the register where we were expected to
2883 if (remainder->isNullValue()) {
2884 BuildMI (*MBB, IP, PPC::OR, 2, TargetReg).addReg(basePtrReg)
2885 .addReg(basePtrReg);
2886 } else if (canUseAsImmediateForOpcode(remainder, 0)) {
2887 BuildMI(*MBB, IP, PPC::ADDI, 2, TargetReg).addReg(basePtrReg)
2888 .addSImm(remainder->getValue());
2890 unsigned Op1r = getReg(remainder, MBB, IP);
2891 BuildMI(*MBB, IP, PPC::ADD, 2, TargetReg).addReg(basePtrReg).addReg(Op1r);
2895 /// visitAllocaInst - If this is a fixed size alloca, allocate space from the
2896 /// frame manager, otherwise do it the hard way.
2898 void ISel::visitAllocaInst(AllocaInst &I) {
2899 // If this is a fixed size alloca in the entry block for the function, we
2900 // statically stack allocate the space, so we don't need to do anything here.
2902 if (dyn_castFixedAlloca(&I)) return;
2904 // Find the data size of the alloca inst's getAllocatedType.
2905 const Type *Ty = I.getAllocatedType();
2906 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
2908 // Create a register to hold the temporary result of multiplying the type size
2909 // constant by the variable amount.
2910 unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
2912 // TotalSizeReg = mul <numelements>, <TypeSize>
2913 MachineBasicBlock::iterator MBBI = BB->end();
2914 ConstantUInt *CUI = ConstantUInt::get(Type::UIntTy, TySize);
2915 doMultiplyConst(BB, MBBI, TotalSizeReg, I.getArraySize(), CUI);
2917 // AddedSize = add <TotalSizeReg>, 15
2918 unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy);
2919 BuildMI(BB, PPC::ADDI, 2, AddedSizeReg).addReg(TotalSizeReg).addSImm(15);
2921 // AlignedSize = and <AddedSize>, ~15
2922 unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
2923 BuildMI(BB, PPC::RLWINM, 4, AlignedSize).addReg(AddedSizeReg).addImm(0)
2924 .addImm(0).addImm(27);
2926 // Subtract size from stack pointer, thereby allocating some space.
2927 BuildMI(BB, PPC::SUB, 2, PPC::R1).addReg(PPC::R1).addReg(AlignedSize);
2929 // Put a pointer to the space into the result register, by copying
2930 // the stack pointer.
2931 BuildMI(BB, PPC::OR, 2, getReg(I)).addReg(PPC::R1).addReg(PPC::R1);
2933 // Inform the Frame Information that we have just allocated a variable-sized
2935 F->getFrameInfo()->CreateVariableSizedObject();
2938 /// visitMallocInst - Malloc instructions are code generated into direct calls
2939 /// to the library malloc.
2941 void ISel::visitMallocInst(MallocInst &I) {
2942 unsigned AllocSize = TM.getTargetData().getTypeSize(I.getAllocatedType());
2945 if (ConstantUInt *C = dyn_cast<ConstantUInt>(I.getOperand(0))) {
2946 Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize));
2948 Arg = makeAnotherReg(Type::UIntTy);
2949 MachineBasicBlock::iterator MBBI = BB->end();
2950 ConstantUInt *CUI = ConstantUInt::get(Type::UIntTy, AllocSize);
2951 doMultiplyConst(BB, MBBI, Arg, I.getOperand(0), CUI);
2954 std::vector<ValueRecord> Args;
2955 Args.push_back(ValueRecord(Arg, Type::UIntTy));
2956 MachineInstr *TheCall =
2957 BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(mallocFn, true);
2958 doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args, false);
2962 /// visitFreeInst - Free instructions are code gen'd to call the free libc
2965 void ISel::visitFreeInst(FreeInst &I) {
2966 std::vector<ValueRecord> Args;
2967 Args.push_back(ValueRecord(I.getOperand(0)));
2968 MachineInstr *TheCall =
2969 BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(freeFn, true);
2970 doCall(ValueRecord(0, Type::VoidTy), TheCall, Args, false);
2973 /// createPPC64ISelSimple - This pass converts an LLVM function into a machine
2974 /// code representation is a very simple peep-hole fashion.
2976 FunctionPass *llvm::createPPC64ISelSimple(TargetMachine &TM) {
2977 return new ISel(TM);