1 //===- PPC64InstrInfo.cpp - PowerPC64 Instruction Information ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "PPC64InstrInfo.h"
16 #include "PPC64GenInstrInfo.inc"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 PPC64InstrInfo::PPC64InstrInfo()
22 : TargetInstrInfo(PPC64Insts, sizeof(PPC64Insts)/sizeof(PPC64Insts[0])) { }
24 bool PPC64InstrInfo::isMoveInstr(const MachineInstr& MI,
26 unsigned& destReg) const {
27 MachineOpCode oc = MI.getOpcode();
28 if (oc == PPC::OR) { // or r1, r2, r2
29 assert(MI.getNumOperands() == 3 &&
30 MI.getOperand(0).isRegister() &&
31 MI.getOperand(1).isRegister() &&
32 MI.getOperand(2).isRegister() &&
33 "invalid PPC OR instruction!");
34 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
35 sourceReg = MI.getOperand(1).getReg();
36 destReg = MI.getOperand(0).getReg();
39 } else if (oc == PPC::ADDI) { // addi r1, r2, 0
40 assert(MI.getNumOperands() == 3 &&
41 MI.getOperand(0).isRegister() &&
42 MI.getOperand(2).isImmediate() &&
43 "invalid PPC ADDI instruction!");
44 if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImmedValue()==0) {
45 sourceReg = MI.getOperand(1).getReg();
46 destReg = MI.getOperand(0).getReg();
49 } else if (oc == PPC::FMR) { // fmr r1, r2
50 assert(MI.getNumOperands() == 2 &&
51 MI.getOperand(0).isRegister() &&
52 MI.getOperand(1).isRegister() &&
53 "invalid PPC FMR instruction");
54 sourceReg = MI.getOperand(1).getReg();
55 destReg = MI.getOperand(0).getReg();