1 //===- PPC64RegisterInfo.cpp - PowerPC64 Register Information ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PowerPC64 implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "PowerPCInstrBuilder.h"
17 #include "PPC64RegisterInfo.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Type.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/Target/TargetFrameInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/ADT/STLExtras.h"
35 // Switch toggling compilation for AIX
36 extern cl::opt<bool> AIX;
39 PPC64RegisterInfo::PPC64RegisterInfo()
40 : PPC64GenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP) {
41 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
42 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
43 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
44 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
45 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
46 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
47 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
48 ImmToIdxMap[PPC::ADDI] = PPC::ADD;
51 static const TargetRegisterClass *getClass(unsigned SrcReg) {
52 if (PPC64::FPRCRegisterClass->contains(SrcReg))
53 return PPC64::FPRCRegisterClass;
54 assert(PPC64::GPRCRegisterClass->contains(SrcReg) && "Reg not FPR or GPR");
55 return PPC64::GPRCRegisterClass;
58 static unsigned getIdx(const TargetRegisterClass *RC) {
59 if (RC == PPC64::GPRCRegisterClass) {
60 switch (RC->getSize()) {
61 default: assert(0 && "Invalid data size!");
67 } else if (RC == PPC64::FPRCRegisterClass) {
68 switch (RC->getSize()) {
69 default: assert(0 && "Invalid data size!");
74 std::cerr << "Invalid register class to getIdx()!\n";
79 PPC64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
80 MachineBasicBlock::iterator MI,
81 unsigned SrcReg, int FrameIdx) const {
82 static const unsigned Opcode[] = {
83 PPC::STB, PPC::STH, PPC::STW, PPC::STD, PPC::STFS, PPC::STFD
85 unsigned OC = Opcode[getIdx(getClass(SrcReg))];
86 if (SrcReg == PPC::LR) {
87 BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11).addReg(PPC::LR);
88 BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
89 addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx);
91 BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
92 addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(SrcReg),FrameIdx);
97 PPC64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
98 MachineBasicBlock::iterator MI,
99 unsigned DestReg, int FrameIdx) const{
100 static const unsigned Opcode[] = {
101 PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LD, PPC::LFS, PPC::LFD
103 unsigned OC = Opcode[getIdx(getClass(DestReg))];
104 if (DestReg == PPC::LR) {
105 BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
106 addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx);
107 BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
109 BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
110 addFrameReference(BuildMI(MBB, MI, OC, 2, DestReg), FrameIdx);
114 void PPC64RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
115 MachineBasicBlock::iterator MI,
116 unsigned DestReg, unsigned SrcReg,
117 const TargetRegisterClass *RC) const {
120 if (RC == PPC64::GPRCRegisterClass) {
121 BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
122 } else if (RC == PPC64::FPRCRegisterClass) {
123 BuildMI(MBB, MI, PPC::FMR, 1, DestReg).addReg(SrcReg);
125 std::cerr << "Attempt to copy register that is not GPR or FPR";
130 //===----------------------------------------------------------------------===//
131 // Stack Frame Processing methods
132 //===----------------------------------------------------------------------===//
134 // hasFP - Return true if the specified function should have a dedicated frame
135 // pointer register. This is true if the function has variable sized allocas or
136 // if frame pointer elimination is disabled.
138 static bool hasFP(MachineFunction &MF) {
139 MachineFrameInfo *MFI = MF.getFrameInfo();
140 return MFI->hasVarSizedObjects();
143 void PPC64RegisterInfo::
144 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
145 MachineBasicBlock::iterator I) const {
147 // If we have a frame pointer, convert as follows:
148 // ADJCALLSTACKDOWN -> addi, r1, r1, -amount
149 // ADJCALLSTACKUP -> addi, r1, r1, amount
150 MachineInstr *Old = I;
151 unsigned Amount = Old->getOperand(0).getImmedValue();
153 // We need to keep the stack aligned properly. To do this, we round the
154 // amount of space needed for the outgoing arguments up to the next
155 // alignment boundary.
156 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
157 Amount = (Amount+Align-1)/Align*Align;
159 // Replace the pseudo instruction with a new instruction...
160 if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
161 MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
164 assert(Old->getOpcode() == PPC::ADJCALLSTACKUP);
165 MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
174 PPC64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
176 MachineInstr &MI = *II;
177 MachineBasicBlock &MBB = *MI.getParent();
178 MachineFunction &MF = *MBB.getParent();
180 while (!MI.getOperand(i).isFrameIndex()) {
182 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
185 int FrameIndex = MI.getOperand(i).getFrameIndex();
187 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
188 MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1);
190 // Take into account whether it's an add or mem instruction
191 unsigned OffIdx = (i == 2) ? 1 : 2;
193 // Now add the frame object offset to the offset from r1.
194 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
195 MI.getOperand(OffIdx).getImmedValue();
197 // If we're not using a Frame Pointer that has been set to the value of the
198 // SP before having the stack size subtracted from it, then add the stack size
199 // to Offset to get the correct offset.
200 Offset += MF.getFrameInfo()->getStackSize();
202 if (Offset > 32767 || Offset < -32768) {
203 // Insert a set of r0 with the full offset value before the ld, st, or add
204 MachineBasicBlock *MBB = MI.getParent();
205 MBB->insert(II, BuildMI(PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16));
206 MBB->insert(II, BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
208 // convert into indexed form of the instruction
209 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
210 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
212 const_cast<std::map<unsigned, unsigned>& >(ImmToIdxMap)[MI.getOpcode()];
213 assert(NewOpcode && "No indexed form of load or store available!");
214 MI.setOpcode(NewOpcode);
215 MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
216 MI.SetMachineOperandReg(2, PPC::R0);
218 MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed,
224 void PPC64RegisterInfo::emitPrologue(MachineFunction &MF) const {
225 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
226 MachineBasicBlock::iterator MBBI = MBB.begin();
227 MachineFrameInfo *MFI = MF.getFrameInfo();
230 // Get the number of bytes to allocate from the FrameInfo
231 unsigned NumBytes = MFI->getStackSize();
233 // If we have calls, we cannot use the red zone to store callee save registers
234 // and we must set up a stack frame, so calculate the necessary size here.
235 if (MFI->hasCalls()) {
236 // We reserve argument space for call sites in the function immediately on
237 // entry to the current function. This eliminates the need for add/sub
238 // brackets around call sites.
239 NumBytes += MFI->getMaxCallFrameSize();
242 // Do we need to allocate space on the stack?
243 if (NumBytes == 0) return;
245 // Add the size of R1 to NumBytes size for the store of R1 to the bottom
246 // of the stack and round the size to a multiple of the alignment.
247 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
248 unsigned GPRSize = getSpillSize(PPC::R1)/8;
249 unsigned Size = hasFP(MF) ? GPRSize + GPRSize : GPRSize;
250 NumBytes = (NumBytes+Size+Align-1)/Align*Align;
252 // Update frame info to pretend that this is part of the stack...
253 MFI->setStackSize(NumBytes);
255 // adjust stack pointer: r1 -= numbytes
256 if (NumBytes <= 32768) {
257 MI=BuildMI(PPC::STDU,3).addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1);
258 MBB.insert(MBBI, MI);
260 int NegNumbytes = -NumBytes;
261 MI = BuildMI(PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16);
262 MBB.insert(MBBI, MI);
263 MI = BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
264 .addImm(NegNumbytes & 0xFFFF);
265 MBB.insert(MBBI, MI);
266 MI = BuildMI(PPC::STDUX, 3).addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
267 MBB.insert(MBBI, MI);
271 MI = BuildMI(PPC::STD, 3).addReg(PPC::R31).addSImm(GPRSize).addReg(PPC::R1);
272 MBB.insert(MBBI, MI);
273 MI = BuildMI(PPC::OR, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
274 MBB.insert(MBBI, MI);
278 void PPC64RegisterInfo::emitEpilogue(MachineFunction &MF,
279 MachineBasicBlock &MBB) const {
280 const MachineFrameInfo *MFI = MF.getFrameInfo();
281 MachineBasicBlock::iterator MBBI = prior(MBB.end());
283 assert(MBBI->getOpcode() == PPC::BLR &&
284 "Can only insert epilog into returning blocks");
286 // Get the number of bytes allocated from the FrameInfo...
287 unsigned NumBytes = MFI->getStackSize();
291 MI = BuildMI(PPC::OR, 2, PPC::R1).addReg(PPC::R31).addReg(PPC::R31);
292 MBB.insert(MBBI, MI);
293 MI = BuildMI(PPC::LD, 2, PPC::R31).addSImm(4).addReg(PPC::R31);
294 MBB.insert(MBBI, MI);
296 MI = BuildMI(PPC::LD, 2, PPC::R1).addSImm(0).addReg(PPC::R1);
297 MBB.insert(MBBI, MI);
301 #include "PPC64GenRegisterInfo.inc"
303 const TargetRegisterClass*
304 PPC64RegisterInfo::getRegClassForType(const Type* Ty) const {
305 switch (Ty->getTypeID()) {
306 default: assert(0 && "Invalid type to getClass!");
308 case Type::SByteTyID:
309 case Type::UByteTyID:
310 case Type::ShortTyID:
311 case Type::UShortTyID:
314 case Type::PointerTyID:
316 case Type::ULongTyID: return &GPRCInstance;
318 case Type::FloatTyID:
319 case Type::DoubleTyID: return &FPRCInstance;