1 //===-- PPCCTRLoops.cpp - Identify and generate CTR loops -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass identifies loops where we can generate the PPC branch instructions
11 // that decrement and test the count register (CTR) (bdnz and friends).
12 // This pass is based on the HexagonHardwareLoops pass.
14 // The pattern that defines the induction variable can changed depending on
15 // prior optimizations. For example, the IndVarSimplify phase run by 'opt'
16 // normalizes induction variables, and the Loop Strength Reduction pass
17 // run by 'llc' may also make changes to the induction variable.
18 // The pattern detected by this phase is due to running Strength Reduction.
20 // Criteria for CTR loops:
21 // - Countable loops (w/ ind. var for a trip count)
22 // - Assumes loops are normalized by IndVarSimplify
23 // - Try inner-most loops first
24 // - No nested CTR loops.
25 // - No function calls in loops.
27 // Note: As with unconverted loops, PPCBranchSelector must be run after this
28 // pass in order to convert long-displacement jumps into jump pairs.
30 //===----------------------------------------------------------------------===//
32 #define DEBUG_TYPE "ctrloops"
34 #include "PPCTargetMachine.h"
35 #include "llvm/Constants.h"
36 #include "llvm/PassSupport.h"
37 #include "llvm/ADT/DenseMap.h"
38 #include "llvm/ADT/Statistic.h"
39 #include "llvm/CodeGen/Passes.h"
40 #include "llvm/CodeGen/MachineDominators.h"
41 #include "llvm/CodeGen/MachineFunction.h"
42 #include "llvm/CodeGen/MachineFunctionPass.h"
43 #include "llvm/CodeGen/MachineInstrBuilder.h"
44 #include "llvm/CodeGen/MachineLoopInfo.h"
45 #include "llvm/CodeGen/MachineRegisterInfo.h"
46 #include "llvm/CodeGen/RegisterScavenging.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include "llvm/Target/TargetInstrInfo.h"
54 STATISTIC(NumCTRLoops, "Number of loops converted to CTR loops");
58 struct PPCCTRLoops : public MachineFunctionPass {
60 MachineRegisterInfo *MRI;
61 const TargetInstrInfo *TII;
64 static char ID; // Pass identification, replacement for typeid
66 PPCCTRLoops() : MachineFunctionPass(ID) {}
68 virtual bool runOnMachineFunction(MachineFunction &MF);
70 const char *getPassName() const { return "PPC CTR Loops"; }
72 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
74 AU.addRequired<MachineDominatorTree>();
75 AU.addPreserved<MachineDominatorTree>();
76 AU.addRequired<MachineLoopInfo>();
77 AU.addPreserved<MachineLoopInfo>();
78 MachineFunctionPass::getAnalysisUsage(AU);
82 /// getCanonicalInductionVariable - Check to see if the loop has a canonical
83 /// induction variable.
84 /// Should be defined in MachineLoop. Based upon version in class Loop.
85 MachineInstr *getCanonicalInductionVariable(MachineLoop *L,
86 MachineInstr *&IOp) const;
88 /// getTripCount - Return a loop-invariant LLVM register indicating the
89 /// number of times the loop will be executed. If the trip-count cannot
90 /// be determined, this return null.
91 CountValue *getTripCount(MachineLoop *L, bool &WordCmp,
92 SmallVector<MachineInstr *, 2> &OldInsts) const;
94 /// isInductionOperation - Return true if the instruction matches the
95 /// pattern for an opertion that defines an induction variable.
96 bool isInductionOperation(const MachineInstr *MI, unsigned IVReg) const;
98 /// isInvalidOperation - Return true if the instruction is not valid within
100 bool isInvalidLoopOperation(const MachineInstr *MI) const;
102 /// containsInavlidInstruction - Return true if the loop contains an
103 /// instruction that inhibits using the CTR loop.
104 bool containsInvalidInstruction(MachineLoop *L) const;
106 /// converToCTRLoop - Given a loop, check if we can convert it to a
107 /// CTR loop. If so, then perform the conversion and return true.
108 bool convertToCTRLoop(MachineLoop *L);
110 /// isDead - Return true if the instruction is now dead.
111 bool isDead(const MachineInstr *MI,
112 SmallVector<MachineInstr *, 1> &DeadPhis) const;
114 /// removeIfDead - Remove the instruction if it is now dead.
115 void removeIfDead(MachineInstr *MI);
118 char PPCCTRLoops::ID = 0;
121 // CountValue class - Abstraction for a trip count of a loop. A
122 // smaller vesrsion of the MachineOperand class without the concerns
123 // of changing the operand representation.
126 enum CountValueType {
135 Values(unsigned r) : RegNum(r) {}
136 Values(int64_t i) : ImmVal(i) {}
141 CountValue(unsigned r, bool neg) : Kind(CV_Register), Contents(r),
143 explicit CountValue(int64_t i) : Kind(CV_Immediate), Contents(i),
145 CountValueType getType() const { return Kind; }
146 bool isReg() const { return Kind == CV_Register; }
147 bool isImm() const { return Kind == CV_Immediate; }
148 bool isNeg() const { return isNegative; }
150 unsigned getReg() const {
151 assert(isReg() && "Wrong CountValue accessor");
152 return Contents.RegNum;
154 void setReg(unsigned Val) {
155 Contents.RegNum = Val;
157 int64_t getImm() const {
158 assert(isImm() && "Wrong CountValue accessor");
160 return -Contents.ImmVal;
162 return Contents.ImmVal;
164 void setImm(int64_t Val) {
165 Contents.ImmVal = Val;
168 void print(raw_ostream &OS, const TargetMachine *TM = 0) const {
169 if (isReg()) { OS << PrintReg(getReg()); }
170 if (isImm()) { OS << getImm(); }
173 } // end anonymous namespace
176 /// isCompareEquals - Returns true if the instruction is a compare equals
177 /// instruction with an immediate operand.
178 static bool isCompareEqualsImm(const MachineInstr *MI, bool &WordCmp) {
179 if (MI->getOpcode() == PPC::CMPWI || MI->getOpcode() == PPC::CMPLWI) {
182 } else if (MI->getOpcode() == PPC::CMPDI || MI->getOpcode() == PPC::CMPLDI) {
191 /// createPPCCTRLoops - Factory for creating
192 /// the CTR loop phase.
193 FunctionPass *llvm::createPPCCTRLoops() {
194 return new PPCCTRLoops();
198 bool PPCCTRLoops::runOnMachineFunction(MachineFunction &MF) {
199 DEBUG(dbgs() << "********* PPC CTR Loops *********\n");
201 bool Changed = false;
203 // get the loop information
204 MLI = &getAnalysis<MachineLoopInfo>();
205 // get the register information
206 MRI = &MF.getRegInfo();
207 // the target specific instructio info.
208 TII = MF.getTarget().getInstrInfo();
210 for (MachineLoopInfo::iterator I = MLI->begin(), E = MLI->end();
213 if (!L->getParentLoop()) {
214 Changed |= convertToCTRLoop(L);
221 /// getCanonicalInductionVariable - Check to see if the loop has a canonical
222 /// induction variable. We check for a simple recurrence pattern - an
223 /// integer recurrence that decrements by one each time through the loop and
224 /// ends at zero. If so, return the phi node that corresponds to it.
226 /// Based upon the similar code in LoopInfo except this code is specific to
228 /// This method assumes that the IndVarSimplify pass has been run by 'opt'.
231 *PPCCTRLoops::getCanonicalInductionVariable(MachineLoop *L,
232 MachineInstr *&IOp) const {
233 MachineBasicBlock *TopMBB = L->getTopBlock();
234 MachineBasicBlock::pred_iterator PI = TopMBB->pred_begin();
235 assert(PI != TopMBB->pred_end() &&
236 "Loop must have more than one incoming edge!");
237 MachineBasicBlock *Backedge = *PI++;
238 if (PI == TopMBB->pred_end()) return 0; // dead loop
239 MachineBasicBlock *Incoming = *PI++;
240 if (PI != TopMBB->pred_end()) return 0; // multiple backedges?
242 // make sure there is one incoming and one backedge and determine which
244 if (L->contains(Incoming)) {
245 if (L->contains(Backedge))
247 std::swap(Incoming, Backedge);
248 } else if (!L->contains(Backedge))
251 // Loop over all of the PHI nodes, looking for a canonical induction variable:
252 // - The PHI node is "reg1 = PHI reg2, BB1, reg3, BB2".
253 // - The recurrence comes from the backedge.
254 // - the definition is an induction operatio.n
255 for (MachineBasicBlock::iterator I = TopMBB->begin(), E = TopMBB->end();
256 I != E && I->isPHI(); ++I) {
257 MachineInstr *MPhi = &*I;
258 unsigned DefReg = MPhi->getOperand(0).getReg();
259 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) {
260 // Check each operand for the value from the backedge.
261 MachineBasicBlock *MBB = MPhi->getOperand(i+1).getMBB();
262 if (L->contains(MBB)) { // operands comes from the backedge
263 // Check if the definition is an induction operation.
264 MachineInstr *DI = MRI->getVRegDef(MPhi->getOperand(i).getReg());
265 if (isInductionOperation(DI, DefReg)) {
275 /// getTripCount - Return a loop-invariant LLVM value indicating the
276 /// number of times the loop will be executed. The trip count can
277 /// be either a register or a constant value. If the trip-count
278 /// cannot be determined, this returns null.
280 /// We find the trip count from the phi instruction that defines the
281 /// induction variable. We follow the links to the CMP instruction
282 /// to get the trip count.
284 /// Based upon getTripCount in LoopInfo.
286 CountValue *PPCCTRLoops::getTripCount(MachineLoop *L, bool &WordCmp,
287 SmallVector<MachineInstr *, 2> &OldInsts) const {
288 // Check that the loop has a induction variable.
290 MachineInstr *IV_Inst = getCanonicalInductionVariable(L, IOp);
291 if (IV_Inst == 0) return 0;
293 // Canonical loops will end with a 'cmpwi/cmpdi cr, IV, Imm',
294 // if Imm is 0, get the count from the PHI opnd
295 // if Imm is -M, than M is the count
296 // Otherwise, Imm is the count
297 MachineOperand *IV_Opnd;
298 const MachineOperand *InitialValue;
299 if (!L->contains(IV_Inst->getOperand(2).getMBB())) {
300 InitialValue = &IV_Inst->getOperand(1);
301 IV_Opnd = &IV_Inst->getOperand(3);
303 InitialValue = &IV_Inst->getOperand(3);
304 IV_Opnd = &IV_Inst->getOperand(1);
307 // Look for the cmp instruction to determine if we
308 // can get a useful trip count. The trip count can
309 // be either a register or an immediate. The location
310 // of the value depends upon the type (reg or imm).
311 while ((IV_Opnd = IV_Opnd->getNextOperandForReg())) {
312 MachineInstr *MI = IV_Opnd->getParent();
313 if (L->contains(MI) && isCompareEqualsImm(MI, WordCmp)) {
314 OldInsts.push_back(MI);
315 OldInsts.push_back(IOp);
317 const MachineOperand &MO = MI->getOperand(2);
318 assert(MO.isImm() && "IV Cmp Operand should be an immediate");
319 int64_t ImmVal = MO.getImm();
321 const MachineInstr *IV_DefInstr = MRI->getVRegDef(IV_Opnd->getReg());
322 assert(L->contains(IV_DefInstr->getParent()) &&
323 "IV definition should occurs in loop");
324 int64_t iv_value = IV_DefInstr->getOperand(2).getImm();
327 // Make sure the induction variable changes by one on each iteration.
328 if (iv_value != 1 && iv_value != -1) {
331 return new CountValue(InitialValue->getReg(), iv_value > 0);
333 assert(InitialValue->isReg() && "Expecting register for init value");
334 const MachineInstr *DefInstr = MRI->getVRegDef(InitialValue->getReg());
336 // Here we need to look for an immediate load (an li or lis/ori pair).
337 if (DefInstr && (DefInstr->getOpcode() == PPC::ORI8 ||
338 DefInstr->getOpcode() == PPC::ORI)) {
339 int64_t start = DefInstr->getOperand(2).getImm();
340 const MachineInstr *DefInstr2 =
341 MRI->getVRegDef(DefInstr->getOperand(0).getReg());
342 if (DefInstr2 && (DefInstr2->getOpcode() == PPC::LIS8 ||
343 DefInstr2->getOpcode() == PPC::LIS)) {
344 start |= DefInstr2->getOperand(1).getImm() << 16;
346 int64_t count = ImmVal - start;
347 if ((count % iv_value) != 0) {
350 return new CountValue(count/iv_value);
352 } else if (DefInstr && (DefInstr->getOpcode() == PPC::LI8 ||
353 DefInstr->getOpcode() == PPC::LI)) {
354 int64_t count = ImmVal - DefInstr->getOperand(1).getImm();
355 if ((count % iv_value) != 0) {
358 return new CountValue(count/iv_value);
366 /// isInductionOperation - return true if the operation is matches the
367 /// pattern that defines an induction variable:
371 PPCCTRLoops::isInductionOperation(const MachineInstr *MI,
372 unsigned IVReg) const {
373 return ((MI->getOpcode() == PPC::ADDI || MI->getOpcode() == PPC::ADDI8) &&
374 MI->getOperand(1).getReg() == IVReg);
377 /// isInvalidOperation - Return true if the operation is invalid within
380 PPCCTRLoops::isInvalidLoopOperation(const MachineInstr *MI) const {
382 // call is not allowed because the callee may use a CTR loop
383 if (MI->getDesc().isCall()) {
386 // check if the instruction defines a CTR loop register
387 // (this will also catch nested CTR loops)
388 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
389 const MachineOperand &MO = MI->getOperand(i);
390 if (MO.isReg() && MO.isDef() &&
391 (MO.getReg() == PPC::CTR || MO.getReg() == PPC::CTR8)) {
398 /// containsInvalidInstruction - Return true if the loop contains
399 /// an instruction that inhibits the use of the CTR loop function.
401 bool PPCCTRLoops::containsInvalidInstruction(MachineLoop *L) const {
402 const std::vector<MachineBasicBlock*> Blocks = L->getBlocks();
403 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
404 MachineBasicBlock *MBB = Blocks[i];
405 for (MachineBasicBlock::iterator
406 MII = MBB->begin(), E = MBB->end(); MII != E; ++MII) {
407 const MachineInstr *MI = &*MII;
408 if (isInvalidLoopOperation(MI)) {
416 /// isDead returns true if the instruction is dead
417 /// (this was essentially copied from DeadMachineInstructionElim::isDead, but
418 /// with special cases for inline asm, physical registers and instructions with
419 /// side effects removed)
420 bool PPCCTRLoops::isDead(const MachineInstr *MI,
421 SmallVector<MachineInstr *, 1> &DeadPhis) const {
422 // Examine each operand.
423 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
424 const MachineOperand &MO = MI->getOperand(i);
425 if (MO.isReg() && MO.isDef()) {
426 unsigned Reg = MO.getReg();
427 if (!MRI->use_nodbg_empty(Reg)) {
428 // This instruction has users, but if the only user is the phi node for the
429 // parent block, and the only use of that phi node is this instruction, then
430 // this instruction is dead: both it (and the phi node) can be removed.
431 MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg);
432 if (llvm::next(I) == MRI->use_end() &&
433 I.getOperand().getParent()->isPHI()) {
434 MachineInstr *OnePhi = I.getOperand().getParent();
436 for (unsigned j = 0, f = OnePhi->getNumOperands(); j != f; ++j) {
437 const MachineOperand &OPO = OnePhi->getOperand(j);
438 if (OPO.isReg() && OPO.isDef()) {
439 unsigned OPReg = OPO.getReg();
441 MachineRegisterInfo::use_iterator nextJ;
442 for (MachineRegisterInfo::use_iterator J = MRI->use_begin(OPReg),
443 E = MRI->use_end(); J!=E; J=nextJ) {
444 nextJ = llvm::next(J);
445 MachineOperand& Use = J.getOperand();
446 MachineInstr *UseMI = Use.getParent();
449 // The phi node has a user that is not MI, bail...
456 DeadPhis.push_back(OnePhi);
458 // This def has a non-debug use. Don't delete the instruction!
465 // If there are no defs with uses, the instruction is dead.
469 void PPCCTRLoops::removeIfDead(MachineInstr *MI) {
470 // This procedure was essentially copied from DeadMachineInstructionElim
472 SmallVector<MachineInstr *, 1> DeadPhis;
473 if (isDead(MI, DeadPhis)) {
474 DEBUG(dbgs() << "CTR looping will remove: " << *MI);
476 // It is possible that some DBG_VALUE instructions refer to this
477 // instruction. Examine each def operand for such references;
478 // if found, mark the DBG_VALUE as undef (but don't delete it).
479 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
480 const MachineOperand &MO = MI->getOperand(i);
481 if (!MO.isReg() || !MO.isDef())
483 unsigned Reg = MO.getReg();
484 MachineRegisterInfo::use_iterator nextI;
485 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg),
486 E = MRI->use_end(); I!=E; I=nextI) {
487 nextI = llvm::next(I); // I is invalidated by the setReg
488 MachineOperand& Use = I.getOperand();
489 MachineInstr *UseMI = Use.getParent();
492 if (Use.isDebug()) // this might also be a instr -> phi -> instr case
493 // which can also be removed.
494 UseMI->getOperand(0).setReg(0U);
498 MI->eraseFromParent();
499 for (unsigned i = 0; i < DeadPhis.size(); ++i) {
500 DeadPhis[i]->eraseFromParent();
505 /// converToCTRLoop - check if the loop is a candidate for
506 /// converting to a CTR loop. If so, then perform the
509 /// This function works on innermost loops first. A loop can
510 /// be converted if it is a counting loop; either a register
511 /// value or an immediate.
513 /// The code makes several assumptions about the representation
514 /// of the loop in llvm.
515 bool PPCCTRLoops::convertToCTRLoop(MachineLoop *L) {
516 bool Changed = false;
517 // Process nested loops first.
518 for (MachineLoop::iterator I = L->begin(), E = L->end(); I != E; ++I) {
519 Changed |= convertToCTRLoop(*I);
521 // If a nested loop has been converted, then we can't convert this loop.
527 SmallVector<MachineInstr *, 2> OldInsts;
528 // Are we able to determine the trip count for the loop?
529 CountValue *TripCount = getTripCount(L, WordCmp, OldInsts);
530 if (TripCount == 0) {
531 DEBUG(dbgs() << "failed to get trip count!\n");
534 // Does the loop contain any invalid instructions?
535 if (containsInvalidInstruction(L)) {
538 MachineBasicBlock *Preheader = L->getLoopPreheader();
539 // No preheader means there's not place for the loop instr.
540 if (Preheader == 0) {
543 MachineBasicBlock::iterator InsertPos = Preheader->getFirstTerminator();
546 if (InsertPos != Preheader->end())
547 dl = InsertPos->getDebugLoc();
549 MachineBasicBlock *LastMBB = L->getExitingBlock();
550 // Don't generate CTR loop if the loop has more than one exit.
554 MachineBasicBlock::iterator LastI = LastMBB->getFirstTerminator();
556 // Determine the loop start.
557 MachineBasicBlock *LoopStart = L->getTopBlock();
558 if (L->getLoopLatch() != LastMBB) {
559 // When the exit and latch are not the same, use the latch block as the
561 // The loop start address is used only after the 1st iteration, and the loop
562 // latch may contains instrs. that need to be executed after the 1st iter.
563 LoopStart = L->getLoopLatch();
564 // Make sure the latch is a successor of the exit, otherwise it won't work.
565 if (!LastMBB->isSuccessor(LoopStart)) {
570 // Convert the loop to a CTR loop
571 DEBUG(dbgs() << "Change to CTR loop at "; L->dump());
573 MachineFunction *MF = LastMBB->getParent();
574 const PPCSubtarget &Subtarget = MF->getTarget().getSubtarget<PPCSubtarget>();
575 bool isPPC64 = Subtarget.isPPC64();
578 if (TripCount->isReg()) {
579 // Create a copy of the loop count register.
580 const TargetRegisterClass *RC =
581 MF->getRegInfo().getRegClass(TripCount->getReg());
582 CountReg = MF->getRegInfo().createVirtualRegister(RC);
583 BuildMI(*Preheader, InsertPos, dl,
584 TII->get(TargetOpcode::COPY), CountReg).addReg(TripCount->getReg());
585 if (TripCount->isNeg()) {
586 unsigned CountReg1 = CountReg;
587 CountReg = MF->getRegInfo().createVirtualRegister(RC);
588 BuildMI(*Preheader, InsertPos, dl,
589 TII->get(isPPC64 ? PPC::NEG8 : PPC::NEG),
590 CountReg).addReg(CountReg1);
593 // On a 64-bit system, if the original comparison was only 32-bit, then
594 // mask out the higher-order part of the count.
595 if (isPPC64 && WordCmp) {
596 unsigned CountReg1 = CountReg;
597 CountReg = MF->getRegInfo().createVirtualRegister(RC);
598 BuildMI(*Preheader, InsertPos, dl,
599 TII->get(PPC::RLDICL), CountReg).addReg(CountReg1
600 ).addImm(0).addImm(32);
603 assert(TripCount->isImm() && "Expecting immedate vaule for trip count");
604 // Put the trip count in a register for transfer into the count register.
605 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
606 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
607 const TargetRegisterClass *RC = isPPC64 ? G8RC : GPRC;
609 int64_t CountImm = TripCount->getImm();
610 if (TripCount->isNeg())
611 CountImm = -CountImm;
613 CountReg = MF->getRegInfo().createVirtualRegister(RC);
614 if (CountImm > 0xFFFF) {
615 BuildMI(*Preheader, InsertPos, dl,
616 TII->get(isPPC64 ? PPC::LIS8 : PPC::LIS),
617 CountReg).addImm(CountImm >> 16);
618 unsigned CountReg1 = CountReg;
619 CountReg = MF->getRegInfo().createVirtualRegister(RC);
620 BuildMI(*Preheader, InsertPos, dl,
621 TII->get(isPPC64 ? PPC::ORI8 : PPC::ORI),
622 CountReg).addReg(CountReg1).addImm(CountImm & 0xFFFF);
624 BuildMI(*Preheader, InsertPos, dl,
625 TII->get(isPPC64 ? PPC::LI8 : PPC::LI),
626 CountReg).addImm(CountImm);
630 // Add the mtctr instruction to the beginning of the loop.
631 BuildMI(*Preheader, InsertPos, dl,
632 TII->get(isPPC64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(CountReg,
633 TripCount->isImm() ? RegState::Kill : 0);
635 // Make sure the loop start always has a reference in the CFG. We need to
636 // create a BlockAddress operand to get this mechanism to work both the
637 // MachineBasicBlock and BasicBlock objects need the flag set.
638 LoopStart->setHasAddressTaken();
639 // This line is needed to set the hasAddressTaken flag on the BasicBlock
641 BlockAddress::get(const_cast<BasicBlock *>(LoopStart->getBasicBlock()));
643 // Replace the loop branch with a bdnz instruction.
644 dl = LastI->getDebugLoc();
645 const std::vector<MachineBasicBlock*> Blocks = L->getBlocks();
646 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
647 MachineBasicBlock *MBB = Blocks[i];
648 if (MBB != Preheader)
649 MBB->addLiveIn(isPPC64 ? PPC::CTR8 : PPC::CTR);
652 // The loop ends with either:
653 // - a conditional branch followed by an unconditional branch, or
654 // - a conditional branch to the loop start.
655 assert(LastI->getOpcode() == PPC::BCC &&
656 "loop end must start with a BCC instruction");
657 // Either the BCC branches to the beginning of the loop, or it
658 // branches out of the loop and there is an unconditional branch
659 // to the start of the loop.
660 MachineBasicBlock *BranchTarget = LastI->getOperand(2).getMBB();
661 BuildMI(*LastMBB, LastI, dl,
662 TII->get((BranchTarget == LoopStart) ?
663 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
664 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(BranchTarget);
666 // Conditional branch; just delete it.
667 LastMBB->erase(LastI);
671 // The induction operation (add) and the comparison (cmpwi) may now be
672 // unneeded. If these are unneeded, then remove them.
673 for (unsigned i = 0; i < OldInsts.size(); ++i)
674 removeIfDead(OldInsts[i]);