1 //===- PPCCallingConv.td - Calling Conventions for PowerPC -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This describes the calling conventions for the PowerPC 32- and 64-bit
13 //===----------------------------------------------------------------------===//
15 /// CCIfSubtarget - Match if the current subtarget has a feature F.
16 class CCIfSubtarget<string F, CCAction A>
17 : CCIf<!strconcat("static_cast<const PPCSubtarget&>"
18 "(State.getMachineFunction().getSubtarget()).",
21 class CCIfNotSubtarget<string F, CCAction A>
22 : CCIf<!strconcat("!static_cast<const PPCSubtarget&>"
23 "(State.getMachineFunction().getSubtarget()).",
27 //===----------------------------------------------------------------------===//
28 // Return Value Calling Convention
29 //===----------------------------------------------------------------------===//
31 // PPC64 AnyReg return-value convention. No explicit register is specified for
32 // the return-value. The register allocator is allowed and expected to choose
35 // This calling convention is currently only supported by the stackmap and
36 // patchpoint intrinsics. All other uses will result in an assert on Debug
37 // builds. On Release builds we fallback to the PPC C calling convention.
38 def RetCC_PPC64_AnyReg : CallingConv<[
39 CCCustom<"CC_PPC_AnyReg_Error">
42 // Return-value convention for PowerPC
43 def RetCC_PPC : CallingConv<[
44 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_PPC64_AnyReg>>,
46 // On PPC64, integer return values are always promoted to i64
47 CCIfType<[i32, i1], CCIfSubtarget<"isPPC64()", CCPromoteToType<i64>>>,
48 CCIfType<[i1], CCIfNotSubtarget<"isPPC64()", CCPromoteToType<i32>>>,
50 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
51 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>,
52 CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,
54 // Floating point types returned as "direct" go into F1 .. F8; note that
55 // only the ELFv2 ABI fully utilizes all these registers.
56 CCIfType<[f32], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
57 CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
59 // QPX vectors are returned in QF1 and QF2.
60 CCIfType<[v4f64, v4f32, v4i1],
61 CCIfSubtarget<"hasQPX()", CCAssignToReg<[QF1, QF2]>>>,
63 // Vector types returned as "direct" go into V2 .. V9; note that only the
64 // ELFv2 ABI fully utilizes all these registers.
65 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32],
66 CCIfSubtarget<"hasAltivec()",
67 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>,
68 CCIfType<[v2f64, v2i64], CCIfSubtarget<"hasVSX()",
69 CCAssignToReg<[VSH2, VSH3, VSH4, VSH5, VSH6, VSH7, VSH8, VSH9]>>>
72 // No explicit register is specified for the AnyReg calling convention. The
73 // register allocator may assign the arguments to any free register.
75 // This calling convention is currently only supported by the stackmap and
76 // patchpoint intrinsics. All other uses will result in an assert on Debug
77 // builds. On Release builds we fallback to the PPC C calling convention.
78 def CC_PPC64_AnyReg : CallingConv<[
79 CCCustom<"CC_PPC_AnyReg_Error">
82 // Note that we don't currently have calling conventions for 64-bit
83 // PowerPC, but handle all the complexities of the ABI in the lowering
84 // logic. FIXME: See if the logic can be simplified with use of CCs.
85 // This may require some extensions to current table generation.
87 // Simple calling convention for 64-bit ELF PowerPC fast isel.
88 // Only handle ints and floats. All ints are promoted to i64.
89 // Vector types and quadword ints are not handled.
90 def CC_PPC64_ELF_FIS : CallingConv<[
91 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_PPC64_AnyReg>>,
93 CCIfType<[i1], CCPromoteToType<i64>>,
94 CCIfType<[i8], CCPromoteToType<i64>>,
95 CCIfType<[i16], CCPromoteToType<i64>>,
96 CCIfType<[i32], CCPromoteToType<i64>>,
97 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>,
98 CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>
101 // Simple return-value convention for 64-bit ELF PowerPC fast isel.
102 // All small ints are promoted to i64. Vector types, quadword ints,
103 // and multiple register returns are "supported" to avoid compile
104 // errors, but none are handled by the fast selector.
105 def RetCC_PPC64_ELF_FIS : CallingConv<[
106 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_PPC64_AnyReg>>,
108 CCIfType<[i1], CCPromoteToType<i64>>,
109 CCIfType<[i8], CCPromoteToType<i64>>,
110 CCIfType<[i16], CCPromoteToType<i64>>,
111 CCIfType<[i32], CCPromoteToType<i64>>,
112 CCIfType<[i64], CCAssignToReg<[X3, X4]>>,
113 CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,
114 CCIfType<[f32], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
115 CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
116 CCIfType<[v4f64, v4f32, v4i1],
117 CCIfSubtarget<"hasQPX()", CCAssignToReg<[QF1, QF2]>>>,
118 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32],
119 CCIfSubtarget<"hasAltivec()",
120 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>,
121 CCIfType<[v2f64, v2i64], CCIfSubtarget<"hasVSX()",
122 CCAssignToReg<[VSH2, VSH3, VSH4, VSH5, VSH6, VSH7, VSH8, VSH9]>>>
125 //===----------------------------------------------------------------------===//
126 // PowerPC System V Release 4 32-bit ABI
127 //===----------------------------------------------------------------------===//
129 def CC_PPC32_SVR4_Common : CallingConv<[
130 CCIfType<[i1], CCPromoteToType<i32>>,
132 // The ABI requires i64 to be passed in two adjacent registers with the first
133 // register having an odd register number.
134 CCIfType<[i32], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>,
136 // The first 8 integer arguments are passed in integer registers.
137 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
139 // Make sure the i64 words from a long double are either both passed in
140 // registers or both passed on the stack.
141 CCIfType<[f64], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignFPArgRegs">>>,
143 // FP values are passed in F1 - F8.
144 CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
146 // Split arguments have an alignment of 8 bytes on the stack.
147 CCIfType<[i32], CCIfSplit<CCAssignToStack<4, 8>>>,
149 CCIfType<[i32], CCAssignToStack<4, 4>>,
151 // Floats are stored in double precision format, thus they have the same
152 // alignment and size as doubles.
153 CCIfType<[f32,f64], CCAssignToStack<8, 8>>,
155 // QPX vectors that are stored in double precision need 32-byte alignment.
156 CCIfType<[v4f64, v4i1], CCAssignToStack<32, 32>>,
158 // Vectors get 16-byte stack slots that are 16-byte aligned.
159 CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64], CCAssignToStack<16, 16>>
162 // This calling convention puts vector arguments always on the stack. It is used
163 // to assign vector arguments which belong to the variable portion of the
164 // parameter list of a variable argument function.
165 def CC_PPC32_SVR4_VarArg : CallingConv<[
166 CCDelegateTo<CC_PPC32_SVR4_Common>
169 // In contrast to CC_PPC32_SVR4_VarArg, this calling convention first tries to
170 // put vector arguments in vector registers before putting them on the stack.
171 def CC_PPC32_SVR4 : CallingConv<[
172 // QPX vectors mirror the scalar FP convention.
173 CCIfType<[v4f64, v4f32, v4i1], CCIfSubtarget<"hasQPX()",
174 CCAssignToReg<[QF1, QF2, QF3, QF4, QF5, QF6, QF7, QF8]>>>,
176 // The first 12 Vector arguments are passed in AltiVec registers.
177 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32],
178 CCIfSubtarget<"hasAltivec()", CCAssignToReg<[V2, V3, V4, V5, V6, V7,
179 V8, V9, V10, V11, V12, V13]>>>,
180 CCIfType<[v2f64, v2i64], CCIfSubtarget<"hasVSX()",
181 CCAssignToReg<[VSH2, VSH3, VSH4, VSH5, VSH6, VSH7, VSH8, VSH9,
182 VSH10, VSH11, VSH12, VSH13]>>>,
184 CCDelegateTo<CC_PPC32_SVR4_Common>
187 // Helper "calling convention" to handle aggregate by value arguments.
188 // Aggregate by value arguments are always placed in the local variable space
189 // of the caller. This calling convention is only used to assign those stack
190 // offsets in the callers stack frame.
192 // Still, the address of the aggregate copy in the callers stack frame is passed
193 // in a GPR (or in the parameter list area if all GPRs are allocated) from the
194 // caller to the callee. The location for the address argument is assigned by
195 // the CC_PPC32_SVR4 calling convention.
197 // The only purpose of CC_PPC32_SVR4_Custom_Dummy is to skip arguments which are
198 // not passed by value.
200 def CC_PPC32_SVR4_ByVal : CallingConv<[
201 CCIfByVal<CCPassByVal<4, 4>>,
203 CCCustom<"CC_PPC32_SVR4_Custom_Dummy">
206 def CSR_Altivec : CalleeSavedRegs<(add V20, V21, V22, V23, V24, V25, V26, V27,
207 V28, V29, V30, V31)>;
209 def CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
210 R21, R22, R23, R24, R25, R26, R27, R28,
211 R29, R30, R31, F14, F15, F16, F17, F18,
212 F19, F20, F21, F22, F23, F24, F25, F26,
213 F27, F28, F29, F30, F31, CR2, CR3, CR4
216 def CSR_Darwin32_Altivec : CalleeSavedRegs<(add CSR_Darwin32, CSR_Altivec)>;
218 def CSR_SVR432 : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
219 R21, R22, R23, R24, R25, R26, R27, R28,
220 R29, R30, R31, F14, F15, F16, F17, F18,
221 F19, F20, F21, F22, F23, F24, F25, F26,
222 F27, F28, F29, F30, F31, CR2, CR3, CR4
225 def CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>;
227 def CSR_Darwin64 : CalleeSavedRegs<(add X13, X14, X15, X16, X17, X18, X19, X20,
228 X21, X22, X23, X24, X25, X26, X27, X28,
229 X29, X30, X31, F14, F15, F16, F17, F18,
230 F19, F20, F21, F22, F23, F24, F25, F26,
231 F27, F28, F29, F30, F31, CR2, CR3, CR4
234 def CSR_Darwin64_Altivec : CalleeSavedRegs<(add CSR_Darwin64, CSR_Altivec)>;
236 def CSR_SVR464 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20,
237 X21, X22, X23, X24, X25, X26, X27, X28,
238 X29, X30, X31, F14, F15, F16, F17, F18,
239 F19, F20, F21, F22, F23, F24, F25, F26,
240 F27, F28, F29, F30, F31, CR2, CR3, CR4
243 def CSR_SVR464_Altivec : CalleeSavedRegs<(add CSR_SVR464, CSR_Altivec)>;
245 def CSR_SVR464_R2 : CalleeSavedRegs<(add CSR_SVR464, X2)>;
247 def CSR_SVR464_R2_Altivec : CalleeSavedRegs<(add CSR_SVR464_Altivec, X2)>;
249 def CSR_NoRegs : CalleeSavedRegs<(add)>;
251 def CSR_64_AllRegs: CalleeSavedRegs<(add X0, (sequence "X%u", 3, 10),
252 (sequence "X%u", 14, 31),
253 (sequence "F%u", 0, 31),
254 (sequence "CR%u", 0, 7))>;
256 def CSR_64_AllRegs_Altivec : CalleeSavedRegs<(add CSR_64_AllRegs,
257 (sequence "V%u", 0, 31))>;
259 def CSR_64_AllRegs_VSX : CalleeSavedRegs<(add CSR_64_AllRegs_Altivec,
260 (sequence "VSL%u", 0, 31),
261 (sequence "VSH%u", 0, 31))>;