1 //===- PPCCallingConv.td - Calling Conventions for PowerPC -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This describes the calling conventions for the PowerPC 32- and 64-bit
13 //===----------------------------------------------------------------------===//
15 /// CCIfSubtarget - Match if the current subtarget has a feature F.
16 class CCIfSubtarget<string F, CCAction A>
17 : CCIf<!strconcat("State.getTarget().getSubtarget<PPCSubtarget>().", F), A>;
19 //===----------------------------------------------------------------------===//
20 // Return Value Calling Convention
21 //===----------------------------------------------------------------------===//
23 // Return-value convention for PowerPC
24 def RetCC_PPC : CallingConv<[
25 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
26 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>,
28 CCIfType<[f32], CCAssignToReg<[F1]>>,
29 CCIfType<[f64], CCAssignToReg<[F1, F2]>>,
31 // Vector types are always returned in V2.
32 CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToReg<[V2]>>
36 //===----------------------------------------------------------------------===//
37 // PowerPC Argument Calling Conventions
38 //===----------------------------------------------------------------------===//
40 def CC_PPC : CallingConv<[
41 // The first 8 integer arguments are passed in integer registers.
42 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
43 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>,
45 // Common sub-targets passes FP values in F1 - F13
47 CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8,F9,F10,F11,F12,F13]>>,
49 // The first 12 Vector arguments are passed in altivec registers.
50 CCIfType<[v16i8, v8i16, v4i32, v4f32],
51 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10,V11,V12,V13]>>
54 // Integer/FP values get stored in stack slots that are 8 bytes in size and
55 // 8-byte aligned if there are no more registers to hold them.
56 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
58 // Vectors get 16-byte stack slots that are 16-byte aligned.
59 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
60 CCAssignToStack<16, 16>>*/
65 //===----------------------------------------------------------------------===//
66 // PowerPC System V Release 4 ABI
67 //===----------------------------------------------------------------------===//
69 def CC_PPC_SVR4_Common : CallingConv<[
70 // The ABI requires i64 to be passed in two adjacent registers with the first
71 // register having an odd register number.
72 CCIfType<[i32], CCIfSplit<CCCustom<"CC_PPC_SVR4_Custom_AlignArgRegs">>>,
74 // The first 8 integer arguments are passed in integer registers.
75 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
77 // Make sure the i64 words from a long double are either both passed in
78 // registers or both passed on the stack.
79 CCIfType<[f64], CCIfSplit<CCCustom<"CC_PPC_SVR4_Custom_AlignFPArgRegs">>>,
81 // FP values are passed in F1 - F8.
82 CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
84 // Split arguments have an alignment of 8 bytes on the stack.
85 CCIfType<[i32], CCIfSplit<CCAssignToStack<4, 8>>>,
87 CCIfType<[i32], CCAssignToStack<4, 4>>,
89 // Floats are stored in double precision format, thus they have the same
90 // alignment and size as doubles.
91 CCIfType<[f32,f64], CCAssignToStack<8, 8>>,
93 // Vectors get 16-byte stack slots that are 16-byte aligned.
94 CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToStack<16, 16>>
97 // This calling convention puts vector arguments always on the stack. It is used
98 // to assign vector arguments which belong to the variable portion of the
99 // parameter list of a variable argument function.
100 def CC_PPC_SVR4_VarArg : CallingConv<[
101 CCDelegateTo<CC_PPC_SVR4_Common>
104 // In contrast to CC_PPC_SVR4_VarArg, this calling convention first tries to put
105 // vector arguments in vector registers before putting them on the stack.
106 def CC_PPC_SVR4 : CallingConv<[
107 // The first 12 Vector arguments are passed in AltiVec registers.
108 CCIfType<[v16i8, v8i16, v4i32, v4f32],
109 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13]>>,
111 CCDelegateTo<CC_PPC_SVR4_Common>
114 // Helper "calling convention" to handle aggregate by value arguments.
115 // Aggregate by value arguments are always placed in the local variable space
116 // of the caller. This calling convention is only used to assign those stack
117 // offsets in the callers stack frame.
119 // Still, the address of the aggregate copy in the callers stack frame is passed
120 // in a GPR (or in the parameter list area if all GPRs are allocated) from the
121 // caller to the callee. The location for the address argument is assigned by
122 // the CC_PPC_SVR4 calling convention.
124 // The only purpose of CC_PPC_SVR4_Custom_Dummy is to skip arguments which are
125 // not passed by value.
127 def CC_PPC_SVR4_ByVal : CallingConv<[
128 CCIfByVal<CCPassByVal<4, 4>>,
130 CCCustom<"CC_PPC_SVR4_Custom_Dummy">
133 def CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
134 R21, R22, R23, R24, R25, R26, R27, R28,
135 R29, R30, R31, F14, F15, F16, F17, F18,
136 F19, F20, F21, F22, F23, F24, F25, F26,
137 F27, F28, F29, F30, F31, CR2, CR3, CR4,
138 V20, V21, V22, V23, V24, V25, V26, V27,
139 V28, V29, V30, V31)>;
141 def CSR_SVR432 : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20, VRSAVE,
142 R21, R22, R23, R24, R25, R26, R27, R28,
143 R29, R30, R31, F14, F15, F16, F17, F18,
144 F19, F20, F21, F22, F23, F24, F25, F26,
145 F27, F28, F29, F30, F31, CR2, CR3, CR4,
146 V20, V21, V22, V23, V24, V25, V26, V27,
147 V28, V29, V30, V31)>;
149 def CSR_Darwin64 : CalleeSavedRegs<(add X13, X14, X15, X16, X17, X18, X19, X20,
150 X21, X22, X23, X24, X25, X26, X27, X28,
151 X29, X30, X31, F14, F15, F16, F17, F18,
152 F19, F20, F21, F22, F23, F24, F25, F26,
153 F27, F28, F29, F30, F31, CR2, CR3, CR4,
154 V20, V21, V22, V23, V24, V25, V26, V27,
155 V28, V29, V30, V31)>;
157 def CSR_SVR464 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20, VRSAVE,
158 X21, X22, X23, X24, X25, X26, X27, X28,
159 X29, X30, X31, F14, F15, F16, F17, F18,
160 F19, F20, F21, F22, F23, F24, F25, F26,
161 F27, F28, F29, F30, F31, CR2, CR3, CR4,
162 V20, V21, V22, V23, V24, V25, V26, V27,
163 V28, V29, V30, V31)>;