1 //===- PPCCallingConv.td - Calling Conventions for PowerPC -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This describes the calling conventions for the PowerPC 32- and 64-bit
13 //===----------------------------------------------------------------------===//
15 /// CCIfSubtarget - Match if the current subtarget has a feature F.
16 class CCIfSubtarget<string F, CCAction A>
17 : CCIf<!strconcat("State.getTarget().getSubtarget<PPCSubtarget>().", F), A>;
18 class CCIfNotSubtarget<string F, CCAction A>
19 : CCIf<!strconcat("!State.getTarget().getSubtarget<PPCSubtarget>().", F), A>;
21 //===----------------------------------------------------------------------===//
22 // Return Value Calling Convention
23 //===----------------------------------------------------------------------===//
25 // Return-value convention for PowerPC
26 def RetCC_PPC : CallingConv<[
27 // On PPC64, integer return values are always promoted to i64
28 CCIfType<[i32, i1], CCIfSubtarget<"isPPC64()", CCPromoteToType<i64>>>,
29 CCIfType<[i1], CCIfNotSubtarget<"isPPC64()", CCPromoteToType<i32>>>,
31 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
32 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>,
33 CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,
35 CCIfType<[f32], CCAssignToReg<[F1, F2]>>,
36 CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4]>>,
38 // Vector types are always returned in V2.
39 CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64], CCAssignToReg<[V2]>>
43 // Note that we don't currently have calling conventions for 64-bit
44 // PowerPC, but handle all the complexities of the ABI in the lowering
45 // logic. FIXME: See if the logic can be simplified with use of CCs.
46 // This may require some extensions to current table generation.
48 // Simple calling convention for 64-bit ELF PowerPC fast isel.
49 // Only handle ints and floats. All ints are promoted to i64.
50 // Vector types and quadword ints are not handled.
51 def CC_PPC64_ELF_FIS : CallingConv<[
52 CCIfType<[i1], CCPromoteToType<i64>>,
53 CCIfType<[i8], CCPromoteToType<i64>>,
54 CCIfType<[i16], CCPromoteToType<i64>>,
55 CCIfType<[i32], CCPromoteToType<i64>>,
56 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>,
57 CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>
60 // Simple return-value convention for 64-bit ELF PowerPC fast isel.
61 // All small ints are promoted to i64. Vector types, quadword ints,
62 // and multiple register returns are "supported" to avoid compile
63 // errors, but none are handled by the fast selector.
64 def RetCC_PPC64_ELF_FIS : CallingConv<[
65 CCIfType<[i1], CCPromoteToType<i64>>,
66 CCIfType<[i8], CCPromoteToType<i64>>,
67 CCIfType<[i16], CCPromoteToType<i64>>,
68 CCIfType<[i32], CCPromoteToType<i64>>,
69 CCIfType<[i64], CCAssignToReg<[X3, X4]>>,
70 CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,
71 CCIfType<[f32], CCAssignToReg<[F1, F2]>>,
72 CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4]>>,
73 CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64], CCAssignToReg<[V2]>>
76 //===----------------------------------------------------------------------===//
77 // PowerPC System V Release 4 32-bit ABI
78 //===----------------------------------------------------------------------===//
80 def CC_PPC32_SVR4_Common : CallingConv<[
81 CCIfType<[i1], CCPromoteToType<i32>>,
83 // The ABI requires i64 to be passed in two adjacent registers with the first
84 // register having an odd register number.
85 CCIfType<[i32], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>,
87 // The first 8 integer arguments are passed in integer registers.
88 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
90 // Make sure the i64 words from a long double are either both passed in
91 // registers or both passed on the stack.
92 CCIfType<[f64], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignFPArgRegs">>>,
94 // FP values are passed in F1 - F8.
95 CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
97 // Split arguments have an alignment of 8 bytes on the stack.
98 CCIfType<[i32], CCIfSplit<CCAssignToStack<4, 8>>>,
100 CCIfType<[i32], CCAssignToStack<4, 4>>,
102 // Floats are stored in double precision format, thus they have the same
103 // alignment and size as doubles.
104 CCIfType<[f32,f64], CCAssignToStack<8, 8>>,
106 // Vectors get 16-byte stack slots that are 16-byte aligned.
107 CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64], CCAssignToStack<16, 16>>
110 // This calling convention puts vector arguments always on the stack. It is used
111 // to assign vector arguments which belong to the variable portion of the
112 // parameter list of a variable argument function.
113 def CC_PPC32_SVR4_VarArg : CallingConv<[
114 CCDelegateTo<CC_PPC32_SVR4_Common>
117 // In contrast to CC_PPC32_SVR4_VarArg, this calling convention first tries to
118 // put vector arguments in vector registers before putting them on the stack.
119 def CC_PPC32_SVR4 : CallingConv<[
120 // The first 12 Vector arguments are passed in AltiVec registers.
121 CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64],
122 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13]>>,
124 CCDelegateTo<CC_PPC32_SVR4_Common>
127 // Helper "calling convention" to handle aggregate by value arguments.
128 // Aggregate by value arguments are always placed in the local variable space
129 // of the caller. This calling convention is only used to assign those stack
130 // offsets in the callers stack frame.
132 // Still, the address of the aggregate copy in the callers stack frame is passed
133 // in a GPR (or in the parameter list area if all GPRs are allocated) from the
134 // caller to the callee. The location for the address argument is assigned by
135 // the CC_PPC32_SVR4 calling convention.
137 // The only purpose of CC_PPC32_SVR4_Custom_Dummy is to skip arguments which are
138 // not passed by value.
140 def CC_PPC32_SVR4_ByVal : CallingConv<[
141 CCIfByVal<CCPassByVal<4, 4>>,
143 CCCustom<"CC_PPC32_SVR4_Custom_Dummy">
146 def CSR_Altivec : CalleeSavedRegs<(add V20, V21, V22, V23, V24, V25, V26, V27,
147 V28, V29, V30, V31)>;
149 def CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
150 R21, R22, R23, R24, R25, R26, R27, R28,
151 R29, R30, R31, F14, F15, F16, F17, F18,
152 F19, F20, F21, F22, F23, F24, F25, F26,
153 F27, F28, F29, F30, F31, CR2, CR3, CR4
156 def CSR_Darwin32_Altivec : CalleeSavedRegs<(add CSR_Darwin32, CSR_Altivec)>;
158 def CSR_SVR432 : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
159 R21, R22, R23, R24, R25, R26, R27, R28,
160 R29, R30, R31, F14, F15, F16, F17, F18,
161 F19, F20, F21, F22, F23, F24, F25, F26,
162 F27, F28, F29, F30, F31, CR2, CR3, CR4
165 def CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>;
167 def CSR_Darwin64 : CalleeSavedRegs<(add X13, X14, X15, X16, X17, X18, X19, X20,
168 X21, X22, X23, X24, X25, X26, X27, X28,
169 X29, X30, X31, F14, F15, F16, F17, F18,
170 F19, F20, F21, F22, F23, F24, F25, F26,
171 F27, F28, F29, F30, F31, CR2, CR3, CR4
174 def CSR_Darwin64_Altivec : CalleeSavedRegs<(add CSR_Darwin64, CSR_Altivec)>;
176 def CSR_SVR464 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20,
177 X21, X22, X23, X24, X25, X26, X27, X28,
178 X29, X30, X31, F14, F15, F16, F17, F18,
179 F19, F20, F21, F22, F23, F24, F25, F26,
180 F27, F28, F29, F30, F31, CR2, CR3, CR4
184 def CSR_SVR464_Altivec : CalleeSavedRegs<(add CSR_SVR464, CSR_Altivec)>;
186 def CSR_NoRegs : CalleeSavedRegs<(add)>;