1 //===- PPCCallingConv.td - Calling Conventions for PowerPC -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This describes the calling conventions for the PowerPC 32- and 64-bit
13 //===----------------------------------------------------------------------===//
15 /// CCIfSubtarget - Match if the current subtarget has a feature F.
16 class CCIfSubtarget<string F, CCAction A>
17 : CCIf<!strconcat("State.getTarget().getSubtarget<PPCSubtarget>().", F), A>;
19 //===----------------------------------------------------------------------===//
20 // Return Value Calling Convention
21 //===----------------------------------------------------------------------===//
23 // Return-value convention for PowerPC
24 def RetCC_PPC : CallingConv<[
25 // On PPC64, integer return values are always promoted to i64
26 CCIfType<[i32], CCIfSubtarget<"isPPC64()", CCPromoteToType<i64>>>,
28 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
29 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>,
30 CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,
32 CCIfType<[f32], CCAssignToReg<[F1, F2]>>,
33 CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4]>>,
35 // Vector types are always returned in V2.
36 CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToReg<[V2]>>
40 //===----------------------------------------------------------------------===//
41 // PowerPC Argument Calling Conventions
42 //===----------------------------------------------------------------------===//
44 def CC_PPC : CallingConv<[
45 // The first 8 integer arguments are passed in integer registers.
46 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
47 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>,
49 // Common sub-targets passes FP values in F1 - F13
51 CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8,F9,F10,F11,F12,F13]>>,
53 // The first 12 Vector arguments are passed in altivec registers.
54 CCIfType<[v16i8, v8i16, v4i32, v4f32],
55 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10,V11,V12,V13]>>
58 // Integer/FP values get stored in stack slots that are 8 bytes in size and
59 // 8-byte aligned if there are no more registers to hold them.
60 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
62 // Vectors get 16-byte stack slots that are 16-byte aligned.
63 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
64 CCAssignToStack<16, 16>>*/
69 //===----------------------------------------------------------------------===//
70 // PowerPC System V Release 4 ABI
71 //===----------------------------------------------------------------------===//
73 def CC_PPC_SVR4_Common : CallingConv<[
74 // The ABI requires i64 to be passed in two adjacent registers with the first
75 // register having an odd register number.
76 CCIfType<[i32], CCIfSplit<CCCustom<"CC_PPC_SVR4_Custom_AlignArgRegs">>>,
78 // The first 8 integer arguments are passed in integer registers.
79 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
81 // Make sure the i64 words from a long double are either both passed in
82 // registers or both passed on the stack.
83 CCIfType<[f64], CCIfSplit<CCCustom<"CC_PPC_SVR4_Custom_AlignFPArgRegs">>>,
85 // FP values are passed in F1 - F8.
86 CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
88 // Split arguments have an alignment of 8 bytes on the stack.
89 CCIfType<[i32], CCIfSplit<CCAssignToStack<4, 8>>>,
91 CCIfType<[i32], CCAssignToStack<4, 4>>,
93 // Floats are stored in double precision format, thus they have the same
94 // alignment and size as doubles.
95 CCIfType<[f32,f64], CCAssignToStack<8, 8>>,
97 // Vectors get 16-byte stack slots that are 16-byte aligned.
98 CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToStack<16, 16>>
101 // This calling convention puts vector arguments always on the stack. It is used
102 // to assign vector arguments which belong to the variable portion of the
103 // parameter list of a variable argument function.
104 def CC_PPC_SVR4_VarArg : CallingConv<[
105 CCDelegateTo<CC_PPC_SVR4_Common>
108 // In contrast to CC_PPC_SVR4_VarArg, this calling convention first tries to put
109 // vector arguments in vector registers before putting them on the stack.
110 def CC_PPC_SVR4 : CallingConv<[
111 // The first 12 Vector arguments are passed in AltiVec registers.
112 CCIfType<[v16i8, v8i16, v4i32, v4f32],
113 CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13]>>,
115 CCDelegateTo<CC_PPC_SVR4_Common>
118 // Helper "calling convention" to handle aggregate by value arguments.
119 // Aggregate by value arguments are always placed in the local variable space
120 // of the caller. This calling convention is only used to assign those stack
121 // offsets in the callers stack frame.
123 // Still, the address of the aggregate copy in the callers stack frame is passed
124 // in a GPR (or in the parameter list area if all GPRs are allocated) from the
125 // caller to the callee. The location for the address argument is assigned by
126 // the CC_PPC_SVR4 calling convention.
128 // The only purpose of CC_PPC_SVR4_Custom_Dummy is to skip arguments which are
129 // not passed by value.
131 def CC_PPC_SVR4_ByVal : CallingConv<[
132 CCIfByVal<CCPassByVal<4, 4>>,
134 CCCustom<"CC_PPC_SVR4_Custom_Dummy">
137 def CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
138 R21, R22, R23, R24, R25, R26, R27, R28,
139 R29, R30, R31, F14, F15, F16, F17, F18,
140 F19, F20, F21, F22, F23, F24, F25, F26,
141 F27, F28, F29, F30, F31, CR2, CR3, CR4,
142 V20, V21, V22, V23, V24, V25, V26, V27,
143 V28, V29, V30, V31)>;
145 def CSR_SVR432 : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20, VRSAVE,
146 R21, R22, R23, R24, R25, R26, R27, R28,
147 R29, R30, R31, F14, F15, F16, F17, F18,
148 F19, F20, F21, F22, F23, F24, F25, F26,
149 F27, F28, F29, F30, F31, CR2, CR3, CR4,
150 V20, V21, V22, V23, V24, V25, V26, V27,
151 V28, V29, V30, V31)>;
153 def CSR_Darwin64 : CalleeSavedRegs<(add X13, X14, X15, X16, X17, X18, X19, X20,
154 X21, X22, X23, X24, X25, X26, X27, X28,
155 X29, X30, X31, F14, F15, F16, F17, F18,
156 F19, F20, F21, F22, F23, F24, F25, F26,
157 F27, F28, F29, F30, F31, CR2, CR3, CR4,
158 V20, V21, V22, V23, V24, V25, V26, V27,
159 V28, V29, V30, V31)>;
161 def CSR_SVR464 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20, VRSAVE,
162 X21, X22, X23, X24, X25, X26, X27, X28,
163 X29, X30, X31, F14, F15, F16, F17, F18,
164 F19, F20, F21, F22, F23, F24, F25, F26,
165 F27, F28, F29, F30, F31, CR2, CR3, CR4,
166 V20, V21, V22, V23, V24, V25, V26, V27,
167 V28, V29, V30, V31)>;