1 //===-- PPCCodeEmitter.cpp - JIT Code Emitter for PowerPC -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the PowerPC 32-bit CodeEmitter and associated machinery to
11 // JIT-compile bitcode to native PowerPC.
13 //===----------------------------------------------------------------------===//
16 #include "PPCRelocations.h"
17 #include "PPCTargetMachine.h"
18 #include "llvm/CodeGen/JITCodeEmitter.h"
19 #include "llvm/CodeGen/MachineFunctionPass.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/IR/Module.h"
23 #include "llvm/PassManager.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/Target/TargetOptions.h"
30 class PPCCodeEmitter : public MachineFunctionPass {
33 MachineModuleInfo *MMI;
35 void getAnalysisUsage(AnalysisUsage &AU) const override {
36 AU.addRequired<MachineModuleInfo>();
37 MachineFunctionPass::getAnalysisUsage(AU);
42 /// MovePCtoLROffset - When/if we see a MovePCtoLR instruction, we record
43 /// its address in the function into this pointer.
44 void *MovePCtoLROffset;
47 PPCCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
48 : MachineFunctionPass(ID), TM(tm), MCE(mce) {}
50 /// getBinaryCodeForInstr - This function, generated by the
51 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
52 /// machine instructions.
53 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
56 MachineRelocation GetRelocation(const MachineOperand &MO,
57 unsigned RelocID) const;
59 /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr
60 unsigned getMachineOpValue(const MachineInstr &MI,
61 const MachineOperand &MO) const;
63 unsigned get_crbitm_encoding(const MachineInstr &MI, unsigned OpNo) const;
64 unsigned getDirectBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
65 unsigned getCondBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
66 unsigned getAbsDirectBrEncoding(const MachineInstr &MI,
68 unsigned getAbsCondBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
70 unsigned getImm16Encoding(const MachineInstr &MI, unsigned OpNo) const;
71 unsigned getMemRIEncoding(const MachineInstr &MI, unsigned OpNo) const;
72 unsigned getMemRIXEncoding(const MachineInstr &MI, unsigned OpNo) const;
73 unsigned getTLSRegEncoding(const MachineInstr &MI, unsigned OpNo) const;
74 unsigned getTLSCallEncoding(const MachineInstr &MI, unsigned OpNo) const;
76 const char *getPassName() const override {
77 return "PowerPC Machine Code Emitter";
80 /// runOnMachineFunction - emits the given MachineFunction to memory
82 bool runOnMachineFunction(MachineFunction &MF) override;
84 /// emitBasicBlock - emits the given MachineBasicBlock to memory
86 void emitBasicBlock(MachineBasicBlock &MBB);
90 char PPCCodeEmitter::ID = 0;
92 /// createPPCCodeEmitterPass - Return a pass that emits the collected PPC code
93 /// to the specified MCE object.
94 FunctionPass *llvm::createPPCJITCodeEmitterPass(PPCTargetMachine &TM,
95 JITCodeEmitter &JCE) {
96 return new PPCCodeEmitter(TM, JCE);
99 bool PPCCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
100 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
101 MF.getTarget().getRelocationModel() != Reloc::Static) &&
102 "JIT relocation model must be set to static or default!");
104 MMI = &getAnalysis<MachineModuleInfo>();
105 MCE.setModuleInfo(MMI);
107 MovePCtoLROffset = nullptr;
108 MCE.startFunction(MF);
109 for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
111 } while (MCE.finishFunction(MF));
116 void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
117 MCE.StartMachineBasicBlock(&MBB);
119 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
120 const MachineInstr &MI = *I;
121 MCE.processDebugLoc(MI.getDebugLoc(), true);
122 switch (MI.getOpcode()) {
124 MCE.emitWordBE(getBinaryCodeForInstr(MI));
126 case TargetOpcode::CFI_INSTRUCTION:
128 case TargetOpcode::EH_LABEL:
129 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
131 case TargetOpcode::IMPLICIT_DEF:
132 case TargetOpcode::KILL:
133 break; // pseudo opcode, no side effects
134 case PPC::MovePCtoLR:
135 case PPC::MovePCtoLR8:
136 assert(TM.getRelocationModel() == Reloc::PIC_);
137 MovePCtoLROffset = (void*)MCE.getCurrentPCValue();
138 MCE.emitWordBE(0x48000005); // bl 1
141 MCE.processDebugLoc(MI.getDebugLoc(), false);
145 unsigned PPCCodeEmitter::get_crbitm_encoding(const MachineInstr &MI,
146 unsigned OpNo) const {
147 const MachineOperand &MO = MI.getOperand(OpNo);
148 assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 ||
149 MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) &&
150 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
151 return 0x80 >> TM.getRegisterInfo()->getEncodingValue(MO.getReg());
154 MachineRelocation PPCCodeEmitter::GetRelocation(const MachineOperand &MO,
155 unsigned RelocID) const {
156 // If in PIC mode, we need to encode the negated address of the
157 // 'movepctolr' into the unrelocated field. After relocation, we'll have
158 // &gv-&movepctolr-4 in the imm field. Once &movepctolr is added to the imm
159 // field, we get &gv. This doesn't happen for branch relocations, which are
160 // always implicitly pc relative.
162 if (TM.getRelocationModel() == Reloc::PIC_) {
163 assert(MovePCtoLROffset && "MovePCtoLR not seen yet?");
164 Cst = -(intptr_t)MovePCtoLROffset - 4;
168 return MachineRelocation::getGV(MCE.getCurrentPCOffset(), RelocID,
169 const_cast<GlobalValue *>(MO.getGlobal()),
170 Cst, isa<Function>(MO.getGlobal()));
172 return MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
173 RelocID, MO.getSymbolName(), Cst);
175 return MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
176 RelocID, MO.getIndex(), Cst);
179 return MachineRelocation::getBB(MCE.getCurrentPCOffset(),
180 RelocID, MO.getMBB());
183 return MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
184 RelocID, MO.getIndex(), Cst);
187 unsigned PPCCodeEmitter::getDirectBrEncoding(const MachineInstr &MI,
188 unsigned OpNo) const {
189 const MachineOperand &MO = MI.getOperand(OpNo);
190 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
192 MCE.addRelocation(GetRelocation(MO, PPC::reloc_pcrel_bx));
196 unsigned PPCCodeEmitter::getCondBrEncoding(const MachineInstr &MI,
197 unsigned OpNo) const {
198 const MachineOperand &MO = MI.getOperand(OpNo);
199 MCE.addRelocation(GetRelocation(MO, PPC::reloc_pcrel_bcx));
203 unsigned PPCCodeEmitter::getAbsDirectBrEncoding(const MachineInstr &MI,
204 unsigned OpNo) const {
205 const MachineOperand &MO = MI.getOperand(OpNo);
206 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
208 llvm_unreachable("Absolute branch relocations unsupported on the old JIT.");
211 unsigned PPCCodeEmitter::getAbsCondBrEncoding(const MachineInstr &MI,
212 unsigned OpNo) const {
213 llvm_unreachable("Absolute branch relocations unsupported on the old JIT.");
216 unsigned PPCCodeEmitter::getImm16Encoding(const MachineInstr &MI,
217 unsigned OpNo) const {
218 const MachineOperand &MO = MI.getOperand(OpNo);
219 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
222 switch (MO.getTargetFlags() & PPCII::MO_ACCESS_MASK) {
223 default: llvm_unreachable("Unsupported target operand flags!");
224 case PPCII::MO_LO: RelocID = PPC::reloc_absolute_low; break;
225 case PPCII::MO_HA: RelocID = PPC::reloc_absolute_high; break;
228 MCE.addRelocation(GetRelocation(MO, RelocID));
232 unsigned PPCCodeEmitter::getMemRIEncoding(const MachineInstr &MI,
233 unsigned OpNo) const {
234 // Encode (imm, reg) as a memri, which has the low 16-bits as the
235 // displacement and the next 5 bits as the register #.
236 assert(MI.getOperand(OpNo+1).isReg());
237 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 16;
239 const MachineOperand &MO = MI.getOperand(OpNo);
241 return (getMachineOpValue(MI, MO) & 0xFFFF) | RegBits;
243 // Add a fixup for the displacement field.
244 MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_low));
248 unsigned PPCCodeEmitter::getMemRIXEncoding(const MachineInstr &MI,
249 unsigned OpNo) const {
250 // Encode (imm, reg) as a memrix, which has the low 14-bits as the
251 // displacement and the next 5 bits as the register #.
252 assert(MI.getOperand(OpNo+1).isReg());
253 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 14;
255 const MachineOperand &MO = MI.getOperand(OpNo);
257 return ((getMachineOpValue(MI, MO) >> 2) & 0x3FFF) | RegBits;
259 MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_low_ix));
264 unsigned PPCCodeEmitter::getTLSRegEncoding(const MachineInstr &MI,
265 unsigned OpNo) const {
266 llvm_unreachable("TLS not supported on the old JIT.");
270 unsigned PPCCodeEmitter::getTLSCallEncoding(const MachineInstr &MI,
271 unsigned OpNo) const {
272 llvm_unreachable("TLS not supported on the old JIT.");
276 unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI,
277 const MachineOperand &MO) const {
280 // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
281 // The GPR operand should come through here though.
282 assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 &&
283 MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) ||
284 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
285 return TM.getRegisterInfo()->getEncodingValue(MO.getReg());
289 "Relocation required in an instruction that we cannot encode!");
293 #include "PPCGenCodeEmitter.inc"