1 //===-- PPCCodeEmitter.cpp - JIT Code Emitter for PowerPC -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the PowerPC 32-bit CodeEmitter and associated machinery to
11 // JIT-compile bitcode to native PowerPC.
13 //===----------------------------------------------------------------------===//
16 #include "PPCRelocations.h"
17 #include "PPCTargetMachine.h"
18 #include "llvm/CodeGen/JITCodeEmitter.h"
19 #include "llvm/CodeGen/MachineFunctionPass.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/IR/Module.h"
23 #include "llvm/PassManager.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/Target/TargetOptions.h"
30 class PPCCodeEmitter : public MachineFunctionPass {
33 MachineModuleInfo *MMI;
35 void getAnalysisUsage(AnalysisUsage &AU) const {
36 AU.addRequired<MachineModuleInfo>();
37 MachineFunctionPass::getAnalysisUsage(AU);
42 /// MovePCtoLROffset - When/if we see a MovePCtoLR instruction, we record
43 /// its address in the function into this pointer.
44 void *MovePCtoLROffset;
47 PPCCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
48 : MachineFunctionPass(ID), TM(tm), MCE(mce) {}
50 /// getBinaryCodeForInstr - This function, generated by the
51 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
52 /// machine instructions.
53 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
56 MachineRelocation GetRelocation(const MachineOperand &MO,
57 unsigned RelocID) const;
59 /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr
60 unsigned getMachineOpValue(const MachineInstr &MI,
61 const MachineOperand &MO) const;
63 unsigned get_crbitm_encoding(const MachineInstr &MI, unsigned OpNo) const;
64 unsigned getDirectBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
65 unsigned getCondBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
67 unsigned getS16ImmEncoding(const MachineInstr &MI, unsigned OpNo) const;
68 unsigned getMemRIEncoding(const MachineInstr &MI, unsigned OpNo) const;
69 unsigned getMemRIXEncoding(const MachineInstr &MI, unsigned OpNo) const;
70 unsigned getTLSRegEncoding(const MachineInstr &MI, unsigned OpNo) const;
72 const char *getPassName() const { return "PowerPC Machine Code Emitter"; }
74 /// runOnMachineFunction - emits the given MachineFunction to memory
76 bool runOnMachineFunction(MachineFunction &MF);
78 /// emitBasicBlock - emits the given MachineBasicBlock to memory
80 void emitBasicBlock(MachineBasicBlock &MBB);
84 char PPCCodeEmitter::ID = 0;
86 /// createPPCCodeEmitterPass - Return a pass that emits the collected PPC code
87 /// to the specified MCE object.
88 FunctionPass *llvm::createPPCJITCodeEmitterPass(PPCTargetMachine &TM,
89 JITCodeEmitter &JCE) {
90 return new PPCCodeEmitter(TM, JCE);
93 bool PPCCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
94 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
95 MF.getTarget().getRelocationModel() != Reloc::Static) &&
96 "JIT relocation model must be set to static or default!");
98 MMI = &getAnalysis<MachineModuleInfo>();
99 MCE.setModuleInfo(MMI);
101 MovePCtoLROffset = 0;
102 MCE.startFunction(MF);
103 for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
105 } while (MCE.finishFunction(MF));
110 void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
111 MCE.StartMachineBasicBlock(&MBB);
113 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
114 const MachineInstr &MI = *I;
115 MCE.processDebugLoc(MI.getDebugLoc(), true);
116 switch (MI.getOpcode()) {
118 MCE.emitWordBE(getBinaryCodeForInstr(MI));
120 case TargetOpcode::PROLOG_LABEL:
121 case TargetOpcode::EH_LABEL:
122 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
124 case TargetOpcode::IMPLICIT_DEF:
125 case TargetOpcode::KILL:
126 break; // pseudo opcode, no side effects
127 case PPC::MovePCtoLR:
128 case PPC::MovePCtoLR8:
129 assert(TM.getRelocationModel() == Reloc::PIC_);
130 MovePCtoLROffset = (void*)MCE.getCurrentPCValue();
131 MCE.emitWordBE(0x48000005); // bl 1
134 MCE.processDebugLoc(MI.getDebugLoc(), false);
138 unsigned PPCCodeEmitter::get_crbitm_encoding(const MachineInstr &MI,
139 unsigned OpNo) const {
140 const MachineOperand &MO = MI.getOperand(OpNo);
141 assert((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MTCRF8 ||
142 MI.getOpcode() == PPC::MFOCRF) &&
143 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
144 return 0x80 >> TM.getRegisterInfo()->getEncodingValue(MO.getReg());
147 MachineRelocation PPCCodeEmitter::GetRelocation(const MachineOperand &MO,
148 unsigned RelocID) const {
149 // If in PIC mode, we need to encode the negated address of the
150 // 'movepctolr' into the unrelocated field. After relocation, we'll have
151 // &gv-&movepctolr-4 in the imm field. Once &movepctolr is added to the imm
152 // field, we get &gv. This doesn't happen for branch relocations, which are
153 // always implicitly pc relative.
155 if (TM.getRelocationModel() == Reloc::PIC_) {
156 assert(MovePCtoLROffset && "MovePCtoLR not seen yet?");
157 Cst = -(intptr_t)MovePCtoLROffset - 4;
161 return MachineRelocation::getGV(MCE.getCurrentPCOffset(), RelocID,
162 const_cast<GlobalValue *>(MO.getGlobal()),
163 Cst, isa<Function>(MO.getGlobal()));
165 return MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
166 RelocID, MO.getSymbolName(), Cst);
168 return MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
169 RelocID, MO.getIndex(), Cst);
172 return MachineRelocation::getBB(MCE.getCurrentPCOffset(),
173 RelocID, MO.getMBB());
176 return MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
177 RelocID, MO.getIndex(), Cst);
180 unsigned PPCCodeEmitter::getDirectBrEncoding(const MachineInstr &MI,
181 unsigned OpNo) const {
182 const MachineOperand &MO = MI.getOperand(OpNo);
183 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
185 MCE.addRelocation(GetRelocation(MO, PPC::reloc_pcrel_bx));
189 unsigned PPCCodeEmitter::getCondBrEncoding(const MachineInstr &MI,
190 unsigned OpNo) const {
191 const MachineOperand &MO = MI.getOperand(OpNo);
192 MCE.addRelocation(GetRelocation(MO, PPC::reloc_pcrel_bcx));
196 unsigned PPCCodeEmitter::getS16ImmEncoding(const MachineInstr &MI,
197 unsigned OpNo) const {
198 const MachineOperand &MO = MI.getOperand(OpNo);
199 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
202 switch (MO.getTargetFlags() & PPCII::MO_ACCESS_MASK) {
203 default: llvm_unreachable("Unsupported target operand flags!");
204 case PPCII::MO_LO: RelocID = PPC::reloc_absolute_low; break;
205 case PPCII::MO_HA: RelocID = PPC::reloc_absolute_high; break;
208 MCE.addRelocation(GetRelocation(MO, RelocID));
212 unsigned PPCCodeEmitter::getMemRIEncoding(const MachineInstr &MI,
213 unsigned OpNo) const {
214 // Encode (imm, reg) as a memri, which has the low 16-bits as the
215 // displacement and the next 5 bits as the register #.
216 assert(MI.getOperand(OpNo+1).isReg());
217 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 16;
219 const MachineOperand &MO = MI.getOperand(OpNo);
221 return (getMachineOpValue(MI, MO) & 0xFFFF) | RegBits;
223 // Add a fixup for the displacement field.
224 MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_low));
228 unsigned PPCCodeEmitter::getMemRIXEncoding(const MachineInstr &MI,
229 unsigned OpNo) const {
230 // Encode (imm, reg) as a memrix, which has the low 14-bits as the
231 // displacement and the next 5 bits as the register #.
232 assert(MI.getOperand(OpNo+1).isReg());
233 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 14;
235 const MachineOperand &MO = MI.getOperand(OpNo);
237 return ((getMachineOpValue(MI, MO) >> 2) & 0x3FFF) | RegBits;
239 MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_low_ix));
244 unsigned PPCCodeEmitter::getTLSRegEncoding(const MachineInstr &MI,
245 unsigned OpNo) const {
246 llvm_unreachable("TLS not supported on the old JIT.");
251 unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI,
252 const MachineOperand &MO) const {
255 // MTCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
256 // The GPR operand should come through here though.
257 assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MTCRF8 &&
258 MI.getOpcode() != PPC::MFOCRF) ||
259 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
260 return TM.getRegisterInfo()->getEncodingValue(MO.getReg());
264 "Relocation required in an instruction that we cannot encode!");
268 #include "PPCGenCodeEmitter.inc"