1 //===-- PPCFastISel.cpp - PowerPC FastISel implementation -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the PowerPC-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // PPCGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "ppcfastisel"
18 #include "PPCISelLowering.h"
19 #include "PPCSubtarget.h"
20 #include "PPCTargetMachine.h"
21 #include "MCTargetDesc/PPCPredicates.h"
22 #include "llvm/ADT/Optional.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/GlobalAlias.h"
32 #include "llvm/IR/GlobalVariable.h"
33 #include "llvm/IR/IntrinsicInst.h"
34 #include "llvm/IR/Operator.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/GetElementPtrTypeIterator.h"
37 #include "llvm/Target/TargetLowering.h"
38 #include "llvm/Target/TargetMachine.h"
44 typedef struct Address {
57 // Innocuous defaults for our address.
59 : BaseType(RegBase), Offset(0) {
64 class PPCFastISel : public FastISel {
66 const TargetMachine &TM;
67 const TargetInstrInfo &TII;
68 const TargetLowering &TLI;
69 const PPCSubtarget &PPCSubTarget;
73 explicit PPCFastISel(FunctionLoweringInfo &FuncInfo,
74 const TargetLibraryInfo *LibInfo)
75 : FastISel(FuncInfo, LibInfo),
76 TM(FuncInfo.MF->getTarget()),
77 TII(*TM.getInstrInfo()),
78 TLI(*TM.getTargetLowering()),
80 *((static_cast<const PPCTargetMachine *>(&TM))->getSubtargetImpl())
82 Context(&FuncInfo.Fn->getContext()) { }
84 // Backend specific FastISel code.
86 virtual bool TargetSelectInstruction(const Instruction *I);
87 virtual unsigned TargetMaterializeConstant(const Constant *C);
88 virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
89 virtual bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
91 virtual bool FastLowerArguments();
92 virtual unsigned FastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm);
93 virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
94 const TargetRegisterClass *RC,
95 unsigned Op0, bool Op0IsKill,
97 virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
98 const TargetRegisterClass *RC,
99 unsigned Op0, bool Op0IsKill);
100 virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
101 const TargetRegisterClass *RC,
102 unsigned Op0, bool Op0IsKill,
103 unsigned Op1, bool Op1IsKill);
105 // Instruction selection routines.
107 bool SelectLoad(const Instruction *I);
108 bool SelectStore(const Instruction *I);
109 bool SelectBranch(const Instruction *I);
110 bool SelectIndirectBr(const Instruction *I);
111 bool SelectCmp(const Instruction *I);
112 bool SelectFPExt(const Instruction *I);
113 bool SelectFPTrunc(const Instruction *I);
114 bool SelectIToFP(const Instruction *I, bool IsSigned);
115 bool SelectFPToI(const Instruction *I, bool IsSigned);
116 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
117 bool SelectCall(const Instruction *I);
118 bool SelectRet(const Instruction *I);
119 bool SelectTrunc(const Instruction *I);
120 bool SelectIntExt(const Instruction *I);
124 bool isTypeLegal(Type *Ty, MVT &VT);
125 bool isLoadTypeLegal(Type *Ty, MVT &VT);
126 bool PPCEmitCmp(const Value *Src1Value, const Value *Src2Value,
127 bool isZExt, unsigned DestReg);
128 bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
129 const TargetRegisterClass *RC, bool IsZExt = true,
130 unsigned FP64LoadOpc = PPC::LFD);
131 bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
132 bool PPCComputeAddress(const Value *Obj, Address &Addr);
133 void PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset,
135 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
136 unsigned DestReg, bool IsZExt);
137 unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT);
138 unsigned PPCMaterializeGV(const GlobalValue *GV, MVT VT);
139 unsigned PPCMaterializeInt(const Constant *C, MVT VT);
140 unsigned PPCMaterialize32BitInt(int64_t Imm,
141 const TargetRegisterClass *RC);
142 unsigned PPCMaterialize64BitInt(int64_t Imm,
143 const TargetRegisterClass *RC);
144 unsigned PPCMoveToIntReg(const Instruction *I, MVT VT,
145 unsigned SrcReg, bool IsSigned);
146 unsigned PPCMoveToFPReg(MVT VT, unsigned SrcReg, bool IsSigned);
148 // Call handling routines.
150 bool processCallArgs(SmallVectorImpl<Value*> &Args,
151 SmallVectorImpl<unsigned> &ArgRegs,
152 SmallVectorImpl<MVT> &ArgVTs,
153 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
154 SmallVectorImpl<unsigned> &RegArgs,
158 void finishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
159 const Instruction *I, CallingConv::ID CC,
160 unsigned &NumBytes, bool IsVarArg);
161 CCAssignFn *usePPC32CCs(unsigned Flag);
164 #include "PPCGenFastISel.inc"
168 } // end anonymous namespace
170 #include "PPCGenCallingConv.inc"
172 // Function whose sole purpose is to kill compiler warnings
173 // stemming from unused functions included from PPCGenCallingConv.inc.
174 CCAssignFn *PPCFastISel::usePPC32CCs(unsigned Flag) {
176 return CC_PPC32_SVR4;
178 return CC_PPC32_SVR4_ByVal;
180 return CC_PPC32_SVR4_VarArg;
185 static Optional<PPC::Predicate> getComparePred(CmpInst::Predicate Pred) {
187 // These are not representable with any single compare.
188 case CmpInst::FCMP_FALSE:
189 case CmpInst::FCMP_UEQ:
190 case CmpInst::FCMP_UGT:
191 case CmpInst::FCMP_UGE:
192 case CmpInst::FCMP_ULT:
193 case CmpInst::FCMP_ULE:
194 case CmpInst::FCMP_UNE:
195 case CmpInst::FCMP_TRUE:
197 return Optional<PPC::Predicate>();
199 case CmpInst::FCMP_OEQ:
200 case CmpInst::ICMP_EQ:
203 case CmpInst::FCMP_OGT:
204 case CmpInst::ICMP_UGT:
205 case CmpInst::ICMP_SGT:
208 case CmpInst::FCMP_OGE:
209 case CmpInst::ICMP_UGE:
210 case CmpInst::ICMP_SGE:
213 case CmpInst::FCMP_OLT:
214 case CmpInst::ICMP_ULT:
215 case CmpInst::ICMP_SLT:
218 case CmpInst::FCMP_OLE:
219 case CmpInst::ICMP_ULE:
220 case CmpInst::ICMP_SLE:
223 case CmpInst::FCMP_ONE:
224 case CmpInst::ICMP_NE:
227 case CmpInst::FCMP_ORD:
230 case CmpInst::FCMP_UNO:
235 // Determine whether the type Ty is simple enough to be handled by
236 // fast-isel, and return its equivalent machine type in VT.
237 // FIXME: Copied directly from ARM -- factor into base class?
238 bool PPCFastISel::isTypeLegal(Type *Ty, MVT &VT) {
239 EVT Evt = TLI.getValueType(Ty, true);
241 // Only handle simple types.
242 if (Evt == MVT::Other || !Evt.isSimple()) return false;
243 VT = Evt.getSimpleVT();
245 // Handle all legal types, i.e. a register that will directly hold this
247 return TLI.isTypeLegal(VT);
250 // Determine whether the type Ty is simple enough to be handled by
251 // fast-isel as a load target, and return its equivalent machine type in VT.
252 bool PPCFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
253 if (isTypeLegal(Ty, VT)) return true;
255 // If this is a type than can be sign or zero-extended to a basic operation
256 // go ahead and accept it now.
257 if (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) {
264 // Given a value Obj, create an Address object Addr that represents its
265 // address. Return false if we can't handle it.
266 bool PPCFastISel::PPCComputeAddress(const Value *Obj, Address &Addr) {
267 const User *U = NULL;
268 unsigned Opcode = Instruction::UserOp1;
269 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
270 // Don't walk into other basic blocks unless the object is an alloca from
271 // another block, otherwise it may not have a virtual register assigned.
272 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
273 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
274 Opcode = I->getOpcode();
277 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
278 Opcode = C->getOpcode();
285 case Instruction::BitCast:
286 // Look through bitcasts.
287 return PPCComputeAddress(U->getOperand(0), Addr);
288 case Instruction::IntToPtr:
289 // Look past no-op inttoptrs.
290 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
291 return PPCComputeAddress(U->getOperand(0), Addr);
293 case Instruction::PtrToInt:
294 // Look past no-op ptrtoints.
295 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
296 return PPCComputeAddress(U->getOperand(0), Addr);
298 case Instruction::GetElementPtr: {
299 Address SavedAddr = Addr;
300 long TmpOffset = Addr.Offset;
302 // Iterate through the GEP folding the constants into offsets where
304 gep_type_iterator GTI = gep_type_begin(U);
305 for (User::const_op_iterator II = U->op_begin() + 1, IE = U->op_end();
306 II != IE; ++II, ++GTI) {
307 const Value *Op = *II;
308 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
309 const StructLayout *SL = TD.getStructLayout(STy);
310 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
311 TmpOffset += SL->getElementOffset(Idx);
313 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
315 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
316 // Constant-offset addressing.
317 TmpOffset += CI->getSExtValue() * S;
320 if (isa<AddOperator>(Op) &&
321 (!isa<Instruction>(Op) ||
322 FuncInfo.MBBMap[cast<Instruction>(Op)->getParent()]
324 isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
325 // An add (in the same block) with a constant operand. Fold the
328 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
329 TmpOffset += CI->getSExtValue() * S;
330 // Iterate on the other operand.
331 Op = cast<AddOperator>(Op)->getOperand(0);
335 goto unsupported_gep;
340 // Try to grab the base operand now.
341 Addr.Offset = TmpOffset;
342 if (PPCComputeAddress(U->getOperand(0), Addr)) return true;
344 // We failed, restore everything and try the other options.
350 case Instruction::Alloca: {
351 const AllocaInst *AI = cast<AllocaInst>(Obj);
352 DenseMap<const AllocaInst*, int>::iterator SI =
353 FuncInfo.StaticAllocaMap.find(AI);
354 if (SI != FuncInfo.StaticAllocaMap.end()) {
355 Addr.BaseType = Address::FrameIndexBase;
356 Addr.Base.FI = SI->second;
363 // FIXME: References to parameters fall through to the behavior
364 // below. They should be able to reference a frame index since
365 // they are stored to the stack, so we can get "ld rx, offset(r1)"
366 // instead of "addi ry, r1, offset / ld rx, 0(ry)". Obj will
367 // just contain the parameter. Try to handle this with a FI.
369 // Try to get this in a register if nothing else has worked.
370 if (Addr.Base.Reg == 0)
371 Addr.Base.Reg = getRegForValue(Obj);
373 // Prevent assignment of base register to X0, which is inappropriate
374 // for loads and stores alike.
375 if (Addr.Base.Reg != 0)
376 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass);
378 return Addr.Base.Reg != 0;
381 // Fix up some addresses that can't be used directly. For example, if
382 // an offset won't fit in an instruction field, we may need to move it
383 // into an index register.
384 void PPCFastISel::PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset,
385 unsigned &IndexReg) {
387 // Check whether the offset fits in the instruction field.
388 if (!isInt<16>(Addr.Offset))
391 // If this is a stack pointer and the offset needs to be simplified then
392 // put the alloca address into a register, set the base type back to
393 // register and continue. This should almost never happen.
394 if (!UseOffset && Addr.BaseType == Address::FrameIndexBase) {
395 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
396 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ADDI8),
397 ResultReg).addFrameIndex(Addr.Base.FI).addImm(0);
398 Addr.Base.Reg = ResultReg;
399 Addr.BaseType = Address::RegBase;
403 IntegerType *OffsetTy = ((VT == MVT::i32) ? Type::getInt32Ty(*Context)
404 : Type::getInt64Ty(*Context));
405 const ConstantInt *Offset =
406 ConstantInt::getSigned(OffsetTy, (int64_t)(Addr.Offset));
407 IndexReg = PPCMaterializeInt(Offset, MVT::i64);
408 assert(IndexReg && "Unexpected error in PPCMaterializeInt!");
412 // Emit a load instruction if possible, returning true if we succeeded,
413 // otherwise false. See commentary below for how the register class of
414 // the load is determined.
415 bool PPCFastISel::PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
416 const TargetRegisterClass *RC,
417 bool IsZExt, unsigned FP64LoadOpc) {
419 bool UseOffset = true;
421 // If ResultReg is given, it determines the register class of the load.
422 // Otherwise, RC is the register class to use. If the result of the
423 // load isn't anticipated in this block, both may be zero, in which
424 // case we must make a conservative guess. In particular, don't assign
425 // R0 or X0 to the result register, as the result may be used in a load,
426 // store, add-immediate, or isel that won't permit this. (Though
427 // perhaps the spill and reload of live-exit values would handle this?)
428 const TargetRegisterClass *UseRC =
429 (ResultReg ? MRI.getRegClass(ResultReg) :
431 (VT == MVT::f64 ? &PPC::F8RCRegClass :
432 (VT == MVT::f32 ? &PPC::F4RCRegClass :
433 (VT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
434 &PPC::GPRC_and_GPRC_NOR0RegClass)))));
436 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass);
438 switch (VT.SimpleTy) {
439 default: // e.g., vector types not handled
442 Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8;
446 (Is32BitInt ? PPC::LHZ : PPC::LHZ8) :
447 (Is32BitInt ? PPC::LHA : PPC::LHA8));
451 (Is32BitInt ? PPC::LWZ : PPC::LWZ8) :
452 (Is32BitInt ? PPC::LWA_32 : PPC::LWA));
453 if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0))
458 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) &&
459 "64-bit load with 32-bit target??");
460 UseOffset = ((Addr.Offset & 3) == 0);
470 // If necessary, materialize the offset into a register and use
471 // the indexed form. Also handle stack pointers with special needs.
472 unsigned IndexReg = 0;
473 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg);
475 ResultReg = createResultReg(UseRC);
477 // Note: If we still have a frame index here, we know the offset is
478 // in range, as otherwise PPCSimplifyAddress would have converted it
480 if (Addr.BaseType == Address::FrameIndexBase) {
482 MachineMemOperand *MMO =
483 FuncInfo.MF->getMachineMemOperand(
484 MachinePointerInfo::getFixedStack(Addr.Base.FI, Addr.Offset),
485 MachineMemOperand::MOLoad, MFI.getObjectSize(Addr.Base.FI),
486 MFI.getObjectAlignment(Addr.Base.FI));
488 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
489 .addImm(Addr.Offset).addFrameIndex(Addr.Base.FI).addMemOperand(MMO);
491 // Base reg with offset in range.
492 } else if (UseOffset) {
494 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
495 .addImm(Addr.Offset).addReg(Addr.Base.Reg);
499 // Get the RR opcode corresponding to the RI one. FIXME: It would be
500 // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it
501 // is hard to get at.
503 default: llvm_unreachable("Unexpected opcode!");
504 case PPC::LBZ: Opc = PPC::LBZX; break;
505 case PPC::LBZ8: Opc = PPC::LBZX8; break;
506 case PPC::LHZ: Opc = PPC::LHZX; break;
507 case PPC::LHZ8: Opc = PPC::LHZX8; break;
508 case PPC::LHA: Opc = PPC::LHAX; break;
509 case PPC::LHA8: Opc = PPC::LHAX8; break;
510 case PPC::LWZ: Opc = PPC::LWZX; break;
511 case PPC::LWZ8: Opc = PPC::LWZX8; break;
512 case PPC::LWA: Opc = PPC::LWAX; break;
513 case PPC::LWA_32: Opc = PPC::LWAX_32; break;
514 case PPC::LD: Opc = PPC::LDX; break;
515 case PPC::LFS: Opc = PPC::LFSX; break;
516 case PPC::LFD: Opc = PPC::LFDX; break;
518 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
519 .addReg(Addr.Base.Reg).addReg(IndexReg);
525 // Attempt to fast-select a load instruction.
526 bool PPCFastISel::SelectLoad(const Instruction *I) {
527 // FIXME: No atomic loads are supported.
528 if (cast<LoadInst>(I)->isAtomic())
531 // Verify we have a legal type before going any further.
533 if (!isLoadTypeLegal(I->getType(), VT))
536 // See if we can handle this address.
538 if (!PPCComputeAddress(I->getOperand(0), Addr))
541 // Look at the currently assigned register for this instruction
542 // to determine the required register class. This is necessary
543 // to constrain RA from using R0/X0 when this is not legal.
544 unsigned AssignedReg = FuncInfo.ValueMap[I];
545 const TargetRegisterClass *RC =
546 AssignedReg ? MRI.getRegClass(AssignedReg) : 0;
548 unsigned ResultReg = 0;
549 if (!PPCEmitLoad(VT, ResultReg, Addr, RC))
551 UpdateValueMap(I, ResultReg);
555 // Emit a store instruction to store SrcReg at Addr.
556 bool PPCFastISel::PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr) {
557 assert(SrcReg && "Nothing to store!");
559 bool UseOffset = true;
561 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg);
562 bool Is32BitInt = RC->hasSuperClassEq(&PPC::GPRCRegClass);
564 switch (VT.SimpleTy) {
565 default: // e.g., vector types not handled
568 Opc = Is32BitInt ? PPC::STB : PPC::STB8;
571 Opc = Is32BitInt ? PPC::STH : PPC::STH8;
574 assert(Is32BitInt && "Not GPRC for i32??");
579 UseOffset = ((Addr.Offset & 3) == 0);
589 // If necessary, materialize the offset into a register and use
590 // the indexed form. Also handle stack pointers with special needs.
591 unsigned IndexReg = 0;
592 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg);
594 // Note: If we still have a frame index here, we know the offset is
595 // in range, as otherwise PPCSimplifyAddress would have converted it
597 if (Addr.BaseType == Address::FrameIndexBase) {
598 MachineMemOperand *MMO =
599 FuncInfo.MF->getMachineMemOperand(
600 MachinePointerInfo::getFixedStack(Addr.Base.FI, Addr.Offset),
601 MachineMemOperand::MOStore, MFI.getObjectSize(Addr.Base.FI),
602 MFI.getObjectAlignment(Addr.Base.FI));
604 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc)).addReg(SrcReg)
605 .addImm(Addr.Offset).addFrameIndex(Addr.Base.FI).addMemOperand(MMO);
607 // Base reg with offset in range.
608 } else if (UseOffset)
609 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc))
610 .addReg(SrcReg).addImm(Addr.Offset).addReg(Addr.Base.Reg);
614 // Get the RR opcode corresponding to the RI one. FIXME: It would be
615 // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it
616 // is hard to get at.
618 default: llvm_unreachable("Unexpected opcode!");
619 case PPC::STB: Opc = PPC::STBX; break;
620 case PPC::STH : Opc = PPC::STHX; break;
621 case PPC::STW : Opc = PPC::STWX; break;
622 case PPC::STB8: Opc = PPC::STBX8; break;
623 case PPC::STH8: Opc = PPC::STHX8; break;
624 case PPC::STW8: Opc = PPC::STWX8; break;
625 case PPC::STD: Opc = PPC::STDX; break;
626 case PPC::STFS: Opc = PPC::STFSX; break;
627 case PPC::STFD: Opc = PPC::STFDX; break;
629 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc))
630 .addReg(SrcReg).addReg(Addr.Base.Reg).addReg(IndexReg);
636 // Attempt to fast-select a store instruction.
637 bool PPCFastISel::SelectStore(const Instruction *I) {
638 Value *Op0 = I->getOperand(0);
641 // FIXME: No atomics loads are supported.
642 if (cast<StoreInst>(I)->isAtomic())
645 // Verify we have a legal type before going any further.
647 if (!isLoadTypeLegal(Op0->getType(), VT))
650 // Get the value to be stored into a register.
651 SrcReg = getRegForValue(Op0);
655 // See if we can handle this address.
657 if (!PPCComputeAddress(I->getOperand(1), Addr))
660 if (!PPCEmitStore(VT, SrcReg, Addr))
666 // Attempt to fast-select a branch instruction.
667 bool PPCFastISel::SelectBranch(const Instruction *I) {
668 const BranchInst *BI = cast<BranchInst>(I);
669 MachineBasicBlock *BrBB = FuncInfo.MBB;
670 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
671 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
673 // For now, just try the simplest case where it's fed by a compare.
674 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
675 Optional<PPC::Predicate> OptPPCPred = getComparePred(CI->getPredicate());
679 PPC::Predicate PPCPred = OptPPCPred.getValue();
681 // Take advantage of fall-through opportunities.
682 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
684 PPCPred = PPC::InvertPredicate(PPCPred);
687 unsigned CondReg = createResultReg(&PPC::CRRCRegClass);
689 if (!PPCEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(),
693 BuildMI(*BrBB, FuncInfo.InsertPt, DL, TII.get(PPC::BCC))
694 .addImm(PPCPred).addReg(CondReg).addMBB(TBB);
695 FastEmitBranch(FBB, DL);
696 FuncInfo.MBB->addSuccessor(TBB);
699 } else if (const ConstantInt *CI =
700 dyn_cast<ConstantInt>(BI->getCondition())) {
701 uint64_t Imm = CI->getZExtValue();
702 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
703 FastEmitBranch(Target, DL);
707 // FIXME: ARM looks for a case where the block containing the compare
708 // has been split from the block containing the branch. If this happens,
709 // there is a vreg available containing the result of the compare. I'm
710 // not sure we can do much, as we've lost the predicate information with
711 // the compare instruction -- we have a 4-bit CR but don't know which bit
716 // Attempt to emit a compare of the two source values. Signed and unsigned
717 // comparisons are supported. Return false if we can't handle it.
718 bool PPCFastISel::PPCEmitCmp(const Value *SrcValue1, const Value *SrcValue2,
719 bool IsZExt, unsigned DestReg) {
720 Type *Ty = SrcValue1->getType();
721 EVT SrcEVT = TLI.getValueType(Ty, true);
722 if (!SrcEVT.isSimple())
724 MVT SrcVT = SrcEVT.getSimpleVT();
726 // See if operand 2 is an immediate encodeable in the compare.
727 // FIXME: Operands are not in canonical order at -O0, so an immediate
728 // operand in position 1 is a lost opportunity for now. We are
729 // similar to ARM in this regard.
733 // Only 16-bit integer constants can be represented in compares for
734 // PowerPC. Others will be materialized into a register.
735 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(SrcValue2)) {
736 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
737 SrcVT == MVT::i8 || SrcVT == MVT::i1) {
738 const APInt &CIVal = ConstInt->getValue();
739 Imm = (IsZExt) ? (long)CIVal.getZExtValue() : (long)CIVal.getSExtValue();
740 if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm)))
746 bool NeedsExt = false;
747 switch (SrcVT.SimpleTy) {
748 default: return false;
750 CmpOpc = PPC::FCMPUS;
753 CmpOpc = PPC::FCMPUD;
759 // Intentional fall-through.
762 CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW;
764 CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI;
768 CmpOpc = IsZExt ? PPC::CMPLD : PPC::CMPD;
770 CmpOpc = IsZExt ? PPC::CMPLDI : PPC::CMPDI;
774 unsigned SrcReg1 = getRegForValue(SrcValue1);
778 unsigned SrcReg2 = 0;
780 SrcReg2 = getRegForValue(SrcValue2);
786 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
787 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt))
792 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
793 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt))
800 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc), DestReg)
801 .addReg(SrcReg1).addReg(SrcReg2);
803 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc), DestReg)
804 .addReg(SrcReg1).addImm(Imm);
809 // Attempt to fast-select a floating-point extend instruction.
810 bool PPCFastISel::SelectFPExt(const Instruction *I) {
811 Value *Src = I->getOperand(0);
812 EVT SrcVT = TLI.getValueType(Src->getType(), true);
813 EVT DestVT = TLI.getValueType(I->getType(), true);
815 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
818 unsigned SrcReg = getRegForValue(Src);
822 // No code is generated for a FP extend.
823 UpdateValueMap(I, SrcReg);
827 // Attempt to fast-select a floating-point truncate instruction.
828 bool PPCFastISel::SelectFPTrunc(const Instruction *I) {
829 Value *Src = I->getOperand(0);
830 EVT SrcVT = TLI.getValueType(Src->getType(), true);
831 EVT DestVT = TLI.getValueType(I->getType(), true);
833 if (SrcVT != MVT::f64 || DestVT != MVT::f32)
836 unsigned SrcReg = getRegForValue(Src);
840 // Round the result to single precision.
841 unsigned DestReg = createResultReg(&PPC::F4RCRegClass);
842 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::FRSP), DestReg)
845 UpdateValueMap(I, DestReg);
849 // Move an i32 or i64 value in a GPR to an f64 value in an FPR.
850 // FIXME: When direct register moves are implemented (see PowerISA 2.08),
851 // those should be used instead of moving via a stack slot when the
852 // subtarget permits.
853 // FIXME: The code here is sloppy for the 4-byte case. Can use a 4-byte
854 // stack slot and 4-byte store/load sequence. Or just sext the 4-byte
855 // case to 8 bytes which produces tighter code but wastes stack space.
856 unsigned PPCFastISel::PPCMoveToFPReg(MVT SrcVT, unsigned SrcReg,
859 // If necessary, extend 32-bit int to 64-bit.
860 if (SrcVT == MVT::i32) {
861 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass);
862 if (!PPCEmitIntExt(MVT::i32, SrcReg, MVT::i64, TmpReg, !IsSigned))
867 // Get a stack slot 8 bytes wide, aligned on an 8-byte boundary.
869 Addr.BaseType = Address::FrameIndexBase;
870 Addr.Base.FI = MFI.CreateStackObject(8, 8, false);
872 // Store the value from the GPR.
873 if (!PPCEmitStore(MVT::i64, SrcReg, Addr))
876 // Load the integer value into an FPR. The kind of load used depends
877 // on a number of conditions.
878 unsigned LoadOpc = PPC::LFD;
880 if (SrcVT == MVT::i32) {
883 LoadOpc = PPC::LFIWZX;
884 else if (PPCSubTarget.hasLFIWAX())
885 LoadOpc = PPC::LFIWAX;
888 const TargetRegisterClass *RC = &PPC::F8RCRegClass;
889 unsigned ResultReg = 0;
890 if (!PPCEmitLoad(MVT::f64, ResultReg, Addr, RC, !IsSigned, LoadOpc))
896 // Attempt to fast-select an integer-to-floating-point conversion.
897 bool PPCFastISel::SelectIToFP(const Instruction *I, bool IsSigned) {
899 Type *DstTy = I->getType();
900 if (!isTypeLegal(DstTy, DstVT))
903 if (DstVT != MVT::f32 && DstVT != MVT::f64)
906 Value *Src = I->getOperand(0);
907 EVT SrcEVT = TLI.getValueType(Src->getType(), true);
908 if (!SrcEVT.isSimple())
911 MVT SrcVT = SrcEVT.getSimpleVT();
913 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 &&
914 SrcVT != MVT::i32 && SrcVT != MVT::i64)
917 unsigned SrcReg = getRegForValue(Src);
921 // We can only lower an unsigned convert if we have the newer
922 // floating-point conversion operations.
923 if (!IsSigned && !PPCSubTarget.hasFPCVT())
926 // FIXME: For now we require the newer floating-point conversion operations
927 // (which are present only on P7 and A2 server models) when converting
928 // to single-precision float. Otherwise we have to generate a lot of
929 // fiddly code to avoid double rounding. If necessary, the fiddly code
930 // can be found in PPCTargetLowering::LowerINT_TO_FP().
931 if (DstVT == MVT::f32 && !PPCSubTarget.hasFPCVT())
934 // Extend the input if necessary.
935 if (SrcVT == MVT::i8 || SrcVT == MVT::i16) {
936 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass);
937 if (!PPCEmitIntExt(SrcVT, SrcReg, MVT::i64, TmpReg, !IsSigned))
943 // Move the integer value to an FPR.
944 unsigned FPReg = PPCMoveToFPReg(SrcVT, SrcReg, IsSigned);
948 // Determine the opcode for the conversion.
949 const TargetRegisterClass *RC = &PPC::F8RCRegClass;
950 unsigned DestReg = createResultReg(RC);
953 if (DstVT == MVT::f32)
954 Opc = IsSigned ? PPC::FCFIDS : PPC::FCFIDUS;
956 Opc = IsSigned ? PPC::FCFID : PPC::FCFIDU;
958 // Generate the convert.
959 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
962 UpdateValueMap(I, DestReg);
966 // Move the floating-point value in SrcReg into an integer destination
967 // register, and return the register (or zero if we can't handle it).
968 // FIXME: When direct register moves are implemented (see PowerISA 2.08),
969 // those should be used instead of moving via a stack slot when the
970 // subtarget permits.
971 unsigned PPCFastISel::PPCMoveToIntReg(const Instruction *I, MVT VT,
972 unsigned SrcReg, bool IsSigned) {
973 // Get a stack slot 8 bytes wide, aligned on an 8-byte boundary.
974 // Note that if have STFIWX available, we could use a 4-byte stack
975 // slot for i32, but this being fast-isel we'll just go with the
976 // easiest code gen possible.
978 Addr.BaseType = Address::FrameIndexBase;
979 Addr.Base.FI = MFI.CreateStackObject(8, 8, false);
981 // Store the value from the FPR.
982 if (!PPCEmitStore(MVT::f64, SrcReg, Addr))
985 // Reload it into a GPR. If we want an i32, modify the address
986 // to have a 4-byte offset so we load from the right place.
990 // Look at the currently assigned register for this instruction
991 // to determine the required register class.
992 unsigned AssignedReg = FuncInfo.ValueMap[I];
993 const TargetRegisterClass *RC =
994 AssignedReg ? MRI.getRegClass(AssignedReg) : 0;
996 unsigned ResultReg = 0;
997 if (!PPCEmitLoad(VT, ResultReg, Addr, RC, !IsSigned))
1003 // Attempt to fast-select a floating-point-to-integer conversion.
1004 bool PPCFastISel::SelectFPToI(const Instruction *I, bool IsSigned) {
1006 Type *DstTy = I->getType();
1007 if (!isTypeLegal(DstTy, DstVT))
1010 if (DstVT != MVT::i32 && DstVT != MVT::i64)
1013 Value *Src = I->getOperand(0);
1014 Type *SrcTy = Src->getType();
1015 if (!isTypeLegal(SrcTy, SrcVT))
1018 if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1021 unsigned SrcReg = getRegForValue(Src);
1025 // Convert f32 to f64 if necessary. This is just a meaningless copy
1026 // to get the register class right. COPY_TO_REGCLASS is needed since
1027 // a COPY from F4RC to F8RC is converted to a F4RC-F4RC copy downstream.
1028 const TargetRegisterClass *InRC = MRI.getRegClass(SrcReg);
1029 if (InRC == &PPC::F4RCRegClass) {
1030 unsigned TmpReg = createResultReg(&PPC::F8RCRegClass);
1031 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1032 TII.get(TargetOpcode::COPY_TO_REGCLASS), TmpReg)
1033 .addReg(SrcReg).addImm(PPC::F8RCRegClassID);
1037 // Determine the opcode for the conversion, which takes place
1038 // entirely within FPRs.
1039 unsigned DestReg = createResultReg(&PPC::F8RCRegClass);
1042 if (DstVT == MVT::i32)
1046 Opc = PPCSubTarget.hasFPCVT() ? PPC::FCTIWUZ : PPC::FCTIDZ;
1048 Opc = IsSigned ? PPC::FCTIDZ : PPC::FCTIDUZ;
1050 // Generate the convert.
1051 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
1054 // Now move the integer value from a float register to an integer register.
1055 unsigned IntReg = PPCMoveToIntReg(I, DstVT, DestReg, IsSigned);
1059 UpdateValueMap(I, IntReg);
1063 // Attempt to fast-select a binary integer operation that isn't already
1064 // handled automatically.
1065 bool PPCFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1066 EVT DestVT = TLI.getValueType(I->getType(), true);
1068 // We can get here in the case when we have a binary operation on a non-legal
1069 // type and the target independent selector doesn't know how to handle it.
1070 if (DestVT != MVT::i16 && DestVT != MVT::i8)
1073 // Look at the currently assigned register for this instruction
1074 // to determine the required register class. If there is no register,
1075 // make a conservative choice (don't assign R0).
1076 unsigned AssignedReg = FuncInfo.ValueMap[I];
1077 const TargetRegisterClass *RC =
1078 (AssignedReg ? MRI.getRegClass(AssignedReg) :
1079 &PPC::GPRC_and_GPRC_NOR0RegClass);
1080 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
1083 switch (ISDOpcode) {
1084 default: return false;
1086 Opc = IsGPRC ? PPC::ADD4 : PPC::ADD8;
1089 Opc = IsGPRC ? PPC::OR : PPC::OR8;
1092 Opc = IsGPRC ? PPC::SUBF : PPC::SUBF8;
1096 unsigned ResultReg = createResultReg(RC ? RC : &PPC::G8RCRegClass);
1097 unsigned SrcReg1 = getRegForValue(I->getOperand(0));
1098 if (SrcReg1 == 0) return false;
1100 // Handle case of small immediate operand.
1101 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(1))) {
1102 const APInt &CIVal = ConstInt->getValue();
1103 int Imm = (int)CIVal.getSExtValue();
1105 if (isInt<16>(Imm)) {
1108 llvm_unreachable("Missing case!");
1111 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1115 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
1128 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1137 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
1144 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
1145 .addReg(SrcReg1).addImm(Imm);
1146 UpdateValueMap(I, ResultReg);
1153 unsigned SrcReg2 = getRegForValue(I->getOperand(1));
1154 if (SrcReg2 == 0) return false;
1156 // Reverse operands for subtract-from.
1157 if (ISDOpcode == ISD::SUB)
1158 std::swap(SrcReg1, SrcReg2);
1160 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
1161 .addReg(SrcReg1).addReg(SrcReg2);
1162 UpdateValueMap(I, ResultReg);
1166 // Handle arguments to a call that we're attempting to fast-select.
1167 // Return false if the arguments are too complex for us at the moment.
1168 bool PPCFastISel::processCallArgs(SmallVectorImpl<Value*> &Args,
1169 SmallVectorImpl<unsigned> &ArgRegs,
1170 SmallVectorImpl<MVT> &ArgVTs,
1171 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1172 SmallVectorImpl<unsigned> &RegArgs,
1176 SmallVector<CCValAssign, 16> ArgLocs;
1177 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, TM, ArgLocs, *Context);
1178 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CC_PPC64_ELF_FIS);
1180 // Bail out if we can't handle any of the arguments.
1181 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1182 CCValAssign &VA = ArgLocs[I];
1183 MVT ArgVT = ArgVTs[VA.getValNo()];
1185 // Skip vector arguments for now, as well as long double and
1186 // uint128_t, and anything that isn't passed in a register.
1187 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64 ||
1188 !VA.isRegLoc() || VA.needsCustom())
1191 // Skip bit-converted arguments for now.
1192 if (VA.getLocInfo() == CCValAssign::BCvt)
1196 // Get a count of how many bytes are to be pushed onto the stack.
1197 NumBytes = CCInfo.getNextStackOffset();
1199 // Issue CALLSEQ_START.
1200 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1201 TII.get(TII.getCallFrameSetupOpcode()))
1204 // Prepare to assign register arguments. Every argument uses up a
1205 // GPR protocol register even if it's passed in a floating-point
1207 unsigned NextGPR = PPC::X3;
1208 unsigned NextFPR = PPC::F1;
1210 // Process arguments.
1211 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1212 CCValAssign &VA = ArgLocs[I];
1213 unsigned Arg = ArgRegs[VA.getValNo()];
1214 MVT ArgVT = ArgVTs[VA.getValNo()];
1216 // Handle argument promotion and bitcasts.
1217 switch (VA.getLocInfo()) {
1219 llvm_unreachable("Unknown loc info!");
1220 case CCValAssign::Full:
1222 case CCValAssign::SExt: {
1223 MVT DestVT = VA.getLocVT();
1224 const TargetRegisterClass *RC =
1225 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1226 unsigned TmpReg = createResultReg(RC);
1227 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/false))
1228 llvm_unreachable("Failed to emit a sext!");
1233 case CCValAssign::AExt:
1234 case CCValAssign::ZExt: {
1235 MVT DestVT = VA.getLocVT();
1236 const TargetRegisterClass *RC =
1237 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1238 unsigned TmpReg = createResultReg(RC);
1239 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/true))
1240 llvm_unreachable("Failed to emit a zext!");
1245 case CCValAssign::BCvt: {
1246 // FIXME: Not yet handled.
1247 llvm_unreachable("Should have bailed before getting here!");
1252 // Copy this argument to the appropriate register.
1254 if (ArgVT == MVT::f32 || ArgVT == MVT::f64) {
1260 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1261 ArgReg).addReg(Arg);
1262 RegArgs.push_back(ArgReg);
1268 // For a call that we've determined we can fast-select, finish the
1269 // call sequence and generate a copy to obtain the return value (if any).
1270 void PPCFastISel::finishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
1271 const Instruction *I, CallingConv::ID CC,
1272 unsigned &NumBytes, bool IsVarArg) {
1273 // Issue CallSEQ_END.
1274 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1275 TII.get(TII.getCallFrameDestroyOpcode()))
1276 .addImm(NumBytes).addImm(0);
1278 // Next, generate a copy to obtain the return value.
1279 // FIXME: No multi-register return values yet, though I don't foresee
1280 // any real difficulties there.
1281 if (RetVT != MVT::isVoid) {
1282 SmallVector<CCValAssign, 16> RVLocs;
1283 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, TM, RVLocs, *Context);
1284 CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1285 CCValAssign &VA = RVLocs[0];
1286 assert(RVLocs.size() == 1 && "No support for multi-reg return values!");
1287 assert(VA.isRegLoc() && "Can only return in registers!");
1289 MVT DestVT = VA.getValVT();
1290 MVT CopyVT = DestVT;
1292 // Ints smaller than a register still arrive in a full 64-bit
1293 // register, so make sure we recognize this.
1294 if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32)
1297 unsigned SourcePhysReg = VA.getLocReg();
1298 unsigned ResultReg = 0;
1300 if (RetVT == CopyVT) {
1301 const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT);
1302 ResultReg = createResultReg(CpyRC);
1304 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1305 TII.get(TargetOpcode::COPY), ResultReg)
1306 .addReg(SourcePhysReg);
1308 // If necessary, round the floating result to single precision.
1309 } else if (CopyVT == MVT::f64) {
1310 ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1311 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::FRSP),
1312 ResultReg).addReg(SourcePhysReg);
1314 // If only the low half of a general register is needed, generate
1315 // a GPRC copy instead of a G8RC copy. (EXTRACT_SUBREG can't be
1316 // used along the fast-isel path (not lowered), and downstream logic
1317 // also doesn't like a direct subreg copy on a physical reg.)
1318 } else if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) {
1319 ResultReg = createResultReg(&PPC::GPRCRegClass);
1320 // Convert physical register from G8RC to GPRC.
1321 SourcePhysReg -= PPC::X0 - PPC::R0;
1322 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1323 TII.get(TargetOpcode::COPY), ResultReg)
1324 .addReg(SourcePhysReg);
1327 assert(ResultReg && "ResultReg unset!");
1328 UsedRegs.push_back(SourcePhysReg);
1329 UpdateValueMap(I, ResultReg);
1333 // Attempt to fast-select a call instruction.
1334 bool PPCFastISel::SelectCall(const Instruction *I) {
1335 const CallInst *CI = cast<CallInst>(I);
1336 const Value *Callee = CI->getCalledValue();
1338 // Can't handle inline asm.
1339 if (isa<InlineAsm>(Callee))
1342 // Allow SelectionDAG isel to handle tail calls.
1343 if (CI->isTailCall())
1346 // Obtain calling convention.
1347 ImmutableCallSite CS(CI);
1348 CallingConv::ID CC = CS.getCallingConv();
1350 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1351 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1352 bool IsVarArg = FTy->isVarArg();
1354 // Not ready for varargs yet.
1358 // Handle simple calls for now, with legal return types and
1359 // those that can be extended.
1360 Type *RetTy = I->getType();
1362 if (RetTy->isVoidTy())
1363 RetVT = MVT::isVoid;
1364 else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
1368 // FIXME: No multi-register return values yet.
1369 if (RetVT != MVT::isVoid && RetVT != MVT::i8 && RetVT != MVT::i16 &&
1370 RetVT != MVT::i32 && RetVT != MVT::i64 && RetVT != MVT::f32 &&
1371 RetVT != MVT::f64) {
1372 SmallVector<CCValAssign, 16> RVLocs;
1373 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, TM, RVLocs, *Context);
1374 CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1375 if (RVLocs.size() > 1)
1379 // Bail early if more than 8 arguments, as we only currently
1380 // handle arguments passed in registers.
1381 unsigned NumArgs = CS.arg_size();
1385 // Set up the argument vectors.
1386 SmallVector<Value*, 8> Args;
1387 SmallVector<unsigned, 8> ArgRegs;
1388 SmallVector<MVT, 8> ArgVTs;
1389 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1391 Args.reserve(NumArgs);
1392 ArgRegs.reserve(NumArgs);
1393 ArgVTs.reserve(NumArgs);
1394 ArgFlags.reserve(NumArgs);
1396 for (ImmutableCallSite::arg_iterator II = CS.arg_begin(), IE = CS.arg_end();
1398 // FIXME: ARM does something for intrinsic calls here, check into that.
1400 unsigned AttrIdx = II - CS.arg_begin() + 1;
1402 // Only handle easy calls for now. It would be reasonably easy
1403 // to handle <= 8-byte structures passed ByVal in registers, but we
1404 // have to ensure they are right-justified in the register.
1405 if (CS.paramHasAttr(AttrIdx, Attribute::InReg) ||
1406 CS.paramHasAttr(AttrIdx, Attribute::StructRet) ||
1407 CS.paramHasAttr(AttrIdx, Attribute::Nest) ||
1408 CS.paramHasAttr(AttrIdx, Attribute::ByVal))
1411 ISD::ArgFlagsTy Flags;
1412 if (CS.paramHasAttr(AttrIdx, Attribute::SExt))
1414 if (CS.paramHasAttr(AttrIdx, Attribute::ZExt))
1417 Type *ArgTy = (*II)->getType();
1419 if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8)
1422 if (ArgVT.isVector())
1425 unsigned Arg = getRegForValue(*II);
1429 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1430 Flags.setOrigAlign(OriginalAlignment);
1432 Args.push_back(*II);
1433 ArgRegs.push_back(Arg);
1434 ArgVTs.push_back(ArgVT);
1435 ArgFlags.push_back(Flags);
1438 // Process the arguments.
1439 SmallVector<unsigned, 8> RegArgs;
1442 if (!processCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
1443 RegArgs, CC, NumBytes, IsVarArg))
1446 // FIXME: No handling for function pointers yet. This requires
1447 // implementing the function descriptor (OPD) setup.
1448 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1452 // Build direct call with NOP for TOC restore.
1453 // FIXME: We can and should optimize away the NOP for local calls.
1454 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1455 TII.get(PPC::BL8_NOP));
1457 MIB.addGlobalAddress(GV);
1459 // Add implicit physical register uses to the call.
1460 for (unsigned II = 0, IE = RegArgs.size(); II != IE; ++II)
1461 MIB.addReg(RegArgs[II], RegState::Implicit);
1463 // Add a register mask with the call-preserved registers. Proper
1464 // defs for return values will be added by setPhysRegsDeadExcept().
1465 MIB.addRegMask(TRI.getCallPreservedMask(CC));
1467 // Finish off the call including any return values.
1468 SmallVector<unsigned, 4> UsedRegs;
1469 finishCall(RetVT, UsedRegs, I, CC, NumBytes, IsVarArg);
1471 // Set all unused physregs defs as dead.
1472 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1477 // Attempt to fast-select a return instruction.
1478 bool PPCFastISel::SelectRet(const Instruction *I) {
1480 if (!FuncInfo.CanLowerReturn)
1483 const ReturnInst *Ret = cast<ReturnInst>(I);
1484 const Function &F = *I->getParent()->getParent();
1486 // Build a list of return value registers.
1487 SmallVector<unsigned, 4> RetRegs;
1488 CallingConv::ID CC = F.getCallingConv();
1490 if (Ret->getNumOperands() > 0) {
1491 SmallVector<ISD::OutputArg, 4> Outs;
1492 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
1494 // Analyze operands of the call, assigning locations to each operand.
1495 SmallVector<CCValAssign, 16> ValLocs;
1496 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs, *Context);
1497 CCInfo.AnalyzeReturn(Outs, RetCC_PPC64_ELF_FIS);
1498 const Value *RV = Ret->getOperand(0);
1500 // FIXME: Only one output register for now.
1501 if (ValLocs.size() > 1)
1504 // Special case for returning a constant integer of any size.
1505 // Materialize the constant as an i64 and copy it to the return
1506 // register. This avoids an unnecessary extend or truncate.
1507 if (isa<ConstantInt>(*RV)) {
1508 const Constant *C = cast<Constant>(RV);
1509 unsigned SrcReg = PPCMaterializeInt(C, MVT::i64);
1510 unsigned RetReg = ValLocs[0].getLocReg();
1511 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1512 RetReg).addReg(SrcReg);
1513 RetRegs.push_back(RetReg);
1516 unsigned Reg = getRegForValue(RV);
1521 // Copy the result values into the output registers.
1522 for (unsigned i = 0; i < ValLocs.size(); ++i) {
1524 CCValAssign &VA = ValLocs[i];
1525 assert(VA.isRegLoc() && "Can only return in registers!");
1526 RetRegs.push_back(VA.getLocReg());
1527 unsigned SrcReg = Reg + VA.getValNo();
1529 EVT RVEVT = TLI.getValueType(RV->getType());
1530 if (!RVEVT.isSimple())
1532 MVT RVVT = RVEVT.getSimpleVT();
1533 MVT DestVT = VA.getLocVT();
1535 if (RVVT != DestVT && RVVT != MVT::i8 &&
1536 RVVT != MVT::i16 && RVVT != MVT::i32)
1539 if (RVVT != DestVT) {
1540 switch (VA.getLocInfo()) {
1542 llvm_unreachable("Unknown loc info!");
1543 case CCValAssign::Full:
1544 llvm_unreachable("Full value assign but types don't match?");
1545 case CCValAssign::AExt:
1546 case CCValAssign::ZExt: {
1547 const TargetRegisterClass *RC =
1548 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1549 unsigned TmpReg = createResultReg(RC);
1550 if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, true))
1555 case CCValAssign::SExt: {
1556 const TargetRegisterClass *RC =
1557 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1558 unsigned TmpReg = createResultReg(RC);
1559 if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, false))
1567 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1568 TII.get(TargetOpcode::COPY), RetRegs[i])
1574 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1577 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1578 MIB.addReg(RetRegs[i], RegState::Implicit);
1583 // Attempt to emit an integer extend of SrcReg into DestReg. Both
1584 // signed and zero extensions are supported. Return false if we
1586 bool PPCFastISel::PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1587 unsigned DestReg, bool IsZExt) {
1588 if (DestVT != MVT::i32 && DestVT != MVT::i64)
1590 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 && SrcVT != MVT::i32)
1593 // Signed extensions use EXTSB, EXTSH, EXTSW.
1596 if (SrcVT == MVT::i8)
1597 Opc = (DestVT == MVT::i32) ? PPC::EXTSB : PPC::EXTSB8_32_64;
1598 else if (SrcVT == MVT::i16)
1599 Opc = (DestVT == MVT::i32) ? PPC::EXTSH : PPC::EXTSH8_32_64;
1601 assert(DestVT == MVT::i64 && "Signed extend from i32 to i32??");
1602 Opc = PPC::EXTSW_32_64;
1604 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
1607 // Unsigned 32-bit extensions use RLWINM.
1608 } else if (DestVT == MVT::i32) {
1610 if (SrcVT == MVT::i8)
1613 assert(SrcVT == MVT::i16 && "Unsigned extend from i32 to i32??");
1616 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::RLWINM),
1618 .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB).addImm(/*ME=*/31);
1620 // Unsigned 64-bit extensions use RLDICL (with a 32-bit source).
1623 if (SrcVT == MVT::i8)
1625 else if (SrcVT == MVT::i16)
1629 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1630 TII.get(PPC::RLDICL_32_64), DestReg)
1631 .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB);
1637 // Attempt to fast-select an indirect branch instruction.
1638 bool PPCFastISel::SelectIndirectBr(const Instruction *I) {
1639 unsigned AddrReg = getRegForValue(I->getOperand(0));
1643 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::MTCTR8))
1645 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::BCTR8));
1647 const IndirectBrInst *IB = cast<IndirectBrInst>(I);
1648 for (unsigned i = 0, e = IB->getNumSuccessors(); i != e; ++i)
1649 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[IB->getSuccessor(i)]);
1654 // Attempt to fast-select a compare instruction.
1655 bool PPCFastISel::SelectCmp(const Instruction *I) {
1656 const CmpInst *CI = cast<CmpInst>(I);
1657 Optional<PPC::Predicate> OptPPCPred = getComparePred(CI->getPredicate());
1661 unsigned CondReg = createResultReg(&PPC::CRRCRegClass);
1663 if (!PPCEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(),
1667 UpdateValueMap(I, CondReg);
1671 // Attempt to fast-select an integer truncate instruction.
1672 bool PPCFastISel::SelectTrunc(const Instruction *I) {
1673 Value *Src = I->getOperand(0);
1674 EVT SrcVT = TLI.getValueType(Src->getType(), true);
1675 EVT DestVT = TLI.getValueType(I->getType(), true);
1677 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16)
1680 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
1683 unsigned SrcReg = getRegForValue(Src);
1687 // The only interesting case is when we need to switch register classes.
1688 if (SrcVT == MVT::i64) {
1689 unsigned ResultReg = createResultReg(&PPC::GPRCRegClass);
1690 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1691 ResultReg).addReg(SrcReg, 0, PPC::sub_32);
1695 UpdateValueMap(I, SrcReg);
1699 // Attempt to fast-select an integer extend instruction.
1700 bool PPCFastISel::SelectIntExt(const Instruction *I) {
1701 Type *DestTy = I->getType();
1702 Value *Src = I->getOperand(0);
1703 Type *SrcTy = Src->getType();
1705 bool IsZExt = isa<ZExtInst>(I);
1706 unsigned SrcReg = getRegForValue(Src);
1707 if (!SrcReg) return false;
1709 EVT SrcEVT, DestEVT;
1710 SrcEVT = TLI.getValueType(SrcTy, true);
1711 DestEVT = TLI.getValueType(DestTy, true);
1712 if (!SrcEVT.isSimple())
1714 if (!DestEVT.isSimple())
1717 MVT SrcVT = SrcEVT.getSimpleVT();
1718 MVT DestVT = DestEVT.getSimpleVT();
1720 // If we know the register class needed for the result of this
1721 // instruction, use it. Otherwise pick the register class of the
1722 // correct size that does not contain X0/R0, since we don't know
1723 // whether downstream uses permit that assignment.
1724 unsigned AssignedReg = FuncInfo.ValueMap[I];
1725 const TargetRegisterClass *RC =
1726 (AssignedReg ? MRI.getRegClass(AssignedReg) :
1727 (DestVT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
1728 &PPC::GPRC_and_GPRC_NOR0RegClass));
1729 unsigned ResultReg = createResultReg(RC);
1731 if (!PPCEmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, IsZExt))
1734 UpdateValueMap(I, ResultReg);
1738 // Attempt to fast-select an instruction that wasn't handled by
1739 // the table-generated machinery.
1740 bool PPCFastISel::TargetSelectInstruction(const Instruction *I) {
1742 switch (I->getOpcode()) {
1743 case Instruction::Load:
1744 return SelectLoad(I);
1745 case Instruction::Store:
1746 return SelectStore(I);
1747 case Instruction::Br:
1748 return SelectBranch(I);
1749 case Instruction::IndirectBr:
1750 return SelectIndirectBr(I);
1751 case Instruction::FPExt:
1752 return SelectFPExt(I);
1753 case Instruction::FPTrunc:
1754 return SelectFPTrunc(I);
1755 case Instruction::SIToFP:
1756 return SelectIToFP(I, /*IsSigned*/ true);
1757 case Instruction::UIToFP:
1758 return SelectIToFP(I, /*IsSigned*/ false);
1759 case Instruction::FPToSI:
1760 return SelectFPToI(I, /*IsSigned*/ true);
1761 case Instruction::FPToUI:
1762 return SelectFPToI(I, /*IsSigned*/ false);
1763 case Instruction::Add:
1764 return SelectBinaryIntOp(I, ISD::ADD);
1765 case Instruction::Or:
1766 return SelectBinaryIntOp(I, ISD::OR);
1767 case Instruction::Sub:
1768 return SelectBinaryIntOp(I, ISD::SUB);
1769 case Instruction::Call:
1770 if (dyn_cast<IntrinsicInst>(I))
1772 return SelectCall(I);
1773 case Instruction::Ret:
1774 return SelectRet(I);
1775 case Instruction::Trunc:
1776 return SelectTrunc(I);
1777 case Instruction::ZExt:
1778 case Instruction::SExt:
1779 return SelectIntExt(I);
1780 // Here add other flavors of Instruction::XXX that automated
1781 // cases don't catch. For example, switches are terminators
1782 // that aren't yet handled.
1789 // Materialize a floating-point constant into a register, and return
1790 // the register number (or zero if we failed to handle it).
1791 unsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) {
1792 // No plans to handle long double here.
1793 if (VT != MVT::f32 && VT != MVT::f64)
1796 // All FP constants are loaded from the constant pool.
1797 unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
1798 assert(Align > 0 && "Unexpectedly missing alignment information!");
1799 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
1800 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
1801 CodeModel::Model CModel = TM.getCodeModel();
1803 MachineMemOperand *MMO =
1804 FuncInfo.MF->getMachineMemOperand(
1805 MachinePointerInfo::getConstantPool(), MachineMemOperand::MOLoad,
1806 (VT == MVT::f32) ? 4 : 8, Align);
1808 unsigned Opc = (VT == MVT::f32) ? PPC::LFS : PPC::LFD;
1809 unsigned TmpReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
1811 // For small code model, generate a LF[SD](0, LDtocCPT(Idx, X2)).
1812 if (CModel == CodeModel::Small || CModel == CodeModel::JITDefault) {
1813 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::LDtocCPT),
1815 .addConstantPoolIndex(Idx).addReg(PPC::X2);
1816 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
1817 .addImm(0).addReg(TmpReg).addMemOperand(MMO);
1819 // Otherwise we generate LF[SD](Idx[lo], ADDIStocHA(X2, Idx)).
1820 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ADDIStocHA),
1821 TmpReg).addReg(PPC::X2).addConstantPoolIndex(Idx);
1822 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
1823 .addConstantPoolIndex(Idx, 0, PPCII::MO_TOC_LO)
1825 .addMemOperand(MMO);
1831 // Materialize the address of a global value into a register, and return
1832 // the register number (or zero if we failed to handle it).
1833 unsigned PPCFastISel::PPCMaterializeGV(const GlobalValue *GV, MVT VT) {
1834 assert(VT == MVT::i64 && "Non-address!");
1835 const TargetRegisterClass *RC = &PPC::G8RC_and_G8RC_NOX0RegClass;
1836 unsigned DestReg = createResultReg(RC);
1838 // Global values may be plain old object addresses, TLS object
1839 // addresses, constant pool entries, or jump tables. How we generate
1840 // code for these may depend on small, medium, or large code model.
1841 CodeModel::Model CModel = TM.getCodeModel();
1843 // FIXME: Jump tables are not yet required because fast-isel doesn't
1844 // handle switches; if that changes, we need them as well. For now,
1845 // what follows assumes everything's a generic (or TLS) global address.
1846 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
1848 // If GV is an alias, use the aliasee for determining thread-locality.
1849 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
1850 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false));
1853 // FIXME: We don't yet handle the complexity of TLS.
1854 bool IsTLS = GVar && GVar->isThreadLocal();
1858 // For small code model, generate a simple TOC load.
1859 if (CModel == CodeModel::Small || CModel == CodeModel::JITDefault)
1860 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::LDtoc), DestReg)
1861 .addGlobalAddress(GV).addReg(PPC::X2);
1863 // If the address is an externally defined symbol, a symbol with
1864 // common or externally available linkage, a function address, or a
1865 // jump table address (not yet needed), or if we are generating code
1866 // for large code model, we generate:
1867 // LDtocL(GV, ADDIStocHA(%X2, GV))
1868 // Otherwise we generate:
1869 // ADDItocL(ADDIStocHA(%X2, GV), GV)
1870 // Either way, start with the ADDIStocHA:
1871 unsigned HighPartReg = createResultReg(RC);
1872 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ADDIStocHA),
1873 HighPartReg).addReg(PPC::X2).addGlobalAddress(GV);
1875 // !GVar implies a function address. An external variable is one
1876 // without an initializer.
1877 // If/when switches are implemented, jump tables should be handled
1878 // on the "if" path here.
1879 if (CModel == CodeModel::Large || !GVar || !GVar->hasInitializer() ||
1880 GVar->hasCommonLinkage() || GVar->hasAvailableExternallyLinkage())
1881 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::LDtocL),
1882 DestReg).addGlobalAddress(GV).addReg(HighPartReg);
1884 // Otherwise generate the ADDItocL.
1885 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ADDItocL),
1886 DestReg).addReg(HighPartReg).addGlobalAddress(GV);
1892 // Materialize a 32-bit integer constant into a register, and return
1893 // the register number (or zero if we failed to handle it).
1894 unsigned PPCFastISel::PPCMaterialize32BitInt(int64_t Imm,
1895 const TargetRegisterClass *RC) {
1896 unsigned Lo = Imm & 0xFFFF;
1897 unsigned Hi = (Imm >> 16) & 0xFFFF;
1899 unsigned ResultReg = createResultReg(RC);
1900 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
1903 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1904 TII.get(IsGPRC ? PPC::LI : PPC::LI8), ResultReg)
1907 // Both Lo and Hi have nonzero bits.
1908 unsigned TmpReg = createResultReg(RC);
1909 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1910 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), TmpReg)
1912 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1913 TII.get(IsGPRC ? PPC::ORI : PPC::ORI8), ResultReg)
1914 .addReg(TmpReg).addImm(Lo);
1917 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1918 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), ResultReg)
1924 // Materialize a 64-bit integer constant into a register, and return
1925 // the register number (or zero if we failed to handle it).
1926 unsigned PPCFastISel::PPCMaterialize64BitInt(int64_t Imm,
1927 const TargetRegisterClass *RC) {
1928 unsigned Remainder = 0;
1931 // If the value doesn't fit in 32 bits, see if we can shift it
1932 // so that it fits in 32 bits.
1933 if (!isInt<32>(Imm)) {
1934 Shift = countTrailingZeros<uint64_t>(Imm);
1935 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
1937 if (isInt<32>(ImmSh))
1946 // Handle the high-order 32 bits (if shifted) or the whole 32 bits
1947 // (if not shifted).
1948 unsigned TmpReg1 = PPCMaterialize32BitInt(Imm, RC);
1952 // If upper 32 bits were not zero, we've built them and need to shift
1956 TmpReg2 = createResultReg(RC);
1957 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::RLDICR),
1958 TmpReg2).addReg(TmpReg1).addImm(Shift).addImm(63 - Shift);
1962 unsigned TmpReg3, Hi, Lo;
1963 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
1964 TmpReg3 = createResultReg(RC);
1965 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ORIS8),
1966 TmpReg3).addReg(TmpReg2).addImm(Hi);
1970 if ((Lo = Remainder & 0xFFFF)) {
1971 unsigned ResultReg = createResultReg(RC);
1972 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ORI8),
1973 ResultReg).addReg(TmpReg3).addImm(Lo);
1981 // Materialize an integer constant into a register, and return
1982 // the register number (or zero if we failed to handle it).
1983 unsigned PPCFastISel::PPCMaterializeInt(const Constant *C, MVT VT) {
1985 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 &&
1986 VT != MVT::i8 && VT != MVT::i1)
1989 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
1990 &PPC::GPRCRegClass);
1992 // If the constant is in range, use a load-immediate.
1993 const ConstantInt *CI = cast<ConstantInt>(C);
1994 if (isInt<16>(CI->getSExtValue())) {
1995 unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI;
1996 unsigned ImmReg = createResultReg(RC);
1997 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ImmReg)
1998 .addImm(CI->getSExtValue());
2002 // Construct the constant piecewise.
2003 int64_t Imm = CI->getZExtValue();
2006 return PPCMaterialize64BitInt(Imm, RC);
2007 else if (VT == MVT::i32)
2008 return PPCMaterialize32BitInt(Imm, RC);
2013 // Materialize a constant into a register, and return the register
2014 // number (or zero if we failed to handle it).
2015 unsigned PPCFastISel::TargetMaterializeConstant(const Constant *C) {
2016 EVT CEVT = TLI.getValueType(C->getType(), true);
2018 // Only handle simple types.
2019 if (!CEVT.isSimple()) return 0;
2020 MVT VT = CEVT.getSimpleVT();
2022 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
2023 return PPCMaterializeFP(CFP, VT);
2024 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
2025 return PPCMaterializeGV(GV, VT);
2026 else if (isa<ConstantInt>(C))
2027 return PPCMaterializeInt(C, VT);
2028 // TBD: Global values.
2033 // Materialize the address created by an alloca into a register, and
2034 // return the register number (or zero if we failed to handle it). TBD.
2035 unsigned PPCFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
2039 // Fold loads into extends when possible.
2040 // FIXME: We can have multiple redundant extend/trunc instructions
2041 // following a load. The folding only picks up one. Extend this
2042 // to check subsequent instructions for the same pattern and remove
2043 // them. Thus ResultReg should be the def reg for the last redundant
2044 // instruction in a chain, and all intervening instructions can be
2045 // removed from parent. Change test/CodeGen/PowerPC/fast-isel-fold.ll
2046 // to add ELF64-NOT: rldicl to the appropriate tests when this works.
2047 bool PPCFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
2048 const LoadInst *LI) {
2049 // Verify we have a legal type before going any further.
2051 if (!isLoadTypeLegal(LI->getType(), VT))
2054 // Combine load followed by zero- or sign-extend.
2055 bool IsZExt = false;
2056 switch(MI->getOpcode()) {
2061 case PPC::RLDICL_32_64: {
2063 unsigned MB = MI->getOperand(3).getImm();
2064 if ((VT == MVT::i8 && MB <= 56) ||
2065 (VT == MVT::i16 && MB <= 48) ||
2066 (VT == MVT::i32 && MB <= 32))
2072 case PPC::RLWINM8: {
2074 unsigned MB = MI->getOperand(3).getImm();
2075 if ((VT == MVT::i8 && MB <= 24) ||
2076 (VT == MVT::i16 && MB <= 16))
2083 case PPC::EXTSB8_32_64:
2084 /* There is no sign-extending load-byte instruction. */
2089 case PPC::EXTSH8_32_64: {
2090 if (VT != MVT::i16 && VT != MVT::i8)
2096 case PPC::EXTSW_32_64: {
2097 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8)
2103 // See if we can handle this address.
2105 if (!PPCComputeAddress(LI->getOperand(0), Addr))
2108 unsigned ResultReg = MI->getOperand(0).getReg();
2110 if (!PPCEmitLoad(VT, ResultReg, Addr, 0, IsZExt))
2113 MI->eraseFromParent();
2117 // Attempt to lower call arguments in a faster way than done by
2118 // the selection DAG code.
2119 bool PPCFastISel::FastLowerArguments() {
2120 // Defer to normal argument lowering for now. It's reasonably
2121 // efficient. Consider doing something like ARM to handle the
2122 // case where all args fit in registers, no varargs, no float
2127 // Handle materializing integer constants into a register. This is not
2128 // automatically generated for PowerPC, so must be explicitly created here.
2129 unsigned PPCFastISel::FastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) {
2131 if (Opc != ISD::Constant)
2134 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 &&
2135 VT != MVT::i8 && VT != MVT::i1)
2138 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
2139 &PPC::GPRCRegClass);
2141 return PPCMaterialize64BitInt(Imm, RC);
2143 return PPCMaterialize32BitInt(Imm, RC);
2146 // Override for ADDI and ADDI8 to set the correct register class
2147 // on RHS operand 0. The automatic infrastructure naively assumes
2148 // GPRC for i32 and G8RC for i64; the concept of "no R0" is lost
2149 // for these cases. At the moment, none of the other automatically
2150 // generated RI instructions require special treatment. However, once
2151 // SelectSelect is implemented, "isel" requires similar handling.
2153 // Also be conservative about the output register class. Avoid
2154 // assigning R0 or X0 to the output register for GPRC and G8RC
2155 // register classes, as any such result could be used in ADDI, etc.,
2156 // where those regs have another meaning.
2157 unsigned PPCFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
2158 const TargetRegisterClass *RC,
2159 unsigned Op0, bool Op0IsKill,
2161 if (MachineInstOpcode == PPC::ADDI)
2162 MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass);
2163 else if (MachineInstOpcode == PPC::ADDI8)
2164 MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass);
2166 const TargetRegisterClass *UseRC =
2167 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2168 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2170 return FastISel::FastEmitInst_ri(MachineInstOpcode, UseRC,
2171 Op0, Op0IsKill, Imm);
2174 // Override for instructions with one register operand to avoid use of
2175 // R0/X0. The automatic infrastructure isn't aware of the context so
2176 // we must be conservative.
2177 unsigned PPCFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
2178 const TargetRegisterClass* RC,
2179 unsigned Op0, bool Op0IsKill) {
2180 const TargetRegisterClass *UseRC =
2181 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2182 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2184 return FastISel::FastEmitInst_r(MachineInstOpcode, UseRC, Op0, Op0IsKill);
2187 // Override for instructions with two register operands to avoid use
2188 // of R0/X0. The automatic infrastructure isn't aware of the context
2189 // so we must be conservative.
2190 unsigned PPCFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
2191 const TargetRegisterClass* RC,
2192 unsigned Op0, bool Op0IsKill,
2193 unsigned Op1, bool Op1IsKill) {
2194 const TargetRegisterClass *UseRC =
2195 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2196 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2198 return FastISel::FastEmitInst_rr(MachineInstOpcode, UseRC, Op0, Op0IsKill,
2203 // Create the fast instruction selector for PowerPC64 ELF.
2204 FastISel *PPC::createFastISel(FunctionLoweringInfo &FuncInfo,
2205 const TargetLibraryInfo *LibInfo) {
2206 const TargetMachine &TM = FuncInfo.MF->getTarget();
2208 // Only available on 64-bit ELF for now.
2209 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>();
2210 if (Subtarget->isPPC64() && Subtarget->isSVR4ABI())
2211 return new PPCFastISel(FuncInfo, LibInfo);