1 //===-- PPCFastISel.cpp - PowerPC FastISel implementation -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the PowerPC-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // PPCGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "MCTargetDesc/PPCPredicates.h"
18 #include "PPCCallingConv.h"
19 #include "PPCISelLowering.h"
20 #include "PPCMachineFunctionInfo.h"
21 #include "PPCSubtarget.h"
22 #include "PPCTargetMachine.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/IR/CallingConv.h"
32 #include "llvm/IR/GetElementPtrTypeIterator.h"
33 #include "llvm/IR/GlobalAlias.h"
34 #include "llvm/IR/GlobalVariable.h"
35 #include "llvm/IR/IntrinsicInst.h"
36 #include "llvm/IR/Operator.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Target/TargetLowering.h"
39 #include "llvm/Target/TargetMachine.h"
41 //===----------------------------------------------------------------------===//
44 // fastLowerArguments: Handle simple cases.
45 // PPCMaterializeGV: Handle TLS.
46 // SelectCall: Handle function pointers.
47 // SelectCall: Handle multi-register return values.
48 // SelectCall: Optimize away nops for local calls.
49 // processCallArgs: Handle bit-converted arguments.
50 // finishCall: Handle multi-register return values.
51 // PPCComputeAddress: Handle parameter references as FrameIndex's.
52 // PPCEmitCmp: Handle immediate as operand 1.
53 // SelectCall: Handle small byval arguments.
54 // SelectIntrinsicCall: Implement.
55 // SelectSelect: Implement.
56 // Consider factoring isTypeLegal into the base class.
57 // Implement switches and jump tables.
59 //===----------------------------------------------------------------------===//
62 #define DEBUG_TYPE "ppcfastisel"
66 typedef struct Address {
79 // Innocuous defaults for our address.
81 : BaseType(RegBase), Offset(0) {
86 class PPCFastISel final : public FastISel {
88 const TargetMachine &TM;
89 const PPCSubtarget *PPCSubTarget;
90 PPCFunctionInfo *PPCFuncInfo;
91 const TargetInstrInfo &TII;
92 const TargetLowering &TLI;
96 explicit PPCFastISel(FunctionLoweringInfo &FuncInfo,
97 const TargetLibraryInfo *LibInfo)
98 : FastISel(FuncInfo, LibInfo), TM(FuncInfo.MF->getTarget()),
99 PPCSubTarget(&FuncInfo.MF->getSubtarget<PPCSubtarget>()),
100 PPCFuncInfo(FuncInfo.MF->getInfo<PPCFunctionInfo>()),
101 TII(*PPCSubTarget->getInstrInfo()),
102 TLI(*PPCSubTarget->getTargetLowering()),
103 Context(&FuncInfo.Fn->getContext()) {}
105 // Backend specific FastISel code.
107 bool fastSelectInstruction(const Instruction *I) override;
108 unsigned fastMaterializeConstant(const Constant *C) override;
109 unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
110 bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
111 const LoadInst *LI) override;
112 bool fastLowerArguments() override;
113 unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
114 unsigned fastEmitInst_ri(unsigned MachineInstOpcode,
115 const TargetRegisterClass *RC,
116 unsigned Op0, bool Op0IsKill,
118 unsigned fastEmitInst_r(unsigned MachineInstOpcode,
119 const TargetRegisterClass *RC,
120 unsigned Op0, bool Op0IsKill);
121 unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
122 const TargetRegisterClass *RC,
123 unsigned Op0, bool Op0IsKill,
124 unsigned Op1, bool Op1IsKill);
126 bool fastLowerCall(CallLoweringInfo &CLI) override;
128 // Instruction selection routines.
130 bool SelectLoad(const Instruction *I);
131 bool SelectStore(const Instruction *I);
132 bool SelectBranch(const Instruction *I);
133 bool SelectIndirectBr(const Instruction *I);
134 bool SelectFPExt(const Instruction *I);
135 bool SelectFPTrunc(const Instruction *I);
136 bool SelectIToFP(const Instruction *I, bool IsSigned);
137 bool SelectFPToI(const Instruction *I, bool IsSigned);
138 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
139 bool SelectRet(const Instruction *I);
140 bool SelectTrunc(const Instruction *I);
141 bool SelectIntExt(const Instruction *I);
145 bool isTypeLegal(Type *Ty, MVT &VT);
146 bool isLoadTypeLegal(Type *Ty, MVT &VT);
147 bool isValueAvailable(const Value *V) const;
148 bool isVSFRCRegister(unsigned Register) const {
149 return MRI.getRegClass(Register)->getID() == PPC::VSFRCRegClassID;
151 bool isVSSRCRegister(unsigned Register) const {
152 return MRI.getRegClass(Register)->getID() == PPC::VSSRCRegClassID;
154 bool PPCEmitCmp(const Value *Src1Value, const Value *Src2Value,
155 bool isZExt, unsigned DestReg);
156 bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
157 const TargetRegisterClass *RC, bool IsZExt = true,
158 unsigned FP64LoadOpc = PPC::LFD);
159 bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
160 bool PPCComputeAddress(const Value *Obj, Address &Addr);
161 void PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset,
163 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
164 unsigned DestReg, bool IsZExt);
165 unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT);
166 unsigned PPCMaterializeGV(const GlobalValue *GV, MVT VT);
167 unsigned PPCMaterializeInt(const ConstantInt *CI, MVT VT,
168 bool UseSExt = true);
169 unsigned PPCMaterialize32BitInt(int64_t Imm,
170 const TargetRegisterClass *RC);
171 unsigned PPCMaterialize64BitInt(int64_t Imm,
172 const TargetRegisterClass *RC);
173 unsigned PPCMoveToIntReg(const Instruction *I, MVT VT,
174 unsigned SrcReg, bool IsSigned);
175 unsigned PPCMoveToFPReg(MVT VT, unsigned SrcReg, bool IsSigned);
177 // Call handling routines.
179 bool processCallArgs(SmallVectorImpl<Value*> &Args,
180 SmallVectorImpl<unsigned> &ArgRegs,
181 SmallVectorImpl<MVT> &ArgVTs,
182 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
183 SmallVectorImpl<unsigned> &RegArgs,
187 bool finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumBytes);
188 CCAssignFn *usePPC32CCs(unsigned Flag);
191 #include "PPCGenFastISel.inc"
195 } // end anonymous namespace
197 #include "PPCGenCallingConv.inc"
199 // Function whose sole purpose is to kill compiler warnings
200 // stemming from unused functions included from PPCGenCallingConv.inc.
201 CCAssignFn *PPCFastISel::usePPC32CCs(unsigned Flag) {
203 return CC_PPC32_SVR4;
205 return CC_PPC32_SVR4_ByVal;
207 return CC_PPC32_SVR4_VarArg;
212 static Optional<PPC::Predicate> getComparePred(CmpInst::Predicate Pred) {
214 // These are not representable with any single compare.
215 case CmpInst::FCMP_FALSE:
216 case CmpInst::FCMP_UEQ:
217 case CmpInst::FCMP_UGT:
218 case CmpInst::FCMP_UGE:
219 case CmpInst::FCMP_ULT:
220 case CmpInst::FCMP_ULE:
221 case CmpInst::FCMP_UNE:
222 case CmpInst::FCMP_TRUE:
224 return Optional<PPC::Predicate>();
226 case CmpInst::FCMP_OEQ:
227 case CmpInst::ICMP_EQ:
230 case CmpInst::FCMP_OGT:
231 case CmpInst::ICMP_UGT:
232 case CmpInst::ICMP_SGT:
235 case CmpInst::FCMP_OGE:
236 case CmpInst::ICMP_UGE:
237 case CmpInst::ICMP_SGE:
240 case CmpInst::FCMP_OLT:
241 case CmpInst::ICMP_ULT:
242 case CmpInst::ICMP_SLT:
245 case CmpInst::FCMP_OLE:
246 case CmpInst::ICMP_ULE:
247 case CmpInst::ICMP_SLE:
250 case CmpInst::FCMP_ONE:
251 case CmpInst::ICMP_NE:
254 case CmpInst::FCMP_ORD:
257 case CmpInst::FCMP_UNO:
262 // Determine whether the type Ty is simple enough to be handled by
263 // fast-isel, and return its equivalent machine type in VT.
264 // FIXME: Copied directly from ARM -- factor into base class?
265 bool PPCFastISel::isTypeLegal(Type *Ty, MVT &VT) {
266 EVT Evt = TLI.getValueType(DL, Ty, true);
268 // Only handle simple types.
269 if (Evt == MVT::Other || !Evt.isSimple()) return false;
270 VT = Evt.getSimpleVT();
272 // Handle all legal types, i.e. a register that will directly hold this
274 return TLI.isTypeLegal(VT);
277 // Determine whether the type Ty is simple enough to be handled by
278 // fast-isel as a load target, and return its equivalent machine type in VT.
279 bool PPCFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
280 if (isTypeLegal(Ty, VT)) return true;
282 // If this is a type than can be sign or zero-extended to a basic operation
283 // go ahead and accept it now.
284 if (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) {
291 bool PPCFastISel::isValueAvailable(const Value *V) const {
292 if (!isa<Instruction>(V))
295 const auto *I = cast<Instruction>(V);
296 return FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB;
299 // Given a value Obj, create an Address object Addr that represents its
300 // address. Return false if we can't handle it.
301 bool PPCFastISel::PPCComputeAddress(const Value *Obj, Address &Addr) {
302 const User *U = nullptr;
303 unsigned Opcode = Instruction::UserOp1;
304 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
305 // Don't walk into other basic blocks unless the object is an alloca from
306 // another block, otherwise it may not have a virtual register assigned.
307 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
308 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
309 Opcode = I->getOpcode();
312 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
313 Opcode = C->getOpcode();
320 case Instruction::BitCast:
321 // Look through bitcasts.
322 return PPCComputeAddress(U->getOperand(0), Addr);
323 case Instruction::IntToPtr:
324 // Look past no-op inttoptrs.
325 if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
326 TLI.getPointerTy(DL))
327 return PPCComputeAddress(U->getOperand(0), Addr);
329 case Instruction::PtrToInt:
330 // Look past no-op ptrtoints.
331 if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
332 return PPCComputeAddress(U->getOperand(0), Addr);
334 case Instruction::GetElementPtr: {
335 Address SavedAddr = Addr;
336 long TmpOffset = Addr.Offset;
338 // Iterate through the GEP folding the constants into offsets where
340 gep_type_iterator GTI = gep_type_begin(U);
341 for (User::const_op_iterator II = U->op_begin() + 1, IE = U->op_end();
342 II != IE; ++II, ++GTI) {
343 const Value *Op = *II;
344 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
345 const StructLayout *SL = DL.getStructLayout(STy);
346 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
347 TmpOffset += SL->getElementOffset(Idx);
349 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
351 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
352 // Constant-offset addressing.
353 TmpOffset += CI->getSExtValue() * S;
356 if (canFoldAddIntoGEP(U, Op)) {
357 // A compatible add with a constant operand. Fold the constant.
359 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
360 TmpOffset += CI->getSExtValue() * S;
361 // Iterate on the other operand.
362 Op = cast<AddOperator>(Op)->getOperand(0);
366 goto unsupported_gep;
371 // Try to grab the base operand now.
372 Addr.Offset = TmpOffset;
373 if (PPCComputeAddress(U->getOperand(0), Addr)) return true;
375 // We failed, restore everything and try the other options.
381 case Instruction::Alloca: {
382 const AllocaInst *AI = cast<AllocaInst>(Obj);
383 DenseMap<const AllocaInst*, int>::iterator SI =
384 FuncInfo.StaticAllocaMap.find(AI);
385 if (SI != FuncInfo.StaticAllocaMap.end()) {
386 Addr.BaseType = Address::FrameIndexBase;
387 Addr.Base.FI = SI->second;
394 // FIXME: References to parameters fall through to the behavior
395 // below. They should be able to reference a frame index since
396 // they are stored to the stack, so we can get "ld rx, offset(r1)"
397 // instead of "addi ry, r1, offset / ld rx, 0(ry)". Obj will
398 // just contain the parameter. Try to handle this with a FI.
400 // Try to get this in a register if nothing else has worked.
401 if (Addr.Base.Reg == 0)
402 Addr.Base.Reg = getRegForValue(Obj);
404 // Prevent assignment of base register to X0, which is inappropriate
405 // for loads and stores alike.
406 if (Addr.Base.Reg != 0)
407 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass);
409 return Addr.Base.Reg != 0;
412 // Fix up some addresses that can't be used directly. For example, if
413 // an offset won't fit in an instruction field, we may need to move it
414 // into an index register.
415 void PPCFastISel::PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset,
416 unsigned &IndexReg) {
418 // Check whether the offset fits in the instruction field.
419 if (!isInt<16>(Addr.Offset))
422 // If this is a stack pointer and the offset needs to be simplified then
423 // put the alloca address into a register, set the base type back to
424 // register and continue. This should almost never happen.
425 if (!UseOffset && Addr.BaseType == Address::FrameIndexBase) {
426 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
427 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8),
428 ResultReg).addFrameIndex(Addr.Base.FI).addImm(0);
429 Addr.Base.Reg = ResultReg;
430 Addr.BaseType = Address::RegBase;
434 IntegerType *OffsetTy = ((VT == MVT::i32) ? Type::getInt32Ty(*Context)
435 : Type::getInt64Ty(*Context));
436 const ConstantInt *Offset =
437 ConstantInt::getSigned(OffsetTy, (int64_t)(Addr.Offset));
438 IndexReg = PPCMaterializeInt(Offset, MVT::i64);
439 assert(IndexReg && "Unexpected error in PPCMaterializeInt!");
443 // Emit a load instruction if possible, returning true if we succeeded,
444 // otherwise false. See commentary below for how the register class of
445 // the load is determined.
446 bool PPCFastISel::PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
447 const TargetRegisterClass *RC,
448 bool IsZExt, unsigned FP64LoadOpc) {
450 bool UseOffset = true;
452 // If ResultReg is given, it determines the register class of the load.
453 // Otherwise, RC is the register class to use. If the result of the
454 // load isn't anticipated in this block, both may be zero, in which
455 // case we must make a conservative guess. In particular, don't assign
456 // R0 or X0 to the result register, as the result may be used in a load,
457 // store, add-immediate, or isel that won't permit this. (Though
458 // perhaps the spill and reload of live-exit values would handle this?)
459 const TargetRegisterClass *UseRC =
460 (ResultReg ? MRI.getRegClass(ResultReg) :
462 (VT == MVT::f64 ? &PPC::F8RCRegClass :
463 (VT == MVT::f32 ? &PPC::F4RCRegClass :
464 (VT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
465 &PPC::GPRC_and_GPRC_NOR0RegClass)))));
467 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass);
469 switch (VT.SimpleTy) {
470 default: // e.g., vector types not handled
473 Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8;
477 (Is32BitInt ? PPC::LHZ : PPC::LHZ8) :
478 (Is32BitInt ? PPC::LHA : PPC::LHA8));
482 (Is32BitInt ? PPC::LWZ : PPC::LWZ8) :
483 (Is32BitInt ? PPC::LWA_32 : PPC::LWA));
484 if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0))
489 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) &&
490 "64-bit load with 32-bit target??");
491 UseOffset = ((Addr.Offset & 3) == 0);
501 // If necessary, materialize the offset into a register and use
502 // the indexed form. Also handle stack pointers with special needs.
503 unsigned IndexReg = 0;
504 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg);
506 // If this is a potential VSX load with an offset of 0, a VSX indexed load can
508 bool IsVSSRC = (ResultReg != 0) && isVSSRCRegister(ResultReg);
509 bool IsVSFRC = (ResultReg != 0) && isVSFRCRegister(ResultReg);
510 bool Is32VSXLoad = IsVSSRC && Opc == PPC::LFS;
511 bool Is64VSXLoad = IsVSSRC && Opc == PPC::LFD;
512 if ((Is32VSXLoad || Is64VSXLoad) &&
513 (Addr.BaseType != Address::FrameIndexBase) && UseOffset &&
514 (Addr.Offset == 0)) {
519 ResultReg = createResultReg(UseRC);
521 // Note: If we still have a frame index here, we know the offset is
522 // in range, as otherwise PPCSimplifyAddress would have converted it
524 if (Addr.BaseType == Address::FrameIndexBase) {
525 // VSX only provides an indexed load.
526 if (Is32VSXLoad || Is64VSXLoad) return false;
528 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
529 MachinePointerInfo::getFixedStack(*FuncInfo.MF, Addr.Base.FI,
531 MachineMemOperand::MOLoad, MFI.getObjectSize(Addr.Base.FI),
532 MFI.getObjectAlignment(Addr.Base.FI));
534 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
535 .addImm(Addr.Offset).addFrameIndex(Addr.Base.FI).addMemOperand(MMO);
537 // Base reg with offset in range.
538 } else if (UseOffset) {
539 // VSX only provides an indexed load.
540 if (Is32VSXLoad || Is64VSXLoad) return false;
542 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
543 .addImm(Addr.Offset).addReg(Addr.Base.Reg);
547 // Get the RR opcode corresponding to the RI one. FIXME: It would be
548 // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it
549 // is hard to get at.
551 default: llvm_unreachable("Unexpected opcode!");
552 case PPC::LBZ: Opc = PPC::LBZX; break;
553 case PPC::LBZ8: Opc = PPC::LBZX8; break;
554 case PPC::LHZ: Opc = PPC::LHZX; break;
555 case PPC::LHZ8: Opc = PPC::LHZX8; break;
556 case PPC::LHA: Opc = PPC::LHAX; break;
557 case PPC::LHA8: Opc = PPC::LHAX8; break;
558 case PPC::LWZ: Opc = PPC::LWZX; break;
559 case PPC::LWZ8: Opc = PPC::LWZX8; break;
560 case PPC::LWA: Opc = PPC::LWAX; break;
561 case PPC::LWA_32: Opc = PPC::LWAX_32; break;
562 case PPC::LD: Opc = PPC::LDX; break;
563 case PPC::LFS: Opc = IsVSSRC ? PPC::LXSSPX : PPC::LFSX; break;
564 case PPC::LFD: Opc = IsVSFRC ? PPC::LXSDX : PPC::LFDX; break;
566 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
567 .addReg(Addr.Base.Reg).addReg(IndexReg);
573 // Attempt to fast-select a load instruction.
574 bool PPCFastISel::SelectLoad(const Instruction *I) {
575 // FIXME: No atomic loads are supported.
576 if (cast<LoadInst>(I)->isAtomic())
579 // Verify we have a legal type before going any further.
581 if (!isLoadTypeLegal(I->getType(), VT))
584 // See if we can handle this address.
586 if (!PPCComputeAddress(I->getOperand(0), Addr))
589 // Look at the currently assigned register for this instruction
590 // to determine the required register class. This is necessary
591 // to constrain RA from using R0/X0 when this is not legal.
592 unsigned AssignedReg = FuncInfo.ValueMap[I];
593 const TargetRegisterClass *RC =
594 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr;
596 unsigned ResultReg = 0;
597 if (!PPCEmitLoad(VT, ResultReg, Addr, RC))
599 updateValueMap(I, ResultReg);
603 // Emit a store instruction to store SrcReg at Addr.
604 bool PPCFastISel::PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr) {
605 assert(SrcReg && "Nothing to store!");
607 bool UseOffset = true;
609 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg);
610 bool Is32BitInt = RC->hasSuperClassEq(&PPC::GPRCRegClass);
612 switch (VT.SimpleTy) {
613 default: // e.g., vector types not handled
616 Opc = Is32BitInt ? PPC::STB : PPC::STB8;
619 Opc = Is32BitInt ? PPC::STH : PPC::STH8;
622 assert(Is32BitInt && "Not GPRC for i32??");
627 UseOffset = ((Addr.Offset & 3) == 0);
637 // If necessary, materialize the offset into a register and use
638 // the indexed form. Also handle stack pointers with special needs.
639 unsigned IndexReg = 0;
640 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg);
642 // If this is a potential VSX store with an offset of 0, a VSX indexed store
644 bool IsVSSRC = isVSSRCRegister(SrcReg);
645 bool IsVSFRC = isVSFRCRegister(SrcReg);
646 bool Is32VSXStore = IsVSSRC && Opc == PPC::STFS;
647 bool Is64VSXStore = IsVSFRC && Opc == PPC::STFD;
648 if ((Is32VSXStore || Is64VSXStore) &&
649 (Addr.BaseType != Address::FrameIndexBase) && UseOffset &&
650 (Addr.Offset == 0)) {
654 // Note: If we still have a frame index here, we know the offset is
655 // in range, as otherwise PPCSimplifyAddress would have converted it
657 if (Addr.BaseType == Address::FrameIndexBase) {
658 // VSX only provides an indexed store.
659 if (Is32VSXStore || Is64VSXStore) return false;
661 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
662 MachinePointerInfo::getFixedStack(*FuncInfo.MF, Addr.Base.FI,
664 MachineMemOperand::MOStore, MFI.getObjectSize(Addr.Base.FI),
665 MFI.getObjectAlignment(Addr.Base.FI));
667 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
670 .addFrameIndex(Addr.Base.FI)
673 // Base reg with offset in range.
674 } else if (UseOffset) {
675 // VSX only provides an indexed store.
676 if (Is32VSXStore || Is64VSXStore) return false;
678 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
679 .addReg(SrcReg).addImm(Addr.Offset).addReg(Addr.Base.Reg);
683 // Get the RR opcode corresponding to the RI one. FIXME: It would be
684 // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it
685 // is hard to get at.
687 default: llvm_unreachable("Unexpected opcode!");
688 case PPC::STB: Opc = PPC::STBX; break;
689 case PPC::STH : Opc = PPC::STHX; break;
690 case PPC::STW : Opc = PPC::STWX; break;
691 case PPC::STB8: Opc = PPC::STBX8; break;
692 case PPC::STH8: Opc = PPC::STHX8; break;
693 case PPC::STW8: Opc = PPC::STWX8; break;
694 case PPC::STD: Opc = PPC::STDX; break;
695 case PPC::STFS: Opc = IsVSSRC ? PPC::STXSSPX : PPC::STFSX; break;
696 case PPC::STFD: Opc = IsVSFRC ? PPC::STXSDX : PPC::STFDX; break;
699 auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
702 // If we have an index register defined we use it in the store inst,
703 // otherwise we use X0 as base as it makes the vector instructions to
704 // use zero in the computation of the effective address regardless the
705 // content of the register.
707 MIB.addReg(Addr.Base.Reg).addReg(IndexReg);
709 MIB.addReg(PPC::ZERO8).addReg(Addr.Base.Reg);
715 // Attempt to fast-select a store instruction.
716 bool PPCFastISel::SelectStore(const Instruction *I) {
717 Value *Op0 = I->getOperand(0);
720 // FIXME: No atomics loads are supported.
721 if (cast<StoreInst>(I)->isAtomic())
724 // Verify we have a legal type before going any further.
726 if (!isLoadTypeLegal(Op0->getType(), VT))
729 // Get the value to be stored into a register.
730 SrcReg = getRegForValue(Op0);
734 // See if we can handle this address.
736 if (!PPCComputeAddress(I->getOperand(1), Addr))
739 if (!PPCEmitStore(VT, SrcReg, Addr))
745 // Attempt to fast-select a branch instruction.
746 bool PPCFastISel::SelectBranch(const Instruction *I) {
747 const BranchInst *BI = cast<BranchInst>(I);
748 MachineBasicBlock *BrBB = FuncInfo.MBB;
749 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
750 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
752 // For now, just try the simplest case where it's fed by a compare.
753 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
754 if (isValueAvailable(CI)) {
755 Optional<PPC::Predicate> OptPPCPred = getComparePred(CI->getPredicate());
759 PPC::Predicate PPCPred = OptPPCPred.getValue();
761 // Take advantage of fall-through opportunities.
762 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
764 PPCPred = PPC::InvertPredicate(PPCPred);
767 unsigned CondReg = createResultReg(&PPC::CRRCRegClass);
769 if (!PPCEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(),
773 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCC))
774 .addImm(PPCPred).addReg(CondReg).addMBB(TBB);
775 finishCondBranch(BI->getParent(), TBB, FBB);
778 } else if (const ConstantInt *CI =
779 dyn_cast<ConstantInt>(BI->getCondition())) {
780 uint64_t Imm = CI->getZExtValue();
781 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
782 fastEmitBranch(Target, DbgLoc);
786 // FIXME: ARM looks for a case where the block containing the compare
787 // has been split from the block containing the branch. If this happens,
788 // there is a vreg available containing the result of the compare. I'm
789 // not sure we can do much, as we've lost the predicate information with
790 // the compare instruction -- we have a 4-bit CR but don't know which bit
795 // Attempt to emit a compare of the two source values. Signed and unsigned
796 // comparisons are supported. Return false if we can't handle it.
797 bool PPCFastISel::PPCEmitCmp(const Value *SrcValue1, const Value *SrcValue2,
798 bool IsZExt, unsigned DestReg) {
799 Type *Ty = SrcValue1->getType();
800 EVT SrcEVT = TLI.getValueType(DL, Ty, true);
801 if (!SrcEVT.isSimple())
803 MVT SrcVT = SrcEVT.getSimpleVT();
805 if (SrcVT == MVT::i1 && PPCSubTarget->useCRBits())
808 // See if operand 2 is an immediate encodeable in the compare.
809 // FIXME: Operands are not in canonical order at -O0, so an immediate
810 // operand in position 1 is a lost opportunity for now. We are
811 // similar to ARM in this regard.
815 // Only 16-bit integer constants can be represented in compares for
816 // PowerPC. Others will be materialized into a register.
817 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(SrcValue2)) {
818 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
819 SrcVT == MVT::i8 || SrcVT == MVT::i1) {
820 const APInt &CIVal = ConstInt->getValue();
821 Imm = (IsZExt) ? (long)CIVal.getZExtValue() : (long)CIVal.getSExtValue();
822 if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm)))
828 bool NeedsExt = false;
829 switch (SrcVT.SimpleTy) {
830 default: return false;
832 CmpOpc = PPC::FCMPUS;
835 CmpOpc = PPC::FCMPUD;
841 // Intentional fall-through.
844 CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW;
846 CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI;
850 CmpOpc = IsZExt ? PPC::CMPLD : PPC::CMPD;
852 CmpOpc = IsZExt ? PPC::CMPLDI : PPC::CMPDI;
856 unsigned SrcReg1 = getRegForValue(SrcValue1);
860 unsigned SrcReg2 = 0;
862 SrcReg2 = getRegForValue(SrcValue2);
868 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
869 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt))
874 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
875 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt))
882 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
883 .addReg(SrcReg1).addReg(SrcReg2);
885 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
886 .addReg(SrcReg1).addImm(Imm);
891 // Attempt to fast-select a floating-point extend instruction.
892 bool PPCFastISel::SelectFPExt(const Instruction *I) {
893 Value *Src = I->getOperand(0);
894 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
895 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
897 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
900 unsigned SrcReg = getRegForValue(Src);
904 // No code is generated for a FP extend.
905 updateValueMap(I, SrcReg);
909 // Attempt to fast-select a floating-point truncate instruction.
910 bool PPCFastISel::SelectFPTrunc(const Instruction *I) {
911 Value *Src = I->getOperand(0);
912 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
913 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
915 if (SrcVT != MVT::f64 || DestVT != MVT::f32)
918 unsigned SrcReg = getRegForValue(Src);
922 // Round the result to single precision.
923 unsigned DestReg = createResultReg(&PPC::F4RCRegClass);
924 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::FRSP), DestReg)
927 updateValueMap(I, DestReg);
931 // Move an i32 or i64 value in a GPR to an f64 value in an FPR.
932 // FIXME: When direct register moves are implemented (see PowerISA 2.07),
933 // those should be used instead of moving via a stack slot when the
934 // subtarget permits.
935 // FIXME: The code here is sloppy for the 4-byte case. Can use a 4-byte
936 // stack slot and 4-byte store/load sequence. Or just sext the 4-byte
937 // case to 8 bytes which produces tighter code but wastes stack space.
938 unsigned PPCFastISel::PPCMoveToFPReg(MVT SrcVT, unsigned SrcReg,
941 // If necessary, extend 32-bit int to 64-bit.
942 if (SrcVT == MVT::i32) {
943 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass);
944 if (!PPCEmitIntExt(MVT::i32, SrcReg, MVT::i64, TmpReg, !IsSigned))
949 // Get a stack slot 8 bytes wide, aligned on an 8-byte boundary.
951 Addr.BaseType = Address::FrameIndexBase;
952 Addr.Base.FI = MFI.CreateStackObject(8, 8, false);
954 // Store the value from the GPR.
955 if (!PPCEmitStore(MVT::i64, SrcReg, Addr))
958 // Load the integer value into an FPR. The kind of load used depends
959 // on a number of conditions.
960 unsigned LoadOpc = PPC::LFD;
962 if (SrcVT == MVT::i32) {
964 LoadOpc = PPC::LFIWZX;
965 Addr.Offset = (PPCSubTarget->isLittleEndian()) ? 0 : 4;
966 } else if (PPCSubTarget->hasLFIWAX()) {
967 LoadOpc = PPC::LFIWAX;
968 Addr.Offset = (PPCSubTarget->isLittleEndian()) ? 0 : 4;
972 const TargetRegisterClass *RC = &PPC::F8RCRegClass;
973 unsigned ResultReg = 0;
974 if (!PPCEmitLoad(MVT::f64, ResultReg, Addr, RC, !IsSigned, LoadOpc))
980 // Attempt to fast-select an integer-to-floating-point conversion.
981 // FIXME: Once fast-isel has better support for VSX, conversions using
982 // direct moves should be implemented.
983 bool PPCFastISel::SelectIToFP(const Instruction *I, bool IsSigned) {
985 Type *DstTy = I->getType();
986 if (!isTypeLegal(DstTy, DstVT))
989 if (DstVT != MVT::f32 && DstVT != MVT::f64)
992 Value *Src = I->getOperand(0);
993 EVT SrcEVT = TLI.getValueType(DL, Src->getType(), true);
994 if (!SrcEVT.isSimple())
997 MVT SrcVT = SrcEVT.getSimpleVT();
999 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 &&
1000 SrcVT != MVT::i32 && SrcVT != MVT::i64)
1003 unsigned SrcReg = getRegForValue(Src);
1007 // We can only lower an unsigned convert if we have the newer
1008 // floating-point conversion operations.
1009 if (!IsSigned && !PPCSubTarget->hasFPCVT())
1012 // FIXME: For now we require the newer floating-point conversion operations
1013 // (which are present only on P7 and A2 server models) when converting
1014 // to single-precision float. Otherwise we have to generate a lot of
1015 // fiddly code to avoid double rounding. If necessary, the fiddly code
1016 // can be found in PPCTargetLowering::LowerINT_TO_FP().
1017 if (DstVT == MVT::f32 && !PPCSubTarget->hasFPCVT())
1020 // Extend the input if necessary.
1021 if (SrcVT == MVT::i8 || SrcVT == MVT::i16) {
1022 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass);
1023 if (!PPCEmitIntExt(SrcVT, SrcReg, MVT::i64, TmpReg, !IsSigned))
1029 // Move the integer value to an FPR.
1030 unsigned FPReg = PPCMoveToFPReg(SrcVT, SrcReg, IsSigned);
1034 // Determine the opcode for the conversion.
1035 const TargetRegisterClass *RC = &PPC::F8RCRegClass;
1036 unsigned DestReg = createResultReg(RC);
1039 if (DstVT == MVT::f32)
1040 Opc = IsSigned ? PPC::FCFIDS : PPC::FCFIDUS;
1042 Opc = IsSigned ? PPC::FCFID : PPC::FCFIDU;
1044 // Generate the convert.
1045 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1048 updateValueMap(I, DestReg);
1052 // Move the floating-point value in SrcReg into an integer destination
1053 // register, and return the register (or zero if we can't handle it).
1054 // FIXME: When direct register moves are implemented (see PowerISA 2.07),
1055 // those should be used instead of moving via a stack slot when the
1056 // subtarget permits.
1057 unsigned PPCFastISel::PPCMoveToIntReg(const Instruction *I, MVT VT,
1058 unsigned SrcReg, bool IsSigned) {
1059 // Get a stack slot 8 bytes wide, aligned on an 8-byte boundary.
1060 // Note that if have STFIWX available, we could use a 4-byte stack
1061 // slot for i32, but this being fast-isel we'll just go with the
1062 // easiest code gen possible.
1064 Addr.BaseType = Address::FrameIndexBase;
1065 Addr.Base.FI = MFI.CreateStackObject(8, 8, false);
1067 // Store the value from the FPR.
1068 if (!PPCEmitStore(MVT::f64, SrcReg, Addr))
1071 // Reload it into a GPR. If we want an i32, modify the address
1072 // to have a 4-byte offset so we load from the right place.
1076 // Look at the currently assigned register for this instruction
1077 // to determine the required register class.
1078 unsigned AssignedReg = FuncInfo.ValueMap[I];
1079 const TargetRegisterClass *RC =
1080 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr;
1082 unsigned ResultReg = 0;
1083 if (!PPCEmitLoad(VT, ResultReg, Addr, RC, !IsSigned))
1089 // Attempt to fast-select a floating-point-to-integer conversion.
1090 // FIXME: Once fast-isel has better support for VSX, conversions using
1091 // direct moves should be implemented.
1092 bool PPCFastISel::SelectFPToI(const Instruction *I, bool IsSigned) {
1094 Type *DstTy = I->getType();
1095 if (!isTypeLegal(DstTy, DstVT))
1098 if (DstVT != MVT::i32 && DstVT != MVT::i64)
1101 // If we don't have FCTIDUZ and we need it, punt to SelectionDAG.
1102 if (DstVT == MVT::i64 && !IsSigned && !PPCSubTarget->hasFPCVT())
1105 Value *Src = I->getOperand(0);
1106 Type *SrcTy = Src->getType();
1107 if (!isTypeLegal(SrcTy, SrcVT))
1110 if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1113 unsigned SrcReg = getRegForValue(Src);
1117 // Convert f32 to f64 if necessary. This is just a meaningless copy
1118 // to get the register class right. COPY_TO_REGCLASS is needed since
1119 // a COPY from F4RC to F8RC is converted to a F4RC-F4RC copy downstream.
1120 const TargetRegisterClass *InRC = MRI.getRegClass(SrcReg);
1121 if (InRC == &PPC::F4RCRegClass) {
1122 unsigned TmpReg = createResultReg(&PPC::F8RCRegClass);
1123 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1124 TII.get(TargetOpcode::COPY_TO_REGCLASS), TmpReg)
1125 .addReg(SrcReg).addImm(PPC::F8RCRegClassID);
1129 // Determine the opcode for the conversion, which takes place
1130 // entirely within FPRs.
1131 unsigned DestReg = createResultReg(&PPC::F8RCRegClass);
1134 if (DstVT == MVT::i32)
1138 Opc = PPCSubTarget->hasFPCVT() ? PPC::FCTIWUZ : PPC::FCTIDZ;
1140 Opc = IsSigned ? PPC::FCTIDZ : PPC::FCTIDUZ;
1142 // Generate the convert.
1143 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1146 // Now move the integer value from a float register to an integer register.
1147 unsigned IntReg = PPCMoveToIntReg(I, DstVT, DestReg, IsSigned);
1151 updateValueMap(I, IntReg);
1155 // Attempt to fast-select a binary integer operation that isn't already
1156 // handled automatically.
1157 bool PPCFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1158 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1160 // We can get here in the case when we have a binary operation on a non-legal
1161 // type and the target independent selector doesn't know how to handle it.
1162 if (DestVT != MVT::i16 && DestVT != MVT::i8)
1165 // Look at the currently assigned register for this instruction
1166 // to determine the required register class. If there is no register,
1167 // make a conservative choice (don't assign R0).
1168 unsigned AssignedReg = FuncInfo.ValueMap[I];
1169 const TargetRegisterClass *RC =
1170 (AssignedReg ? MRI.getRegClass(AssignedReg) :
1171 &PPC::GPRC_and_GPRC_NOR0RegClass);
1172 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
1175 switch (ISDOpcode) {
1176 default: return false;
1178 Opc = IsGPRC ? PPC::ADD4 : PPC::ADD8;
1181 Opc = IsGPRC ? PPC::OR : PPC::OR8;
1184 Opc = IsGPRC ? PPC::SUBF : PPC::SUBF8;
1188 unsigned ResultReg = createResultReg(RC ? RC : &PPC::G8RCRegClass);
1189 unsigned SrcReg1 = getRegForValue(I->getOperand(0));
1190 if (SrcReg1 == 0) return false;
1192 // Handle case of small immediate operand.
1193 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(1))) {
1194 const APInt &CIVal = ConstInt->getValue();
1195 int Imm = (int)CIVal.getSExtValue();
1197 if (isInt<16>(Imm)) {
1200 llvm_unreachable("Missing case!");
1203 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1207 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
1220 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1229 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
1236 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
1240 updateValueMap(I, ResultReg);
1247 unsigned SrcReg2 = getRegForValue(I->getOperand(1));
1248 if (SrcReg2 == 0) return false;
1250 // Reverse operands for subtract-from.
1251 if (ISDOpcode == ISD::SUB)
1252 std::swap(SrcReg1, SrcReg2);
1254 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1255 .addReg(SrcReg1).addReg(SrcReg2);
1256 updateValueMap(I, ResultReg);
1260 // Handle arguments to a call that we're attempting to fast-select.
1261 // Return false if the arguments are too complex for us at the moment.
1262 bool PPCFastISel::processCallArgs(SmallVectorImpl<Value*> &Args,
1263 SmallVectorImpl<unsigned> &ArgRegs,
1264 SmallVectorImpl<MVT> &ArgVTs,
1265 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1266 SmallVectorImpl<unsigned> &RegArgs,
1270 SmallVector<CCValAssign, 16> ArgLocs;
1271 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, ArgLocs, *Context);
1273 // Reserve space for the linkage area on the stack.
1274 unsigned LinkageSize = PPCSubTarget->getFrameLowering()->getLinkageSize();
1275 CCInfo.AllocateStack(LinkageSize, 8);
1277 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CC_PPC64_ELF_FIS);
1279 // Bail out if we can't handle any of the arguments.
1280 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1281 CCValAssign &VA = ArgLocs[I];
1282 MVT ArgVT = ArgVTs[VA.getValNo()];
1284 // Skip vector arguments for now, as well as long double and
1285 // uint128_t, and anything that isn't passed in a register.
1286 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64 || ArgVT == MVT::i1 ||
1287 !VA.isRegLoc() || VA.needsCustom())
1290 // Skip bit-converted arguments for now.
1291 if (VA.getLocInfo() == CCValAssign::BCvt)
1295 // Get a count of how many bytes are to be pushed onto the stack.
1296 NumBytes = CCInfo.getNextStackOffset();
1298 // The prolog code of the callee may store up to 8 GPR argument registers to
1299 // the stack, allowing va_start to index over them in memory if its varargs.
1300 // Because we cannot tell if this is needed on the caller side, we have to
1301 // conservatively assume that it is needed. As such, make sure we have at
1302 // least enough stack space for the caller to store the 8 GPRs.
1303 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
1304 NumBytes = std::max(NumBytes, LinkageSize + 64);
1306 // Issue CALLSEQ_START.
1307 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1308 TII.get(TII.getCallFrameSetupOpcode()))
1311 // Prepare to assign register arguments. Every argument uses up a
1312 // GPR protocol register even if it's passed in a floating-point
1313 // register (unless we're using the fast calling convention).
1314 unsigned NextGPR = PPC::X3;
1315 unsigned NextFPR = PPC::F1;
1317 // Process arguments.
1318 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1319 CCValAssign &VA = ArgLocs[I];
1320 unsigned Arg = ArgRegs[VA.getValNo()];
1321 MVT ArgVT = ArgVTs[VA.getValNo()];
1323 // Handle argument promotion and bitcasts.
1324 switch (VA.getLocInfo()) {
1326 llvm_unreachable("Unknown loc info!");
1327 case CCValAssign::Full:
1329 case CCValAssign::SExt: {
1330 MVT DestVT = VA.getLocVT();
1331 const TargetRegisterClass *RC =
1332 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1333 unsigned TmpReg = createResultReg(RC);
1334 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/false))
1335 llvm_unreachable("Failed to emit a sext!");
1340 case CCValAssign::AExt:
1341 case CCValAssign::ZExt: {
1342 MVT DestVT = VA.getLocVT();
1343 const TargetRegisterClass *RC =
1344 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1345 unsigned TmpReg = createResultReg(RC);
1346 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/true))
1347 llvm_unreachable("Failed to emit a zext!");
1352 case CCValAssign::BCvt: {
1353 // FIXME: Not yet handled.
1354 llvm_unreachable("Should have bailed before getting here!");
1359 // Copy this argument to the appropriate register.
1361 if (ArgVT == MVT::f32 || ArgVT == MVT::f64) {
1363 if (CC != CallingConv::Fast)
1368 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1369 TII.get(TargetOpcode::COPY), ArgReg).addReg(Arg);
1370 RegArgs.push_back(ArgReg);
1376 // For a call that we've determined we can fast-select, finish the
1377 // call sequence and generate a copy to obtain the return value (if any).
1378 bool PPCFastISel::finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumBytes) {
1379 CallingConv::ID CC = CLI.CallConv;
1381 // Issue CallSEQ_END.
1382 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1383 TII.get(TII.getCallFrameDestroyOpcode()))
1384 .addImm(NumBytes).addImm(0);
1386 // Next, generate a copy to obtain the return value.
1387 // FIXME: No multi-register return values yet, though I don't foresee
1388 // any real difficulties there.
1389 if (RetVT != MVT::isVoid) {
1390 SmallVector<CCValAssign, 16> RVLocs;
1391 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1392 CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1393 CCValAssign &VA = RVLocs[0];
1394 assert(RVLocs.size() == 1 && "No support for multi-reg return values!");
1395 assert(VA.isRegLoc() && "Can only return in registers!");
1397 MVT DestVT = VA.getValVT();
1398 MVT CopyVT = DestVT;
1400 // Ints smaller than a register still arrive in a full 64-bit
1401 // register, so make sure we recognize this.
1402 if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32)
1405 unsigned SourcePhysReg = VA.getLocReg();
1406 unsigned ResultReg = 0;
1408 if (RetVT == CopyVT) {
1409 const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT);
1410 ResultReg = createResultReg(CpyRC);
1412 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1413 TII.get(TargetOpcode::COPY), ResultReg)
1414 .addReg(SourcePhysReg);
1416 // If necessary, round the floating result to single precision.
1417 } else if (CopyVT == MVT::f64) {
1418 ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1419 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::FRSP),
1420 ResultReg).addReg(SourcePhysReg);
1422 // If only the low half of a general register is needed, generate
1423 // a GPRC copy instead of a G8RC copy. (EXTRACT_SUBREG can't be
1424 // used along the fast-isel path (not lowered), and downstream logic
1425 // also doesn't like a direct subreg copy on a physical reg.)
1426 } else if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) {
1427 ResultReg = createResultReg(&PPC::GPRCRegClass);
1428 // Convert physical register from G8RC to GPRC.
1429 SourcePhysReg -= PPC::X0 - PPC::R0;
1430 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1431 TII.get(TargetOpcode::COPY), ResultReg)
1432 .addReg(SourcePhysReg);
1435 assert(ResultReg && "ResultReg unset!");
1436 CLI.InRegs.push_back(SourcePhysReg);
1437 CLI.ResultReg = ResultReg;
1438 CLI.NumResultRegs = 1;
1444 bool PPCFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1445 CallingConv::ID CC = CLI.CallConv;
1446 bool IsTailCall = CLI.IsTailCall;
1447 bool IsVarArg = CLI.IsVarArg;
1448 const Value *Callee = CLI.Callee;
1449 const MCSymbol *Symbol = CLI.Symbol;
1451 if (!Callee && !Symbol)
1454 // Allow SelectionDAG isel to handle tail calls.
1458 // Let SDISel handle vararg functions.
1462 // Handle simple calls for now, with legal return types and
1463 // those that can be extended.
1464 Type *RetTy = CLI.RetTy;
1466 if (RetTy->isVoidTy())
1467 RetVT = MVT::isVoid;
1468 else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
1471 else if (RetVT == MVT::i1 && PPCSubTarget->useCRBits())
1472 // We can't handle boolean returns when CR bits are in use.
1475 // FIXME: No multi-register return values yet.
1476 if (RetVT != MVT::isVoid && RetVT != MVT::i8 && RetVT != MVT::i16 &&
1477 RetVT != MVT::i32 && RetVT != MVT::i64 && RetVT != MVT::f32 &&
1478 RetVT != MVT::f64) {
1479 SmallVector<CCValAssign, 16> RVLocs;
1480 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs, *Context);
1481 CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1482 if (RVLocs.size() > 1)
1486 // Bail early if more than 8 arguments, as we only currently
1487 // handle arguments passed in registers.
1488 unsigned NumArgs = CLI.OutVals.size();
1492 // Set up the argument vectors.
1493 SmallVector<Value*, 8> Args;
1494 SmallVector<unsigned, 8> ArgRegs;
1495 SmallVector<MVT, 8> ArgVTs;
1496 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1498 Args.reserve(NumArgs);
1499 ArgRegs.reserve(NumArgs);
1500 ArgVTs.reserve(NumArgs);
1501 ArgFlags.reserve(NumArgs);
1503 for (unsigned i = 0, ie = NumArgs; i != ie; ++i) {
1504 // Only handle easy calls for now. It would be reasonably easy
1505 // to handle <= 8-byte structures passed ByVal in registers, but we
1506 // have to ensure they are right-justified in the register.
1507 ISD::ArgFlagsTy Flags = CLI.OutFlags[i];
1508 if (Flags.isInReg() || Flags.isSRet() || Flags.isNest() || Flags.isByVal())
1511 Value *ArgValue = CLI.OutVals[i];
1512 Type *ArgTy = ArgValue->getType();
1514 if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8)
1517 if (ArgVT.isVector())
1520 unsigned Arg = getRegForValue(ArgValue);
1524 Args.push_back(ArgValue);
1525 ArgRegs.push_back(Arg);
1526 ArgVTs.push_back(ArgVT);
1527 ArgFlags.push_back(Flags);
1530 // Process the arguments.
1531 SmallVector<unsigned, 8> RegArgs;
1534 if (!processCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
1535 RegArgs, CC, NumBytes, IsVarArg))
1538 MachineInstrBuilder MIB;
1539 // FIXME: No handling for function pointers yet. This requires
1540 // implementing the function descriptor (OPD) setup.
1541 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1543 // patchpoints are a special case; they always dispatch to a pointer value.
1544 // However, we don't actually want to generate the indirect call sequence
1545 // here (that will be generated, as necessary, during asm printing), and
1546 // the call we generate here will be erased by FastISel::selectPatchpoint,
1547 // so don't try very hard...
1548 if (CLI.IsPatchPoint)
1549 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::NOP));
1553 // Build direct call with NOP for TOC restore.
1554 // FIXME: We can and should optimize away the NOP for local calls.
1555 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1556 TII.get(PPC::BL8_NOP));
1558 MIB.addGlobalAddress(GV);
1561 // Add implicit physical register uses to the call.
1562 for (unsigned II = 0, IE = RegArgs.size(); II != IE; ++II)
1563 MIB.addReg(RegArgs[II], RegState::Implicit);
1565 // Direct calls, in both the ELF V1 and V2 ABIs, need the TOC register live
1567 PPCFuncInfo->setUsesTOCBasePtr();
1568 MIB.addReg(PPC::X2, RegState::Implicit);
1570 // Add a register mask with the call-preserved registers. Proper
1571 // defs for return values will be added by setPhysRegsDeadExcept().
1572 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1576 // Finish off the call including any return values.
1577 return finishCall(RetVT, CLI, NumBytes);
1580 // Attempt to fast-select a return instruction.
1581 bool PPCFastISel::SelectRet(const Instruction *I) {
1583 if (!FuncInfo.CanLowerReturn)
1586 const ReturnInst *Ret = cast<ReturnInst>(I);
1587 const Function &F = *I->getParent()->getParent();
1589 // Build a list of return value registers.
1590 SmallVector<unsigned, 4> RetRegs;
1591 CallingConv::ID CC = F.getCallingConv();
1593 if (Ret->getNumOperands() > 0) {
1594 SmallVector<ISD::OutputArg, 4> Outs;
1595 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
1597 // Analyze operands of the call, assigning locations to each operand.
1598 SmallVector<CCValAssign, 16> ValLocs;
1599 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, *Context);
1600 CCInfo.AnalyzeReturn(Outs, RetCC_PPC64_ELF_FIS);
1601 const Value *RV = Ret->getOperand(0);
1603 // FIXME: Only one output register for now.
1604 if (ValLocs.size() > 1)
1607 // Special case for returning a constant integer of any size - materialize
1608 // the constant as an i64 and copy it to the return register.
1609 if (const ConstantInt *CI = dyn_cast<ConstantInt>(RV)) {
1610 CCValAssign &VA = ValLocs[0];
1612 unsigned RetReg = VA.getLocReg();
1613 // We still need to worry about properly extending the sign. For example,
1614 // we could have only a single bit or a constant that needs zero
1615 // extension rather than sign extension. Make sure we pass the return
1616 // value extension property to integer materialization.
1618 PPCMaterializeInt(CI, MVT::i64, VA.getLocInfo() != CCValAssign::ZExt);
1620 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1621 TII.get(TargetOpcode::COPY), RetReg).addReg(SrcReg);
1623 RetRegs.push_back(RetReg);
1626 unsigned Reg = getRegForValue(RV);
1631 // Copy the result values into the output registers.
1632 for (unsigned i = 0; i < ValLocs.size(); ++i) {
1634 CCValAssign &VA = ValLocs[i];
1635 assert(VA.isRegLoc() && "Can only return in registers!");
1636 RetRegs.push_back(VA.getLocReg());
1637 unsigned SrcReg = Reg + VA.getValNo();
1639 EVT RVEVT = TLI.getValueType(DL, RV->getType());
1640 if (!RVEVT.isSimple())
1642 MVT RVVT = RVEVT.getSimpleVT();
1643 MVT DestVT = VA.getLocVT();
1645 if (RVVT != DestVT && RVVT != MVT::i8 &&
1646 RVVT != MVT::i16 && RVVT != MVT::i32)
1649 if (RVVT != DestVT) {
1650 switch (VA.getLocInfo()) {
1652 llvm_unreachable("Unknown loc info!");
1653 case CCValAssign::Full:
1654 llvm_unreachable("Full value assign but types don't match?");
1655 case CCValAssign::AExt:
1656 case CCValAssign::ZExt: {
1657 const TargetRegisterClass *RC =
1658 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1659 unsigned TmpReg = createResultReg(RC);
1660 if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, true))
1665 case CCValAssign::SExt: {
1666 const TargetRegisterClass *RC =
1667 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1668 unsigned TmpReg = createResultReg(RC);
1669 if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, false))
1677 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1678 TII.get(TargetOpcode::COPY), RetRegs[i])
1684 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1685 TII.get(PPC::BLR8));
1687 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1688 MIB.addReg(RetRegs[i], RegState::Implicit);
1693 // Attempt to emit an integer extend of SrcReg into DestReg. Both
1694 // signed and zero extensions are supported. Return false if we
1696 bool PPCFastISel::PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1697 unsigned DestReg, bool IsZExt) {
1698 if (DestVT != MVT::i32 && DestVT != MVT::i64)
1700 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 && SrcVT != MVT::i32)
1703 // Signed extensions use EXTSB, EXTSH, EXTSW.
1706 if (SrcVT == MVT::i8)
1707 Opc = (DestVT == MVT::i32) ? PPC::EXTSB : PPC::EXTSB8_32_64;
1708 else if (SrcVT == MVT::i16)
1709 Opc = (DestVT == MVT::i32) ? PPC::EXTSH : PPC::EXTSH8_32_64;
1711 assert(DestVT == MVT::i64 && "Signed extend from i32 to i32??");
1712 Opc = PPC::EXTSW_32_64;
1714 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1717 // Unsigned 32-bit extensions use RLWINM.
1718 } else if (DestVT == MVT::i32) {
1720 if (SrcVT == MVT::i8)
1723 assert(SrcVT == MVT::i16 && "Unsigned extend from i32 to i32??");
1726 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::RLWINM),
1728 .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB).addImm(/*ME=*/31);
1730 // Unsigned 64-bit extensions use RLDICL (with a 32-bit source).
1733 if (SrcVT == MVT::i8)
1735 else if (SrcVT == MVT::i16)
1739 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1740 TII.get(PPC::RLDICL_32_64), DestReg)
1741 .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB);
1747 // Attempt to fast-select an indirect branch instruction.
1748 bool PPCFastISel::SelectIndirectBr(const Instruction *I) {
1749 unsigned AddrReg = getRegForValue(I->getOperand(0));
1753 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::MTCTR8))
1755 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCTR8));
1757 const IndirectBrInst *IB = cast<IndirectBrInst>(I);
1758 for (const BasicBlock *SuccBB : IB->successors())
1759 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[SuccBB]);
1764 // Attempt to fast-select an integer truncate instruction.
1765 bool PPCFastISel::SelectTrunc(const Instruction *I) {
1766 Value *Src = I->getOperand(0);
1767 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
1768 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1770 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16)
1773 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
1776 unsigned SrcReg = getRegForValue(Src);
1780 // The only interesting case is when we need to switch register classes.
1781 if (SrcVT == MVT::i64) {
1782 unsigned ResultReg = createResultReg(&PPC::GPRCRegClass);
1783 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1784 TII.get(TargetOpcode::COPY),
1785 ResultReg).addReg(SrcReg, 0, PPC::sub_32);
1789 updateValueMap(I, SrcReg);
1793 // Attempt to fast-select an integer extend instruction.
1794 bool PPCFastISel::SelectIntExt(const Instruction *I) {
1795 Type *DestTy = I->getType();
1796 Value *Src = I->getOperand(0);
1797 Type *SrcTy = Src->getType();
1799 bool IsZExt = isa<ZExtInst>(I);
1800 unsigned SrcReg = getRegForValue(Src);
1801 if (!SrcReg) return false;
1803 EVT SrcEVT, DestEVT;
1804 SrcEVT = TLI.getValueType(DL, SrcTy, true);
1805 DestEVT = TLI.getValueType(DL, DestTy, true);
1806 if (!SrcEVT.isSimple())
1808 if (!DestEVT.isSimple())
1811 MVT SrcVT = SrcEVT.getSimpleVT();
1812 MVT DestVT = DestEVT.getSimpleVT();
1814 // If we know the register class needed for the result of this
1815 // instruction, use it. Otherwise pick the register class of the
1816 // correct size that does not contain X0/R0, since we don't know
1817 // whether downstream uses permit that assignment.
1818 unsigned AssignedReg = FuncInfo.ValueMap[I];
1819 const TargetRegisterClass *RC =
1820 (AssignedReg ? MRI.getRegClass(AssignedReg) :
1821 (DestVT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
1822 &PPC::GPRC_and_GPRC_NOR0RegClass));
1823 unsigned ResultReg = createResultReg(RC);
1825 if (!PPCEmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, IsZExt))
1828 updateValueMap(I, ResultReg);
1832 // Attempt to fast-select an instruction that wasn't handled by
1833 // the table-generated machinery.
1834 bool PPCFastISel::fastSelectInstruction(const Instruction *I) {
1836 switch (I->getOpcode()) {
1837 case Instruction::Load:
1838 return SelectLoad(I);
1839 case Instruction::Store:
1840 return SelectStore(I);
1841 case Instruction::Br:
1842 return SelectBranch(I);
1843 case Instruction::IndirectBr:
1844 return SelectIndirectBr(I);
1845 case Instruction::FPExt:
1846 return SelectFPExt(I);
1847 case Instruction::FPTrunc:
1848 return SelectFPTrunc(I);
1849 case Instruction::SIToFP:
1850 return SelectIToFP(I, /*IsSigned*/ true);
1851 case Instruction::UIToFP:
1852 return SelectIToFP(I, /*IsSigned*/ false);
1853 case Instruction::FPToSI:
1854 return SelectFPToI(I, /*IsSigned*/ true);
1855 case Instruction::FPToUI:
1856 return SelectFPToI(I, /*IsSigned*/ false);
1857 case Instruction::Add:
1858 return SelectBinaryIntOp(I, ISD::ADD);
1859 case Instruction::Or:
1860 return SelectBinaryIntOp(I, ISD::OR);
1861 case Instruction::Sub:
1862 return SelectBinaryIntOp(I, ISD::SUB);
1863 case Instruction::Call:
1864 return selectCall(I);
1865 case Instruction::Ret:
1866 return SelectRet(I);
1867 case Instruction::Trunc:
1868 return SelectTrunc(I);
1869 case Instruction::ZExt:
1870 case Instruction::SExt:
1871 return SelectIntExt(I);
1872 // Here add other flavors of Instruction::XXX that automated
1873 // cases don't catch. For example, switches are terminators
1874 // that aren't yet handled.
1881 // Materialize a floating-point constant into a register, and return
1882 // the register number (or zero if we failed to handle it).
1883 unsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) {
1884 // No plans to handle long double here.
1885 if (VT != MVT::f32 && VT != MVT::f64)
1888 // All FP constants are loaded from the constant pool.
1889 unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
1890 assert(Align > 0 && "Unexpectedly missing alignment information!");
1891 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
1892 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
1893 CodeModel::Model CModel = TM.getCodeModel();
1895 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
1896 MachinePointerInfo::getConstantPool(*FuncInfo.MF),
1897 MachineMemOperand::MOLoad, (VT == MVT::f32) ? 4 : 8, Align);
1899 unsigned Opc = (VT == MVT::f32) ? PPC::LFS : PPC::LFD;
1900 unsigned TmpReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
1902 PPCFuncInfo->setUsesTOCBasePtr();
1903 // For small code model, generate a LF[SD](0, LDtocCPT(Idx, X2)).
1904 if (CModel == CodeModel::Small || CModel == CodeModel::JITDefault) {
1905 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocCPT),
1907 .addConstantPoolIndex(Idx).addReg(PPC::X2);
1908 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1909 .addImm(0).addReg(TmpReg).addMemOperand(MMO);
1911 // Otherwise we generate LF[SD](Idx[lo], ADDIStocHA(X2, Idx)).
1912 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA),
1913 TmpReg).addReg(PPC::X2).addConstantPoolIndex(Idx);
1914 // But for large code model, we must generate a LDtocL followed
1916 if (CModel == CodeModel::Large) {
1917 unsigned TmpReg2 = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
1918 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL),
1919 TmpReg2).addConstantPoolIndex(Idx).addReg(TmpReg);
1920 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1921 .addImm(0).addReg(TmpReg2);
1923 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1924 .addConstantPoolIndex(Idx, 0, PPCII::MO_TOC_LO)
1926 .addMemOperand(MMO);
1932 // Materialize the address of a global value into a register, and return
1933 // the register number (or zero if we failed to handle it).
1934 unsigned PPCFastISel::PPCMaterializeGV(const GlobalValue *GV, MVT VT) {
1935 assert(VT == MVT::i64 && "Non-address!");
1936 const TargetRegisterClass *RC = &PPC::G8RC_and_G8RC_NOX0RegClass;
1937 unsigned DestReg = createResultReg(RC);
1939 // Global values may be plain old object addresses, TLS object
1940 // addresses, constant pool entries, or jump tables. How we generate
1941 // code for these may depend on small, medium, or large code model.
1942 CodeModel::Model CModel = TM.getCodeModel();
1944 // FIXME: Jump tables are not yet required because fast-isel doesn't
1945 // handle switches; if that changes, we need them as well. For now,
1946 // what follows assumes everything's a generic (or TLS) global address.
1948 // FIXME: We don't yet handle the complexity of TLS.
1949 if (GV->isThreadLocal())
1952 PPCFuncInfo->setUsesTOCBasePtr();
1953 // For small code model, generate a simple TOC load.
1954 if (CModel == CodeModel::Small || CModel == CodeModel::JITDefault)
1955 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtoc),
1957 .addGlobalAddress(GV)
1960 // If the address is an externally defined symbol, a symbol with common
1961 // or externally available linkage, a non-local function address, or a
1962 // jump table address (not yet needed), or if we are generating code
1963 // for large code model, we generate:
1964 // LDtocL(GV, ADDIStocHA(%X2, GV))
1965 // Otherwise we generate:
1966 // ADDItocL(ADDIStocHA(%X2, GV), GV)
1967 // Either way, start with the ADDIStocHA:
1968 unsigned HighPartReg = createResultReg(RC);
1969 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA),
1970 HighPartReg).addReg(PPC::X2).addGlobalAddress(GV);
1972 unsigned char GVFlags = PPCSubTarget->classifyGlobalReference(GV);
1973 if (GVFlags & PPCII::MO_NLP_FLAG) {
1974 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL),
1975 DestReg).addGlobalAddress(GV).addReg(HighPartReg);
1977 // Otherwise generate the ADDItocL.
1978 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDItocL),
1979 DestReg).addReg(HighPartReg).addGlobalAddress(GV);
1986 // Materialize a 32-bit integer constant into a register, and return
1987 // the register number (or zero if we failed to handle it).
1988 unsigned PPCFastISel::PPCMaterialize32BitInt(int64_t Imm,
1989 const TargetRegisterClass *RC) {
1990 unsigned Lo = Imm & 0xFFFF;
1991 unsigned Hi = (Imm >> 16) & 0xFFFF;
1993 unsigned ResultReg = createResultReg(RC);
1994 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
1997 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1998 TII.get(IsGPRC ? PPC::LI : PPC::LI8), ResultReg)
2001 // Both Lo and Hi have nonzero bits.
2002 unsigned TmpReg = createResultReg(RC);
2003 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2004 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), TmpReg)
2006 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2007 TII.get(IsGPRC ? PPC::ORI : PPC::ORI8), ResultReg)
2008 .addReg(TmpReg).addImm(Lo);
2011 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2012 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), ResultReg)
2018 // Materialize a 64-bit integer constant into a register, and return
2019 // the register number (or zero if we failed to handle it).
2020 unsigned PPCFastISel::PPCMaterialize64BitInt(int64_t Imm,
2021 const TargetRegisterClass *RC) {
2022 unsigned Remainder = 0;
2025 // If the value doesn't fit in 32 bits, see if we can shift it
2026 // so that it fits in 32 bits.
2027 if (!isInt<32>(Imm)) {
2028 Shift = countTrailingZeros<uint64_t>(Imm);
2029 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
2031 if (isInt<32>(ImmSh))
2040 // Handle the high-order 32 bits (if shifted) or the whole 32 bits
2041 // (if not shifted).
2042 unsigned TmpReg1 = PPCMaterialize32BitInt(Imm, RC);
2046 // If upper 32 bits were not zero, we've built them and need to shift
2050 TmpReg2 = createResultReg(RC);
2051 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::RLDICR),
2052 TmpReg2).addReg(TmpReg1).addImm(Shift).addImm(63 - Shift);
2056 unsigned TmpReg3, Hi, Lo;
2057 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
2058 TmpReg3 = createResultReg(RC);
2059 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ORIS8),
2060 TmpReg3).addReg(TmpReg2).addImm(Hi);
2064 if ((Lo = Remainder & 0xFFFF)) {
2065 unsigned ResultReg = createResultReg(RC);
2066 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ORI8),
2067 ResultReg).addReg(TmpReg3).addImm(Lo);
2075 // Materialize an integer constant into a register, and return
2076 // the register number (or zero if we failed to handle it).
2077 unsigned PPCFastISel::PPCMaterializeInt(const ConstantInt *CI, MVT VT,
2079 // If we're using CR bit registers for i1 values, handle that as a special
2081 if (VT == MVT::i1 && PPCSubTarget->useCRBits()) {
2082 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass);
2083 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2084 TII.get(CI->isZero() ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2088 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 &&
2089 VT != MVT::i8 && VT != MVT::i1)
2092 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
2093 &PPC::GPRCRegClass);
2094 int64_t Imm = UseSExt ? CI->getSExtValue() : CI->getZExtValue();
2096 // If the constant is in range, use a load-immediate.
2097 // Since LI will sign extend the constant we need to make sure that for
2098 // our zeroext constants that the sign extended constant fits into 16-bits -
2099 // a range of 0..0x7fff.
2100 if (isInt<16>(Imm)) {
2101 unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI;
2102 unsigned ImmReg = createResultReg(RC);
2103 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ImmReg)
2108 // Construct the constant piecewise.
2110 return PPCMaterialize64BitInt(Imm, RC);
2111 else if (VT == MVT::i32)
2112 return PPCMaterialize32BitInt(Imm, RC);
2117 // Materialize a constant into a register, and return the register
2118 // number (or zero if we failed to handle it).
2119 unsigned PPCFastISel::fastMaterializeConstant(const Constant *C) {
2120 EVT CEVT = TLI.getValueType(DL, C->getType(), true);
2122 // Only handle simple types.
2123 if (!CEVT.isSimple()) return 0;
2124 MVT VT = CEVT.getSimpleVT();
2126 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
2127 return PPCMaterializeFP(CFP, VT);
2128 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
2129 return PPCMaterializeGV(GV, VT);
2130 else if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
2131 return PPCMaterializeInt(CI, VT, VT != MVT::i1);
2136 // Materialize the address created by an alloca into a register, and
2137 // return the register number (or zero if we failed to handle it).
2138 unsigned PPCFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
2139 // Don't handle dynamic allocas.
2140 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
2143 if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
2145 DenseMap<const AllocaInst*, int>::iterator SI =
2146 FuncInfo.StaticAllocaMap.find(AI);
2148 if (SI != FuncInfo.StaticAllocaMap.end()) {
2149 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
2150 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8),
2151 ResultReg).addFrameIndex(SI->second).addImm(0);
2158 // Fold loads into extends when possible.
2159 // FIXME: We can have multiple redundant extend/trunc instructions
2160 // following a load. The folding only picks up one. Extend this
2161 // to check subsequent instructions for the same pattern and remove
2162 // them. Thus ResultReg should be the def reg for the last redundant
2163 // instruction in a chain, and all intervening instructions can be
2164 // removed from parent. Change test/CodeGen/PowerPC/fast-isel-fold.ll
2165 // to add ELF64-NOT: rldicl to the appropriate tests when this works.
2166 bool PPCFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
2167 const LoadInst *LI) {
2168 // Verify we have a legal type before going any further.
2170 if (!isLoadTypeLegal(LI->getType(), VT))
2173 // Combine load followed by zero- or sign-extend.
2174 bool IsZExt = false;
2175 switch(MI->getOpcode()) {
2180 case PPC::RLDICL_32_64: {
2182 unsigned MB = MI->getOperand(3).getImm();
2183 if ((VT == MVT::i8 && MB <= 56) ||
2184 (VT == MVT::i16 && MB <= 48) ||
2185 (VT == MVT::i32 && MB <= 32))
2191 case PPC::RLWINM8: {
2193 unsigned MB = MI->getOperand(3).getImm();
2194 if ((VT == MVT::i8 && MB <= 24) ||
2195 (VT == MVT::i16 && MB <= 16))
2202 case PPC::EXTSB8_32_64:
2203 /* There is no sign-extending load-byte instruction. */
2208 case PPC::EXTSH8_32_64: {
2209 if (VT != MVT::i16 && VT != MVT::i8)
2215 case PPC::EXTSW_32_64: {
2216 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8)
2222 // See if we can handle this address.
2224 if (!PPCComputeAddress(LI->getOperand(0), Addr))
2227 unsigned ResultReg = MI->getOperand(0).getReg();
2229 if (!PPCEmitLoad(VT, ResultReg, Addr, nullptr, IsZExt))
2232 MI->eraseFromParent();
2236 // Attempt to lower call arguments in a faster way than done by
2237 // the selection DAG code.
2238 bool PPCFastISel::fastLowerArguments() {
2239 // Defer to normal argument lowering for now. It's reasonably
2240 // efficient. Consider doing something like ARM to handle the
2241 // case where all args fit in registers, no varargs, no float
2246 // Handle materializing integer constants into a register. This is not
2247 // automatically generated for PowerPC, so must be explicitly created here.
2248 unsigned PPCFastISel::fastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) {
2250 if (Opc != ISD::Constant)
2253 // If we're using CR bit registers for i1 values, handle that as a special
2255 if (VT == MVT::i1 && PPCSubTarget->useCRBits()) {
2256 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass);
2257 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2258 TII.get(Imm == 0 ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2262 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 &&
2263 VT != MVT::i8 && VT != MVT::i1)
2266 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
2267 &PPC::GPRCRegClass);
2269 return PPCMaterialize64BitInt(Imm, RC);
2271 return PPCMaterialize32BitInt(Imm, RC);
2274 // Override for ADDI and ADDI8 to set the correct register class
2275 // on RHS operand 0. The automatic infrastructure naively assumes
2276 // GPRC for i32 and G8RC for i64; the concept of "no R0" is lost
2277 // for these cases. At the moment, none of the other automatically
2278 // generated RI instructions require special treatment. However, once
2279 // SelectSelect is implemented, "isel" requires similar handling.
2281 // Also be conservative about the output register class. Avoid
2282 // assigning R0 or X0 to the output register for GPRC and G8RC
2283 // register classes, as any such result could be used in ADDI, etc.,
2284 // where those regs have another meaning.
2285 unsigned PPCFastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
2286 const TargetRegisterClass *RC,
2287 unsigned Op0, bool Op0IsKill,
2289 if (MachineInstOpcode == PPC::ADDI)
2290 MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass);
2291 else if (MachineInstOpcode == PPC::ADDI8)
2292 MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass);
2294 const TargetRegisterClass *UseRC =
2295 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2296 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2298 return FastISel::fastEmitInst_ri(MachineInstOpcode, UseRC,
2299 Op0, Op0IsKill, Imm);
2302 // Override for instructions with one register operand to avoid use of
2303 // R0/X0. The automatic infrastructure isn't aware of the context so
2304 // we must be conservative.
2305 unsigned PPCFastISel::fastEmitInst_r(unsigned MachineInstOpcode,
2306 const TargetRegisterClass* RC,
2307 unsigned Op0, bool Op0IsKill) {
2308 const TargetRegisterClass *UseRC =
2309 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2310 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2312 return FastISel::fastEmitInst_r(MachineInstOpcode, UseRC, Op0, Op0IsKill);
2315 // Override for instructions with two register operands to avoid use
2316 // of R0/X0. The automatic infrastructure isn't aware of the context
2317 // so we must be conservative.
2318 unsigned PPCFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
2319 const TargetRegisterClass* RC,
2320 unsigned Op0, bool Op0IsKill,
2321 unsigned Op1, bool Op1IsKill) {
2322 const TargetRegisterClass *UseRC =
2323 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2324 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2326 return FastISel::fastEmitInst_rr(MachineInstOpcode, UseRC, Op0, Op0IsKill,
2331 // Create the fast instruction selector for PowerPC64 ELF.
2332 FastISel *PPC::createFastISel(FunctionLoweringInfo &FuncInfo,
2333 const TargetLibraryInfo *LibInfo) {
2334 // Only available on 64-bit ELF for now.
2335 const PPCSubtarget &Subtarget = FuncInfo.MF->getSubtarget<PPCSubtarget>();
2336 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI())
2337 return new PPCFastISel(FuncInfo, LibInfo);