1 //===-- PPCFastISel.cpp - PowerPC FastISel implementation -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the PowerPC-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // PPCGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "MCTargetDesc/PPCPredicates.h"
18 #include "PPCISelLowering.h"
19 #include "PPCSubtarget.h"
20 #include "PPCTargetMachine.h"
21 #include "llvm/ADT/Optional.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/FastISel.h"
24 #include "llvm/CodeGen/FunctionLoweringInfo.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/IR/CallingConv.h"
30 #include "llvm/IR/GetElementPtrTypeIterator.h"
31 #include "llvm/IR/GlobalAlias.h"
32 #include "llvm/IR/GlobalVariable.h"
33 #include "llvm/IR/IntrinsicInst.h"
34 #include "llvm/IR/Operator.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Target/TargetLowering.h"
37 #include "llvm/Target/TargetMachine.h"
39 //===----------------------------------------------------------------------===//
42 // FastLowerArguments: Handle simple cases.
43 // PPCMaterializeGV: Handle TLS.
44 // SelectCall: Handle function pointers.
45 // SelectCall: Handle multi-register return values.
46 // SelectCall: Optimize away nops for local calls.
47 // processCallArgs: Handle bit-converted arguments.
48 // finishCall: Handle multi-register return values.
49 // PPCComputeAddress: Handle parameter references as FrameIndex's.
50 // PPCEmitCmp: Handle immediate as operand 1.
51 // SelectCall: Handle small byval arguments.
52 // SelectIntrinsicCall: Implement.
53 // SelectSelect: Implement.
54 // Consider factoring isTypeLegal into the base class.
55 // Implement switches and jump tables.
57 //===----------------------------------------------------------------------===//
60 #define DEBUG_TYPE "ppcfastisel"
64 typedef struct Address {
77 // Innocuous defaults for our address.
79 : BaseType(RegBase), Offset(0) {
84 class PPCFastISel final : public FastISel {
86 const TargetMachine &TM;
87 const TargetInstrInfo &TII;
88 const TargetLowering &TLI;
89 const PPCSubtarget *PPCSubTarget;
93 explicit PPCFastISel(FunctionLoweringInfo &FuncInfo,
94 const TargetLibraryInfo *LibInfo)
95 : FastISel(FuncInfo, LibInfo),
96 TM(FuncInfo.MF->getTarget()),
97 TII(*TM.getInstrInfo()),
98 TLI(*TM.getTargetLowering()),
99 PPCSubTarget(&TM.getSubtarget<PPCSubtarget>()),
100 Context(&FuncInfo.Fn->getContext()) { }
102 // Backend specific FastISel code.
104 bool TargetSelectInstruction(const Instruction *I) override;
105 unsigned TargetMaterializeConstant(const Constant *C) override;
106 unsigned TargetMaterializeAlloca(const AllocaInst *AI) override;
107 bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
108 const LoadInst *LI) override;
109 bool FastLowerArguments() override;
110 unsigned FastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
111 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
112 const TargetRegisterClass *RC,
113 unsigned Op0, bool Op0IsKill,
115 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
116 const TargetRegisterClass *RC,
117 unsigned Op0, bool Op0IsKill);
118 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
119 const TargetRegisterClass *RC,
120 unsigned Op0, bool Op0IsKill,
121 unsigned Op1, bool Op1IsKill);
123 // Instruction selection routines.
125 bool SelectLoad(const Instruction *I);
126 bool SelectStore(const Instruction *I);
127 bool SelectBranch(const Instruction *I);
128 bool SelectIndirectBr(const Instruction *I);
129 bool SelectFPExt(const Instruction *I);
130 bool SelectFPTrunc(const Instruction *I);
131 bool SelectIToFP(const Instruction *I, bool IsSigned);
132 bool SelectFPToI(const Instruction *I, bool IsSigned);
133 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
134 bool SelectCall(const Instruction *I);
135 bool SelectRet(const Instruction *I);
136 bool SelectTrunc(const Instruction *I);
137 bool SelectIntExt(const Instruction *I);
141 bool isTypeLegal(Type *Ty, MVT &VT);
142 bool isLoadTypeLegal(Type *Ty, MVT &VT);
143 bool PPCEmitCmp(const Value *Src1Value, const Value *Src2Value,
144 bool isZExt, unsigned DestReg);
145 bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
146 const TargetRegisterClass *RC, bool IsZExt = true,
147 unsigned FP64LoadOpc = PPC::LFD);
148 bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
149 bool PPCComputeAddress(const Value *Obj, Address &Addr);
150 void PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset,
152 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
153 unsigned DestReg, bool IsZExt);
154 unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT);
155 unsigned PPCMaterializeGV(const GlobalValue *GV, MVT VT);
156 unsigned PPCMaterializeInt(const Constant *C, MVT VT);
157 unsigned PPCMaterialize32BitInt(int64_t Imm,
158 const TargetRegisterClass *RC);
159 unsigned PPCMaterialize64BitInt(int64_t Imm,
160 const TargetRegisterClass *RC);
161 unsigned PPCMoveToIntReg(const Instruction *I, MVT VT,
162 unsigned SrcReg, bool IsSigned);
163 unsigned PPCMoveToFPReg(MVT VT, unsigned SrcReg, bool IsSigned);
165 // Call handling routines.
167 bool processCallArgs(SmallVectorImpl<Value*> &Args,
168 SmallVectorImpl<unsigned> &ArgRegs,
169 SmallVectorImpl<MVT> &ArgVTs,
170 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
171 SmallVectorImpl<unsigned> &RegArgs,
175 void finishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
176 const Instruction *I, CallingConv::ID CC,
177 unsigned &NumBytes, bool IsVarArg);
178 CCAssignFn *usePPC32CCs(unsigned Flag);
181 #include "PPCGenFastISel.inc"
185 } // end anonymous namespace
187 #include "PPCGenCallingConv.inc"
189 // Function whose sole purpose is to kill compiler warnings
190 // stemming from unused functions included from PPCGenCallingConv.inc.
191 CCAssignFn *PPCFastISel::usePPC32CCs(unsigned Flag) {
193 return CC_PPC32_SVR4;
195 return CC_PPC32_SVR4_ByVal;
197 return CC_PPC32_SVR4_VarArg;
202 static Optional<PPC::Predicate> getComparePred(CmpInst::Predicate Pred) {
204 // These are not representable with any single compare.
205 case CmpInst::FCMP_FALSE:
206 case CmpInst::FCMP_UEQ:
207 case CmpInst::FCMP_UGT:
208 case CmpInst::FCMP_UGE:
209 case CmpInst::FCMP_ULT:
210 case CmpInst::FCMP_ULE:
211 case CmpInst::FCMP_UNE:
212 case CmpInst::FCMP_TRUE:
214 return Optional<PPC::Predicate>();
216 case CmpInst::FCMP_OEQ:
217 case CmpInst::ICMP_EQ:
220 case CmpInst::FCMP_OGT:
221 case CmpInst::ICMP_UGT:
222 case CmpInst::ICMP_SGT:
225 case CmpInst::FCMP_OGE:
226 case CmpInst::ICMP_UGE:
227 case CmpInst::ICMP_SGE:
230 case CmpInst::FCMP_OLT:
231 case CmpInst::ICMP_ULT:
232 case CmpInst::ICMP_SLT:
235 case CmpInst::FCMP_OLE:
236 case CmpInst::ICMP_ULE:
237 case CmpInst::ICMP_SLE:
240 case CmpInst::FCMP_ONE:
241 case CmpInst::ICMP_NE:
244 case CmpInst::FCMP_ORD:
247 case CmpInst::FCMP_UNO:
252 // Determine whether the type Ty is simple enough to be handled by
253 // fast-isel, and return its equivalent machine type in VT.
254 // FIXME: Copied directly from ARM -- factor into base class?
255 bool PPCFastISel::isTypeLegal(Type *Ty, MVT &VT) {
256 EVT Evt = TLI.getValueType(Ty, true);
258 // Only handle simple types.
259 if (Evt == MVT::Other || !Evt.isSimple()) return false;
260 VT = Evt.getSimpleVT();
262 // Handle all legal types, i.e. a register that will directly hold this
264 return TLI.isTypeLegal(VT);
267 // Determine whether the type Ty is simple enough to be handled by
268 // fast-isel as a load target, and return its equivalent machine type in VT.
269 bool PPCFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
270 if (isTypeLegal(Ty, VT)) return true;
272 // If this is a type than can be sign or zero-extended to a basic operation
273 // go ahead and accept it now.
274 if (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) {
281 // Given a value Obj, create an Address object Addr that represents its
282 // address. Return false if we can't handle it.
283 bool PPCFastISel::PPCComputeAddress(const Value *Obj, Address &Addr) {
284 const User *U = nullptr;
285 unsigned Opcode = Instruction::UserOp1;
286 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
287 // Don't walk into other basic blocks unless the object is an alloca from
288 // another block, otherwise it may not have a virtual register assigned.
289 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
290 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
291 Opcode = I->getOpcode();
294 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
295 Opcode = C->getOpcode();
302 case Instruction::BitCast:
303 // Look through bitcasts.
304 return PPCComputeAddress(U->getOperand(0), Addr);
305 case Instruction::IntToPtr:
306 // Look past no-op inttoptrs.
307 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
308 return PPCComputeAddress(U->getOperand(0), Addr);
310 case Instruction::PtrToInt:
311 // Look past no-op ptrtoints.
312 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
313 return PPCComputeAddress(U->getOperand(0), Addr);
315 case Instruction::GetElementPtr: {
316 Address SavedAddr = Addr;
317 long TmpOffset = Addr.Offset;
319 // Iterate through the GEP folding the constants into offsets where
321 gep_type_iterator GTI = gep_type_begin(U);
322 for (User::const_op_iterator II = U->op_begin() + 1, IE = U->op_end();
323 II != IE; ++II, ++GTI) {
324 const Value *Op = *II;
325 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
326 const StructLayout *SL = DL.getStructLayout(STy);
327 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
328 TmpOffset += SL->getElementOffset(Idx);
330 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
332 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
333 // Constant-offset addressing.
334 TmpOffset += CI->getSExtValue() * S;
337 if (canFoldAddIntoGEP(U, Op)) {
338 // A compatible add with a constant operand. Fold the constant.
340 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
341 TmpOffset += CI->getSExtValue() * S;
342 // Iterate on the other operand.
343 Op = cast<AddOperator>(Op)->getOperand(0);
347 goto unsupported_gep;
352 // Try to grab the base operand now.
353 Addr.Offset = TmpOffset;
354 if (PPCComputeAddress(U->getOperand(0), Addr)) return true;
356 // We failed, restore everything and try the other options.
362 case Instruction::Alloca: {
363 const AllocaInst *AI = cast<AllocaInst>(Obj);
364 DenseMap<const AllocaInst*, int>::iterator SI =
365 FuncInfo.StaticAllocaMap.find(AI);
366 if (SI != FuncInfo.StaticAllocaMap.end()) {
367 Addr.BaseType = Address::FrameIndexBase;
368 Addr.Base.FI = SI->second;
375 // FIXME: References to parameters fall through to the behavior
376 // below. They should be able to reference a frame index since
377 // they are stored to the stack, so we can get "ld rx, offset(r1)"
378 // instead of "addi ry, r1, offset / ld rx, 0(ry)". Obj will
379 // just contain the parameter. Try to handle this with a FI.
381 // Try to get this in a register if nothing else has worked.
382 if (Addr.Base.Reg == 0)
383 Addr.Base.Reg = getRegForValue(Obj);
385 // Prevent assignment of base register to X0, which is inappropriate
386 // for loads and stores alike.
387 if (Addr.Base.Reg != 0)
388 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass);
390 return Addr.Base.Reg != 0;
393 // Fix up some addresses that can't be used directly. For example, if
394 // an offset won't fit in an instruction field, we may need to move it
395 // into an index register.
396 void PPCFastISel::PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset,
397 unsigned &IndexReg) {
399 // Check whether the offset fits in the instruction field.
400 if (!isInt<16>(Addr.Offset))
403 // If this is a stack pointer and the offset needs to be simplified then
404 // put the alloca address into a register, set the base type back to
405 // register and continue. This should almost never happen.
406 if (!UseOffset && Addr.BaseType == Address::FrameIndexBase) {
407 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
408 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8),
409 ResultReg).addFrameIndex(Addr.Base.FI).addImm(0);
410 Addr.Base.Reg = ResultReg;
411 Addr.BaseType = Address::RegBase;
415 IntegerType *OffsetTy = ((VT == MVT::i32) ? Type::getInt32Ty(*Context)
416 : Type::getInt64Ty(*Context));
417 const ConstantInt *Offset =
418 ConstantInt::getSigned(OffsetTy, (int64_t)(Addr.Offset));
419 IndexReg = PPCMaterializeInt(Offset, MVT::i64);
420 assert(IndexReg && "Unexpected error in PPCMaterializeInt!");
424 // Emit a load instruction if possible, returning true if we succeeded,
425 // otherwise false. See commentary below for how the register class of
426 // the load is determined.
427 bool PPCFastISel::PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
428 const TargetRegisterClass *RC,
429 bool IsZExt, unsigned FP64LoadOpc) {
431 bool UseOffset = true;
433 // If ResultReg is given, it determines the register class of the load.
434 // Otherwise, RC is the register class to use. If the result of the
435 // load isn't anticipated in this block, both may be zero, in which
436 // case we must make a conservative guess. In particular, don't assign
437 // R0 or X0 to the result register, as the result may be used in a load,
438 // store, add-immediate, or isel that won't permit this. (Though
439 // perhaps the spill and reload of live-exit values would handle this?)
440 const TargetRegisterClass *UseRC =
441 (ResultReg ? MRI.getRegClass(ResultReg) :
443 (VT == MVT::f64 ? &PPC::F8RCRegClass :
444 (VT == MVT::f32 ? &PPC::F4RCRegClass :
445 (VT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
446 &PPC::GPRC_and_GPRC_NOR0RegClass)))));
448 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass);
450 switch (VT.SimpleTy) {
451 default: // e.g., vector types not handled
454 Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8;
458 (Is32BitInt ? PPC::LHZ : PPC::LHZ8) :
459 (Is32BitInt ? PPC::LHA : PPC::LHA8));
463 (Is32BitInt ? PPC::LWZ : PPC::LWZ8) :
464 (Is32BitInt ? PPC::LWA_32 : PPC::LWA));
465 if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0))
470 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) &&
471 "64-bit load with 32-bit target??");
472 UseOffset = ((Addr.Offset & 3) == 0);
482 // If necessary, materialize the offset into a register and use
483 // the indexed form. Also handle stack pointers with special needs.
484 unsigned IndexReg = 0;
485 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg);
487 ResultReg = createResultReg(UseRC);
489 // Note: If we still have a frame index here, we know the offset is
490 // in range, as otherwise PPCSimplifyAddress would have converted it
492 if (Addr.BaseType == Address::FrameIndexBase) {
494 MachineMemOperand *MMO =
495 FuncInfo.MF->getMachineMemOperand(
496 MachinePointerInfo::getFixedStack(Addr.Base.FI, Addr.Offset),
497 MachineMemOperand::MOLoad, MFI.getObjectSize(Addr.Base.FI),
498 MFI.getObjectAlignment(Addr.Base.FI));
500 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
501 .addImm(Addr.Offset).addFrameIndex(Addr.Base.FI).addMemOperand(MMO);
503 // Base reg with offset in range.
504 } else if (UseOffset) {
506 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
507 .addImm(Addr.Offset).addReg(Addr.Base.Reg);
511 // Get the RR opcode corresponding to the RI one. FIXME: It would be
512 // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it
513 // is hard to get at.
515 default: llvm_unreachable("Unexpected opcode!");
516 case PPC::LBZ: Opc = PPC::LBZX; break;
517 case PPC::LBZ8: Opc = PPC::LBZX8; break;
518 case PPC::LHZ: Opc = PPC::LHZX; break;
519 case PPC::LHZ8: Opc = PPC::LHZX8; break;
520 case PPC::LHA: Opc = PPC::LHAX; break;
521 case PPC::LHA8: Opc = PPC::LHAX8; break;
522 case PPC::LWZ: Opc = PPC::LWZX; break;
523 case PPC::LWZ8: Opc = PPC::LWZX8; break;
524 case PPC::LWA: Opc = PPC::LWAX; break;
525 case PPC::LWA_32: Opc = PPC::LWAX_32; break;
526 case PPC::LD: Opc = PPC::LDX; break;
527 case PPC::LFS: Opc = PPC::LFSX; break;
528 case PPC::LFD: Opc = PPC::LFDX; break;
530 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
531 .addReg(Addr.Base.Reg).addReg(IndexReg);
537 // Attempt to fast-select a load instruction.
538 bool PPCFastISel::SelectLoad(const Instruction *I) {
539 // FIXME: No atomic loads are supported.
540 if (cast<LoadInst>(I)->isAtomic())
543 // Verify we have a legal type before going any further.
545 if (!isLoadTypeLegal(I->getType(), VT))
548 // See if we can handle this address.
550 if (!PPCComputeAddress(I->getOperand(0), Addr))
553 // Look at the currently assigned register for this instruction
554 // to determine the required register class. This is necessary
555 // to constrain RA from using R0/X0 when this is not legal.
556 unsigned AssignedReg = FuncInfo.ValueMap[I];
557 const TargetRegisterClass *RC =
558 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr;
560 unsigned ResultReg = 0;
561 if (!PPCEmitLoad(VT, ResultReg, Addr, RC))
563 UpdateValueMap(I, ResultReg);
567 // Emit a store instruction to store SrcReg at Addr.
568 bool PPCFastISel::PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr) {
569 assert(SrcReg && "Nothing to store!");
571 bool UseOffset = true;
573 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg);
574 bool Is32BitInt = RC->hasSuperClassEq(&PPC::GPRCRegClass);
576 switch (VT.SimpleTy) {
577 default: // e.g., vector types not handled
580 Opc = Is32BitInt ? PPC::STB : PPC::STB8;
583 Opc = Is32BitInt ? PPC::STH : PPC::STH8;
586 assert(Is32BitInt && "Not GPRC for i32??");
591 UseOffset = ((Addr.Offset & 3) == 0);
601 // If necessary, materialize the offset into a register and use
602 // the indexed form. Also handle stack pointers with special needs.
603 unsigned IndexReg = 0;
604 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg);
606 // Note: If we still have a frame index here, we know the offset is
607 // in range, as otherwise PPCSimplifyAddress would have converted it
609 if (Addr.BaseType == Address::FrameIndexBase) {
610 MachineMemOperand *MMO =
611 FuncInfo.MF->getMachineMemOperand(
612 MachinePointerInfo::getFixedStack(Addr.Base.FI, Addr.Offset),
613 MachineMemOperand::MOStore, MFI.getObjectSize(Addr.Base.FI),
614 MFI.getObjectAlignment(Addr.Base.FI));
616 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
619 .addFrameIndex(Addr.Base.FI)
622 // Base reg with offset in range.
623 } else if (UseOffset)
624 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
625 .addReg(SrcReg).addImm(Addr.Offset).addReg(Addr.Base.Reg);
629 // Get the RR opcode corresponding to the RI one. FIXME: It would be
630 // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it
631 // is hard to get at.
633 default: llvm_unreachable("Unexpected opcode!");
634 case PPC::STB: Opc = PPC::STBX; break;
635 case PPC::STH : Opc = PPC::STHX; break;
636 case PPC::STW : Opc = PPC::STWX; break;
637 case PPC::STB8: Opc = PPC::STBX8; break;
638 case PPC::STH8: Opc = PPC::STHX8; break;
639 case PPC::STW8: Opc = PPC::STWX8; break;
640 case PPC::STD: Opc = PPC::STDX; break;
641 case PPC::STFS: Opc = PPC::STFSX; break;
642 case PPC::STFD: Opc = PPC::STFDX; break;
644 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
645 .addReg(SrcReg).addReg(Addr.Base.Reg).addReg(IndexReg);
651 // Attempt to fast-select a store instruction.
652 bool PPCFastISel::SelectStore(const Instruction *I) {
653 Value *Op0 = I->getOperand(0);
656 // FIXME: No atomics loads are supported.
657 if (cast<StoreInst>(I)->isAtomic())
660 // Verify we have a legal type before going any further.
662 if (!isLoadTypeLegal(Op0->getType(), VT))
665 // Get the value to be stored into a register.
666 SrcReg = getRegForValue(Op0);
670 // See if we can handle this address.
672 if (!PPCComputeAddress(I->getOperand(1), Addr))
675 if (!PPCEmitStore(VT, SrcReg, Addr))
681 // Attempt to fast-select a branch instruction.
682 bool PPCFastISel::SelectBranch(const Instruction *I) {
683 const BranchInst *BI = cast<BranchInst>(I);
684 MachineBasicBlock *BrBB = FuncInfo.MBB;
685 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
686 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
688 // For now, just try the simplest case where it's fed by a compare.
689 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
690 Optional<PPC::Predicate> OptPPCPred = getComparePred(CI->getPredicate());
694 PPC::Predicate PPCPred = OptPPCPred.getValue();
696 // Take advantage of fall-through opportunities.
697 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
699 PPCPred = PPC::InvertPredicate(PPCPred);
702 unsigned CondReg = createResultReg(&PPC::CRRCRegClass);
704 if (!PPCEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(),
708 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCC))
709 .addImm(PPCPred).addReg(CondReg).addMBB(TBB);
710 FastEmitBranch(FBB, DbgLoc);
711 FuncInfo.MBB->addSuccessor(TBB);
714 } else if (const ConstantInt *CI =
715 dyn_cast<ConstantInt>(BI->getCondition())) {
716 uint64_t Imm = CI->getZExtValue();
717 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
718 FastEmitBranch(Target, DbgLoc);
722 // FIXME: ARM looks for a case where the block containing the compare
723 // has been split from the block containing the branch. If this happens,
724 // there is a vreg available containing the result of the compare. I'm
725 // not sure we can do much, as we've lost the predicate information with
726 // the compare instruction -- we have a 4-bit CR but don't know which bit
731 // Attempt to emit a compare of the two source values. Signed and unsigned
732 // comparisons are supported. Return false if we can't handle it.
733 bool PPCFastISel::PPCEmitCmp(const Value *SrcValue1, const Value *SrcValue2,
734 bool IsZExt, unsigned DestReg) {
735 Type *Ty = SrcValue1->getType();
736 EVT SrcEVT = TLI.getValueType(Ty, true);
737 if (!SrcEVT.isSimple())
739 MVT SrcVT = SrcEVT.getSimpleVT();
741 if (SrcVT == MVT::i1 && PPCSubTarget->useCRBits())
744 // See if operand 2 is an immediate encodeable in the compare.
745 // FIXME: Operands are not in canonical order at -O0, so an immediate
746 // operand in position 1 is a lost opportunity for now. We are
747 // similar to ARM in this regard.
751 // Only 16-bit integer constants can be represented in compares for
752 // PowerPC. Others will be materialized into a register.
753 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(SrcValue2)) {
754 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
755 SrcVT == MVT::i8 || SrcVT == MVT::i1) {
756 const APInt &CIVal = ConstInt->getValue();
757 Imm = (IsZExt) ? (long)CIVal.getZExtValue() : (long)CIVal.getSExtValue();
758 if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm)))
764 bool NeedsExt = false;
765 switch (SrcVT.SimpleTy) {
766 default: return false;
768 CmpOpc = PPC::FCMPUS;
771 CmpOpc = PPC::FCMPUD;
777 // Intentional fall-through.
780 CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW;
782 CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI;
786 CmpOpc = IsZExt ? PPC::CMPLD : PPC::CMPD;
788 CmpOpc = IsZExt ? PPC::CMPLDI : PPC::CMPDI;
792 unsigned SrcReg1 = getRegForValue(SrcValue1);
796 unsigned SrcReg2 = 0;
798 SrcReg2 = getRegForValue(SrcValue2);
804 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
805 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt))
810 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
811 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt))
818 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
819 .addReg(SrcReg1).addReg(SrcReg2);
821 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
822 .addReg(SrcReg1).addImm(Imm);
827 // Attempt to fast-select a floating-point extend instruction.
828 bool PPCFastISel::SelectFPExt(const Instruction *I) {
829 Value *Src = I->getOperand(0);
830 EVT SrcVT = TLI.getValueType(Src->getType(), true);
831 EVT DestVT = TLI.getValueType(I->getType(), true);
833 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
836 unsigned SrcReg = getRegForValue(Src);
840 // No code is generated for a FP extend.
841 UpdateValueMap(I, SrcReg);
845 // Attempt to fast-select a floating-point truncate instruction.
846 bool PPCFastISel::SelectFPTrunc(const Instruction *I) {
847 Value *Src = I->getOperand(0);
848 EVT SrcVT = TLI.getValueType(Src->getType(), true);
849 EVT DestVT = TLI.getValueType(I->getType(), true);
851 if (SrcVT != MVT::f64 || DestVT != MVT::f32)
854 unsigned SrcReg = getRegForValue(Src);
858 // Round the result to single precision.
859 unsigned DestReg = createResultReg(&PPC::F4RCRegClass);
860 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::FRSP), DestReg)
863 UpdateValueMap(I, DestReg);
867 // Move an i32 or i64 value in a GPR to an f64 value in an FPR.
868 // FIXME: When direct register moves are implemented (see PowerISA 2.08),
869 // those should be used instead of moving via a stack slot when the
870 // subtarget permits.
871 // FIXME: The code here is sloppy for the 4-byte case. Can use a 4-byte
872 // stack slot and 4-byte store/load sequence. Or just sext the 4-byte
873 // case to 8 bytes which produces tighter code but wastes stack space.
874 unsigned PPCFastISel::PPCMoveToFPReg(MVT SrcVT, unsigned SrcReg,
877 // If necessary, extend 32-bit int to 64-bit.
878 if (SrcVT == MVT::i32) {
879 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass);
880 if (!PPCEmitIntExt(MVT::i32, SrcReg, MVT::i64, TmpReg, !IsSigned))
885 // Get a stack slot 8 bytes wide, aligned on an 8-byte boundary.
887 Addr.BaseType = Address::FrameIndexBase;
888 Addr.Base.FI = MFI.CreateStackObject(8, 8, false);
890 // Store the value from the GPR.
891 if (!PPCEmitStore(MVT::i64, SrcReg, Addr))
894 // Load the integer value into an FPR. The kind of load used depends
895 // on a number of conditions.
896 unsigned LoadOpc = PPC::LFD;
898 if (SrcVT == MVT::i32) {
900 LoadOpc = PPC::LFIWZX;
902 } else if (PPCSubTarget->hasLFIWAX()) {
903 LoadOpc = PPC::LFIWAX;
908 const TargetRegisterClass *RC = &PPC::F8RCRegClass;
909 unsigned ResultReg = 0;
910 if (!PPCEmitLoad(MVT::f64, ResultReg, Addr, RC, !IsSigned, LoadOpc))
916 // Attempt to fast-select an integer-to-floating-point conversion.
917 bool PPCFastISel::SelectIToFP(const Instruction *I, bool IsSigned) {
919 Type *DstTy = I->getType();
920 if (!isTypeLegal(DstTy, DstVT))
923 if (DstVT != MVT::f32 && DstVT != MVT::f64)
926 Value *Src = I->getOperand(0);
927 EVT SrcEVT = TLI.getValueType(Src->getType(), true);
928 if (!SrcEVT.isSimple())
931 MVT SrcVT = SrcEVT.getSimpleVT();
933 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 &&
934 SrcVT != MVT::i32 && SrcVT != MVT::i64)
937 unsigned SrcReg = getRegForValue(Src);
941 // We can only lower an unsigned convert if we have the newer
942 // floating-point conversion operations.
943 if (!IsSigned && !PPCSubTarget->hasFPCVT())
946 // FIXME: For now we require the newer floating-point conversion operations
947 // (which are present only on P7 and A2 server models) when converting
948 // to single-precision float. Otherwise we have to generate a lot of
949 // fiddly code to avoid double rounding. If necessary, the fiddly code
950 // can be found in PPCTargetLowering::LowerINT_TO_FP().
951 if (DstVT == MVT::f32 && !PPCSubTarget->hasFPCVT())
954 // Extend the input if necessary.
955 if (SrcVT == MVT::i8 || SrcVT == MVT::i16) {
956 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass);
957 if (!PPCEmitIntExt(SrcVT, SrcReg, MVT::i64, TmpReg, !IsSigned))
963 // Move the integer value to an FPR.
964 unsigned FPReg = PPCMoveToFPReg(SrcVT, SrcReg, IsSigned);
968 // Determine the opcode for the conversion.
969 const TargetRegisterClass *RC = &PPC::F8RCRegClass;
970 unsigned DestReg = createResultReg(RC);
973 if (DstVT == MVT::f32)
974 Opc = IsSigned ? PPC::FCFIDS : PPC::FCFIDUS;
976 Opc = IsSigned ? PPC::FCFID : PPC::FCFIDU;
978 // Generate the convert.
979 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
982 UpdateValueMap(I, DestReg);
986 // Move the floating-point value in SrcReg into an integer destination
987 // register, and return the register (or zero if we can't handle it).
988 // FIXME: When direct register moves are implemented (see PowerISA 2.08),
989 // those should be used instead of moving via a stack slot when the
990 // subtarget permits.
991 unsigned PPCFastISel::PPCMoveToIntReg(const Instruction *I, MVT VT,
992 unsigned SrcReg, bool IsSigned) {
993 // Get a stack slot 8 bytes wide, aligned on an 8-byte boundary.
994 // Note that if have STFIWX available, we could use a 4-byte stack
995 // slot for i32, but this being fast-isel we'll just go with the
996 // easiest code gen possible.
998 Addr.BaseType = Address::FrameIndexBase;
999 Addr.Base.FI = MFI.CreateStackObject(8, 8, false);
1001 // Store the value from the FPR.
1002 if (!PPCEmitStore(MVT::f64, SrcReg, Addr))
1005 // Reload it into a GPR. If we want an i32, modify the address
1006 // to have a 4-byte offset so we load from the right place.
1010 // Look at the currently assigned register for this instruction
1011 // to determine the required register class.
1012 unsigned AssignedReg = FuncInfo.ValueMap[I];
1013 const TargetRegisterClass *RC =
1014 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr;
1016 unsigned ResultReg = 0;
1017 if (!PPCEmitLoad(VT, ResultReg, Addr, RC, !IsSigned))
1023 // Attempt to fast-select a floating-point-to-integer conversion.
1024 bool PPCFastISel::SelectFPToI(const Instruction *I, bool IsSigned) {
1026 Type *DstTy = I->getType();
1027 if (!isTypeLegal(DstTy, DstVT))
1030 if (DstVT != MVT::i32 && DstVT != MVT::i64)
1033 // If we don't have FCTIDUZ and we need it, punt to SelectionDAG.
1034 if (DstVT == MVT::i64 && !IsSigned && !PPCSubTarget->hasFPCVT())
1037 Value *Src = I->getOperand(0);
1038 Type *SrcTy = Src->getType();
1039 if (!isTypeLegal(SrcTy, SrcVT))
1042 if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1045 unsigned SrcReg = getRegForValue(Src);
1049 // Convert f32 to f64 if necessary. This is just a meaningless copy
1050 // to get the register class right. COPY_TO_REGCLASS is needed since
1051 // a COPY from F4RC to F8RC is converted to a F4RC-F4RC copy downstream.
1052 const TargetRegisterClass *InRC = MRI.getRegClass(SrcReg);
1053 if (InRC == &PPC::F4RCRegClass) {
1054 unsigned TmpReg = createResultReg(&PPC::F8RCRegClass);
1055 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1056 TII.get(TargetOpcode::COPY_TO_REGCLASS), TmpReg)
1057 .addReg(SrcReg).addImm(PPC::F8RCRegClassID);
1061 // Determine the opcode for the conversion, which takes place
1062 // entirely within FPRs.
1063 unsigned DestReg = createResultReg(&PPC::F8RCRegClass);
1066 if (DstVT == MVT::i32)
1070 Opc = PPCSubTarget->hasFPCVT() ? PPC::FCTIWUZ : PPC::FCTIDZ;
1072 Opc = IsSigned ? PPC::FCTIDZ : PPC::FCTIDUZ;
1074 // Generate the convert.
1075 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1078 // Now move the integer value from a float register to an integer register.
1079 unsigned IntReg = PPCMoveToIntReg(I, DstVT, DestReg, IsSigned);
1083 UpdateValueMap(I, IntReg);
1087 // Attempt to fast-select a binary integer operation that isn't already
1088 // handled automatically.
1089 bool PPCFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1090 EVT DestVT = TLI.getValueType(I->getType(), true);
1092 // We can get here in the case when we have a binary operation on a non-legal
1093 // type and the target independent selector doesn't know how to handle it.
1094 if (DestVT != MVT::i16 && DestVT != MVT::i8)
1097 // Look at the currently assigned register for this instruction
1098 // to determine the required register class. If there is no register,
1099 // make a conservative choice (don't assign R0).
1100 unsigned AssignedReg = FuncInfo.ValueMap[I];
1101 const TargetRegisterClass *RC =
1102 (AssignedReg ? MRI.getRegClass(AssignedReg) :
1103 &PPC::GPRC_and_GPRC_NOR0RegClass);
1104 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
1107 switch (ISDOpcode) {
1108 default: return false;
1110 Opc = IsGPRC ? PPC::ADD4 : PPC::ADD8;
1113 Opc = IsGPRC ? PPC::OR : PPC::OR8;
1116 Opc = IsGPRC ? PPC::SUBF : PPC::SUBF8;
1120 unsigned ResultReg = createResultReg(RC ? RC : &PPC::G8RCRegClass);
1121 unsigned SrcReg1 = getRegForValue(I->getOperand(0));
1122 if (SrcReg1 == 0) return false;
1124 // Handle case of small immediate operand.
1125 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(1))) {
1126 const APInt &CIVal = ConstInt->getValue();
1127 int Imm = (int)CIVal.getSExtValue();
1129 if (isInt<16>(Imm)) {
1132 llvm_unreachable("Missing case!");
1135 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1139 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
1152 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1161 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
1168 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
1172 UpdateValueMap(I, ResultReg);
1179 unsigned SrcReg2 = getRegForValue(I->getOperand(1));
1180 if (SrcReg2 == 0) return false;
1182 // Reverse operands for subtract-from.
1183 if (ISDOpcode == ISD::SUB)
1184 std::swap(SrcReg1, SrcReg2);
1186 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1187 .addReg(SrcReg1).addReg(SrcReg2);
1188 UpdateValueMap(I, ResultReg);
1192 // Handle arguments to a call that we're attempting to fast-select.
1193 // Return false if the arguments are too complex for us at the moment.
1194 bool PPCFastISel::processCallArgs(SmallVectorImpl<Value*> &Args,
1195 SmallVectorImpl<unsigned> &ArgRegs,
1196 SmallVectorImpl<MVT> &ArgVTs,
1197 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1198 SmallVectorImpl<unsigned> &RegArgs,
1202 SmallVector<CCValAssign, 16> ArgLocs;
1203 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, TM, ArgLocs, *Context);
1205 // Reserve space for the linkage area on the stack.
1206 bool isELFv2ABI = PPCSubTarget->isELFv2ABI();
1207 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
1209 CCInfo.AllocateStack(LinkageSize, 8);
1211 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CC_PPC64_ELF_FIS);
1213 // Bail out if we can't handle any of the arguments.
1214 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1215 CCValAssign &VA = ArgLocs[I];
1216 MVT ArgVT = ArgVTs[VA.getValNo()];
1218 // Skip vector arguments for now, as well as long double and
1219 // uint128_t, and anything that isn't passed in a register.
1220 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64 || ArgVT == MVT::i1 ||
1221 !VA.isRegLoc() || VA.needsCustom())
1224 // Skip bit-converted arguments for now.
1225 if (VA.getLocInfo() == CCValAssign::BCvt)
1229 // Get a count of how many bytes are to be pushed onto the stack.
1230 NumBytes = CCInfo.getNextStackOffset();
1232 // The prolog code of the callee may store up to 8 GPR argument registers to
1233 // the stack, allowing va_start to index over them in memory if its varargs.
1234 // Because we cannot tell if this is needed on the caller side, we have to
1235 // conservatively assume that it is needed. As such, make sure we have at
1236 // least enough stack space for the caller to store the 8 GPRs.
1237 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
1238 NumBytes = std::max(NumBytes, LinkageSize + 64);
1240 // Issue CALLSEQ_START.
1241 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1242 TII.get(TII.getCallFrameSetupOpcode()))
1245 // Prepare to assign register arguments. Every argument uses up a
1246 // GPR protocol register even if it's passed in a floating-point
1248 unsigned NextGPR = PPC::X3;
1249 unsigned NextFPR = PPC::F1;
1251 // Process arguments.
1252 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1253 CCValAssign &VA = ArgLocs[I];
1254 unsigned Arg = ArgRegs[VA.getValNo()];
1255 MVT ArgVT = ArgVTs[VA.getValNo()];
1257 // Handle argument promotion and bitcasts.
1258 switch (VA.getLocInfo()) {
1260 llvm_unreachable("Unknown loc info!");
1261 case CCValAssign::Full:
1263 case CCValAssign::SExt: {
1264 MVT DestVT = VA.getLocVT();
1265 const TargetRegisterClass *RC =
1266 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1267 unsigned TmpReg = createResultReg(RC);
1268 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/false))
1269 llvm_unreachable("Failed to emit a sext!");
1274 case CCValAssign::AExt:
1275 case CCValAssign::ZExt: {
1276 MVT DestVT = VA.getLocVT();
1277 const TargetRegisterClass *RC =
1278 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1279 unsigned TmpReg = createResultReg(RC);
1280 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/true))
1281 llvm_unreachable("Failed to emit a zext!");
1286 case CCValAssign::BCvt: {
1287 // FIXME: Not yet handled.
1288 llvm_unreachable("Should have bailed before getting here!");
1293 // Copy this argument to the appropriate register.
1295 if (ArgVT == MVT::f32 || ArgVT == MVT::f64) {
1301 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1302 TII.get(TargetOpcode::COPY), ArgReg).addReg(Arg);
1303 RegArgs.push_back(ArgReg);
1309 // For a call that we've determined we can fast-select, finish the
1310 // call sequence and generate a copy to obtain the return value (if any).
1311 void PPCFastISel::finishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
1312 const Instruction *I, CallingConv::ID CC,
1313 unsigned &NumBytes, bool IsVarArg) {
1314 // Issue CallSEQ_END.
1315 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1316 TII.get(TII.getCallFrameDestroyOpcode()))
1317 .addImm(NumBytes).addImm(0);
1319 // Next, generate a copy to obtain the return value.
1320 // FIXME: No multi-register return values yet, though I don't foresee
1321 // any real difficulties there.
1322 if (RetVT != MVT::isVoid) {
1323 SmallVector<CCValAssign, 16> RVLocs;
1324 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, TM, RVLocs, *Context);
1325 CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1326 CCValAssign &VA = RVLocs[0];
1327 assert(RVLocs.size() == 1 && "No support for multi-reg return values!");
1328 assert(VA.isRegLoc() && "Can only return in registers!");
1330 MVT DestVT = VA.getValVT();
1331 MVT CopyVT = DestVT;
1333 // Ints smaller than a register still arrive in a full 64-bit
1334 // register, so make sure we recognize this.
1335 if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32)
1338 unsigned SourcePhysReg = VA.getLocReg();
1339 unsigned ResultReg = 0;
1341 if (RetVT == CopyVT) {
1342 const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT);
1343 ResultReg = createResultReg(CpyRC);
1345 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1346 TII.get(TargetOpcode::COPY), ResultReg)
1347 .addReg(SourcePhysReg);
1349 // If necessary, round the floating result to single precision.
1350 } else if (CopyVT == MVT::f64) {
1351 ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1352 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::FRSP),
1353 ResultReg).addReg(SourcePhysReg);
1355 // If only the low half of a general register is needed, generate
1356 // a GPRC copy instead of a G8RC copy. (EXTRACT_SUBREG can't be
1357 // used along the fast-isel path (not lowered), and downstream logic
1358 // also doesn't like a direct subreg copy on a physical reg.)
1359 } else if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) {
1360 ResultReg = createResultReg(&PPC::GPRCRegClass);
1361 // Convert physical register from G8RC to GPRC.
1362 SourcePhysReg -= PPC::X0 - PPC::R0;
1363 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1364 TII.get(TargetOpcode::COPY), ResultReg)
1365 .addReg(SourcePhysReg);
1368 assert(ResultReg && "ResultReg unset!");
1369 UsedRegs.push_back(SourcePhysReg);
1370 UpdateValueMap(I, ResultReg);
1374 // Attempt to fast-select a call instruction.
1375 bool PPCFastISel::SelectCall(const Instruction *I) {
1376 const CallInst *CI = cast<CallInst>(I);
1377 const Value *Callee = CI->getCalledValue();
1379 // Can't handle inline asm.
1380 if (isa<InlineAsm>(Callee))
1383 // Allow SelectionDAG isel to handle tail calls.
1384 if (CI->isTailCall())
1387 // Obtain calling convention.
1388 ImmutableCallSite CS(CI);
1389 CallingConv::ID CC = CS.getCallingConv();
1391 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1392 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1393 bool IsVarArg = FTy->isVarArg();
1395 // Not ready for varargs yet.
1399 // Handle simple calls for now, with legal return types and
1400 // those that can be extended.
1401 Type *RetTy = I->getType();
1403 if (RetTy->isVoidTy())
1404 RetVT = MVT::isVoid;
1405 else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
1409 // FIXME: No multi-register return values yet.
1410 if (RetVT != MVT::isVoid && RetVT != MVT::i8 && RetVT != MVT::i16 &&
1411 RetVT != MVT::i32 && RetVT != MVT::i64 && RetVT != MVT::f32 &&
1412 RetVT != MVT::f64) {
1413 SmallVector<CCValAssign, 16> RVLocs;
1414 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, TM, RVLocs, *Context);
1415 CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1416 if (RVLocs.size() > 1)
1420 // Bail early if more than 8 arguments, as we only currently
1421 // handle arguments passed in registers.
1422 unsigned NumArgs = CS.arg_size();
1426 // Set up the argument vectors.
1427 SmallVector<Value*, 8> Args;
1428 SmallVector<unsigned, 8> ArgRegs;
1429 SmallVector<MVT, 8> ArgVTs;
1430 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1432 Args.reserve(NumArgs);
1433 ArgRegs.reserve(NumArgs);
1434 ArgVTs.reserve(NumArgs);
1435 ArgFlags.reserve(NumArgs);
1437 for (ImmutableCallSite::arg_iterator II = CS.arg_begin(), IE = CS.arg_end();
1439 // FIXME: ARM does something for intrinsic calls here, check into that.
1441 unsigned AttrIdx = II - CS.arg_begin() + 1;
1443 // Only handle easy calls for now. It would be reasonably easy
1444 // to handle <= 8-byte structures passed ByVal in registers, but we
1445 // have to ensure they are right-justified in the register.
1446 if (CS.paramHasAttr(AttrIdx, Attribute::InReg) ||
1447 CS.paramHasAttr(AttrIdx, Attribute::StructRet) ||
1448 CS.paramHasAttr(AttrIdx, Attribute::Nest) ||
1449 CS.paramHasAttr(AttrIdx, Attribute::ByVal))
1452 ISD::ArgFlagsTy Flags;
1453 if (CS.paramHasAttr(AttrIdx, Attribute::SExt))
1455 if (CS.paramHasAttr(AttrIdx, Attribute::ZExt))
1458 Type *ArgTy = (*II)->getType();
1460 if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8)
1463 if (ArgVT.isVector())
1466 unsigned Arg = getRegForValue(*II);
1470 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
1471 Flags.setOrigAlign(OriginalAlignment);
1473 Args.push_back(*II);
1474 ArgRegs.push_back(Arg);
1475 ArgVTs.push_back(ArgVT);
1476 ArgFlags.push_back(Flags);
1479 // Process the arguments.
1480 SmallVector<unsigned, 8> RegArgs;
1483 if (!processCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
1484 RegArgs, CC, NumBytes, IsVarArg))
1487 // FIXME: No handling for function pointers yet. This requires
1488 // implementing the function descriptor (OPD) setup.
1489 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1493 // Build direct call with NOP for TOC restore.
1494 // FIXME: We can and should optimize away the NOP for local calls.
1495 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1496 TII.get(PPC::BL8_NOP));
1498 MIB.addGlobalAddress(GV);
1500 // Add implicit physical register uses to the call.
1501 for (unsigned II = 0, IE = RegArgs.size(); II != IE; ++II)
1502 MIB.addReg(RegArgs[II], RegState::Implicit);
1504 // Direct calls in the ELFv2 ABI need the TOC register live into the call.
1505 if (PPCSubTarget->isELFv2ABI())
1506 MIB.addReg(PPC::X2, RegState::Implicit);
1508 // Add a register mask with the call-preserved registers. Proper
1509 // defs for return values will be added by setPhysRegsDeadExcept().
1510 MIB.addRegMask(TRI.getCallPreservedMask(CC));
1512 // Finish off the call including any return values.
1513 SmallVector<unsigned, 4> UsedRegs;
1514 finishCall(RetVT, UsedRegs, I, CC, NumBytes, IsVarArg);
1516 // Set all unused physregs defs as dead.
1517 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1522 // Attempt to fast-select a return instruction.
1523 bool PPCFastISel::SelectRet(const Instruction *I) {
1525 if (!FuncInfo.CanLowerReturn)
1528 const ReturnInst *Ret = cast<ReturnInst>(I);
1529 const Function &F = *I->getParent()->getParent();
1531 // Build a list of return value registers.
1532 SmallVector<unsigned, 4> RetRegs;
1533 CallingConv::ID CC = F.getCallingConv();
1535 if (Ret->getNumOperands() > 0) {
1536 SmallVector<ISD::OutputArg, 4> Outs;
1537 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
1539 // Analyze operands of the call, assigning locations to each operand.
1540 SmallVector<CCValAssign, 16> ValLocs;
1541 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs, *Context);
1542 CCInfo.AnalyzeReturn(Outs, RetCC_PPC64_ELF_FIS);
1543 const Value *RV = Ret->getOperand(0);
1545 // FIXME: Only one output register for now.
1546 if (ValLocs.size() > 1)
1549 // Special case for returning a constant integer of any size.
1550 // Materialize the constant as an i64 and copy it to the return
1551 // register. This avoids an unnecessary extend or truncate.
1552 if (isa<ConstantInt>(*RV)) {
1553 const Constant *C = cast<Constant>(RV);
1554 unsigned SrcReg = PPCMaterializeInt(C, MVT::i64);
1555 unsigned RetReg = ValLocs[0].getLocReg();
1556 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1557 TII.get(TargetOpcode::COPY), RetReg).addReg(SrcReg);
1558 RetRegs.push_back(RetReg);
1561 unsigned Reg = getRegForValue(RV);
1566 // Copy the result values into the output registers.
1567 for (unsigned i = 0; i < ValLocs.size(); ++i) {
1569 CCValAssign &VA = ValLocs[i];
1570 assert(VA.isRegLoc() && "Can only return in registers!");
1571 RetRegs.push_back(VA.getLocReg());
1572 unsigned SrcReg = Reg + VA.getValNo();
1574 EVT RVEVT = TLI.getValueType(RV->getType());
1575 if (!RVEVT.isSimple())
1577 MVT RVVT = RVEVT.getSimpleVT();
1578 MVT DestVT = VA.getLocVT();
1580 if (RVVT != DestVT && RVVT != MVT::i8 &&
1581 RVVT != MVT::i16 && RVVT != MVT::i32)
1584 if (RVVT != DestVT) {
1585 switch (VA.getLocInfo()) {
1587 llvm_unreachable("Unknown loc info!");
1588 case CCValAssign::Full:
1589 llvm_unreachable("Full value assign but types don't match?");
1590 case CCValAssign::AExt:
1591 case CCValAssign::ZExt: {
1592 const TargetRegisterClass *RC =
1593 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1594 unsigned TmpReg = createResultReg(RC);
1595 if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, true))
1600 case CCValAssign::SExt: {
1601 const TargetRegisterClass *RC =
1602 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1603 unsigned TmpReg = createResultReg(RC);
1604 if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, false))
1612 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1613 TII.get(TargetOpcode::COPY), RetRegs[i])
1619 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1622 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1623 MIB.addReg(RetRegs[i], RegState::Implicit);
1628 // Attempt to emit an integer extend of SrcReg into DestReg. Both
1629 // signed and zero extensions are supported. Return false if we
1631 bool PPCFastISel::PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1632 unsigned DestReg, bool IsZExt) {
1633 if (DestVT != MVT::i32 && DestVT != MVT::i64)
1635 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 && SrcVT != MVT::i32)
1638 // Signed extensions use EXTSB, EXTSH, EXTSW.
1641 if (SrcVT == MVT::i8)
1642 Opc = (DestVT == MVT::i32) ? PPC::EXTSB : PPC::EXTSB8_32_64;
1643 else if (SrcVT == MVT::i16)
1644 Opc = (DestVT == MVT::i32) ? PPC::EXTSH : PPC::EXTSH8_32_64;
1646 assert(DestVT == MVT::i64 && "Signed extend from i32 to i32??");
1647 Opc = PPC::EXTSW_32_64;
1649 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1652 // Unsigned 32-bit extensions use RLWINM.
1653 } else if (DestVT == MVT::i32) {
1655 if (SrcVT == MVT::i8)
1658 assert(SrcVT == MVT::i16 && "Unsigned extend from i32 to i32??");
1661 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::RLWINM),
1663 .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB).addImm(/*ME=*/31);
1665 // Unsigned 64-bit extensions use RLDICL (with a 32-bit source).
1668 if (SrcVT == MVT::i8)
1670 else if (SrcVT == MVT::i16)
1674 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1675 TII.get(PPC::RLDICL_32_64), DestReg)
1676 .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB);
1682 // Attempt to fast-select an indirect branch instruction.
1683 bool PPCFastISel::SelectIndirectBr(const Instruction *I) {
1684 unsigned AddrReg = getRegForValue(I->getOperand(0));
1688 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::MTCTR8))
1690 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCTR8));
1692 const IndirectBrInst *IB = cast<IndirectBrInst>(I);
1693 for (unsigned i = 0, e = IB->getNumSuccessors(); i != e; ++i)
1694 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[IB->getSuccessor(i)]);
1699 // Attempt to fast-select an integer truncate instruction.
1700 bool PPCFastISel::SelectTrunc(const Instruction *I) {
1701 Value *Src = I->getOperand(0);
1702 EVT SrcVT = TLI.getValueType(Src->getType(), true);
1703 EVT DestVT = TLI.getValueType(I->getType(), true);
1705 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16)
1708 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
1711 unsigned SrcReg = getRegForValue(Src);
1715 // The only interesting case is when we need to switch register classes.
1716 if (SrcVT == MVT::i64) {
1717 unsigned ResultReg = createResultReg(&PPC::GPRCRegClass);
1718 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1719 TII.get(TargetOpcode::COPY),
1720 ResultReg).addReg(SrcReg, 0, PPC::sub_32);
1724 UpdateValueMap(I, SrcReg);
1728 // Attempt to fast-select an integer extend instruction.
1729 bool PPCFastISel::SelectIntExt(const Instruction *I) {
1730 Type *DestTy = I->getType();
1731 Value *Src = I->getOperand(0);
1732 Type *SrcTy = Src->getType();
1734 bool IsZExt = isa<ZExtInst>(I);
1735 unsigned SrcReg = getRegForValue(Src);
1736 if (!SrcReg) return false;
1738 EVT SrcEVT, DestEVT;
1739 SrcEVT = TLI.getValueType(SrcTy, true);
1740 DestEVT = TLI.getValueType(DestTy, true);
1741 if (!SrcEVT.isSimple())
1743 if (!DestEVT.isSimple())
1746 MVT SrcVT = SrcEVT.getSimpleVT();
1747 MVT DestVT = DestEVT.getSimpleVT();
1749 // If we know the register class needed for the result of this
1750 // instruction, use it. Otherwise pick the register class of the
1751 // correct size that does not contain X0/R0, since we don't know
1752 // whether downstream uses permit that assignment.
1753 unsigned AssignedReg = FuncInfo.ValueMap[I];
1754 const TargetRegisterClass *RC =
1755 (AssignedReg ? MRI.getRegClass(AssignedReg) :
1756 (DestVT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
1757 &PPC::GPRC_and_GPRC_NOR0RegClass));
1758 unsigned ResultReg = createResultReg(RC);
1760 if (!PPCEmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, IsZExt))
1763 UpdateValueMap(I, ResultReg);
1767 // Attempt to fast-select an instruction that wasn't handled by
1768 // the table-generated machinery.
1769 bool PPCFastISel::TargetSelectInstruction(const Instruction *I) {
1771 switch (I->getOpcode()) {
1772 case Instruction::Load:
1773 return SelectLoad(I);
1774 case Instruction::Store:
1775 return SelectStore(I);
1776 case Instruction::Br:
1777 return SelectBranch(I);
1778 case Instruction::IndirectBr:
1779 return SelectIndirectBr(I);
1780 case Instruction::FPExt:
1781 return SelectFPExt(I);
1782 case Instruction::FPTrunc:
1783 return SelectFPTrunc(I);
1784 case Instruction::SIToFP:
1785 return SelectIToFP(I, /*IsSigned*/ true);
1786 case Instruction::UIToFP:
1787 return SelectIToFP(I, /*IsSigned*/ false);
1788 case Instruction::FPToSI:
1789 return SelectFPToI(I, /*IsSigned*/ true);
1790 case Instruction::FPToUI:
1791 return SelectFPToI(I, /*IsSigned*/ false);
1792 case Instruction::Add:
1793 return SelectBinaryIntOp(I, ISD::ADD);
1794 case Instruction::Or:
1795 return SelectBinaryIntOp(I, ISD::OR);
1796 case Instruction::Sub:
1797 return SelectBinaryIntOp(I, ISD::SUB);
1798 case Instruction::Call:
1799 if (dyn_cast<IntrinsicInst>(I))
1801 return SelectCall(I);
1802 case Instruction::Ret:
1803 return SelectRet(I);
1804 case Instruction::Trunc:
1805 return SelectTrunc(I);
1806 case Instruction::ZExt:
1807 case Instruction::SExt:
1808 return SelectIntExt(I);
1809 // Here add other flavors of Instruction::XXX that automated
1810 // cases don't catch. For example, switches are terminators
1811 // that aren't yet handled.
1818 // Materialize a floating-point constant into a register, and return
1819 // the register number (or zero if we failed to handle it).
1820 unsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) {
1821 // No plans to handle long double here.
1822 if (VT != MVT::f32 && VT != MVT::f64)
1825 // All FP constants are loaded from the constant pool.
1826 unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
1827 assert(Align > 0 && "Unexpectedly missing alignment information!");
1828 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
1829 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
1830 CodeModel::Model CModel = TM.getCodeModel();
1832 MachineMemOperand *MMO =
1833 FuncInfo.MF->getMachineMemOperand(
1834 MachinePointerInfo::getConstantPool(), MachineMemOperand::MOLoad,
1835 (VT == MVT::f32) ? 4 : 8, Align);
1837 unsigned Opc = (VT == MVT::f32) ? PPC::LFS : PPC::LFD;
1838 unsigned TmpReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
1840 // For small code model, generate a LF[SD](0, LDtocCPT(Idx, X2)).
1841 if (CModel == CodeModel::Small || CModel == CodeModel::JITDefault) {
1842 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocCPT),
1844 .addConstantPoolIndex(Idx).addReg(PPC::X2);
1845 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1846 .addImm(0).addReg(TmpReg).addMemOperand(MMO);
1848 // Otherwise we generate LF[SD](Idx[lo], ADDIStocHA(X2, Idx)).
1849 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA),
1850 TmpReg).addReg(PPC::X2).addConstantPoolIndex(Idx);
1851 // But for large code model, we must generate a LDtocL followed
1853 if (CModel == CodeModel::Large) {
1854 unsigned TmpReg2 = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
1855 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL),
1856 TmpReg2).addConstantPoolIndex(Idx).addReg(TmpReg);
1857 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1858 .addImm(0).addReg(TmpReg2);
1860 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1861 .addConstantPoolIndex(Idx, 0, PPCII::MO_TOC_LO)
1863 .addMemOperand(MMO);
1869 // Materialize the address of a global value into a register, and return
1870 // the register number (or zero if we failed to handle it).
1871 unsigned PPCFastISel::PPCMaterializeGV(const GlobalValue *GV, MVT VT) {
1872 assert(VT == MVT::i64 && "Non-address!");
1873 const TargetRegisterClass *RC = &PPC::G8RC_and_G8RC_NOX0RegClass;
1874 unsigned DestReg = createResultReg(RC);
1876 // Global values may be plain old object addresses, TLS object
1877 // addresses, constant pool entries, or jump tables. How we generate
1878 // code for these may depend on small, medium, or large code model.
1879 CodeModel::Model CModel = TM.getCodeModel();
1881 // FIXME: Jump tables are not yet required because fast-isel doesn't
1882 // handle switches; if that changes, we need them as well. For now,
1883 // what follows assumes everything's a generic (or TLS) global address.
1885 // FIXME: We don't yet handle the complexity of TLS.
1886 if (GV->isThreadLocal())
1889 // For small code model, generate a simple TOC load.
1890 if (CModel == CodeModel::Small || CModel == CodeModel::JITDefault)
1891 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtoc),
1893 .addGlobalAddress(GV)
1896 // If the address is an externally defined symbol, a symbol with common
1897 // or externally available linkage, a non-local function address, or a
1898 // jump table address (not yet needed), or if we are generating code
1899 // for large code model, we generate:
1900 // LDtocL(GV, ADDIStocHA(%X2, GV))
1901 // Otherwise we generate:
1902 // ADDItocL(ADDIStocHA(%X2, GV), GV)
1903 // Either way, start with the ADDIStocHA:
1904 unsigned HighPartReg = createResultReg(RC);
1905 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA),
1906 HighPartReg).addReg(PPC::X2).addGlobalAddress(GV);
1908 // If/when switches are implemented, jump tables should be handled
1909 // on the "if" path here.
1910 if (CModel == CodeModel::Large ||
1911 (GV->getType()->getElementType()->isFunctionTy() &&
1912 (GV->isDeclaration() || GV->isWeakForLinker())) ||
1913 GV->isDeclaration() || GV->hasCommonLinkage() ||
1914 GV->hasAvailableExternallyLinkage())
1915 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL),
1916 DestReg).addGlobalAddress(GV).addReg(HighPartReg);
1918 // Otherwise generate the ADDItocL.
1919 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDItocL),
1920 DestReg).addReg(HighPartReg).addGlobalAddress(GV);
1926 // Materialize a 32-bit integer constant into a register, and return
1927 // the register number (or zero if we failed to handle it).
1928 unsigned PPCFastISel::PPCMaterialize32BitInt(int64_t Imm,
1929 const TargetRegisterClass *RC) {
1930 unsigned Lo = Imm & 0xFFFF;
1931 unsigned Hi = (Imm >> 16) & 0xFFFF;
1933 unsigned ResultReg = createResultReg(RC);
1934 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
1937 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1938 TII.get(IsGPRC ? PPC::LI : PPC::LI8), ResultReg)
1941 // Both Lo and Hi have nonzero bits.
1942 unsigned TmpReg = createResultReg(RC);
1943 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1944 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), TmpReg)
1946 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1947 TII.get(IsGPRC ? PPC::ORI : PPC::ORI8), ResultReg)
1948 .addReg(TmpReg).addImm(Lo);
1951 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1952 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), ResultReg)
1958 // Materialize a 64-bit integer constant into a register, and return
1959 // the register number (or zero if we failed to handle it).
1960 unsigned PPCFastISel::PPCMaterialize64BitInt(int64_t Imm,
1961 const TargetRegisterClass *RC) {
1962 unsigned Remainder = 0;
1965 // If the value doesn't fit in 32 bits, see if we can shift it
1966 // so that it fits in 32 bits.
1967 if (!isInt<32>(Imm)) {
1968 Shift = countTrailingZeros<uint64_t>(Imm);
1969 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
1971 if (isInt<32>(ImmSh))
1980 // Handle the high-order 32 bits (if shifted) or the whole 32 bits
1981 // (if not shifted).
1982 unsigned TmpReg1 = PPCMaterialize32BitInt(Imm, RC);
1986 // If upper 32 bits were not zero, we've built them and need to shift
1990 TmpReg2 = createResultReg(RC);
1991 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::RLDICR),
1992 TmpReg2).addReg(TmpReg1).addImm(Shift).addImm(63 - Shift);
1996 unsigned TmpReg3, Hi, Lo;
1997 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
1998 TmpReg3 = createResultReg(RC);
1999 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ORIS8),
2000 TmpReg3).addReg(TmpReg2).addImm(Hi);
2004 if ((Lo = Remainder & 0xFFFF)) {
2005 unsigned ResultReg = createResultReg(RC);
2006 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ORI8),
2007 ResultReg).addReg(TmpReg3).addImm(Lo);
2015 // Materialize an integer constant into a register, and return
2016 // the register number (or zero if we failed to handle it).
2017 unsigned PPCFastISel::PPCMaterializeInt(const Constant *C, MVT VT) {
2018 // If we're using CR bit registers for i1 values, handle that as a special
2020 if (VT == MVT::i1 && PPCSubTarget->useCRBits()) {
2021 const ConstantInt *CI = cast<ConstantInt>(C);
2022 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass);
2023 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2024 TII.get(CI->isZero() ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2028 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 &&
2029 VT != MVT::i8 && VT != MVT::i1)
2032 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
2033 &PPC::GPRCRegClass);
2035 // If the constant is in range, use a load-immediate.
2036 const ConstantInt *CI = cast<ConstantInt>(C);
2037 if (isInt<16>(CI->getSExtValue())) {
2038 unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI;
2039 unsigned ImmReg = createResultReg(RC);
2040 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ImmReg)
2041 .addImm(CI->getSExtValue());
2045 // Construct the constant piecewise.
2046 int64_t Imm = CI->getZExtValue();
2049 return PPCMaterialize64BitInt(Imm, RC);
2050 else if (VT == MVT::i32)
2051 return PPCMaterialize32BitInt(Imm, RC);
2056 // Materialize a constant into a register, and return the register
2057 // number (or zero if we failed to handle it).
2058 unsigned PPCFastISel::TargetMaterializeConstant(const Constant *C) {
2059 EVT CEVT = TLI.getValueType(C->getType(), true);
2061 // Only handle simple types.
2062 if (!CEVT.isSimple()) return 0;
2063 MVT VT = CEVT.getSimpleVT();
2065 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
2066 return PPCMaterializeFP(CFP, VT);
2067 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
2068 return PPCMaterializeGV(GV, VT);
2069 else if (isa<ConstantInt>(C))
2070 return PPCMaterializeInt(C, VT);
2075 // Materialize the address created by an alloca into a register, and
2076 // return the register number (or zero if we failed to handle it).
2077 unsigned PPCFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
2078 // Don't handle dynamic allocas.
2079 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
2082 if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
2084 DenseMap<const AllocaInst*, int>::iterator SI =
2085 FuncInfo.StaticAllocaMap.find(AI);
2087 if (SI != FuncInfo.StaticAllocaMap.end()) {
2088 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
2089 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8),
2090 ResultReg).addFrameIndex(SI->second).addImm(0);
2097 // Fold loads into extends when possible.
2098 // FIXME: We can have multiple redundant extend/trunc instructions
2099 // following a load. The folding only picks up one. Extend this
2100 // to check subsequent instructions for the same pattern and remove
2101 // them. Thus ResultReg should be the def reg for the last redundant
2102 // instruction in a chain, and all intervening instructions can be
2103 // removed from parent. Change test/CodeGen/PowerPC/fast-isel-fold.ll
2104 // to add ELF64-NOT: rldicl to the appropriate tests when this works.
2105 bool PPCFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
2106 const LoadInst *LI) {
2107 // Verify we have a legal type before going any further.
2109 if (!isLoadTypeLegal(LI->getType(), VT))
2112 // Combine load followed by zero- or sign-extend.
2113 bool IsZExt = false;
2114 switch(MI->getOpcode()) {
2119 case PPC::RLDICL_32_64: {
2121 unsigned MB = MI->getOperand(3).getImm();
2122 if ((VT == MVT::i8 && MB <= 56) ||
2123 (VT == MVT::i16 && MB <= 48) ||
2124 (VT == MVT::i32 && MB <= 32))
2130 case PPC::RLWINM8: {
2132 unsigned MB = MI->getOperand(3).getImm();
2133 if ((VT == MVT::i8 && MB <= 24) ||
2134 (VT == MVT::i16 && MB <= 16))
2141 case PPC::EXTSB8_32_64:
2142 /* There is no sign-extending load-byte instruction. */
2147 case PPC::EXTSH8_32_64: {
2148 if (VT != MVT::i16 && VT != MVT::i8)
2154 case PPC::EXTSW_32_64: {
2155 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8)
2161 // See if we can handle this address.
2163 if (!PPCComputeAddress(LI->getOperand(0), Addr))
2166 unsigned ResultReg = MI->getOperand(0).getReg();
2168 if (!PPCEmitLoad(VT, ResultReg, Addr, nullptr, IsZExt))
2171 MI->eraseFromParent();
2175 // Attempt to lower call arguments in a faster way than done by
2176 // the selection DAG code.
2177 bool PPCFastISel::FastLowerArguments() {
2178 // Defer to normal argument lowering for now. It's reasonably
2179 // efficient. Consider doing something like ARM to handle the
2180 // case where all args fit in registers, no varargs, no float
2185 // Handle materializing integer constants into a register. This is not
2186 // automatically generated for PowerPC, so must be explicitly created here.
2187 unsigned PPCFastISel::FastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) {
2189 if (Opc != ISD::Constant)
2192 // If we're using CR bit registers for i1 values, handle that as a special
2194 if (VT == MVT::i1 && PPCSubTarget->useCRBits()) {
2195 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass);
2196 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2197 TII.get(Imm == 0 ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2201 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 &&
2202 VT != MVT::i8 && VT != MVT::i1)
2205 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
2206 &PPC::GPRCRegClass);
2208 return PPCMaterialize64BitInt(Imm, RC);
2210 return PPCMaterialize32BitInt(Imm, RC);
2213 // Override for ADDI and ADDI8 to set the correct register class
2214 // on RHS operand 0. The automatic infrastructure naively assumes
2215 // GPRC for i32 and G8RC for i64; the concept of "no R0" is lost
2216 // for these cases. At the moment, none of the other automatically
2217 // generated RI instructions require special treatment. However, once
2218 // SelectSelect is implemented, "isel" requires similar handling.
2220 // Also be conservative about the output register class. Avoid
2221 // assigning R0 or X0 to the output register for GPRC and G8RC
2222 // register classes, as any such result could be used in ADDI, etc.,
2223 // where those regs have another meaning.
2224 unsigned PPCFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
2225 const TargetRegisterClass *RC,
2226 unsigned Op0, bool Op0IsKill,
2228 if (MachineInstOpcode == PPC::ADDI)
2229 MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass);
2230 else if (MachineInstOpcode == PPC::ADDI8)
2231 MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass);
2233 const TargetRegisterClass *UseRC =
2234 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2235 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2237 return FastISel::FastEmitInst_ri(MachineInstOpcode, UseRC,
2238 Op0, Op0IsKill, Imm);
2241 // Override for instructions with one register operand to avoid use of
2242 // R0/X0. The automatic infrastructure isn't aware of the context so
2243 // we must be conservative.
2244 unsigned PPCFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
2245 const TargetRegisterClass* RC,
2246 unsigned Op0, bool Op0IsKill) {
2247 const TargetRegisterClass *UseRC =
2248 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2249 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2251 return FastISel::FastEmitInst_r(MachineInstOpcode, UseRC, Op0, Op0IsKill);
2254 // Override for instructions with two register operands to avoid use
2255 // of R0/X0. The automatic infrastructure isn't aware of the context
2256 // so we must be conservative.
2257 unsigned PPCFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
2258 const TargetRegisterClass* RC,
2259 unsigned Op0, bool Op0IsKill,
2260 unsigned Op1, bool Op1IsKill) {
2261 const TargetRegisterClass *UseRC =
2262 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2263 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2265 return FastISel::FastEmitInst_rr(MachineInstOpcode, UseRC, Op0, Op0IsKill,
2270 // Create the fast instruction selector for PowerPC64 ELF.
2271 FastISel *PPC::createFastISel(FunctionLoweringInfo &FuncInfo,
2272 const TargetLibraryInfo *LibInfo) {
2273 const TargetMachine &TM = FuncInfo.MF->getTarget();
2275 // Only available on 64-bit ELF for now.
2276 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>();
2277 if (Subtarget->isPPC64() && Subtarget->isSVR4ABI())
2278 return new PPCFastISel(FuncInfo, LibInfo);