1 //===-- PPCFastISel.cpp - PowerPC FastISel implementation -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the PowerPC-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // PPCGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "ppcfastisel"
18 #include "PPCISelLowering.h"
19 #include "PPCSubtarget.h"
20 #include "PPCTargetMachine.h"
21 #include "MCTargetDesc/PPCPredicates.h"
22 #include "llvm/ADT/Optional.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/GlobalAlias.h"
32 #include "llvm/IR/GlobalVariable.h"
33 #include "llvm/IR/IntrinsicInst.h"
34 #include "llvm/IR/Operator.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/GetElementPtrTypeIterator.h"
37 #include "llvm/Target/TargetLowering.h"
38 #include "llvm/Target/TargetMachine.h"
44 typedef struct Address {
57 // Innocuous defaults for our address.
59 : BaseType(RegBase), Offset(0) {
64 class PPCFastISel : public FastISel {
66 const TargetMachine &TM;
67 const TargetInstrInfo &TII;
68 const TargetLowering &TLI;
69 const PPCSubtarget &PPCSubTarget;
73 explicit PPCFastISel(FunctionLoweringInfo &FuncInfo,
74 const TargetLibraryInfo *LibInfo)
75 : FastISel(FuncInfo, LibInfo),
76 TM(FuncInfo.MF->getTarget()),
77 TII(*TM.getInstrInfo()),
78 TLI(*TM.getTargetLowering()),
80 *((static_cast<const PPCTargetMachine *>(&TM))->getSubtargetImpl())
82 Context(&FuncInfo.Fn->getContext()) { }
84 // Backend specific FastISel code.
86 virtual bool TargetSelectInstruction(const Instruction *I);
87 virtual unsigned TargetMaterializeConstant(const Constant *C);
88 virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
89 virtual bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
91 virtual bool FastLowerArguments();
92 virtual unsigned FastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm);
93 virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
94 const TargetRegisterClass *RC,
95 unsigned Op0, bool Op0IsKill,
97 virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
98 const TargetRegisterClass *RC,
99 unsigned Op0, bool Op0IsKill);
100 virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
101 const TargetRegisterClass *RC,
102 unsigned Op0, bool Op0IsKill,
103 unsigned Op1, bool Op1IsKill);
105 // Instruction selection routines.
107 bool SelectLoad(const Instruction *I);
108 bool SelectStore(const Instruction *I);
109 bool SelectBranch(const Instruction *I);
110 bool SelectIndirectBr(const Instruction *I);
111 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
112 bool SelectRet(const Instruction *I);
113 bool SelectIntExt(const Instruction *I);
117 bool isTypeLegal(Type *Ty, MVT &VT);
118 bool isLoadTypeLegal(Type *Ty, MVT &VT);
119 bool PPCEmitCmp(const Value *Src1Value, const Value *Src2Value,
120 bool isZExt, unsigned DestReg);
121 bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
122 const TargetRegisterClass *RC, bool IsZExt = true,
123 unsigned FP64LoadOpc = PPC::LFD);
124 bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
125 bool PPCComputeAddress(const Value *Obj, Address &Addr);
126 void PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset,
128 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
129 unsigned DestReg, bool IsZExt);
130 unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT);
131 unsigned PPCMaterializeGV(const GlobalValue *GV, MVT VT);
132 unsigned PPCMaterializeInt(const Constant *C, MVT VT);
133 unsigned PPCMaterialize32BitInt(int64_t Imm,
134 const TargetRegisterClass *RC);
135 unsigned PPCMaterialize64BitInt(int64_t Imm,
136 const TargetRegisterClass *RC);
138 // Call handling routines.
140 CCAssignFn *usePPC32CCs(unsigned Flag);
143 #include "PPCGenFastISel.inc"
147 } // end anonymous namespace
149 #include "PPCGenCallingConv.inc"
151 // Function whose sole purpose is to kill compiler warnings
152 // stemming from unused functions included from PPCGenCallingConv.inc.
153 CCAssignFn *PPCFastISel::usePPC32CCs(unsigned Flag) {
155 return CC_PPC32_SVR4;
157 return CC_PPC32_SVR4_ByVal;
159 return CC_PPC32_SVR4_VarArg;
164 static Optional<PPC::Predicate> getComparePred(CmpInst::Predicate Pred) {
166 // These are not representable with any single compare.
167 case CmpInst::FCMP_FALSE:
168 case CmpInst::FCMP_UEQ:
169 case CmpInst::FCMP_UGT:
170 case CmpInst::FCMP_UGE:
171 case CmpInst::FCMP_ULT:
172 case CmpInst::FCMP_ULE:
173 case CmpInst::FCMP_UNE:
174 case CmpInst::FCMP_TRUE:
176 return Optional<PPC::Predicate>();
178 case CmpInst::FCMP_OEQ:
179 case CmpInst::ICMP_EQ:
182 case CmpInst::FCMP_OGT:
183 case CmpInst::ICMP_UGT:
184 case CmpInst::ICMP_SGT:
187 case CmpInst::FCMP_OGE:
188 case CmpInst::ICMP_UGE:
189 case CmpInst::ICMP_SGE:
192 case CmpInst::FCMP_OLT:
193 case CmpInst::ICMP_ULT:
194 case CmpInst::ICMP_SLT:
197 case CmpInst::FCMP_OLE:
198 case CmpInst::ICMP_ULE:
199 case CmpInst::ICMP_SLE:
202 case CmpInst::FCMP_ONE:
203 case CmpInst::ICMP_NE:
206 case CmpInst::FCMP_ORD:
209 case CmpInst::FCMP_UNO:
214 // Determine whether the type Ty is simple enough to be handled by
215 // fast-isel, and return its equivalent machine type in VT.
216 // FIXME: Copied directly from ARM -- factor into base class?
217 bool PPCFastISel::isTypeLegal(Type *Ty, MVT &VT) {
218 EVT Evt = TLI.getValueType(Ty, true);
220 // Only handle simple types.
221 if (Evt == MVT::Other || !Evt.isSimple()) return false;
222 VT = Evt.getSimpleVT();
224 // Handle all legal types, i.e. a register that will directly hold this
226 return TLI.isTypeLegal(VT);
229 // Determine whether the type Ty is simple enough to be handled by
230 // fast-isel as a load target, and return its equivalent machine type in VT.
231 bool PPCFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
232 if (isTypeLegal(Ty, VT)) return true;
234 // If this is a type than can be sign or zero-extended to a basic operation
235 // go ahead and accept it now.
236 if (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) {
243 // Given a value Obj, create an Address object Addr that represents its
244 // address. Return false if we can't handle it.
245 bool PPCFastISel::PPCComputeAddress(const Value *Obj, Address &Addr) {
246 const User *U = NULL;
247 unsigned Opcode = Instruction::UserOp1;
248 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
249 // Don't walk into other basic blocks unless the object is an alloca from
250 // another block, otherwise it may not have a virtual register assigned.
251 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
252 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
253 Opcode = I->getOpcode();
256 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
257 Opcode = C->getOpcode();
264 case Instruction::BitCast:
265 // Look through bitcasts.
266 return PPCComputeAddress(U->getOperand(0), Addr);
267 case Instruction::IntToPtr:
268 // Look past no-op inttoptrs.
269 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
270 return PPCComputeAddress(U->getOperand(0), Addr);
272 case Instruction::PtrToInt:
273 // Look past no-op ptrtoints.
274 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
275 return PPCComputeAddress(U->getOperand(0), Addr);
277 case Instruction::GetElementPtr: {
278 Address SavedAddr = Addr;
279 long TmpOffset = Addr.Offset;
281 // Iterate through the GEP folding the constants into offsets where
283 gep_type_iterator GTI = gep_type_begin(U);
284 for (User::const_op_iterator II = U->op_begin() + 1, IE = U->op_end();
285 II != IE; ++II, ++GTI) {
286 const Value *Op = *II;
287 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
288 const StructLayout *SL = TD.getStructLayout(STy);
289 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
290 TmpOffset += SL->getElementOffset(Idx);
292 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
294 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
295 // Constant-offset addressing.
296 TmpOffset += CI->getSExtValue() * S;
299 if (isa<AddOperator>(Op) &&
300 (!isa<Instruction>(Op) ||
301 FuncInfo.MBBMap[cast<Instruction>(Op)->getParent()]
303 isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
304 // An add (in the same block) with a constant operand. Fold the
307 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
308 TmpOffset += CI->getSExtValue() * S;
309 // Iterate on the other operand.
310 Op = cast<AddOperator>(Op)->getOperand(0);
314 goto unsupported_gep;
319 // Try to grab the base operand now.
320 Addr.Offset = TmpOffset;
321 if (PPCComputeAddress(U->getOperand(0), Addr)) return true;
323 // We failed, restore everything and try the other options.
329 case Instruction::Alloca: {
330 const AllocaInst *AI = cast<AllocaInst>(Obj);
331 DenseMap<const AllocaInst*, int>::iterator SI =
332 FuncInfo.StaticAllocaMap.find(AI);
333 if (SI != FuncInfo.StaticAllocaMap.end()) {
334 Addr.BaseType = Address::FrameIndexBase;
335 Addr.Base.FI = SI->second;
342 // FIXME: References to parameters fall through to the behavior
343 // below. They should be able to reference a frame index since
344 // they are stored to the stack, so we can get "ld rx, offset(r1)"
345 // instead of "addi ry, r1, offset / ld rx, 0(ry)". Obj will
346 // just contain the parameter. Try to handle this with a FI.
348 // Try to get this in a register if nothing else has worked.
349 if (Addr.Base.Reg == 0)
350 Addr.Base.Reg = getRegForValue(Obj);
352 // Prevent assignment of base register to X0, which is inappropriate
353 // for loads and stores alike.
354 if (Addr.Base.Reg != 0)
355 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass);
357 return Addr.Base.Reg != 0;
360 // Fix up some addresses that can't be used directly. For example, if
361 // an offset won't fit in an instruction field, we may need to move it
362 // into an index register.
363 void PPCFastISel::PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset,
364 unsigned &IndexReg) {
366 // Check whether the offset fits in the instruction field.
367 if (!isInt<16>(Addr.Offset))
370 // If this is a stack pointer and the offset needs to be simplified then
371 // put the alloca address into a register, set the base type back to
372 // register and continue. This should almost never happen.
373 if (!UseOffset && Addr.BaseType == Address::FrameIndexBase) {
374 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
375 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ADDI8),
376 ResultReg).addFrameIndex(Addr.Base.FI).addImm(0);
377 Addr.Base.Reg = ResultReg;
378 Addr.BaseType = Address::RegBase;
382 IntegerType *OffsetTy = ((VT == MVT::i32) ? Type::getInt32Ty(*Context)
383 : Type::getInt64Ty(*Context));
384 const ConstantInt *Offset =
385 ConstantInt::getSigned(OffsetTy, (int64_t)(Addr.Offset));
386 IndexReg = PPCMaterializeInt(Offset, MVT::i64);
387 assert(IndexReg && "Unexpected error in PPCMaterializeInt!");
391 // Emit a load instruction if possible, returning true if we succeeded,
392 // otherwise false. See commentary below for how the register class of
393 // the load is determined.
394 bool PPCFastISel::PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
395 const TargetRegisterClass *RC,
396 bool IsZExt, unsigned FP64LoadOpc) {
398 bool UseOffset = true;
400 // If ResultReg is given, it determines the register class of the load.
401 // Otherwise, RC is the register class to use. If the result of the
402 // load isn't anticipated in this block, both may be zero, in which
403 // case we must make a conservative guess. In particular, don't assign
404 // R0 or X0 to the result register, as the result may be used in a load,
405 // store, add-immediate, or isel that won't permit this. (Though
406 // perhaps the spill and reload of live-exit values would handle this?)
407 const TargetRegisterClass *UseRC =
408 (ResultReg ? MRI.getRegClass(ResultReg) :
410 (VT == MVT::f64 ? &PPC::F8RCRegClass :
411 (VT == MVT::f32 ? &PPC::F4RCRegClass :
412 (VT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
413 &PPC::GPRC_and_GPRC_NOR0RegClass)))));
415 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass);
417 switch (VT.SimpleTy) {
418 default: // e.g., vector types not handled
421 Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8;
425 (Is32BitInt ? PPC::LHZ : PPC::LHZ8) :
426 (Is32BitInt ? PPC::LHA : PPC::LHA8));
430 (Is32BitInt ? PPC::LWZ : PPC::LWZ8) :
431 (Is32BitInt ? PPC::LWA_32 : PPC::LWA));
432 if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0))
437 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) &&
438 "64-bit load with 32-bit target??");
439 UseOffset = ((Addr.Offset & 3) == 0);
449 // If necessary, materialize the offset into a register and use
450 // the indexed form. Also handle stack pointers with special needs.
451 unsigned IndexReg = 0;
452 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg);
454 ResultReg = createResultReg(UseRC);
456 // Note: If we still have a frame index here, we know the offset is
457 // in range, as otherwise PPCSimplifyAddress would have converted it
459 if (Addr.BaseType == Address::FrameIndexBase) {
461 MachineMemOperand *MMO =
462 FuncInfo.MF->getMachineMemOperand(
463 MachinePointerInfo::getFixedStack(Addr.Base.FI, Addr.Offset),
464 MachineMemOperand::MOLoad, MFI.getObjectSize(Addr.Base.FI),
465 MFI.getObjectAlignment(Addr.Base.FI));
467 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
468 .addImm(Addr.Offset).addFrameIndex(Addr.Base.FI).addMemOperand(MMO);
470 // Base reg with offset in range.
471 } else if (UseOffset) {
473 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
474 .addImm(Addr.Offset).addReg(Addr.Base.Reg);
478 // Get the RR opcode corresponding to the RI one. FIXME: It would be
479 // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it
480 // is hard to get at.
482 default: llvm_unreachable("Unexpected opcode!");
483 case PPC::LBZ: Opc = PPC::LBZX; break;
484 case PPC::LBZ8: Opc = PPC::LBZX8; break;
485 case PPC::LHZ: Opc = PPC::LHZX; break;
486 case PPC::LHZ8: Opc = PPC::LHZX8; break;
487 case PPC::LHA: Opc = PPC::LHAX; break;
488 case PPC::LHA8: Opc = PPC::LHAX8; break;
489 case PPC::LWZ: Opc = PPC::LWZX; break;
490 case PPC::LWZ8: Opc = PPC::LWZX8; break;
491 case PPC::LWA: Opc = PPC::LWAX; break;
492 case PPC::LWA_32: Opc = PPC::LWAX_32; break;
493 case PPC::LD: Opc = PPC::LDX; break;
494 case PPC::LFS: Opc = PPC::LFSX; break;
495 case PPC::LFD: Opc = PPC::LFDX; break;
497 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
498 .addReg(Addr.Base.Reg).addReg(IndexReg);
504 // Attempt to fast-select a load instruction.
505 bool PPCFastISel::SelectLoad(const Instruction *I) {
506 // FIXME: No atomic loads are supported.
507 if (cast<LoadInst>(I)->isAtomic())
510 // Verify we have a legal type before going any further.
512 if (!isLoadTypeLegal(I->getType(), VT))
515 // See if we can handle this address.
517 if (!PPCComputeAddress(I->getOperand(0), Addr))
520 // Look at the currently assigned register for this instruction
521 // to determine the required register class. This is necessary
522 // to constrain RA from using R0/X0 when this is not legal.
523 unsigned AssignedReg = FuncInfo.ValueMap[I];
524 const TargetRegisterClass *RC =
525 AssignedReg ? MRI.getRegClass(AssignedReg) : 0;
527 unsigned ResultReg = 0;
528 if (!PPCEmitLoad(VT, ResultReg, Addr, RC))
530 UpdateValueMap(I, ResultReg);
534 // Emit a store instruction to store SrcReg at Addr.
535 bool PPCFastISel::PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr) {
536 assert(SrcReg && "Nothing to store!");
538 bool UseOffset = true;
540 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg);
541 bool Is32BitInt = RC->hasSuperClassEq(&PPC::GPRCRegClass);
543 switch (VT.SimpleTy) {
544 default: // e.g., vector types not handled
547 Opc = Is32BitInt ? PPC::STB : PPC::STB8;
550 Opc = Is32BitInt ? PPC::STH : PPC::STH8;
553 assert(Is32BitInt && "Not GPRC for i32??");
558 UseOffset = ((Addr.Offset & 3) == 0);
568 // If necessary, materialize the offset into a register and use
569 // the indexed form. Also handle stack pointers with special needs.
570 unsigned IndexReg = 0;
571 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg);
573 // Note: If we still have a frame index here, we know the offset is
574 // in range, as otherwise PPCSimplifyAddress would have converted it
576 if (Addr.BaseType == Address::FrameIndexBase) {
577 MachineMemOperand *MMO =
578 FuncInfo.MF->getMachineMemOperand(
579 MachinePointerInfo::getFixedStack(Addr.Base.FI, Addr.Offset),
580 MachineMemOperand::MOStore, MFI.getObjectSize(Addr.Base.FI),
581 MFI.getObjectAlignment(Addr.Base.FI));
583 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc)).addReg(SrcReg)
584 .addImm(Addr.Offset).addFrameIndex(Addr.Base.FI).addMemOperand(MMO);
586 // Base reg with offset in range.
587 } else if (UseOffset) {
588 if (Addr.Offset == 0 && Opc == PPC::STW8)
589 dbgs() << "Possible problem here.\n";
590 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc))
591 .addReg(SrcReg).addImm(Addr.Offset).addReg(Addr.Base.Reg);
595 // Get the RR opcode corresponding to the RI one. FIXME: It would be
596 // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it
597 // is hard to get at.
599 default: llvm_unreachable("Unexpected opcode!");
600 case PPC::STB: Opc = PPC::STBX; break;
601 case PPC::STH : Opc = PPC::STHX; break;
602 case PPC::STW : Opc = PPC::STWX; break;
603 case PPC::STB8: Opc = PPC::STBX8; break;
604 case PPC::STH8: Opc = PPC::STHX8; break;
605 case PPC::STW8: Opc = PPC::STWX8; break;
606 case PPC::STD: Opc = PPC::STDX; break;
607 case PPC::STFS: Opc = PPC::STFSX; break;
608 case PPC::STFD: Opc = PPC::STFDX; break;
610 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc))
611 .addReg(SrcReg).addReg(Addr.Base.Reg).addReg(IndexReg);
617 // Attempt to fast-select a store instruction.
618 bool PPCFastISel::SelectStore(const Instruction *I) {
619 Value *Op0 = I->getOperand(0);
622 // FIXME: No atomics loads are supported.
623 if (cast<StoreInst>(I)->isAtomic())
626 // Verify we have a legal type before going any further.
628 if (!isLoadTypeLegal(Op0->getType(), VT))
631 // Get the value to be stored into a register.
632 SrcReg = getRegForValue(Op0);
636 // See if we can handle this address.
638 if (!PPCComputeAddress(I->getOperand(1), Addr))
641 if (!PPCEmitStore(VT, SrcReg, Addr))
647 // Attempt to fast-select a branch instruction.
648 bool PPCFastISel::SelectBranch(const Instruction *I) {
649 const BranchInst *BI = cast<BranchInst>(I);
650 MachineBasicBlock *BrBB = FuncInfo.MBB;
651 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
652 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
654 // For now, just try the simplest case where it's fed by a compare.
655 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
656 Optional<PPC::Predicate> OptPPCPred = getComparePred(CI->getPredicate());
660 PPC::Predicate PPCPred = OptPPCPred.getValue();
662 // Take advantage of fall-through opportunities.
663 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
665 PPCPred = PPC::InvertPredicate(PPCPred);
668 unsigned CondReg = createResultReg(&PPC::CRRCRegClass);
670 if (!PPCEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(),
674 BuildMI(*BrBB, FuncInfo.InsertPt, DL, TII.get(PPC::BCC))
675 .addImm(PPCPred).addReg(CondReg).addMBB(TBB);
676 FastEmitBranch(FBB, DL);
677 FuncInfo.MBB->addSuccessor(TBB);
680 } else if (const ConstantInt *CI =
681 dyn_cast<ConstantInt>(BI->getCondition())) {
682 uint64_t Imm = CI->getZExtValue();
683 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
684 FastEmitBranch(Target, DL);
688 // FIXME: ARM looks for a case where the block containing the compare
689 // has been split from the block containing the branch. If this happens,
690 // there is a vreg available containing the result of the compare. I'm
691 // not sure we can do much, as we've lost the predicate information with
692 // the compare instruction -- we have a 4-bit CR but don't know which bit
697 // Attempt to emit a compare of the two source values. Signed and unsigned
698 // comparisons are supported. Return false if we can't handle it.
699 bool PPCFastISel::PPCEmitCmp(const Value *SrcValue1, const Value *SrcValue2,
700 bool IsZExt, unsigned DestReg) {
701 Type *Ty = SrcValue1->getType();
702 EVT SrcEVT = TLI.getValueType(Ty, true);
703 if (!SrcEVT.isSimple())
705 MVT SrcVT = SrcEVT.getSimpleVT();
707 // See if operand 2 is an immediate encodeable in the compare.
708 // FIXME: Operands are not in canonical order at -O0, so an immediate
709 // operand in position 1 is a lost opportunity for now. We are
710 // similar to ARM in this regard.
714 // Only 16-bit integer constants can be represented in compares for
715 // PowerPC. Others will be materialized into a register.
716 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(SrcValue2)) {
717 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
718 SrcVT == MVT::i8 || SrcVT == MVT::i1) {
719 const APInt &CIVal = ConstInt->getValue();
720 Imm = (IsZExt) ? (long)CIVal.getZExtValue() : (long)CIVal.getSExtValue();
721 if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm)))
727 bool NeedsExt = false;
728 switch (SrcVT.SimpleTy) {
729 default: return false;
731 CmpOpc = PPC::FCMPUS;
734 CmpOpc = PPC::FCMPUD;
740 // Intentional fall-through.
743 CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW;
745 CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI;
749 CmpOpc = IsZExt ? PPC::CMPLD : PPC::CMPD;
751 CmpOpc = IsZExt ? PPC::CMPLDI : PPC::CMPDI;
755 unsigned SrcReg1 = getRegForValue(SrcValue1);
759 unsigned SrcReg2 = 0;
761 SrcReg2 = getRegForValue(SrcValue2);
767 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
768 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt))
773 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
774 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt))
781 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc), DestReg)
782 .addReg(SrcReg1).addReg(SrcReg2);
784 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc), DestReg)
785 .addReg(SrcReg1).addImm(Imm);
790 // Attempt to fast-select a binary integer operation that isn't already
791 // handled automatically.
792 bool PPCFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
793 EVT DestVT = TLI.getValueType(I->getType(), true);
795 // We can get here in the case when we have a binary operation on a non-legal
796 // type and the target independent selector doesn't know how to handle it.
797 if (DestVT != MVT::i16 && DestVT != MVT::i8)
800 // Look at the currently assigned register for this instruction
801 // to determine the required register class. If there is no register,
802 // make a conservative choice (don't assign R0).
803 unsigned AssignedReg = FuncInfo.ValueMap[I];
804 const TargetRegisterClass *RC =
805 (AssignedReg ? MRI.getRegClass(AssignedReg) :
806 &PPC::GPRC_and_GPRC_NOR0RegClass);
807 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
811 default: return false;
813 Opc = IsGPRC ? PPC::ADD4 : PPC::ADD8;
816 Opc = IsGPRC ? PPC::OR : PPC::OR8;
819 Opc = IsGPRC ? PPC::SUBF : PPC::SUBF8;
823 unsigned ResultReg = createResultReg(RC ? RC : &PPC::G8RCRegClass);
824 unsigned SrcReg1 = getRegForValue(I->getOperand(0));
825 if (SrcReg1 == 0) return false;
827 // Handle case of small immediate operand.
828 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(1))) {
829 const APInt &CIVal = ConstInt->getValue();
830 int Imm = (int)CIVal.getSExtValue();
832 if (isInt<16>(Imm)) {
835 llvm_unreachable("Missing case!");
838 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
842 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
855 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
864 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
871 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
872 .addReg(SrcReg1).addImm(Imm);
873 UpdateValueMap(I, ResultReg);
880 unsigned SrcReg2 = getRegForValue(I->getOperand(1));
881 if (SrcReg2 == 0) return false;
883 // Reverse operands for subtract-from.
884 if (ISDOpcode == ISD::SUB)
885 std::swap(SrcReg1, SrcReg2);
887 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
888 .addReg(SrcReg1).addReg(SrcReg2);
889 UpdateValueMap(I, ResultReg);
893 // Attempt to fast-select a return instruction.
894 bool PPCFastISel::SelectRet(const Instruction *I) {
896 if (!FuncInfo.CanLowerReturn)
899 const ReturnInst *Ret = cast<ReturnInst>(I);
900 const Function &F = *I->getParent()->getParent();
902 // Build a list of return value registers.
903 SmallVector<unsigned, 4> RetRegs;
904 CallingConv::ID CC = F.getCallingConv();
906 if (Ret->getNumOperands() > 0) {
907 SmallVector<ISD::OutputArg, 4> Outs;
908 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
910 // Analyze operands of the call, assigning locations to each operand.
911 SmallVector<CCValAssign, 16> ValLocs;
912 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs, *Context);
913 CCInfo.AnalyzeReturn(Outs, RetCC_PPC64_ELF_FIS);
914 const Value *RV = Ret->getOperand(0);
916 // FIXME: Only one output register for now.
917 if (ValLocs.size() > 1)
920 // Special case for returning a constant integer of any size.
921 // Materialize the constant as an i64 and copy it to the return
922 // register. This avoids an unnecessary extend or truncate.
923 if (isa<ConstantInt>(*RV)) {
924 const Constant *C = cast<Constant>(RV);
925 unsigned SrcReg = PPCMaterializeInt(C, MVT::i64);
926 unsigned RetReg = ValLocs[0].getLocReg();
927 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
928 RetReg).addReg(SrcReg);
929 RetRegs.push_back(RetReg);
932 unsigned Reg = getRegForValue(RV);
937 // Copy the result values into the output registers.
938 for (unsigned i = 0; i < ValLocs.size(); ++i) {
940 CCValAssign &VA = ValLocs[i];
941 assert(VA.isRegLoc() && "Can only return in registers!");
942 RetRegs.push_back(VA.getLocReg());
943 unsigned SrcReg = Reg + VA.getValNo();
945 EVT RVEVT = TLI.getValueType(RV->getType());
946 if (!RVEVT.isSimple())
948 MVT RVVT = RVEVT.getSimpleVT();
949 MVT DestVT = VA.getLocVT();
951 if (RVVT != DestVT && RVVT != MVT::i8 &&
952 RVVT != MVT::i16 && RVVT != MVT::i32)
955 if (RVVT != DestVT) {
956 switch (VA.getLocInfo()) {
958 llvm_unreachable("Unknown loc info!");
959 case CCValAssign::Full:
960 llvm_unreachable("Full value assign but types don't match?");
961 case CCValAssign::AExt:
962 case CCValAssign::ZExt: {
963 const TargetRegisterClass *RC =
964 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
965 unsigned TmpReg = createResultReg(RC);
966 if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, true))
971 case CCValAssign::SExt: {
972 const TargetRegisterClass *RC =
973 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
974 unsigned TmpReg = createResultReg(RC);
975 if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, false))
983 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
984 TII.get(TargetOpcode::COPY), RetRegs[i])
990 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
993 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
994 MIB.addReg(RetRegs[i], RegState::Implicit);
999 // Attempt to emit an integer extend of SrcReg into DestReg. Both
1000 // signed and zero extensions are supported. Return false if we
1002 bool PPCFastISel::PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1003 unsigned DestReg, bool IsZExt) {
1004 if (DestVT != MVT::i32 && DestVT != MVT::i64)
1006 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 && SrcVT != MVT::i32)
1009 // Signed extensions use EXTSB, EXTSH, EXTSW.
1012 if (SrcVT == MVT::i8)
1013 Opc = (DestVT == MVT::i32) ? PPC::EXTSB : PPC::EXTSB8_32_64;
1014 else if (SrcVT == MVT::i16)
1015 Opc = (DestVT == MVT::i32) ? PPC::EXTSH : PPC::EXTSH8_32_64;
1017 assert(DestVT == MVT::i64 && "Signed extend from i32 to i32??");
1018 Opc = PPC::EXTSW_32_64;
1020 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
1023 // Unsigned 32-bit extensions use RLWINM.
1024 } else if (DestVT == MVT::i32) {
1026 if (SrcVT == MVT::i8)
1029 assert(SrcVT == MVT::i16 && "Unsigned extend from i32 to i32??");
1032 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::RLWINM),
1034 .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB).addImm(/*ME=*/31);
1036 // Unsigned 64-bit extensions use RLDICL (with a 32-bit source).
1039 if (SrcVT == MVT::i8)
1041 else if (SrcVT == MVT::i16)
1045 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1046 TII.get(PPC::RLDICL_32_64), DestReg)
1047 .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB);
1053 // Attempt to fast-select an indirect branch instruction.
1054 bool PPCFastISel::SelectIndirectBr(const Instruction *I) {
1055 unsigned AddrReg = getRegForValue(I->getOperand(0));
1059 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::MTCTR8))
1061 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::BCTR8));
1063 const IndirectBrInst *IB = cast<IndirectBrInst>(I);
1064 for (unsigned i = 0, e = IB->getNumSuccessors(); i != e; ++i)
1065 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[IB->getSuccessor(i)]);
1070 // Attempt to fast-select an integer extend instruction.
1071 bool PPCFastISel::SelectIntExt(const Instruction *I) {
1072 Type *DestTy = I->getType();
1073 Value *Src = I->getOperand(0);
1074 Type *SrcTy = Src->getType();
1076 bool IsZExt = isa<ZExtInst>(I);
1077 unsigned SrcReg = getRegForValue(Src);
1078 if (!SrcReg) return false;
1080 EVT SrcEVT, DestEVT;
1081 SrcEVT = TLI.getValueType(SrcTy, true);
1082 DestEVT = TLI.getValueType(DestTy, true);
1083 if (!SrcEVT.isSimple())
1085 if (!DestEVT.isSimple())
1088 MVT SrcVT = SrcEVT.getSimpleVT();
1089 MVT DestVT = DestEVT.getSimpleVT();
1091 // If we know the register class needed for the result of this
1092 // instruction, use it. Otherwise pick the register class of the
1093 // correct size that does not contain X0/R0, since we don't know
1094 // whether downstream uses permit that assignment.
1095 unsigned AssignedReg = FuncInfo.ValueMap[I];
1096 const TargetRegisterClass *RC =
1097 (AssignedReg ? MRI.getRegClass(AssignedReg) :
1098 (DestVT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
1099 &PPC::GPRC_and_GPRC_NOR0RegClass));
1100 unsigned ResultReg = createResultReg(RC);
1102 if (!PPCEmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, IsZExt))
1105 UpdateValueMap(I, ResultReg);
1109 // Attempt to fast-select an instruction that wasn't handled by
1110 // the table-generated machinery.
1111 bool PPCFastISel::TargetSelectInstruction(const Instruction *I) {
1113 switch (I->getOpcode()) {
1114 case Instruction::Load:
1115 return SelectLoad(I);
1116 case Instruction::Store:
1117 return SelectStore(I);
1118 case Instruction::Br:
1119 return SelectBranch(I);
1120 case Instruction::IndirectBr:
1121 return SelectIndirectBr(I);
1122 case Instruction::Add:
1123 return SelectBinaryIntOp(I, ISD::ADD);
1124 case Instruction::Or:
1125 return SelectBinaryIntOp(I, ISD::OR);
1126 case Instruction::Sub:
1127 return SelectBinaryIntOp(I, ISD::SUB);
1128 case Instruction::Ret:
1129 return SelectRet(I);
1130 case Instruction::ZExt:
1131 case Instruction::SExt:
1132 return SelectIntExt(I);
1133 // Here add other flavors of Instruction::XXX that automated
1134 // cases don't catch. For example, switches are terminators
1135 // that aren't yet handled.
1142 // Materialize a floating-point constant into a register, and return
1143 // the register number (or zero if we failed to handle it).
1144 unsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) {
1145 // No plans to handle long double here.
1146 if (VT != MVT::f32 && VT != MVT::f64)
1149 // All FP constants are loaded from the constant pool.
1150 unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
1151 assert(Align > 0 && "Unexpectedly missing alignment information!");
1152 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
1153 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
1154 CodeModel::Model CModel = TM.getCodeModel();
1156 MachineMemOperand *MMO =
1157 FuncInfo.MF->getMachineMemOperand(
1158 MachinePointerInfo::getConstantPool(), MachineMemOperand::MOLoad,
1159 (VT == MVT::f32) ? 4 : 8, Align);
1161 unsigned Opc = (VT == MVT::f32) ? PPC::LFS : PPC::LFD;
1162 unsigned TmpReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
1164 // For small code model, generate a LF[SD](0, LDtocCPT(Idx, X2)).
1165 if (CModel == CodeModel::Small || CModel == CodeModel::JITDefault) {
1166 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::LDtocCPT),
1168 .addConstantPoolIndex(Idx).addReg(PPC::X2);
1169 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
1170 .addImm(0).addReg(TmpReg).addMemOperand(MMO);
1172 // Otherwise we generate LF[SD](Idx[lo], ADDIStocHA(X2, Idx)).
1173 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ADDIStocHA),
1174 TmpReg).addReg(PPC::X2).addConstantPoolIndex(Idx);
1175 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
1176 .addConstantPoolIndex(Idx, 0, PPCII::MO_TOC_LO)
1178 .addMemOperand(MMO);
1184 // Materialize the address of a global value into a register, and return
1185 // the register number (or zero if we failed to handle it).
1186 unsigned PPCFastISel::PPCMaterializeGV(const GlobalValue *GV, MVT VT) {
1187 assert(VT == MVT::i64 && "Non-address!");
1188 const TargetRegisterClass *RC = &PPC::G8RC_and_G8RC_NOX0RegClass;
1189 unsigned DestReg = createResultReg(RC);
1191 // Global values may be plain old object addresses, TLS object
1192 // addresses, constant pool entries, or jump tables. How we generate
1193 // code for these may depend on small, medium, or large code model.
1194 CodeModel::Model CModel = TM.getCodeModel();
1196 // FIXME: Jump tables are not yet required because fast-isel doesn't
1197 // handle switches; if that changes, we need them as well. For now,
1198 // what follows assumes everything's a generic (or TLS) global address.
1199 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
1201 // If GV is an alias, use the aliasee for determining thread-locality.
1202 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
1203 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal(false));
1204 assert((GVar || isa<Function>(GV)) && "Unexpected GV subclass!");
1207 // FIXME: We don't yet handle the complexity of TLS.
1208 bool IsTLS = GVar && GVar->isThreadLocal();
1212 // For small code model, generate a simple TOC load.
1213 if (CModel == CodeModel::Small || CModel == CodeModel::JITDefault)
1214 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::LDtoc), DestReg)
1215 .addGlobalAddress(GV).addReg(PPC::X2);
1217 // If the address is an externally defined symbol, a symbol with
1218 // common or externally available linkage, a function address, or a
1219 // jump table address (not yet needed), or if we are generating code
1220 // for large code model, we generate:
1221 // LDtocL(GV, ADDIStocHA(%X2, GV))
1222 // Otherwise we generate:
1223 // ADDItocL(ADDIStocHA(%X2, GV), GV)
1224 // Either way, start with the ADDIStocHA:
1225 unsigned HighPartReg = createResultReg(RC);
1226 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ADDIStocHA),
1227 HighPartReg).addReg(PPC::X2).addGlobalAddress(GV);
1229 // !GVar implies a function address. An external variable is one
1230 // without an initializer.
1231 // If/when switches are implemented, jump tables should be handled
1232 // on the "if" path here.
1233 if (CModel == CodeModel::Large || !GVar || !GVar->hasInitializer() ||
1234 GVar->hasCommonLinkage() || GVar->hasAvailableExternallyLinkage())
1235 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::LDtocL),
1236 DestReg).addGlobalAddress(GV).addReg(HighPartReg);
1238 // Otherwise generate the ADDItocL.
1239 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ADDItocL),
1240 DestReg).addReg(HighPartReg).addGlobalAddress(GV);
1246 // Materialize a 32-bit integer constant into a register, and return
1247 // the register number (or zero if we failed to handle it).
1248 unsigned PPCFastISel::PPCMaterialize32BitInt(int64_t Imm,
1249 const TargetRegisterClass *RC) {
1250 unsigned Lo = Imm & 0xFFFF;
1251 unsigned Hi = (Imm >> 16) & 0xFFFF;
1253 unsigned ResultReg = createResultReg(RC);
1254 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
1257 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1258 TII.get(IsGPRC ? PPC::LI : PPC::LI8), ResultReg)
1261 // Both Lo and Hi have nonzero bits.
1262 unsigned TmpReg = createResultReg(RC);
1263 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1264 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), TmpReg)
1266 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1267 TII.get(IsGPRC ? PPC::ORI : PPC::ORI8), ResultReg)
1268 .addReg(TmpReg).addImm(Lo);
1271 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1272 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), ResultReg)
1278 // Materialize a 64-bit integer constant into a register, and return
1279 // the register number (or zero if we failed to handle it).
1280 unsigned PPCFastISel::PPCMaterialize64BitInt(int64_t Imm,
1281 const TargetRegisterClass *RC) {
1282 unsigned Remainder = 0;
1285 // If the value doesn't fit in 32 bits, see if we can shift it
1286 // so that it fits in 32 bits.
1287 if (!isInt<32>(Imm)) {
1288 Shift = countTrailingZeros<uint64_t>(Imm);
1289 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
1291 if (isInt<32>(ImmSh))
1300 // Handle the high-order 32 bits (if shifted) or the whole 32 bits
1301 // (if not shifted).
1302 unsigned TmpReg1 = PPCMaterialize32BitInt(Imm, RC);
1306 // If upper 32 bits were not zero, we've built them and need to shift
1310 TmpReg2 = createResultReg(RC);
1311 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::RLDICR),
1312 TmpReg2).addReg(TmpReg1).addImm(Shift).addImm(63 - Shift);
1316 unsigned TmpReg3, Hi, Lo;
1317 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
1318 TmpReg3 = createResultReg(RC);
1319 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ORIS8),
1320 TmpReg3).addReg(TmpReg2).addImm(Hi);
1324 if ((Lo = Remainder & 0xFFFF)) {
1325 unsigned ResultReg = createResultReg(RC);
1326 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ORI8),
1327 ResultReg).addReg(TmpReg3).addImm(Lo);
1335 // Materialize an integer constant into a register, and return
1336 // the register number (or zero if we failed to handle it).
1337 unsigned PPCFastISel::PPCMaterializeInt(const Constant *C, MVT VT) {
1339 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 &&
1340 VT != MVT::i8 && VT != MVT::i1)
1343 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
1344 &PPC::GPRCRegClass);
1346 // If the constant is in range, use a load-immediate.
1347 const ConstantInt *CI = cast<ConstantInt>(C);
1348 if (isInt<16>(CI->getSExtValue())) {
1349 unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI;
1350 unsigned ImmReg = createResultReg(RC);
1351 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ImmReg)
1352 .addImm(CI->getSExtValue());
1356 // Construct the constant piecewise.
1357 int64_t Imm = CI->getZExtValue();
1360 return PPCMaterialize64BitInt(Imm, RC);
1361 else if (VT == MVT::i32)
1362 return PPCMaterialize32BitInt(Imm, RC);
1367 // Materialize a constant into a register, and return the register
1368 // number (or zero if we failed to handle it).
1369 unsigned PPCFastISel::TargetMaterializeConstant(const Constant *C) {
1370 EVT CEVT = TLI.getValueType(C->getType(), true);
1372 // Only handle simple types.
1373 if (!CEVT.isSimple()) return 0;
1374 MVT VT = CEVT.getSimpleVT();
1376 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1377 return PPCMaterializeFP(CFP, VT);
1378 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1379 return PPCMaterializeGV(GV, VT);
1380 else if (isa<ConstantInt>(C))
1381 return PPCMaterializeInt(C, VT);
1382 // TBD: Global values.
1387 // Materialize the address created by an alloca into a register, and
1388 // return the register number (or zero if we failed to handle it). TBD.
1389 unsigned PPCFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
1393 // Fold loads into extends when possible.
1394 // FIXME: We can have multiple redundant extend/trunc instructions
1395 // following a load. The folding only picks up one. Extend this
1396 // to check subsequent instructions for the same pattern and remove
1397 // them. Thus ResultReg should be the def reg for the last redundant
1398 // instruction in a chain, and all intervening instructions can be
1399 // removed from parent. Change test/CodeGen/PowerPC/fast-isel-fold.ll
1400 // to add ELF64-NOT: rldicl to the appropriate tests when this works.
1401 bool PPCFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
1402 const LoadInst *LI) {
1403 // Verify we have a legal type before going any further.
1405 if (!isLoadTypeLegal(LI->getType(), VT))
1408 // Combine load followed by zero- or sign-extend.
1409 bool IsZExt = false;
1410 switch(MI->getOpcode()) {
1415 case PPC::RLDICL_32_64: {
1417 unsigned MB = MI->getOperand(3).getImm();
1418 if ((VT == MVT::i8 && MB <= 56) ||
1419 (VT == MVT::i16 && MB <= 48) ||
1420 (VT == MVT::i32 && MB <= 32))
1426 case PPC::RLWINM8: {
1428 unsigned MB = MI->getOperand(3).getImm();
1429 if ((VT == MVT::i8 && MB <= 24) ||
1430 (VT == MVT::i16 && MB <= 16))
1437 case PPC::EXTSB8_32_64:
1438 /* There is no sign-extending load-byte instruction. */
1443 case PPC::EXTSH8_32_64: {
1444 if (VT != MVT::i16 && VT != MVT::i8)
1450 case PPC::EXTSW_32_64: {
1451 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8)
1457 // See if we can handle this address.
1459 if (!PPCComputeAddress(LI->getOperand(0), Addr))
1462 unsigned ResultReg = MI->getOperand(0).getReg();
1464 if (!PPCEmitLoad(VT, ResultReg, Addr, 0, IsZExt))
1467 MI->eraseFromParent();
1471 // Attempt to lower call arguments in a faster way than done by
1472 // the selection DAG code.
1473 bool PPCFastISel::FastLowerArguments() {
1474 // Defer to normal argument lowering for now. It's reasonably
1475 // efficient. Consider doing something like ARM to handle the
1476 // case where all args fit in registers, no varargs, no float
1481 // Handle materializing integer constants into a register. This is not
1482 // automatically generated for PowerPC, so must be explicitly created here.
1483 unsigned PPCFastISel::FastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) {
1485 if (Opc != ISD::Constant)
1488 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 &&
1489 VT != MVT::i8 && VT != MVT::i1)
1492 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
1493 &PPC::GPRCRegClass);
1495 return PPCMaterialize64BitInt(Imm, RC);
1497 return PPCMaterialize32BitInt(Imm, RC);
1500 // Override for ADDI and ADDI8 to set the correct register class
1501 // on RHS operand 0. The automatic infrastructure naively assumes
1502 // GPRC for i32 and G8RC for i64; the concept of "no R0" is lost
1503 // for these cases. At the moment, none of the other automatically
1504 // generated RI instructions require special treatment. However, once
1505 // SelectSelect is implemented, "isel" requires similar handling.
1507 // Also be conservative about the output register class. Avoid
1508 // assigning R0 or X0 to the output register for GPRC and G8RC
1509 // register classes, as any such result could be used in ADDI, etc.,
1510 // where those regs have another meaning.
1511 unsigned PPCFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
1512 const TargetRegisterClass *RC,
1513 unsigned Op0, bool Op0IsKill,
1515 if (MachineInstOpcode == PPC::ADDI)
1516 MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass);
1517 else if (MachineInstOpcode == PPC::ADDI8)
1518 MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass);
1520 const TargetRegisterClass *UseRC =
1521 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
1522 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
1524 return FastISel::FastEmitInst_ri(MachineInstOpcode, UseRC,
1525 Op0, Op0IsKill, Imm);
1528 // Override for instructions with one register operand to avoid use of
1529 // R0/X0. The automatic infrastructure isn't aware of the context so
1530 // we must be conservative.
1531 unsigned PPCFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
1532 const TargetRegisterClass* RC,
1533 unsigned Op0, bool Op0IsKill) {
1534 const TargetRegisterClass *UseRC =
1535 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
1536 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
1538 return FastISel::FastEmitInst_r(MachineInstOpcode, UseRC, Op0, Op0IsKill);
1541 // Override for instructions with two register operands to avoid use
1542 // of R0/X0. The automatic infrastructure isn't aware of the context
1543 // so we must be conservative.
1544 unsigned PPCFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
1545 const TargetRegisterClass* RC,
1546 unsigned Op0, bool Op0IsKill,
1547 unsigned Op1, bool Op1IsKill) {
1548 const TargetRegisterClass *UseRC =
1549 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
1550 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
1552 return FastISel::FastEmitInst_rr(MachineInstOpcode, UseRC, Op0, Op0IsKill,
1557 // Create the fast instruction selector for PowerPC64 ELF.
1558 FastISel *PPC::createFastISel(FunctionLoweringInfo &FuncInfo,
1559 const TargetLibraryInfo *LibInfo) {
1560 const TargetMachine &TM = FuncInfo.MF->getTarget();
1562 // Only available on 64-bit ELF for now.
1563 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>();
1564 if (Subtarget->isPPC64() && Subtarget->isSVR4ABI())
1565 return new PPCFastISel(FuncInfo, LibInfo);