1 //===-- PPCFastISel.cpp - PowerPC FastISel implementation -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the PowerPC-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // PPCGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "MCTargetDesc/PPCPredicates.h"
18 #include "PPCCallingConv.h"
19 #include "PPCISelLowering.h"
20 #include "PPCMachineFunctionInfo.h"
21 #include "PPCSubtarget.h"
22 #include "PPCTargetMachine.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/IR/CallingConv.h"
32 #include "llvm/IR/GetElementPtrTypeIterator.h"
33 #include "llvm/IR/GlobalAlias.h"
34 #include "llvm/IR/GlobalVariable.h"
35 #include "llvm/IR/IntrinsicInst.h"
36 #include "llvm/IR/Operator.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Target/TargetLowering.h"
39 #include "llvm/Target/TargetMachine.h"
41 //===----------------------------------------------------------------------===//
44 // fastLowerArguments: Handle simple cases.
45 // PPCMaterializeGV: Handle TLS.
46 // SelectCall: Handle function pointers.
47 // SelectCall: Handle multi-register return values.
48 // SelectCall: Optimize away nops for local calls.
49 // processCallArgs: Handle bit-converted arguments.
50 // finishCall: Handle multi-register return values.
51 // PPCComputeAddress: Handle parameter references as FrameIndex's.
52 // PPCEmitCmp: Handle immediate as operand 1.
53 // SelectCall: Handle small byval arguments.
54 // SelectIntrinsicCall: Implement.
55 // SelectSelect: Implement.
56 // Consider factoring isTypeLegal into the base class.
57 // Implement switches and jump tables.
59 //===----------------------------------------------------------------------===//
62 #define DEBUG_TYPE "ppcfastisel"
66 typedef struct Address {
79 // Innocuous defaults for our address.
81 : BaseType(RegBase), Offset(0) {
86 class PPCFastISel final : public FastISel {
88 const TargetMachine &TM;
89 const PPCSubtarget *PPCSubTarget;
90 PPCFunctionInfo *PPCFuncInfo;
91 const TargetInstrInfo &TII;
92 const TargetLowering &TLI;
96 explicit PPCFastISel(FunctionLoweringInfo &FuncInfo,
97 const TargetLibraryInfo *LibInfo)
98 : FastISel(FuncInfo, LibInfo), TM(FuncInfo.MF->getTarget()),
99 PPCSubTarget(&FuncInfo.MF->getSubtarget<PPCSubtarget>()),
100 PPCFuncInfo(FuncInfo.MF->getInfo<PPCFunctionInfo>()),
101 TII(*PPCSubTarget->getInstrInfo()),
102 TLI(*PPCSubTarget->getTargetLowering()),
103 Context(&FuncInfo.Fn->getContext()) {}
105 // Backend specific FastISel code.
107 bool fastSelectInstruction(const Instruction *I) override;
108 unsigned fastMaterializeConstant(const Constant *C) override;
109 unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
110 bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
111 const LoadInst *LI) override;
112 bool fastLowerArguments() override;
113 unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
114 unsigned fastEmitInst_ri(unsigned MachineInstOpcode,
115 const TargetRegisterClass *RC,
116 unsigned Op0, bool Op0IsKill,
118 unsigned fastEmitInst_r(unsigned MachineInstOpcode,
119 const TargetRegisterClass *RC,
120 unsigned Op0, bool Op0IsKill);
121 unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
122 const TargetRegisterClass *RC,
123 unsigned Op0, bool Op0IsKill,
124 unsigned Op1, bool Op1IsKill);
126 bool fastLowerCall(CallLoweringInfo &CLI) override;
128 // Instruction selection routines.
130 bool SelectLoad(const Instruction *I);
131 bool SelectStore(const Instruction *I);
132 bool SelectBranch(const Instruction *I);
133 bool SelectIndirectBr(const Instruction *I);
134 bool SelectFPExt(const Instruction *I);
135 bool SelectFPTrunc(const Instruction *I);
136 bool SelectIToFP(const Instruction *I, bool IsSigned);
137 bool SelectFPToI(const Instruction *I, bool IsSigned);
138 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
139 bool SelectRet(const Instruction *I);
140 bool SelectTrunc(const Instruction *I);
141 bool SelectIntExt(const Instruction *I);
145 bool isTypeLegal(Type *Ty, MVT &VT);
146 bool isLoadTypeLegal(Type *Ty, MVT &VT);
147 bool isValueAvailable(const Value *V) const;
148 bool isVSFRCRegister(unsigned Register) const {
149 return MRI.getRegClass(Register)->getID() == PPC::VSFRCRegClassID;
151 bool isVSSRCRegister(unsigned Register) const {
152 return MRI.getRegClass(Register)->getID() == PPC::VSSRCRegClassID;
154 bool PPCEmitCmp(const Value *Src1Value, const Value *Src2Value,
155 bool isZExt, unsigned DestReg);
156 bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
157 const TargetRegisterClass *RC, bool IsZExt = true,
158 unsigned FP64LoadOpc = PPC::LFD);
159 bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
160 bool PPCComputeAddress(const Value *Obj, Address &Addr);
161 void PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset,
163 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
164 unsigned DestReg, bool IsZExt);
165 unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT);
166 unsigned PPCMaterializeGV(const GlobalValue *GV, MVT VT);
167 unsigned PPCMaterializeInt(const Constant *C, MVT VT, bool UseSExt = true);
168 unsigned PPCMaterialize32BitInt(int64_t Imm,
169 const TargetRegisterClass *RC);
170 unsigned PPCMaterialize64BitInt(int64_t Imm,
171 const TargetRegisterClass *RC);
172 unsigned PPCMoveToIntReg(const Instruction *I, MVT VT,
173 unsigned SrcReg, bool IsSigned);
174 unsigned PPCMoveToFPReg(MVT VT, unsigned SrcReg, bool IsSigned);
176 // Call handling routines.
178 bool processCallArgs(SmallVectorImpl<Value*> &Args,
179 SmallVectorImpl<unsigned> &ArgRegs,
180 SmallVectorImpl<MVT> &ArgVTs,
181 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
182 SmallVectorImpl<unsigned> &RegArgs,
186 bool finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumBytes);
187 CCAssignFn *usePPC32CCs(unsigned Flag);
190 #include "PPCGenFastISel.inc"
194 } // end anonymous namespace
196 #include "PPCGenCallingConv.inc"
198 // Function whose sole purpose is to kill compiler warnings
199 // stemming from unused functions included from PPCGenCallingConv.inc.
200 CCAssignFn *PPCFastISel::usePPC32CCs(unsigned Flag) {
202 return CC_PPC32_SVR4;
204 return CC_PPC32_SVR4_ByVal;
206 return CC_PPC32_SVR4_VarArg;
211 static Optional<PPC::Predicate> getComparePred(CmpInst::Predicate Pred) {
213 // These are not representable with any single compare.
214 case CmpInst::FCMP_FALSE:
215 case CmpInst::FCMP_UEQ:
216 case CmpInst::FCMP_UGT:
217 case CmpInst::FCMP_UGE:
218 case CmpInst::FCMP_ULT:
219 case CmpInst::FCMP_ULE:
220 case CmpInst::FCMP_UNE:
221 case CmpInst::FCMP_TRUE:
223 return Optional<PPC::Predicate>();
225 case CmpInst::FCMP_OEQ:
226 case CmpInst::ICMP_EQ:
229 case CmpInst::FCMP_OGT:
230 case CmpInst::ICMP_UGT:
231 case CmpInst::ICMP_SGT:
234 case CmpInst::FCMP_OGE:
235 case CmpInst::ICMP_UGE:
236 case CmpInst::ICMP_SGE:
239 case CmpInst::FCMP_OLT:
240 case CmpInst::ICMP_ULT:
241 case CmpInst::ICMP_SLT:
244 case CmpInst::FCMP_OLE:
245 case CmpInst::ICMP_ULE:
246 case CmpInst::ICMP_SLE:
249 case CmpInst::FCMP_ONE:
250 case CmpInst::ICMP_NE:
253 case CmpInst::FCMP_ORD:
256 case CmpInst::FCMP_UNO:
261 // Determine whether the type Ty is simple enough to be handled by
262 // fast-isel, and return its equivalent machine type in VT.
263 // FIXME: Copied directly from ARM -- factor into base class?
264 bool PPCFastISel::isTypeLegal(Type *Ty, MVT &VT) {
265 EVT Evt = TLI.getValueType(Ty, true);
267 // Only handle simple types.
268 if (Evt == MVT::Other || !Evt.isSimple()) return false;
269 VT = Evt.getSimpleVT();
271 // Handle all legal types, i.e. a register that will directly hold this
273 return TLI.isTypeLegal(VT);
276 // Determine whether the type Ty is simple enough to be handled by
277 // fast-isel as a load target, and return its equivalent machine type in VT.
278 bool PPCFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
279 if (isTypeLegal(Ty, VT)) return true;
281 // If this is a type than can be sign or zero-extended to a basic operation
282 // go ahead and accept it now.
283 if (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) {
290 bool PPCFastISel::isValueAvailable(const Value *V) const {
291 if (!isa<Instruction>(V))
294 const auto *I = cast<Instruction>(V);
295 if (FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB)
301 // Given a value Obj, create an Address object Addr that represents its
302 // address. Return false if we can't handle it.
303 bool PPCFastISel::PPCComputeAddress(const Value *Obj, Address &Addr) {
304 const User *U = nullptr;
305 unsigned Opcode = Instruction::UserOp1;
306 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
307 // Don't walk into other basic blocks unless the object is an alloca from
308 // another block, otherwise it may not have a virtual register assigned.
309 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
310 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
311 Opcode = I->getOpcode();
314 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
315 Opcode = C->getOpcode();
322 case Instruction::BitCast:
323 // Look through bitcasts.
324 return PPCComputeAddress(U->getOperand(0), Addr);
325 case Instruction::IntToPtr:
326 // Look past no-op inttoptrs.
327 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
328 return PPCComputeAddress(U->getOperand(0), Addr);
330 case Instruction::PtrToInt:
331 // Look past no-op ptrtoints.
332 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
333 return PPCComputeAddress(U->getOperand(0), Addr);
335 case Instruction::GetElementPtr: {
336 Address SavedAddr = Addr;
337 long TmpOffset = Addr.Offset;
339 // Iterate through the GEP folding the constants into offsets where
341 gep_type_iterator GTI = gep_type_begin(U);
342 for (User::const_op_iterator II = U->op_begin() + 1, IE = U->op_end();
343 II != IE; ++II, ++GTI) {
344 const Value *Op = *II;
345 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
346 const StructLayout *SL = DL.getStructLayout(STy);
347 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
348 TmpOffset += SL->getElementOffset(Idx);
350 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
352 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
353 // Constant-offset addressing.
354 TmpOffset += CI->getSExtValue() * S;
357 if (canFoldAddIntoGEP(U, Op)) {
358 // A compatible add with a constant operand. Fold the constant.
360 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
361 TmpOffset += CI->getSExtValue() * S;
362 // Iterate on the other operand.
363 Op = cast<AddOperator>(Op)->getOperand(0);
367 goto unsupported_gep;
372 // Try to grab the base operand now.
373 Addr.Offset = TmpOffset;
374 if (PPCComputeAddress(U->getOperand(0), Addr)) return true;
376 // We failed, restore everything and try the other options.
382 case Instruction::Alloca: {
383 const AllocaInst *AI = cast<AllocaInst>(Obj);
384 DenseMap<const AllocaInst*, int>::iterator SI =
385 FuncInfo.StaticAllocaMap.find(AI);
386 if (SI != FuncInfo.StaticAllocaMap.end()) {
387 Addr.BaseType = Address::FrameIndexBase;
388 Addr.Base.FI = SI->second;
395 // FIXME: References to parameters fall through to the behavior
396 // below. They should be able to reference a frame index since
397 // they are stored to the stack, so we can get "ld rx, offset(r1)"
398 // instead of "addi ry, r1, offset / ld rx, 0(ry)". Obj will
399 // just contain the parameter. Try to handle this with a FI.
401 // Try to get this in a register if nothing else has worked.
402 if (Addr.Base.Reg == 0)
403 Addr.Base.Reg = getRegForValue(Obj);
405 // Prevent assignment of base register to X0, which is inappropriate
406 // for loads and stores alike.
407 if (Addr.Base.Reg != 0)
408 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass);
410 return Addr.Base.Reg != 0;
413 // Fix up some addresses that can't be used directly. For example, if
414 // an offset won't fit in an instruction field, we may need to move it
415 // into an index register.
416 void PPCFastISel::PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset,
417 unsigned &IndexReg) {
419 // Check whether the offset fits in the instruction field.
420 if (!isInt<16>(Addr.Offset))
423 // If this is a stack pointer and the offset needs to be simplified then
424 // put the alloca address into a register, set the base type back to
425 // register and continue. This should almost never happen.
426 if (!UseOffset && Addr.BaseType == Address::FrameIndexBase) {
427 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
428 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8),
429 ResultReg).addFrameIndex(Addr.Base.FI).addImm(0);
430 Addr.Base.Reg = ResultReg;
431 Addr.BaseType = Address::RegBase;
435 IntegerType *OffsetTy = ((VT == MVT::i32) ? Type::getInt32Ty(*Context)
436 : Type::getInt64Ty(*Context));
437 const ConstantInt *Offset =
438 ConstantInt::getSigned(OffsetTy, (int64_t)(Addr.Offset));
439 IndexReg = PPCMaterializeInt(Offset, MVT::i64);
440 assert(IndexReg && "Unexpected error in PPCMaterializeInt!");
444 // Emit a load instruction if possible, returning true if we succeeded,
445 // otherwise false. See commentary below for how the register class of
446 // the load is determined.
447 bool PPCFastISel::PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
448 const TargetRegisterClass *RC,
449 bool IsZExt, unsigned FP64LoadOpc) {
451 bool UseOffset = true;
453 // If ResultReg is given, it determines the register class of the load.
454 // Otherwise, RC is the register class to use. If the result of the
455 // load isn't anticipated in this block, both may be zero, in which
456 // case we must make a conservative guess. In particular, don't assign
457 // R0 or X0 to the result register, as the result may be used in a load,
458 // store, add-immediate, or isel that won't permit this. (Though
459 // perhaps the spill and reload of live-exit values would handle this?)
460 const TargetRegisterClass *UseRC =
461 (ResultReg ? MRI.getRegClass(ResultReg) :
463 (VT == MVT::f64 ? &PPC::F8RCRegClass :
464 (VT == MVT::f32 ? &PPC::F4RCRegClass :
465 (VT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
466 &PPC::GPRC_and_GPRC_NOR0RegClass)))));
468 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass);
470 switch (VT.SimpleTy) {
471 default: // e.g., vector types not handled
474 Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8;
478 (Is32BitInt ? PPC::LHZ : PPC::LHZ8) :
479 (Is32BitInt ? PPC::LHA : PPC::LHA8));
483 (Is32BitInt ? PPC::LWZ : PPC::LWZ8) :
484 (Is32BitInt ? PPC::LWA_32 : PPC::LWA));
485 if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0))
490 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) &&
491 "64-bit load with 32-bit target??");
492 UseOffset = ((Addr.Offset & 3) == 0);
502 // If necessary, materialize the offset into a register and use
503 // the indexed form. Also handle stack pointers with special needs.
504 unsigned IndexReg = 0;
505 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg);
507 // If this is a potential VSX load with an offset of 0, a VSX indexed load can
509 bool IsVSSRC = (ResultReg != 0) && isVSSRCRegister(ResultReg);
510 bool IsVSFRC = (ResultReg != 0) && isVSFRCRegister(ResultReg);
511 bool Is32VSXLoad = IsVSSRC && Opc == PPC::LFS;
512 bool Is64VSXLoad = IsVSSRC && Opc == PPC::LFD;
513 if ((Is32VSXLoad || Is64VSXLoad) &&
514 (Addr.BaseType != Address::FrameIndexBase) && UseOffset &&
515 (Addr.Offset == 0)) {
520 ResultReg = createResultReg(UseRC);
522 // Note: If we still have a frame index here, we know the offset is
523 // in range, as otherwise PPCSimplifyAddress would have converted it
525 if (Addr.BaseType == Address::FrameIndexBase) {
526 // VSX only provides an indexed load.
527 if (Is32VSXLoad || Is64VSXLoad) return false;
529 MachineMemOperand *MMO =
530 FuncInfo.MF->getMachineMemOperand(
531 MachinePointerInfo::getFixedStack(Addr.Base.FI, Addr.Offset),
532 MachineMemOperand::MOLoad, MFI.getObjectSize(Addr.Base.FI),
533 MFI.getObjectAlignment(Addr.Base.FI));
535 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
536 .addImm(Addr.Offset).addFrameIndex(Addr.Base.FI).addMemOperand(MMO);
538 // Base reg with offset in range.
539 } else if (UseOffset) {
540 // VSX only provides an indexed load.
541 if (Is32VSXLoad || Is64VSXLoad) return false;
543 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
544 .addImm(Addr.Offset).addReg(Addr.Base.Reg);
548 // Get the RR opcode corresponding to the RI one. FIXME: It would be
549 // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it
550 // is hard to get at.
552 default: llvm_unreachable("Unexpected opcode!");
553 case PPC::LBZ: Opc = PPC::LBZX; break;
554 case PPC::LBZ8: Opc = PPC::LBZX8; break;
555 case PPC::LHZ: Opc = PPC::LHZX; break;
556 case PPC::LHZ8: Opc = PPC::LHZX8; break;
557 case PPC::LHA: Opc = PPC::LHAX; break;
558 case PPC::LHA8: Opc = PPC::LHAX8; break;
559 case PPC::LWZ: Opc = PPC::LWZX; break;
560 case PPC::LWZ8: Opc = PPC::LWZX8; break;
561 case PPC::LWA: Opc = PPC::LWAX; break;
562 case PPC::LWA_32: Opc = PPC::LWAX_32; break;
563 case PPC::LD: Opc = PPC::LDX; break;
564 case PPC::LFS: Opc = IsVSSRC ? PPC::LXSSPX : PPC::LFSX; break;
565 case PPC::LFD: Opc = IsVSFRC ? PPC::LXSDX : PPC::LFDX; break;
567 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
568 .addReg(Addr.Base.Reg).addReg(IndexReg);
574 // Attempt to fast-select a load instruction.
575 bool PPCFastISel::SelectLoad(const Instruction *I) {
576 // FIXME: No atomic loads are supported.
577 if (cast<LoadInst>(I)->isAtomic())
580 // Verify we have a legal type before going any further.
582 if (!isLoadTypeLegal(I->getType(), VT))
585 // See if we can handle this address.
587 if (!PPCComputeAddress(I->getOperand(0), Addr))
590 // Look at the currently assigned register for this instruction
591 // to determine the required register class. This is necessary
592 // to constrain RA from using R0/X0 when this is not legal.
593 unsigned AssignedReg = FuncInfo.ValueMap[I];
594 const TargetRegisterClass *RC =
595 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr;
597 unsigned ResultReg = 0;
598 if (!PPCEmitLoad(VT, ResultReg, Addr, RC))
600 updateValueMap(I, ResultReg);
604 // Emit a store instruction to store SrcReg at Addr.
605 bool PPCFastISel::PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr) {
606 assert(SrcReg && "Nothing to store!");
608 bool UseOffset = true;
610 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg);
611 bool Is32BitInt = RC->hasSuperClassEq(&PPC::GPRCRegClass);
613 switch (VT.SimpleTy) {
614 default: // e.g., vector types not handled
617 Opc = Is32BitInt ? PPC::STB : PPC::STB8;
620 Opc = Is32BitInt ? PPC::STH : PPC::STH8;
623 assert(Is32BitInt && "Not GPRC for i32??");
628 UseOffset = ((Addr.Offset & 3) == 0);
638 // If necessary, materialize the offset into a register and use
639 // the indexed form. Also handle stack pointers with special needs.
640 unsigned IndexReg = 0;
641 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg);
643 // If this is a potential VSX store with an offset of 0, a VSX indexed store
645 bool IsVSSRC = isVSSRCRegister(SrcReg);
646 bool IsVSFRC = isVSFRCRegister(SrcReg);
647 bool Is32VSXStore = IsVSSRC && Opc == PPC::STFS;
648 bool Is64VSXStore = IsVSFRC && Opc == PPC::STFD;
649 if ((Is32VSXStore || Is64VSXStore) &&
650 (Addr.BaseType != Address::FrameIndexBase) && UseOffset &&
651 (Addr.Offset == 0)) {
655 // Note: If we still have a frame index here, we know the offset is
656 // in range, as otherwise PPCSimplifyAddress would have converted it
658 if (Addr.BaseType == Address::FrameIndexBase) {
659 // VSX only provides an indexed store.
660 if (Is32VSXStore || Is64VSXStore) return false;
662 MachineMemOperand *MMO =
663 FuncInfo.MF->getMachineMemOperand(
664 MachinePointerInfo::getFixedStack(Addr.Base.FI, Addr.Offset),
665 MachineMemOperand::MOStore, MFI.getObjectSize(Addr.Base.FI),
666 MFI.getObjectAlignment(Addr.Base.FI));
668 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
671 .addFrameIndex(Addr.Base.FI)
674 // Base reg with offset in range.
675 } else if (UseOffset) {
676 // VSX only provides an indexed store.
677 if (Is32VSXStore || Is64VSXStore) return false;
679 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
680 .addReg(SrcReg).addImm(Addr.Offset).addReg(Addr.Base.Reg);
684 // Get the RR opcode corresponding to the RI one. FIXME: It would be
685 // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it
686 // is hard to get at.
688 default: llvm_unreachable("Unexpected opcode!");
689 case PPC::STB: Opc = PPC::STBX; break;
690 case PPC::STH : Opc = PPC::STHX; break;
691 case PPC::STW : Opc = PPC::STWX; break;
692 case PPC::STB8: Opc = PPC::STBX8; break;
693 case PPC::STH8: Opc = PPC::STHX8; break;
694 case PPC::STW8: Opc = PPC::STWX8; break;
695 case PPC::STD: Opc = PPC::STDX; break;
696 case PPC::STFS: Opc = IsVSSRC ? PPC::STXSSPX : PPC::STFSX; break;
697 case PPC::STFD: Opc = IsVSFRC ? PPC::STXSDX : PPC::STFDX; break;
700 auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
703 // If we have an index register defined we use it in the store inst,
704 // otherwise we use X0 as base as it makes the vector instructions to
705 // use zero in the computation of the effective address regardless the
706 // content of the register.
708 MIB.addReg(Addr.Base.Reg).addReg(IndexReg);
710 MIB.addReg(PPC::ZERO8).addReg(Addr.Base.Reg);
716 // Attempt to fast-select a store instruction.
717 bool PPCFastISel::SelectStore(const Instruction *I) {
718 Value *Op0 = I->getOperand(0);
721 // FIXME: No atomics loads are supported.
722 if (cast<StoreInst>(I)->isAtomic())
725 // Verify we have a legal type before going any further.
727 if (!isLoadTypeLegal(Op0->getType(), VT))
730 // Get the value to be stored into a register.
731 SrcReg = getRegForValue(Op0);
735 // See if we can handle this address.
737 if (!PPCComputeAddress(I->getOperand(1), Addr))
740 if (!PPCEmitStore(VT, SrcReg, Addr))
746 // Attempt to fast-select a branch instruction.
747 bool PPCFastISel::SelectBranch(const Instruction *I) {
748 const BranchInst *BI = cast<BranchInst>(I);
749 MachineBasicBlock *BrBB = FuncInfo.MBB;
750 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
751 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
753 // For now, just try the simplest case where it's fed by a compare.
754 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
755 if (isValueAvailable(CI)) {
756 Optional<PPC::Predicate> OptPPCPred = getComparePred(CI->getPredicate());
760 PPC::Predicate PPCPred = OptPPCPred.getValue();
762 // Take advantage of fall-through opportunities.
763 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
765 PPCPred = PPC::InvertPredicate(PPCPred);
768 unsigned CondReg = createResultReg(&PPC::CRRCRegClass);
770 if (!PPCEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(),
774 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCC))
775 .addImm(PPCPred).addReg(CondReg).addMBB(TBB);
776 fastEmitBranch(FBB, DbgLoc);
777 FuncInfo.MBB->addSuccessor(TBB);
780 } else if (const ConstantInt *CI =
781 dyn_cast<ConstantInt>(BI->getCondition())) {
782 uint64_t Imm = CI->getZExtValue();
783 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
784 fastEmitBranch(Target, DbgLoc);
788 // FIXME: ARM looks for a case where the block containing the compare
789 // has been split from the block containing the branch. If this happens,
790 // there is a vreg available containing the result of the compare. I'm
791 // not sure we can do much, as we've lost the predicate information with
792 // the compare instruction -- we have a 4-bit CR but don't know which bit
797 // Attempt to emit a compare of the two source values. Signed and unsigned
798 // comparisons are supported. Return false if we can't handle it.
799 bool PPCFastISel::PPCEmitCmp(const Value *SrcValue1, const Value *SrcValue2,
800 bool IsZExt, unsigned DestReg) {
801 Type *Ty = SrcValue1->getType();
802 EVT SrcEVT = TLI.getValueType(Ty, true);
803 if (!SrcEVT.isSimple())
805 MVT SrcVT = SrcEVT.getSimpleVT();
807 if (SrcVT == MVT::i1 && PPCSubTarget->useCRBits())
810 // See if operand 2 is an immediate encodeable in the compare.
811 // FIXME: Operands are not in canonical order at -O0, so an immediate
812 // operand in position 1 is a lost opportunity for now. We are
813 // similar to ARM in this regard.
817 // Only 16-bit integer constants can be represented in compares for
818 // PowerPC. Others will be materialized into a register.
819 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(SrcValue2)) {
820 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
821 SrcVT == MVT::i8 || SrcVT == MVT::i1) {
822 const APInt &CIVal = ConstInt->getValue();
823 Imm = (IsZExt) ? (long)CIVal.getZExtValue() : (long)CIVal.getSExtValue();
824 if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm)))
830 bool NeedsExt = false;
831 switch (SrcVT.SimpleTy) {
832 default: return false;
834 CmpOpc = PPC::FCMPUS;
837 CmpOpc = PPC::FCMPUD;
843 // Intentional fall-through.
846 CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW;
848 CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI;
852 CmpOpc = IsZExt ? PPC::CMPLD : PPC::CMPD;
854 CmpOpc = IsZExt ? PPC::CMPLDI : PPC::CMPDI;
858 unsigned SrcReg1 = getRegForValue(SrcValue1);
862 unsigned SrcReg2 = 0;
864 SrcReg2 = getRegForValue(SrcValue2);
870 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
871 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt))
876 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
877 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt))
884 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
885 .addReg(SrcReg1).addReg(SrcReg2);
887 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
888 .addReg(SrcReg1).addImm(Imm);
893 // Attempt to fast-select a floating-point extend instruction.
894 bool PPCFastISel::SelectFPExt(const Instruction *I) {
895 Value *Src = I->getOperand(0);
896 EVT SrcVT = TLI.getValueType(Src->getType(), true);
897 EVT DestVT = TLI.getValueType(I->getType(), true);
899 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
902 unsigned SrcReg = getRegForValue(Src);
906 // No code is generated for a FP extend.
907 updateValueMap(I, SrcReg);
911 // Attempt to fast-select a floating-point truncate instruction.
912 bool PPCFastISel::SelectFPTrunc(const Instruction *I) {
913 Value *Src = I->getOperand(0);
914 EVT SrcVT = TLI.getValueType(Src->getType(), true);
915 EVT DestVT = TLI.getValueType(I->getType(), true);
917 if (SrcVT != MVT::f64 || DestVT != MVT::f32)
920 unsigned SrcReg = getRegForValue(Src);
924 // Round the result to single precision.
925 unsigned DestReg = createResultReg(&PPC::F4RCRegClass);
926 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::FRSP), DestReg)
929 updateValueMap(I, DestReg);
933 // Move an i32 or i64 value in a GPR to an f64 value in an FPR.
934 // FIXME: When direct register moves are implemented (see PowerISA 2.07),
935 // those should be used instead of moving via a stack slot when the
936 // subtarget permits.
937 // FIXME: The code here is sloppy for the 4-byte case. Can use a 4-byte
938 // stack slot and 4-byte store/load sequence. Or just sext the 4-byte
939 // case to 8 bytes which produces tighter code but wastes stack space.
940 unsigned PPCFastISel::PPCMoveToFPReg(MVT SrcVT, unsigned SrcReg,
943 // If necessary, extend 32-bit int to 64-bit.
944 if (SrcVT == MVT::i32) {
945 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass);
946 if (!PPCEmitIntExt(MVT::i32, SrcReg, MVT::i64, TmpReg, !IsSigned))
951 // Get a stack slot 8 bytes wide, aligned on an 8-byte boundary.
953 Addr.BaseType = Address::FrameIndexBase;
954 Addr.Base.FI = MFI.CreateStackObject(8, 8, false);
956 // Store the value from the GPR.
957 if (!PPCEmitStore(MVT::i64, SrcReg, Addr))
960 // Load the integer value into an FPR. The kind of load used depends
961 // on a number of conditions.
962 unsigned LoadOpc = PPC::LFD;
964 if (SrcVT == MVT::i32) {
966 LoadOpc = PPC::LFIWZX;
967 Addr.Offset = (PPCSubTarget->isLittleEndian()) ? 0 : 4;
968 } else if (PPCSubTarget->hasLFIWAX()) {
969 LoadOpc = PPC::LFIWAX;
970 Addr.Offset = (PPCSubTarget->isLittleEndian()) ? 0 : 4;
974 const TargetRegisterClass *RC = &PPC::F8RCRegClass;
975 unsigned ResultReg = 0;
976 if (!PPCEmitLoad(MVT::f64, ResultReg, Addr, RC, !IsSigned, LoadOpc))
982 // Attempt to fast-select an integer-to-floating-point conversion.
983 // FIXME: Once fast-isel has better support for VSX, conversions using
984 // direct moves should be implemented.
985 bool PPCFastISel::SelectIToFP(const Instruction *I, bool IsSigned) {
987 Type *DstTy = I->getType();
988 if (!isTypeLegal(DstTy, DstVT))
991 if (DstVT != MVT::f32 && DstVT != MVT::f64)
994 Value *Src = I->getOperand(0);
995 EVT SrcEVT = TLI.getValueType(Src->getType(), true);
996 if (!SrcEVT.isSimple())
999 MVT SrcVT = SrcEVT.getSimpleVT();
1001 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 &&
1002 SrcVT != MVT::i32 && SrcVT != MVT::i64)
1005 unsigned SrcReg = getRegForValue(Src);
1009 // We can only lower an unsigned convert if we have the newer
1010 // floating-point conversion operations.
1011 if (!IsSigned && !PPCSubTarget->hasFPCVT())
1014 // FIXME: For now we require the newer floating-point conversion operations
1015 // (which are present only on P7 and A2 server models) when converting
1016 // to single-precision float. Otherwise we have to generate a lot of
1017 // fiddly code to avoid double rounding. If necessary, the fiddly code
1018 // can be found in PPCTargetLowering::LowerINT_TO_FP().
1019 if (DstVT == MVT::f32 && !PPCSubTarget->hasFPCVT())
1022 // Extend the input if necessary.
1023 if (SrcVT == MVT::i8 || SrcVT == MVT::i16) {
1024 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass);
1025 if (!PPCEmitIntExt(SrcVT, SrcReg, MVT::i64, TmpReg, !IsSigned))
1031 // Move the integer value to an FPR.
1032 unsigned FPReg = PPCMoveToFPReg(SrcVT, SrcReg, IsSigned);
1036 // Determine the opcode for the conversion.
1037 const TargetRegisterClass *RC = &PPC::F8RCRegClass;
1038 unsigned DestReg = createResultReg(RC);
1041 if (DstVT == MVT::f32)
1042 Opc = IsSigned ? PPC::FCFIDS : PPC::FCFIDUS;
1044 Opc = IsSigned ? PPC::FCFID : PPC::FCFIDU;
1046 // Generate the convert.
1047 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1050 updateValueMap(I, DestReg);
1054 // Move the floating-point value in SrcReg into an integer destination
1055 // register, and return the register (or zero if we can't handle it).
1056 // FIXME: When direct register moves are implemented (see PowerISA 2.07),
1057 // those should be used instead of moving via a stack slot when the
1058 // subtarget permits.
1059 unsigned PPCFastISel::PPCMoveToIntReg(const Instruction *I, MVT VT,
1060 unsigned SrcReg, bool IsSigned) {
1061 // Get a stack slot 8 bytes wide, aligned on an 8-byte boundary.
1062 // Note that if have STFIWX available, we could use a 4-byte stack
1063 // slot for i32, but this being fast-isel we'll just go with the
1064 // easiest code gen possible.
1066 Addr.BaseType = Address::FrameIndexBase;
1067 Addr.Base.FI = MFI.CreateStackObject(8, 8, false);
1069 // Store the value from the FPR.
1070 if (!PPCEmitStore(MVT::f64, SrcReg, Addr))
1073 // Reload it into a GPR. If we want an i32, modify the address
1074 // to have a 4-byte offset so we load from the right place.
1078 // Look at the currently assigned register for this instruction
1079 // to determine the required register class.
1080 unsigned AssignedReg = FuncInfo.ValueMap[I];
1081 const TargetRegisterClass *RC =
1082 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr;
1084 unsigned ResultReg = 0;
1085 if (!PPCEmitLoad(VT, ResultReg, Addr, RC, !IsSigned))
1091 // Attempt to fast-select a floating-point-to-integer conversion.
1092 // FIXME: Once fast-isel has better support for VSX, conversions using
1093 // direct moves should be implemented.
1094 bool PPCFastISel::SelectFPToI(const Instruction *I, bool IsSigned) {
1096 Type *DstTy = I->getType();
1097 if (!isTypeLegal(DstTy, DstVT))
1100 if (DstVT != MVT::i32 && DstVT != MVT::i64)
1103 // If we don't have FCTIDUZ and we need it, punt to SelectionDAG.
1104 if (DstVT == MVT::i64 && !IsSigned && !PPCSubTarget->hasFPCVT())
1107 Value *Src = I->getOperand(0);
1108 Type *SrcTy = Src->getType();
1109 if (!isTypeLegal(SrcTy, SrcVT))
1112 if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1115 unsigned SrcReg = getRegForValue(Src);
1119 // Convert f32 to f64 if necessary. This is just a meaningless copy
1120 // to get the register class right. COPY_TO_REGCLASS is needed since
1121 // a COPY from F4RC to F8RC is converted to a F4RC-F4RC copy downstream.
1122 const TargetRegisterClass *InRC = MRI.getRegClass(SrcReg);
1123 if (InRC == &PPC::F4RCRegClass) {
1124 unsigned TmpReg = createResultReg(&PPC::F8RCRegClass);
1125 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1126 TII.get(TargetOpcode::COPY_TO_REGCLASS), TmpReg)
1127 .addReg(SrcReg).addImm(PPC::F8RCRegClassID);
1131 // Determine the opcode for the conversion, which takes place
1132 // entirely within FPRs.
1133 unsigned DestReg = createResultReg(&PPC::F8RCRegClass);
1136 if (DstVT == MVT::i32)
1140 Opc = PPCSubTarget->hasFPCVT() ? PPC::FCTIWUZ : PPC::FCTIDZ;
1142 Opc = IsSigned ? PPC::FCTIDZ : PPC::FCTIDUZ;
1144 // Generate the convert.
1145 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1148 // Now move the integer value from a float register to an integer register.
1149 unsigned IntReg = PPCMoveToIntReg(I, DstVT, DestReg, IsSigned);
1153 updateValueMap(I, IntReg);
1157 // Attempt to fast-select a binary integer operation that isn't already
1158 // handled automatically.
1159 bool PPCFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1160 EVT DestVT = TLI.getValueType(I->getType(), true);
1162 // We can get here in the case when we have a binary operation on a non-legal
1163 // type and the target independent selector doesn't know how to handle it.
1164 if (DestVT != MVT::i16 && DestVT != MVT::i8)
1167 // Look at the currently assigned register for this instruction
1168 // to determine the required register class. If there is no register,
1169 // make a conservative choice (don't assign R0).
1170 unsigned AssignedReg = FuncInfo.ValueMap[I];
1171 const TargetRegisterClass *RC =
1172 (AssignedReg ? MRI.getRegClass(AssignedReg) :
1173 &PPC::GPRC_and_GPRC_NOR0RegClass);
1174 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
1177 switch (ISDOpcode) {
1178 default: return false;
1180 Opc = IsGPRC ? PPC::ADD4 : PPC::ADD8;
1183 Opc = IsGPRC ? PPC::OR : PPC::OR8;
1186 Opc = IsGPRC ? PPC::SUBF : PPC::SUBF8;
1190 unsigned ResultReg = createResultReg(RC ? RC : &PPC::G8RCRegClass);
1191 unsigned SrcReg1 = getRegForValue(I->getOperand(0));
1192 if (SrcReg1 == 0) return false;
1194 // Handle case of small immediate operand.
1195 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(1))) {
1196 const APInt &CIVal = ConstInt->getValue();
1197 int Imm = (int)CIVal.getSExtValue();
1199 if (isInt<16>(Imm)) {
1202 llvm_unreachable("Missing case!");
1205 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1209 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
1222 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1231 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
1238 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
1242 updateValueMap(I, ResultReg);
1249 unsigned SrcReg2 = getRegForValue(I->getOperand(1));
1250 if (SrcReg2 == 0) return false;
1252 // Reverse operands for subtract-from.
1253 if (ISDOpcode == ISD::SUB)
1254 std::swap(SrcReg1, SrcReg2);
1256 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1257 .addReg(SrcReg1).addReg(SrcReg2);
1258 updateValueMap(I, ResultReg);
1262 // Handle arguments to a call that we're attempting to fast-select.
1263 // Return false if the arguments are too complex for us at the moment.
1264 bool PPCFastISel::processCallArgs(SmallVectorImpl<Value*> &Args,
1265 SmallVectorImpl<unsigned> &ArgRegs,
1266 SmallVectorImpl<MVT> &ArgVTs,
1267 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1268 SmallVectorImpl<unsigned> &RegArgs,
1272 SmallVector<CCValAssign, 16> ArgLocs;
1273 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, ArgLocs, *Context);
1275 // Reserve space for the linkage area on the stack.
1276 unsigned LinkageSize = PPCSubTarget->getFrameLowering()->getLinkageSize();
1277 CCInfo.AllocateStack(LinkageSize, 8);
1279 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CC_PPC64_ELF_FIS);
1281 // Bail out if we can't handle any of the arguments.
1282 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1283 CCValAssign &VA = ArgLocs[I];
1284 MVT ArgVT = ArgVTs[VA.getValNo()];
1286 // Skip vector arguments for now, as well as long double and
1287 // uint128_t, and anything that isn't passed in a register.
1288 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64 || ArgVT == MVT::i1 ||
1289 !VA.isRegLoc() || VA.needsCustom())
1292 // Skip bit-converted arguments for now.
1293 if (VA.getLocInfo() == CCValAssign::BCvt)
1297 // Get a count of how many bytes are to be pushed onto the stack.
1298 NumBytes = CCInfo.getNextStackOffset();
1300 // The prolog code of the callee may store up to 8 GPR argument registers to
1301 // the stack, allowing va_start to index over them in memory if its varargs.
1302 // Because we cannot tell if this is needed on the caller side, we have to
1303 // conservatively assume that it is needed. As such, make sure we have at
1304 // least enough stack space for the caller to store the 8 GPRs.
1305 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
1306 NumBytes = std::max(NumBytes, LinkageSize + 64);
1308 // Issue CALLSEQ_START.
1309 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1310 TII.get(TII.getCallFrameSetupOpcode()))
1313 // Prepare to assign register arguments. Every argument uses up a
1314 // GPR protocol register even if it's passed in a floating-point
1315 // register (unless we're using the fast calling convention).
1316 unsigned NextGPR = PPC::X3;
1317 unsigned NextFPR = PPC::F1;
1319 // Process arguments.
1320 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1321 CCValAssign &VA = ArgLocs[I];
1322 unsigned Arg = ArgRegs[VA.getValNo()];
1323 MVT ArgVT = ArgVTs[VA.getValNo()];
1325 // Handle argument promotion and bitcasts.
1326 switch (VA.getLocInfo()) {
1328 llvm_unreachable("Unknown loc info!");
1329 case CCValAssign::Full:
1331 case CCValAssign::SExt: {
1332 MVT DestVT = VA.getLocVT();
1333 const TargetRegisterClass *RC =
1334 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1335 unsigned TmpReg = createResultReg(RC);
1336 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/false))
1337 llvm_unreachable("Failed to emit a sext!");
1342 case CCValAssign::AExt:
1343 case CCValAssign::ZExt: {
1344 MVT DestVT = VA.getLocVT();
1345 const TargetRegisterClass *RC =
1346 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1347 unsigned TmpReg = createResultReg(RC);
1348 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/true))
1349 llvm_unreachable("Failed to emit a zext!");
1354 case CCValAssign::BCvt: {
1355 // FIXME: Not yet handled.
1356 llvm_unreachable("Should have bailed before getting here!");
1361 // Copy this argument to the appropriate register.
1363 if (ArgVT == MVT::f32 || ArgVT == MVT::f64) {
1365 if (CC != CallingConv::Fast)
1370 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1371 TII.get(TargetOpcode::COPY), ArgReg).addReg(Arg);
1372 RegArgs.push_back(ArgReg);
1378 // For a call that we've determined we can fast-select, finish the
1379 // call sequence and generate a copy to obtain the return value (if any).
1380 bool PPCFastISel::finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumBytes) {
1381 CallingConv::ID CC = CLI.CallConv;
1383 // Issue CallSEQ_END.
1384 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1385 TII.get(TII.getCallFrameDestroyOpcode()))
1386 .addImm(NumBytes).addImm(0);
1388 // Next, generate a copy to obtain the return value.
1389 // FIXME: No multi-register return values yet, though I don't foresee
1390 // any real difficulties there.
1391 if (RetVT != MVT::isVoid) {
1392 SmallVector<CCValAssign, 16> RVLocs;
1393 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1394 CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1395 CCValAssign &VA = RVLocs[0];
1396 assert(RVLocs.size() == 1 && "No support for multi-reg return values!");
1397 assert(VA.isRegLoc() && "Can only return in registers!");
1399 MVT DestVT = VA.getValVT();
1400 MVT CopyVT = DestVT;
1402 // Ints smaller than a register still arrive in a full 64-bit
1403 // register, so make sure we recognize this.
1404 if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32)
1407 unsigned SourcePhysReg = VA.getLocReg();
1408 unsigned ResultReg = 0;
1410 if (RetVT == CopyVT) {
1411 const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT);
1412 ResultReg = createResultReg(CpyRC);
1414 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1415 TII.get(TargetOpcode::COPY), ResultReg)
1416 .addReg(SourcePhysReg);
1418 // If necessary, round the floating result to single precision.
1419 } else if (CopyVT == MVT::f64) {
1420 ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1421 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::FRSP),
1422 ResultReg).addReg(SourcePhysReg);
1424 // If only the low half of a general register is needed, generate
1425 // a GPRC copy instead of a G8RC copy. (EXTRACT_SUBREG can't be
1426 // used along the fast-isel path (not lowered), and downstream logic
1427 // also doesn't like a direct subreg copy on a physical reg.)
1428 } else if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) {
1429 ResultReg = createResultReg(&PPC::GPRCRegClass);
1430 // Convert physical register from G8RC to GPRC.
1431 SourcePhysReg -= PPC::X0 - PPC::R0;
1432 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1433 TII.get(TargetOpcode::COPY), ResultReg)
1434 .addReg(SourcePhysReg);
1437 assert(ResultReg && "ResultReg unset!");
1438 CLI.InRegs.push_back(SourcePhysReg);
1439 CLI.ResultReg = ResultReg;
1440 CLI.NumResultRegs = 1;
1446 bool PPCFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1447 CallingConv::ID CC = CLI.CallConv;
1448 bool IsTailCall = CLI.IsTailCall;
1449 bool IsVarArg = CLI.IsVarArg;
1450 const Value *Callee = CLI.Callee;
1451 const MCSymbol *Symbol = CLI.Symbol;
1453 if (!Callee && !Symbol)
1456 // Allow SelectionDAG isel to handle tail calls.
1460 // Let SDISel handle vararg functions.
1464 // Handle simple calls for now, with legal return types and
1465 // those that can be extended.
1466 Type *RetTy = CLI.RetTy;
1468 if (RetTy->isVoidTy())
1469 RetVT = MVT::isVoid;
1470 else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
1473 else if (RetVT == MVT::i1 && PPCSubTarget->useCRBits())
1474 // We can't handle boolean returns when CR bits are in use.
1477 // FIXME: No multi-register return values yet.
1478 if (RetVT != MVT::isVoid && RetVT != MVT::i8 && RetVT != MVT::i16 &&
1479 RetVT != MVT::i32 && RetVT != MVT::i64 && RetVT != MVT::f32 &&
1480 RetVT != MVT::f64) {
1481 SmallVector<CCValAssign, 16> RVLocs;
1482 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs, *Context);
1483 CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1484 if (RVLocs.size() > 1)
1488 // Bail early if more than 8 arguments, as we only currently
1489 // handle arguments passed in registers.
1490 unsigned NumArgs = CLI.OutVals.size();
1494 // Set up the argument vectors.
1495 SmallVector<Value*, 8> Args;
1496 SmallVector<unsigned, 8> ArgRegs;
1497 SmallVector<MVT, 8> ArgVTs;
1498 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1500 Args.reserve(NumArgs);
1501 ArgRegs.reserve(NumArgs);
1502 ArgVTs.reserve(NumArgs);
1503 ArgFlags.reserve(NumArgs);
1505 for (unsigned i = 0, ie = NumArgs; i != ie; ++i) {
1506 // Only handle easy calls for now. It would be reasonably easy
1507 // to handle <= 8-byte structures passed ByVal in registers, but we
1508 // have to ensure they are right-justified in the register.
1509 ISD::ArgFlagsTy Flags = CLI.OutFlags[i];
1510 if (Flags.isInReg() || Flags.isSRet() || Flags.isNest() || Flags.isByVal())
1513 Value *ArgValue = CLI.OutVals[i];
1514 Type *ArgTy = ArgValue->getType();
1516 if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8)
1519 if (ArgVT.isVector())
1522 unsigned Arg = getRegForValue(ArgValue);
1526 Args.push_back(ArgValue);
1527 ArgRegs.push_back(Arg);
1528 ArgVTs.push_back(ArgVT);
1529 ArgFlags.push_back(Flags);
1532 // Process the arguments.
1533 SmallVector<unsigned, 8> RegArgs;
1536 if (!processCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
1537 RegArgs, CC, NumBytes, IsVarArg))
1540 MachineInstrBuilder MIB;
1541 // FIXME: No handling for function pointers yet. This requires
1542 // implementing the function descriptor (OPD) setup.
1543 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1545 // patchpoints are a special case; they always dispatch to a pointer value.
1546 // However, we don't actually want to generate the indirect call sequence
1547 // here (that will be generated, as necessary, during asm printing), and
1548 // the call we generate here will be erased by FastISel::selectPatchpoint,
1549 // so don't try very hard...
1550 if (CLI.IsPatchPoint)
1551 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::NOP));
1555 // Build direct call with NOP for TOC restore.
1556 // FIXME: We can and should optimize away the NOP for local calls.
1557 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1558 TII.get(PPC::BL8_NOP));
1560 MIB.addGlobalAddress(GV);
1563 // Add implicit physical register uses to the call.
1564 for (unsigned II = 0, IE = RegArgs.size(); II != IE; ++II)
1565 MIB.addReg(RegArgs[II], RegState::Implicit);
1567 // Direct calls, in both the ELF V1 and V2 ABIs, need the TOC register live
1569 PPCFuncInfo->setUsesTOCBasePtr();
1570 MIB.addReg(PPC::X2, RegState::Implicit);
1572 // Add a register mask with the call-preserved registers. Proper
1573 // defs for return values will be added by setPhysRegsDeadExcept().
1574 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1578 // Finish off the call including any return values.
1579 return finishCall(RetVT, CLI, NumBytes);
1582 // Attempt to fast-select a return instruction.
1583 bool PPCFastISel::SelectRet(const Instruction *I) {
1585 if (!FuncInfo.CanLowerReturn)
1588 const ReturnInst *Ret = cast<ReturnInst>(I);
1589 const Function &F = *I->getParent()->getParent();
1591 // Build a list of return value registers.
1592 SmallVector<unsigned, 4> RetRegs;
1593 CallingConv::ID CC = F.getCallingConv();
1595 if (Ret->getNumOperands() > 0) {
1596 SmallVector<ISD::OutputArg, 4> Outs;
1597 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
1599 // Analyze operands of the call, assigning locations to each operand.
1600 SmallVector<CCValAssign, 16> ValLocs;
1601 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, *Context);
1602 CCInfo.AnalyzeReturn(Outs, RetCC_PPC64_ELF_FIS);
1603 const Value *RV = Ret->getOperand(0);
1605 // FIXME: Only one output register for now.
1606 if (ValLocs.size() > 1)
1609 // Special case for returning a constant integer of any size.
1610 // Materialize the constant as an i64 and copy it to the return
1611 // register. We still need to worry about properly extending the sign. E.g:
1612 // If the constant has only one bit, it means it is a boolean. Therefore
1613 // we can't use PPCMaterializeInt because it extends the sign which will
1614 // cause negations of the returned value to be incorrect as they are
1615 // implemented as the flip of the least significant bit.
1616 if (isa<ConstantInt>(*RV)) {
1617 const Constant *C = cast<Constant>(RV);
1619 CCValAssign &VA = ValLocs[0];
1621 unsigned RetReg = VA.getLocReg();
1622 unsigned SrcReg = PPCMaterializeInt(C, MVT::i64,
1623 VA.getLocInfo() == CCValAssign::SExt);
1625 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1626 TII.get(TargetOpcode::COPY), RetReg).addReg(SrcReg);
1628 RetRegs.push_back(RetReg);
1631 unsigned Reg = getRegForValue(RV);
1636 // Copy the result values into the output registers.
1637 for (unsigned i = 0; i < ValLocs.size(); ++i) {
1639 CCValAssign &VA = ValLocs[i];
1640 assert(VA.isRegLoc() && "Can only return in registers!");
1641 RetRegs.push_back(VA.getLocReg());
1642 unsigned SrcReg = Reg + VA.getValNo();
1644 EVT RVEVT = TLI.getValueType(RV->getType());
1645 if (!RVEVT.isSimple())
1647 MVT RVVT = RVEVT.getSimpleVT();
1648 MVT DestVT = VA.getLocVT();
1650 if (RVVT != DestVT && RVVT != MVT::i8 &&
1651 RVVT != MVT::i16 && RVVT != MVT::i32)
1654 if (RVVT != DestVT) {
1655 switch (VA.getLocInfo()) {
1657 llvm_unreachable("Unknown loc info!");
1658 case CCValAssign::Full:
1659 llvm_unreachable("Full value assign but types don't match?");
1660 case CCValAssign::AExt:
1661 case CCValAssign::ZExt: {
1662 const TargetRegisterClass *RC =
1663 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1664 unsigned TmpReg = createResultReg(RC);
1665 if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, true))
1670 case CCValAssign::SExt: {
1671 const TargetRegisterClass *RC =
1672 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1673 unsigned TmpReg = createResultReg(RC);
1674 if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, false))
1682 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1683 TII.get(TargetOpcode::COPY), RetRegs[i])
1689 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1690 TII.get(PPC::BLR8));
1692 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1693 MIB.addReg(RetRegs[i], RegState::Implicit);
1698 // Attempt to emit an integer extend of SrcReg into DestReg. Both
1699 // signed and zero extensions are supported. Return false if we
1701 bool PPCFastISel::PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1702 unsigned DestReg, bool IsZExt) {
1703 if (DestVT != MVT::i32 && DestVT != MVT::i64)
1705 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 && SrcVT != MVT::i32)
1708 // Signed extensions use EXTSB, EXTSH, EXTSW.
1711 if (SrcVT == MVT::i8)
1712 Opc = (DestVT == MVT::i32) ? PPC::EXTSB : PPC::EXTSB8_32_64;
1713 else if (SrcVT == MVT::i16)
1714 Opc = (DestVT == MVT::i32) ? PPC::EXTSH : PPC::EXTSH8_32_64;
1716 assert(DestVT == MVT::i64 && "Signed extend from i32 to i32??");
1717 Opc = PPC::EXTSW_32_64;
1719 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1722 // Unsigned 32-bit extensions use RLWINM.
1723 } else if (DestVT == MVT::i32) {
1725 if (SrcVT == MVT::i8)
1728 assert(SrcVT == MVT::i16 && "Unsigned extend from i32 to i32??");
1731 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::RLWINM),
1733 .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB).addImm(/*ME=*/31);
1735 // Unsigned 64-bit extensions use RLDICL (with a 32-bit source).
1738 if (SrcVT == MVT::i8)
1740 else if (SrcVT == MVT::i16)
1744 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1745 TII.get(PPC::RLDICL_32_64), DestReg)
1746 .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB);
1752 // Attempt to fast-select an indirect branch instruction.
1753 bool PPCFastISel::SelectIndirectBr(const Instruction *I) {
1754 unsigned AddrReg = getRegForValue(I->getOperand(0));
1758 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::MTCTR8))
1760 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCTR8));
1762 const IndirectBrInst *IB = cast<IndirectBrInst>(I);
1763 for (unsigned i = 0, e = IB->getNumSuccessors(); i != e; ++i)
1764 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[IB->getSuccessor(i)]);
1769 // Attempt to fast-select an integer truncate instruction.
1770 bool PPCFastISel::SelectTrunc(const Instruction *I) {
1771 Value *Src = I->getOperand(0);
1772 EVT SrcVT = TLI.getValueType(Src->getType(), true);
1773 EVT DestVT = TLI.getValueType(I->getType(), true);
1775 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16)
1778 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
1781 unsigned SrcReg = getRegForValue(Src);
1785 // The only interesting case is when we need to switch register classes.
1786 if (SrcVT == MVT::i64) {
1787 unsigned ResultReg = createResultReg(&PPC::GPRCRegClass);
1788 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1789 TII.get(TargetOpcode::COPY),
1790 ResultReg).addReg(SrcReg, 0, PPC::sub_32);
1794 updateValueMap(I, SrcReg);
1798 // Attempt to fast-select an integer extend instruction.
1799 bool PPCFastISel::SelectIntExt(const Instruction *I) {
1800 Type *DestTy = I->getType();
1801 Value *Src = I->getOperand(0);
1802 Type *SrcTy = Src->getType();
1804 bool IsZExt = isa<ZExtInst>(I);
1805 unsigned SrcReg = getRegForValue(Src);
1806 if (!SrcReg) return false;
1808 EVT SrcEVT, DestEVT;
1809 SrcEVT = TLI.getValueType(SrcTy, true);
1810 DestEVT = TLI.getValueType(DestTy, true);
1811 if (!SrcEVT.isSimple())
1813 if (!DestEVT.isSimple())
1816 MVT SrcVT = SrcEVT.getSimpleVT();
1817 MVT DestVT = DestEVT.getSimpleVT();
1819 // If we know the register class needed for the result of this
1820 // instruction, use it. Otherwise pick the register class of the
1821 // correct size that does not contain X0/R0, since we don't know
1822 // whether downstream uses permit that assignment.
1823 unsigned AssignedReg = FuncInfo.ValueMap[I];
1824 const TargetRegisterClass *RC =
1825 (AssignedReg ? MRI.getRegClass(AssignedReg) :
1826 (DestVT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
1827 &PPC::GPRC_and_GPRC_NOR0RegClass));
1828 unsigned ResultReg = createResultReg(RC);
1830 if (!PPCEmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, IsZExt))
1833 updateValueMap(I, ResultReg);
1837 // Attempt to fast-select an instruction that wasn't handled by
1838 // the table-generated machinery.
1839 bool PPCFastISel::fastSelectInstruction(const Instruction *I) {
1841 switch (I->getOpcode()) {
1842 case Instruction::Load:
1843 return SelectLoad(I);
1844 case Instruction::Store:
1845 return SelectStore(I);
1846 case Instruction::Br:
1847 return SelectBranch(I);
1848 case Instruction::IndirectBr:
1849 return SelectIndirectBr(I);
1850 case Instruction::FPExt:
1851 return SelectFPExt(I);
1852 case Instruction::FPTrunc:
1853 return SelectFPTrunc(I);
1854 case Instruction::SIToFP:
1855 return SelectIToFP(I, /*IsSigned*/ true);
1856 case Instruction::UIToFP:
1857 return SelectIToFP(I, /*IsSigned*/ false);
1858 case Instruction::FPToSI:
1859 return SelectFPToI(I, /*IsSigned*/ true);
1860 case Instruction::FPToUI:
1861 return SelectFPToI(I, /*IsSigned*/ false);
1862 case Instruction::Add:
1863 return SelectBinaryIntOp(I, ISD::ADD);
1864 case Instruction::Or:
1865 return SelectBinaryIntOp(I, ISD::OR);
1866 case Instruction::Sub:
1867 return SelectBinaryIntOp(I, ISD::SUB);
1868 case Instruction::Call:
1869 return selectCall(I);
1870 case Instruction::Ret:
1871 return SelectRet(I);
1872 case Instruction::Trunc:
1873 return SelectTrunc(I);
1874 case Instruction::ZExt:
1875 case Instruction::SExt:
1876 return SelectIntExt(I);
1877 // Here add other flavors of Instruction::XXX that automated
1878 // cases don't catch. For example, switches are terminators
1879 // that aren't yet handled.
1886 // Materialize a floating-point constant into a register, and return
1887 // the register number (or zero if we failed to handle it).
1888 unsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) {
1889 // No plans to handle long double here.
1890 if (VT != MVT::f32 && VT != MVT::f64)
1893 // All FP constants are loaded from the constant pool.
1894 unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
1895 assert(Align > 0 && "Unexpectedly missing alignment information!");
1896 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
1897 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
1898 CodeModel::Model CModel = TM.getCodeModel();
1900 MachineMemOperand *MMO =
1901 FuncInfo.MF->getMachineMemOperand(
1902 MachinePointerInfo::getConstantPool(), MachineMemOperand::MOLoad,
1903 (VT == MVT::f32) ? 4 : 8, Align);
1905 unsigned Opc = (VT == MVT::f32) ? PPC::LFS : PPC::LFD;
1906 unsigned TmpReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
1908 PPCFuncInfo->setUsesTOCBasePtr();
1909 // For small code model, generate a LF[SD](0, LDtocCPT(Idx, X2)).
1910 if (CModel == CodeModel::Small || CModel == CodeModel::JITDefault) {
1911 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocCPT),
1913 .addConstantPoolIndex(Idx).addReg(PPC::X2);
1914 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1915 .addImm(0).addReg(TmpReg).addMemOperand(MMO);
1917 // Otherwise we generate LF[SD](Idx[lo], ADDIStocHA(X2, Idx)).
1918 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA),
1919 TmpReg).addReg(PPC::X2).addConstantPoolIndex(Idx);
1920 // But for large code model, we must generate a LDtocL followed
1922 if (CModel == CodeModel::Large) {
1923 unsigned TmpReg2 = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
1924 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL),
1925 TmpReg2).addConstantPoolIndex(Idx).addReg(TmpReg);
1926 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1927 .addImm(0).addReg(TmpReg2);
1929 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1930 .addConstantPoolIndex(Idx, 0, PPCII::MO_TOC_LO)
1932 .addMemOperand(MMO);
1938 // Materialize the address of a global value into a register, and return
1939 // the register number (or zero if we failed to handle it).
1940 unsigned PPCFastISel::PPCMaterializeGV(const GlobalValue *GV, MVT VT) {
1941 assert(VT == MVT::i64 && "Non-address!");
1942 const TargetRegisterClass *RC = &PPC::G8RC_and_G8RC_NOX0RegClass;
1943 unsigned DestReg = createResultReg(RC);
1945 // Global values may be plain old object addresses, TLS object
1946 // addresses, constant pool entries, or jump tables. How we generate
1947 // code for these may depend on small, medium, or large code model.
1948 CodeModel::Model CModel = TM.getCodeModel();
1950 // FIXME: Jump tables are not yet required because fast-isel doesn't
1951 // handle switches; if that changes, we need them as well. For now,
1952 // what follows assumes everything's a generic (or TLS) global address.
1954 // FIXME: We don't yet handle the complexity of TLS.
1955 if (GV->isThreadLocal())
1958 PPCFuncInfo->setUsesTOCBasePtr();
1959 // For small code model, generate a simple TOC load.
1960 if (CModel == CodeModel::Small || CModel == CodeModel::JITDefault)
1961 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtoc),
1963 .addGlobalAddress(GV)
1966 // If the address is an externally defined symbol, a symbol with common
1967 // or externally available linkage, a non-local function address, or a
1968 // jump table address (not yet needed), or if we are generating code
1969 // for large code model, we generate:
1970 // LDtocL(GV, ADDIStocHA(%X2, GV))
1971 // Otherwise we generate:
1972 // ADDItocL(ADDIStocHA(%X2, GV), GV)
1973 // Either way, start with the ADDIStocHA:
1974 unsigned HighPartReg = createResultReg(RC);
1975 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA),
1976 HighPartReg).addReg(PPC::X2).addGlobalAddress(GV);
1978 // If/when switches are implemented, jump tables should be handled
1979 // on the "if" path here.
1980 if (CModel == CodeModel::Large ||
1981 (GV->getType()->getElementType()->isFunctionTy() &&
1982 !GV->isStrongDefinitionForLinker()) ||
1983 GV->isDeclaration() || GV->hasCommonLinkage() ||
1984 GV->hasAvailableExternallyLinkage())
1985 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL),
1986 DestReg).addGlobalAddress(GV).addReg(HighPartReg);
1988 // Otherwise generate the ADDItocL.
1989 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDItocL),
1990 DestReg).addReg(HighPartReg).addGlobalAddress(GV);
1996 // Materialize a 32-bit integer constant into a register, and return
1997 // the register number (or zero if we failed to handle it).
1998 unsigned PPCFastISel::PPCMaterialize32BitInt(int64_t Imm,
1999 const TargetRegisterClass *RC) {
2000 unsigned Lo = Imm & 0xFFFF;
2001 unsigned Hi = (Imm >> 16) & 0xFFFF;
2003 unsigned ResultReg = createResultReg(RC);
2004 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
2007 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2008 TII.get(IsGPRC ? PPC::LI : PPC::LI8), ResultReg)
2011 // Both Lo and Hi have nonzero bits.
2012 unsigned TmpReg = createResultReg(RC);
2013 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2014 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), TmpReg)
2016 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2017 TII.get(IsGPRC ? PPC::ORI : PPC::ORI8), ResultReg)
2018 .addReg(TmpReg).addImm(Lo);
2021 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2022 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), ResultReg)
2028 // Materialize a 64-bit integer constant into a register, and return
2029 // the register number (or zero if we failed to handle it).
2030 unsigned PPCFastISel::PPCMaterialize64BitInt(int64_t Imm,
2031 const TargetRegisterClass *RC) {
2032 unsigned Remainder = 0;
2035 // If the value doesn't fit in 32 bits, see if we can shift it
2036 // so that it fits in 32 bits.
2037 if (!isInt<32>(Imm)) {
2038 Shift = countTrailingZeros<uint64_t>(Imm);
2039 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
2041 if (isInt<32>(ImmSh))
2050 // Handle the high-order 32 bits (if shifted) or the whole 32 bits
2051 // (if not shifted).
2052 unsigned TmpReg1 = PPCMaterialize32BitInt(Imm, RC);
2056 // If upper 32 bits were not zero, we've built them and need to shift
2060 TmpReg2 = createResultReg(RC);
2061 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::RLDICR),
2062 TmpReg2).addReg(TmpReg1).addImm(Shift).addImm(63 - Shift);
2066 unsigned TmpReg3, Hi, Lo;
2067 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
2068 TmpReg3 = createResultReg(RC);
2069 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ORIS8),
2070 TmpReg3).addReg(TmpReg2).addImm(Hi);
2074 if ((Lo = Remainder & 0xFFFF)) {
2075 unsigned ResultReg = createResultReg(RC);
2076 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ORI8),
2077 ResultReg).addReg(TmpReg3).addImm(Lo);
2085 // Materialize an integer constant into a register, and return
2086 // the register number (or zero if we failed to handle it).
2087 unsigned PPCFastISel::PPCMaterializeInt(const Constant *C, MVT VT,
2089 // If we're using CR bit registers for i1 values, handle that as a special
2091 if (VT == MVT::i1 && PPCSubTarget->useCRBits()) {
2092 const ConstantInt *CI = cast<ConstantInt>(C);
2093 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass);
2094 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2095 TII.get(CI->isZero() ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2099 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 &&
2100 VT != MVT::i8 && VT != MVT::i1)
2103 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
2104 &PPC::GPRCRegClass);
2106 // If the constant is in range, use a load-immediate.
2107 const ConstantInt *CI = cast<ConstantInt>(C);
2108 if (isInt<16>(CI->getSExtValue())) {
2109 unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI;
2110 unsigned ImmReg = createResultReg(RC);
2111 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ImmReg)
2112 .addImm( (UseSExt) ? CI->getSExtValue() : CI->getZExtValue() );
2116 // Construct the constant piecewise.
2117 int64_t Imm = CI->getZExtValue();
2120 return PPCMaterialize64BitInt(Imm, RC);
2121 else if (VT == MVT::i32)
2122 return PPCMaterialize32BitInt(Imm, RC);
2127 // Materialize a constant into a register, and return the register
2128 // number (or zero if we failed to handle it).
2129 unsigned PPCFastISel::fastMaterializeConstant(const Constant *C) {
2130 EVT CEVT = TLI.getValueType(C->getType(), true);
2132 // Only handle simple types.
2133 if (!CEVT.isSimple()) return 0;
2134 MVT VT = CEVT.getSimpleVT();
2136 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
2137 return PPCMaterializeFP(CFP, VT);
2138 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
2139 return PPCMaterializeGV(GV, VT);
2140 else if (isa<ConstantInt>(C))
2141 return PPCMaterializeInt(C, VT, VT != MVT::i1);
2146 // Materialize the address created by an alloca into a register, and
2147 // return the register number (or zero if we failed to handle it).
2148 unsigned PPCFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
2149 // Don't handle dynamic allocas.
2150 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
2153 if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
2155 DenseMap<const AllocaInst*, int>::iterator SI =
2156 FuncInfo.StaticAllocaMap.find(AI);
2158 if (SI != FuncInfo.StaticAllocaMap.end()) {
2159 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
2160 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8),
2161 ResultReg).addFrameIndex(SI->second).addImm(0);
2168 // Fold loads into extends when possible.
2169 // FIXME: We can have multiple redundant extend/trunc instructions
2170 // following a load. The folding only picks up one. Extend this
2171 // to check subsequent instructions for the same pattern and remove
2172 // them. Thus ResultReg should be the def reg for the last redundant
2173 // instruction in a chain, and all intervening instructions can be
2174 // removed from parent. Change test/CodeGen/PowerPC/fast-isel-fold.ll
2175 // to add ELF64-NOT: rldicl to the appropriate tests when this works.
2176 bool PPCFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
2177 const LoadInst *LI) {
2178 // Verify we have a legal type before going any further.
2180 if (!isLoadTypeLegal(LI->getType(), VT))
2183 // Combine load followed by zero- or sign-extend.
2184 bool IsZExt = false;
2185 switch(MI->getOpcode()) {
2190 case PPC::RLDICL_32_64: {
2192 unsigned MB = MI->getOperand(3).getImm();
2193 if ((VT == MVT::i8 && MB <= 56) ||
2194 (VT == MVT::i16 && MB <= 48) ||
2195 (VT == MVT::i32 && MB <= 32))
2201 case PPC::RLWINM8: {
2203 unsigned MB = MI->getOperand(3).getImm();
2204 if ((VT == MVT::i8 && MB <= 24) ||
2205 (VT == MVT::i16 && MB <= 16))
2212 case PPC::EXTSB8_32_64:
2213 /* There is no sign-extending load-byte instruction. */
2218 case PPC::EXTSH8_32_64: {
2219 if (VT != MVT::i16 && VT != MVT::i8)
2225 case PPC::EXTSW_32_64: {
2226 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8)
2232 // See if we can handle this address.
2234 if (!PPCComputeAddress(LI->getOperand(0), Addr))
2237 unsigned ResultReg = MI->getOperand(0).getReg();
2239 if (!PPCEmitLoad(VT, ResultReg, Addr, nullptr, IsZExt))
2242 MI->eraseFromParent();
2246 // Attempt to lower call arguments in a faster way than done by
2247 // the selection DAG code.
2248 bool PPCFastISel::fastLowerArguments() {
2249 // Defer to normal argument lowering for now. It's reasonably
2250 // efficient. Consider doing something like ARM to handle the
2251 // case where all args fit in registers, no varargs, no float
2256 // Handle materializing integer constants into a register. This is not
2257 // automatically generated for PowerPC, so must be explicitly created here.
2258 unsigned PPCFastISel::fastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) {
2260 if (Opc != ISD::Constant)
2263 // If we're using CR bit registers for i1 values, handle that as a special
2265 if (VT == MVT::i1 && PPCSubTarget->useCRBits()) {
2266 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass);
2267 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2268 TII.get(Imm == 0 ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2272 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 &&
2273 VT != MVT::i8 && VT != MVT::i1)
2276 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
2277 &PPC::GPRCRegClass);
2279 return PPCMaterialize64BitInt(Imm, RC);
2281 return PPCMaterialize32BitInt(Imm, RC);
2284 // Override for ADDI and ADDI8 to set the correct register class
2285 // on RHS operand 0. The automatic infrastructure naively assumes
2286 // GPRC for i32 and G8RC for i64; the concept of "no R0" is lost
2287 // for these cases. At the moment, none of the other automatically
2288 // generated RI instructions require special treatment. However, once
2289 // SelectSelect is implemented, "isel" requires similar handling.
2291 // Also be conservative about the output register class. Avoid
2292 // assigning R0 or X0 to the output register for GPRC and G8RC
2293 // register classes, as any such result could be used in ADDI, etc.,
2294 // where those regs have another meaning.
2295 unsigned PPCFastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
2296 const TargetRegisterClass *RC,
2297 unsigned Op0, bool Op0IsKill,
2299 if (MachineInstOpcode == PPC::ADDI)
2300 MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass);
2301 else if (MachineInstOpcode == PPC::ADDI8)
2302 MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass);
2304 const TargetRegisterClass *UseRC =
2305 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2306 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2308 return FastISel::fastEmitInst_ri(MachineInstOpcode, UseRC,
2309 Op0, Op0IsKill, Imm);
2312 // Override for instructions with one register operand to avoid use of
2313 // R0/X0. The automatic infrastructure isn't aware of the context so
2314 // we must be conservative.
2315 unsigned PPCFastISel::fastEmitInst_r(unsigned MachineInstOpcode,
2316 const TargetRegisterClass* RC,
2317 unsigned Op0, bool Op0IsKill) {
2318 const TargetRegisterClass *UseRC =
2319 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2320 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2322 return FastISel::fastEmitInst_r(MachineInstOpcode, UseRC, Op0, Op0IsKill);
2325 // Override for instructions with two register operands to avoid use
2326 // of R0/X0. The automatic infrastructure isn't aware of the context
2327 // so we must be conservative.
2328 unsigned PPCFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
2329 const TargetRegisterClass* RC,
2330 unsigned Op0, bool Op0IsKill,
2331 unsigned Op1, bool Op1IsKill) {
2332 const TargetRegisterClass *UseRC =
2333 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2334 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2336 return FastISel::fastEmitInst_rr(MachineInstOpcode, UseRC, Op0, Op0IsKill,
2341 // Create the fast instruction selector for PowerPC64 ELF.
2342 FastISel *PPC::createFastISel(FunctionLoweringInfo &FuncInfo,
2343 const TargetLibraryInfo *LibInfo) {
2344 // Only available on 64-bit ELF for now.
2345 const PPCSubtarget &Subtarget = FuncInfo.MF->getSubtarget<PPCSubtarget>();
2346 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI())
2347 return new PPCFastISel(FuncInfo, LibInfo);