1 //===-- PPCFastISel.cpp - PowerPC FastISel implementation -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the PowerPC-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // PPCGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "MCTargetDesc/PPCPredicates.h"
18 #include "PPCCallingConv.h"
19 #include "PPCISelLowering.h"
20 #include "PPCMachineFunctionInfo.h"
21 #include "PPCSubtarget.h"
22 #include "PPCTargetMachine.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/IR/CallingConv.h"
32 #include "llvm/IR/GetElementPtrTypeIterator.h"
33 #include "llvm/IR/GlobalAlias.h"
34 #include "llvm/IR/GlobalVariable.h"
35 #include "llvm/IR/IntrinsicInst.h"
36 #include "llvm/IR/Operator.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Target/TargetLowering.h"
39 #include "llvm/Target/TargetMachine.h"
41 //===----------------------------------------------------------------------===//
44 // fastLowerArguments: Handle simple cases.
45 // PPCMaterializeGV: Handle TLS.
46 // SelectCall: Handle function pointers.
47 // SelectCall: Handle multi-register return values.
48 // SelectCall: Optimize away nops for local calls.
49 // processCallArgs: Handle bit-converted arguments.
50 // finishCall: Handle multi-register return values.
51 // PPCComputeAddress: Handle parameter references as FrameIndex's.
52 // PPCEmitCmp: Handle immediate as operand 1.
53 // SelectCall: Handle small byval arguments.
54 // SelectIntrinsicCall: Implement.
55 // SelectSelect: Implement.
56 // Consider factoring isTypeLegal into the base class.
57 // Implement switches and jump tables.
59 //===----------------------------------------------------------------------===//
62 #define DEBUG_TYPE "ppcfastisel"
66 typedef struct Address {
79 // Innocuous defaults for our address.
81 : BaseType(RegBase), Offset(0) {
86 class PPCFastISel final : public FastISel {
88 const TargetMachine &TM;
89 const PPCSubtarget *PPCSubTarget;
90 PPCFunctionInfo *PPCFuncInfo;
91 const TargetInstrInfo &TII;
92 const TargetLowering &TLI;
96 explicit PPCFastISel(FunctionLoweringInfo &FuncInfo,
97 const TargetLibraryInfo *LibInfo)
98 : FastISel(FuncInfo, LibInfo), TM(FuncInfo.MF->getTarget()),
99 PPCSubTarget(&FuncInfo.MF->getSubtarget<PPCSubtarget>()),
100 PPCFuncInfo(FuncInfo.MF->getInfo<PPCFunctionInfo>()),
101 TII(*PPCSubTarget->getInstrInfo()),
102 TLI(*PPCSubTarget->getTargetLowering()),
103 Context(&FuncInfo.Fn->getContext()) {}
105 // Backend specific FastISel code.
107 bool fastSelectInstruction(const Instruction *I) override;
108 unsigned fastMaterializeConstant(const Constant *C) override;
109 unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
110 bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
111 const LoadInst *LI) override;
112 bool fastLowerArguments() override;
113 unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
114 unsigned fastEmitInst_ri(unsigned MachineInstOpcode,
115 const TargetRegisterClass *RC,
116 unsigned Op0, bool Op0IsKill,
118 unsigned fastEmitInst_r(unsigned MachineInstOpcode,
119 const TargetRegisterClass *RC,
120 unsigned Op0, bool Op0IsKill);
121 unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
122 const TargetRegisterClass *RC,
123 unsigned Op0, bool Op0IsKill,
124 unsigned Op1, bool Op1IsKill);
126 bool fastLowerCall(CallLoweringInfo &CLI) override;
128 // Instruction selection routines.
130 bool SelectLoad(const Instruction *I);
131 bool SelectStore(const Instruction *I);
132 bool SelectBranch(const Instruction *I);
133 bool SelectIndirectBr(const Instruction *I);
134 bool SelectFPExt(const Instruction *I);
135 bool SelectFPTrunc(const Instruction *I);
136 bool SelectIToFP(const Instruction *I, bool IsSigned);
137 bool SelectFPToI(const Instruction *I, bool IsSigned);
138 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
139 bool SelectRet(const Instruction *I);
140 bool SelectTrunc(const Instruction *I);
141 bool SelectIntExt(const Instruction *I);
145 bool isTypeLegal(Type *Ty, MVT &VT);
146 bool isLoadTypeLegal(Type *Ty, MVT &VT);
147 bool isVSFRCRegister(unsigned Register) const {
148 return MRI.getRegClass(Register)->getID() == PPC::VSFRCRegClassID;
150 bool PPCEmitCmp(const Value *Src1Value, const Value *Src2Value,
151 bool isZExt, unsigned DestReg);
152 bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
153 const TargetRegisterClass *RC, bool IsZExt = true,
154 unsigned FP64LoadOpc = PPC::LFD);
155 bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
156 bool PPCComputeAddress(const Value *Obj, Address &Addr);
157 void PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset,
159 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
160 unsigned DestReg, bool IsZExt);
161 unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT);
162 unsigned PPCMaterializeGV(const GlobalValue *GV, MVT VT);
163 unsigned PPCMaterializeInt(const Constant *C, MVT VT, bool UseSExt = true);
164 unsigned PPCMaterialize32BitInt(int64_t Imm,
165 const TargetRegisterClass *RC);
166 unsigned PPCMaterialize64BitInt(int64_t Imm,
167 const TargetRegisterClass *RC);
168 unsigned PPCMoveToIntReg(const Instruction *I, MVT VT,
169 unsigned SrcReg, bool IsSigned);
170 unsigned PPCMoveToFPReg(MVT VT, unsigned SrcReg, bool IsSigned);
172 // Call handling routines.
174 bool processCallArgs(SmallVectorImpl<Value*> &Args,
175 SmallVectorImpl<unsigned> &ArgRegs,
176 SmallVectorImpl<MVT> &ArgVTs,
177 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
178 SmallVectorImpl<unsigned> &RegArgs,
182 bool finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumBytes);
183 CCAssignFn *usePPC32CCs(unsigned Flag);
186 #include "PPCGenFastISel.inc"
190 } // end anonymous namespace
192 #include "PPCGenCallingConv.inc"
194 // Function whose sole purpose is to kill compiler warnings
195 // stemming from unused functions included from PPCGenCallingConv.inc.
196 CCAssignFn *PPCFastISel::usePPC32CCs(unsigned Flag) {
198 return CC_PPC32_SVR4;
200 return CC_PPC32_SVR4_ByVal;
202 return CC_PPC32_SVR4_VarArg;
207 static Optional<PPC::Predicate> getComparePred(CmpInst::Predicate Pred) {
209 // These are not representable with any single compare.
210 case CmpInst::FCMP_FALSE:
211 case CmpInst::FCMP_UEQ:
212 case CmpInst::FCMP_UGT:
213 case CmpInst::FCMP_UGE:
214 case CmpInst::FCMP_ULT:
215 case CmpInst::FCMP_ULE:
216 case CmpInst::FCMP_UNE:
217 case CmpInst::FCMP_TRUE:
219 return Optional<PPC::Predicate>();
221 case CmpInst::FCMP_OEQ:
222 case CmpInst::ICMP_EQ:
225 case CmpInst::FCMP_OGT:
226 case CmpInst::ICMP_UGT:
227 case CmpInst::ICMP_SGT:
230 case CmpInst::FCMP_OGE:
231 case CmpInst::ICMP_UGE:
232 case CmpInst::ICMP_SGE:
235 case CmpInst::FCMP_OLT:
236 case CmpInst::ICMP_ULT:
237 case CmpInst::ICMP_SLT:
240 case CmpInst::FCMP_OLE:
241 case CmpInst::ICMP_ULE:
242 case CmpInst::ICMP_SLE:
245 case CmpInst::FCMP_ONE:
246 case CmpInst::ICMP_NE:
249 case CmpInst::FCMP_ORD:
252 case CmpInst::FCMP_UNO:
257 // Determine whether the type Ty is simple enough to be handled by
258 // fast-isel, and return its equivalent machine type in VT.
259 // FIXME: Copied directly from ARM -- factor into base class?
260 bool PPCFastISel::isTypeLegal(Type *Ty, MVT &VT) {
261 EVT Evt = TLI.getValueType(Ty, true);
263 // Only handle simple types.
264 if (Evt == MVT::Other || !Evt.isSimple()) return false;
265 VT = Evt.getSimpleVT();
267 // Handle all legal types, i.e. a register that will directly hold this
269 return TLI.isTypeLegal(VT);
272 // Determine whether the type Ty is simple enough to be handled by
273 // fast-isel as a load target, and return its equivalent machine type in VT.
274 bool PPCFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
275 if (isTypeLegal(Ty, VT)) return true;
277 // If this is a type than can be sign or zero-extended to a basic operation
278 // go ahead and accept it now.
279 if (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) {
286 // Given a value Obj, create an Address object Addr that represents its
287 // address. Return false if we can't handle it.
288 bool PPCFastISel::PPCComputeAddress(const Value *Obj, Address &Addr) {
289 const User *U = nullptr;
290 unsigned Opcode = Instruction::UserOp1;
291 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
292 // Don't walk into other basic blocks unless the object is an alloca from
293 // another block, otherwise it may not have a virtual register assigned.
294 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
295 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
296 Opcode = I->getOpcode();
299 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
300 Opcode = C->getOpcode();
307 case Instruction::BitCast:
308 // Look through bitcasts.
309 return PPCComputeAddress(U->getOperand(0), Addr);
310 case Instruction::IntToPtr:
311 // Look past no-op inttoptrs.
312 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
313 return PPCComputeAddress(U->getOperand(0), Addr);
315 case Instruction::PtrToInt:
316 // Look past no-op ptrtoints.
317 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
318 return PPCComputeAddress(U->getOperand(0), Addr);
320 case Instruction::GetElementPtr: {
321 Address SavedAddr = Addr;
322 long TmpOffset = Addr.Offset;
324 // Iterate through the GEP folding the constants into offsets where
326 gep_type_iterator GTI = gep_type_begin(U);
327 for (User::const_op_iterator II = U->op_begin() + 1, IE = U->op_end();
328 II != IE; ++II, ++GTI) {
329 const Value *Op = *II;
330 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
331 const StructLayout *SL = DL.getStructLayout(STy);
332 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
333 TmpOffset += SL->getElementOffset(Idx);
335 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
337 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
338 // Constant-offset addressing.
339 TmpOffset += CI->getSExtValue() * S;
342 if (canFoldAddIntoGEP(U, Op)) {
343 // A compatible add with a constant operand. Fold the constant.
345 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
346 TmpOffset += CI->getSExtValue() * S;
347 // Iterate on the other operand.
348 Op = cast<AddOperator>(Op)->getOperand(0);
352 goto unsupported_gep;
357 // Try to grab the base operand now.
358 Addr.Offset = TmpOffset;
359 if (PPCComputeAddress(U->getOperand(0), Addr)) return true;
361 // We failed, restore everything and try the other options.
367 case Instruction::Alloca: {
368 const AllocaInst *AI = cast<AllocaInst>(Obj);
369 DenseMap<const AllocaInst*, int>::iterator SI =
370 FuncInfo.StaticAllocaMap.find(AI);
371 if (SI != FuncInfo.StaticAllocaMap.end()) {
372 Addr.BaseType = Address::FrameIndexBase;
373 Addr.Base.FI = SI->second;
380 // FIXME: References to parameters fall through to the behavior
381 // below. They should be able to reference a frame index since
382 // they are stored to the stack, so we can get "ld rx, offset(r1)"
383 // instead of "addi ry, r1, offset / ld rx, 0(ry)". Obj will
384 // just contain the parameter. Try to handle this with a FI.
386 // Try to get this in a register if nothing else has worked.
387 if (Addr.Base.Reg == 0)
388 Addr.Base.Reg = getRegForValue(Obj);
390 // Prevent assignment of base register to X0, which is inappropriate
391 // for loads and stores alike.
392 if (Addr.Base.Reg != 0)
393 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass);
395 return Addr.Base.Reg != 0;
398 // Fix up some addresses that can't be used directly. For example, if
399 // an offset won't fit in an instruction field, we may need to move it
400 // into an index register.
401 void PPCFastISel::PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset,
402 unsigned &IndexReg) {
404 // Check whether the offset fits in the instruction field.
405 if (!isInt<16>(Addr.Offset))
408 // If this is a stack pointer and the offset needs to be simplified then
409 // put the alloca address into a register, set the base type back to
410 // register and continue. This should almost never happen.
411 if (!UseOffset && Addr.BaseType == Address::FrameIndexBase) {
412 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
413 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8),
414 ResultReg).addFrameIndex(Addr.Base.FI).addImm(0);
415 Addr.Base.Reg = ResultReg;
416 Addr.BaseType = Address::RegBase;
420 IntegerType *OffsetTy = ((VT == MVT::i32) ? Type::getInt32Ty(*Context)
421 : Type::getInt64Ty(*Context));
422 const ConstantInt *Offset =
423 ConstantInt::getSigned(OffsetTy, (int64_t)(Addr.Offset));
424 IndexReg = PPCMaterializeInt(Offset, MVT::i64);
425 assert(IndexReg && "Unexpected error in PPCMaterializeInt!");
429 // Emit a load instruction if possible, returning true if we succeeded,
430 // otherwise false. See commentary below for how the register class of
431 // the load is determined.
432 bool PPCFastISel::PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
433 const TargetRegisterClass *RC,
434 bool IsZExt, unsigned FP64LoadOpc) {
436 bool UseOffset = true;
438 // If ResultReg is given, it determines the register class of the load.
439 // Otherwise, RC is the register class to use. If the result of the
440 // load isn't anticipated in this block, both may be zero, in which
441 // case we must make a conservative guess. In particular, don't assign
442 // R0 or X0 to the result register, as the result may be used in a load,
443 // store, add-immediate, or isel that won't permit this. (Though
444 // perhaps the spill and reload of live-exit values would handle this?)
445 const TargetRegisterClass *UseRC =
446 (ResultReg ? MRI.getRegClass(ResultReg) :
448 (VT == MVT::f64 ? &PPC::F8RCRegClass :
449 (VT == MVT::f32 ? &PPC::F4RCRegClass :
450 (VT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
451 &PPC::GPRC_and_GPRC_NOR0RegClass)))));
453 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass);
455 switch (VT.SimpleTy) {
456 default: // e.g., vector types not handled
459 Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8;
463 (Is32BitInt ? PPC::LHZ : PPC::LHZ8) :
464 (Is32BitInt ? PPC::LHA : PPC::LHA8));
468 (Is32BitInt ? PPC::LWZ : PPC::LWZ8) :
469 (Is32BitInt ? PPC::LWA_32 : PPC::LWA));
470 if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0))
475 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) &&
476 "64-bit load with 32-bit target??");
477 UseOffset = ((Addr.Offset & 3) == 0);
487 // If necessary, materialize the offset into a register and use
488 // the indexed form. Also handle stack pointers with special needs.
489 unsigned IndexReg = 0;
490 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg);
492 // If this is a potential VSX load with an offset of 0, a VSX indexed load can
494 bool IsVSFRC = (ResultReg != 0) && isVSFRCRegister(ResultReg);
495 if (IsVSFRC && (Opc == PPC::LFD) &&
496 (Addr.BaseType != Address::FrameIndexBase) && UseOffset &&
497 (Addr.Offset == 0)) {
502 ResultReg = createResultReg(UseRC);
504 // Note: If we still have a frame index here, we know the offset is
505 // in range, as otherwise PPCSimplifyAddress would have converted it
507 if (Addr.BaseType == Address::FrameIndexBase) {
508 // VSX only provides an indexed load.
509 if (IsVSFRC && Opc == PPC::LFD) return false;
511 MachineMemOperand *MMO =
512 FuncInfo.MF->getMachineMemOperand(
513 MachinePointerInfo::getFixedStack(Addr.Base.FI, Addr.Offset),
514 MachineMemOperand::MOLoad, MFI.getObjectSize(Addr.Base.FI),
515 MFI.getObjectAlignment(Addr.Base.FI));
517 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
518 .addImm(Addr.Offset).addFrameIndex(Addr.Base.FI).addMemOperand(MMO);
520 // Base reg with offset in range.
521 } else if (UseOffset) {
522 // VSX only provides an indexed load.
523 if (IsVSFRC && Opc == PPC::LFD) return false;
525 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
526 .addImm(Addr.Offset).addReg(Addr.Base.Reg);
530 // Get the RR opcode corresponding to the RI one. FIXME: It would be
531 // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it
532 // is hard to get at.
534 default: llvm_unreachable("Unexpected opcode!");
535 case PPC::LBZ: Opc = PPC::LBZX; break;
536 case PPC::LBZ8: Opc = PPC::LBZX8; break;
537 case PPC::LHZ: Opc = PPC::LHZX; break;
538 case PPC::LHZ8: Opc = PPC::LHZX8; break;
539 case PPC::LHA: Opc = PPC::LHAX; break;
540 case PPC::LHA8: Opc = PPC::LHAX8; break;
541 case PPC::LWZ: Opc = PPC::LWZX; break;
542 case PPC::LWZ8: Opc = PPC::LWZX8; break;
543 case PPC::LWA: Opc = PPC::LWAX; break;
544 case PPC::LWA_32: Opc = PPC::LWAX_32; break;
545 case PPC::LD: Opc = PPC::LDX; break;
546 case PPC::LFS: Opc = PPC::LFSX; break;
547 case PPC::LFD: Opc = IsVSFRC ? PPC::LXSDX : PPC::LFDX; break;
549 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
550 .addReg(Addr.Base.Reg).addReg(IndexReg);
556 // Attempt to fast-select a load instruction.
557 bool PPCFastISel::SelectLoad(const Instruction *I) {
558 // FIXME: No atomic loads are supported.
559 if (cast<LoadInst>(I)->isAtomic())
562 // Verify we have a legal type before going any further.
564 if (!isLoadTypeLegal(I->getType(), VT))
567 // See if we can handle this address.
569 if (!PPCComputeAddress(I->getOperand(0), Addr))
572 // Look at the currently assigned register for this instruction
573 // to determine the required register class. This is necessary
574 // to constrain RA from using R0/X0 when this is not legal.
575 unsigned AssignedReg = FuncInfo.ValueMap[I];
576 const TargetRegisterClass *RC =
577 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr;
579 unsigned ResultReg = 0;
580 if (!PPCEmitLoad(VT, ResultReg, Addr, RC))
582 updateValueMap(I, ResultReg);
586 // Emit a store instruction to store SrcReg at Addr.
587 bool PPCFastISel::PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr) {
588 assert(SrcReg && "Nothing to store!");
590 bool UseOffset = true;
592 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg);
593 bool Is32BitInt = RC->hasSuperClassEq(&PPC::GPRCRegClass);
595 switch (VT.SimpleTy) {
596 default: // e.g., vector types not handled
599 Opc = Is32BitInt ? PPC::STB : PPC::STB8;
602 Opc = Is32BitInt ? PPC::STH : PPC::STH8;
605 assert(Is32BitInt && "Not GPRC for i32??");
610 UseOffset = ((Addr.Offset & 3) == 0);
620 // If necessary, materialize the offset into a register and use
621 // the indexed form. Also handle stack pointers with special needs.
622 unsigned IndexReg = 0;
623 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg);
625 // If this is a potential VSX store with an offset of 0, a VSX indexed store
627 bool IsVSFRC = isVSFRCRegister(SrcReg);
628 if (IsVSFRC && (Opc == PPC::STFD) &&
629 (Addr.BaseType != Address::FrameIndexBase) && UseOffset &&
630 (Addr.Offset == 0)) {
634 // Note: If we still have a frame index here, we know the offset is
635 // in range, as otherwise PPCSimplifyAddress would have converted it
637 if (Addr.BaseType == Address::FrameIndexBase) {
638 // VSX only provides an indexed store.
639 if (IsVSFRC && Opc == PPC::STFD) return false;
641 MachineMemOperand *MMO =
642 FuncInfo.MF->getMachineMemOperand(
643 MachinePointerInfo::getFixedStack(Addr.Base.FI, Addr.Offset),
644 MachineMemOperand::MOStore, MFI.getObjectSize(Addr.Base.FI),
645 MFI.getObjectAlignment(Addr.Base.FI));
647 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
650 .addFrameIndex(Addr.Base.FI)
653 // Base reg with offset in range.
654 } else if (UseOffset) {
655 // VSX only provides an indexed store.
656 if (IsVSFRC && Opc == PPC::STFD) return false;
658 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
659 .addReg(SrcReg).addImm(Addr.Offset).addReg(Addr.Base.Reg);
663 // Get the RR opcode corresponding to the RI one. FIXME: It would be
664 // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it
665 // is hard to get at.
667 default: llvm_unreachable("Unexpected opcode!");
668 case PPC::STB: Opc = PPC::STBX; break;
669 case PPC::STH : Opc = PPC::STHX; break;
670 case PPC::STW : Opc = PPC::STWX; break;
671 case PPC::STB8: Opc = PPC::STBX8; break;
672 case PPC::STH8: Opc = PPC::STHX8; break;
673 case PPC::STW8: Opc = PPC::STWX8; break;
674 case PPC::STD: Opc = PPC::STDX; break;
675 case PPC::STFS: Opc = PPC::STFSX; break;
676 case PPC::STFD: Opc = IsVSFRC ? PPC::STXSDX : PPC::STFDX; break;
679 auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
682 // If we have an index register defined we use it in the store inst,
683 // otherwise we use X0 as base as it makes the vector instructions to
684 // use zero in the computation of the effective address regardless the
685 // content of the register.
687 MIB.addReg(Addr.Base.Reg).addReg(IndexReg);
689 MIB.addReg(PPC::ZERO8).addReg(Addr.Base.Reg);
695 // Attempt to fast-select a store instruction.
696 bool PPCFastISel::SelectStore(const Instruction *I) {
697 Value *Op0 = I->getOperand(0);
700 // FIXME: No atomics loads are supported.
701 if (cast<StoreInst>(I)->isAtomic())
704 // Verify we have a legal type before going any further.
706 if (!isLoadTypeLegal(Op0->getType(), VT))
709 // Get the value to be stored into a register.
710 SrcReg = getRegForValue(Op0);
714 // See if we can handle this address.
716 if (!PPCComputeAddress(I->getOperand(1), Addr))
719 if (!PPCEmitStore(VT, SrcReg, Addr))
725 // Attempt to fast-select a branch instruction.
726 bool PPCFastISel::SelectBranch(const Instruction *I) {
727 const BranchInst *BI = cast<BranchInst>(I);
728 MachineBasicBlock *BrBB = FuncInfo.MBB;
729 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
730 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
732 // For now, just try the simplest case where it's fed by a compare.
733 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
734 Optional<PPC::Predicate> OptPPCPred = getComparePred(CI->getPredicate());
738 PPC::Predicate PPCPred = OptPPCPred.getValue();
740 // Take advantage of fall-through opportunities.
741 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
743 PPCPred = PPC::InvertPredicate(PPCPred);
746 unsigned CondReg = createResultReg(&PPC::CRRCRegClass);
748 if (!PPCEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(),
752 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCC))
753 .addImm(PPCPred).addReg(CondReg).addMBB(TBB);
754 fastEmitBranch(FBB, DbgLoc);
755 FuncInfo.MBB->addSuccessor(TBB);
758 } else if (const ConstantInt *CI =
759 dyn_cast<ConstantInt>(BI->getCondition())) {
760 uint64_t Imm = CI->getZExtValue();
761 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
762 fastEmitBranch(Target, DbgLoc);
766 // FIXME: ARM looks for a case where the block containing the compare
767 // has been split from the block containing the branch. If this happens,
768 // there is a vreg available containing the result of the compare. I'm
769 // not sure we can do much, as we've lost the predicate information with
770 // the compare instruction -- we have a 4-bit CR but don't know which bit
775 // Attempt to emit a compare of the two source values. Signed and unsigned
776 // comparisons are supported. Return false if we can't handle it.
777 bool PPCFastISel::PPCEmitCmp(const Value *SrcValue1, const Value *SrcValue2,
778 bool IsZExt, unsigned DestReg) {
779 Type *Ty = SrcValue1->getType();
780 EVT SrcEVT = TLI.getValueType(Ty, true);
781 if (!SrcEVT.isSimple())
783 MVT SrcVT = SrcEVT.getSimpleVT();
785 if (SrcVT == MVT::i1 && PPCSubTarget->useCRBits())
788 // See if operand 2 is an immediate encodeable in the compare.
789 // FIXME: Operands are not in canonical order at -O0, so an immediate
790 // operand in position 1 is a lost opportunity for now. We are
791 // similar to ARM in this regard.
795 // Only 16-bit integer constants can be represented in compares for
796 // PowerPC. Others will be materialized into a register.
797 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(SrcValue2)) {
798 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
799 SrcVT == MVT::i8 || SrcVT == MVT::i1) {
800 const APInt &CIVal = ConstInt->getValue();
801 Imm = (IsZExt) ? (long)CIVal.getZExtValue() : (long)CIVal.getSExtValue();
802 if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm)))
808 bool NeedsExt = false;
809 switch (SrcVT.SimpleTy) {
810 default: return false;
812 CmpOpc = PPC::FCMPUS;
815 CmpOpc = PPC::FCMPUD;
821 // Intentional fall-through.
824 CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW;
826 CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI;
830 CmpOpc = IsZExt ? PPC::CMPLD : PPC::CMPD;
832 CmpOpc = IsZExt ? PPC::CMPLDI : PPC::CMPDI;
836 unsigned SrcReg1 = getRegForValue(SrcValue1);
840 unsigned SrcReg2 = 0;
842 SrcReg2 = getRegForValue(SrcValue2);
848 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
849 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt))
854 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
855 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt))
862 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
863 .addReg(SrcReg1).addReg(SrcReg2);
865 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
866 .addReg(SrcReg1).addImm(Imm);
871 // Attempt to fast-select a floating-point extend instruction.
872 bool PPCFastISel::SelectFPExt(const Instruction *I) {
873 Value *Src = I->getOperand(0);
874 EVT SrcVT = TLI.getValueType(Src->getType(), true);
875 EVT DestVT = TLI.getValueType(I->getType(), true);
877 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
880 unsigned SrcReg = getRegForValue(Src);
884 // No code is generated for a FP extend.
885 updateValueMap(I, SrcReg);
889 // Attempt to fast-select a floating-point truncate instruction.
890 bool PPCFastISel::SelectFPTrunc(const Instruction *I) {
891 Value *Src = I->getOperand(0);
892 EVT SrcVT = TLI.getValueType(Src->getType(), true);
893 EVT DestVT = TLI.getValueType(I->getType(), true);
895 if (SrcVT != MVT::f64 || DestVT != MVT::f32)
898 unsigned SrcReg = getRegForValue(Src);
902 // Round the result to single precision.
903 unsigned DestReg = createResultReg(&PPC::F4RCRegClass);
904 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::FRSP), DestReg)
907 updateValueMap(I, DestReg);
911 // Move an i32 or i64 value in a GPR to an f64 value in an FPR.
912 // FIXME: When direct register moves are implemented (see PowerISA 2.07),
913 // those should be used instead of moving via a stack slot when the
914 // subtarget permits.
915 // FIXME: The code here is sloppy for the 4-byte case. Can use a 4-byte
916 // stack slot and 4-byte store/load sequence. Or just sext the 4-byte
917 // case to 8 bytes which produces tighter code but wastes stack space.
918 unsigned PPCFastISel::PPCMoveToFPReg(MVT SrcVT, unsigned SrcReg,
921 // If necessary, extend 32-bit int to 64-bit.
922 if (SrcVT == MVT::i32) {
923 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass);
924 if (!PPCEmitIntExt(MVT::i32, SrcReg, MVT::i64, TmpReg, !IsSigned))
929 // Get a stack slot 8 bytes wide, aligned on an 8-byte boundary.
931 Addr.BaseType = Address::FrameIndexBase;
932 Addr.Base.FI = MFI.CreateStackObject(8, 8, false);
934 // Store the value from the GPR.
935 if (!PPCEmitStore(MVT::i64, SrcReg, Addr))
938 // Load the integer value into an FPR. The kind of load used depends
939 // on a number of conditions.
940 unsigned LoadOpc = PPC::LFD;
942 if (SrcVT == MVT::i32) {
944 LoadOpc = PPC::LFIWZX;
945 Addr.Offset = (PPCSubTarget->isLittleEndian()) ? 0 : 4;
946 } else if (PPCSubTarget->hasLFIWAX()) {
947 LoadOpc = PPC::LFIWAX;
948 Addr.Offset = (PPCSubTarget->isLittleEndian()) ? 0 : 4;
952 const TargetRegisterClass *RC = &PPC::F8RCRegClass;
953 unsigned ResultReg = 0;
954 if (!PPCEmitLoad(MVT::f64, ResultReg, Addr, RC, !IsSigned, LoadOpc))
960 // Attempt to fast-select an integer-to-floating-point conversion.
961 bool PPCFastISel::SelectIToFP(const Instruction *I, bool IsSigned) {
963 Type *DstTy = I->getType();
964 if (!isTypeLegal(DstTy, DstVT))
967 if (DstVT != MVT::f32 && DstVT != MVT::f64)
970 Value *Src = I->getOperand(0);
971 EVT SrcEVT = TLI.getValueType(Src->getType(), true);
972 if (!SrcEVT.isSimple())
975 MVT SrcVT = SrcEVT.getSimpleVT();
977 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 &&
978 SrcVT != MVT::i32 && SrcVT != MVT::i64)
981 unsigned SrcReg = getRegForValue(Src);
985 // We can only lower an unsigned convert if we have the newer
986 // floating-point conversion operations.
987 if (!IsSigned && !PPCSubTarget->hasFPCVT())
990 // FIXME: For now we require the newer floating-point conversion operations
991 // (which are present only on P7 and A2 server models) when converting
992 // to single-precision float. Otherwise we have to generate a lot of
993 // fiddly code to avoid double rounding. If necessary, the fiddly code
994 // can be found in PPCTargetLowering::LowerINT_TO_FP().
995 if (DstVT == MVT::f32 && !PPCSubTarget->hasFPCVT())
998 // Extend the input if necessary.
999 if (SrcVT == MVT::i8 || SrcVT == MVT::i16) {
1000 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass);
1001 if (!PPCEmitIntExt(SrcVT, SrcReg, MVT::i64, TmpReg, !IsSigned))
1007 // Move the integer value to an FPR.
1008 unsigned FPReg = PPCMoveToFPReg(SrcVT, SrcReg, IsSigned);
1012 // Determine the opcode for the conversion.
1013 const TargetRegisterClass *RC = &PPC::F8RCRegClass;
1014 unsigned DestReg = createResultReg(RC);
1017 if (DstVT == MVT::f32)
1018 Opc = IsSigned ? PPC::FCFIDS : PPC::FCFIDUS;
1020 Opc = IsSigned ? PPC::FCFID : PPC::FCFIDU;
1022 // Generate the convert.
1023 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1026 updateValueMap(I, DestReg);
1030 // Move the floating-point value in SrcReg into an integer destination
1031 // register, and return the register (or zero if we can't handle it).
1032 // FIXME: When direct register moves are implemented (see PowerISA 2.07),
1033 // those should be used instead of moving via a stack slot when the
1034 // subtarget permits.
1035 unsigned PPCFastISel::PPCMoveToIntReg(const Instruction *I, MVT VT,
1036 unsigned SrcReg, bool IsSigned) {
1037 // Get a stack slot 8 bytes wide, aligned on an 8-byte boundary.
1038 // Note that if have STFIWX available, we could use a 4-byte stack
1039 // slot for i32, but this being fast-isel we'll just go with the
1040 // easiest code gen possible.
1042 Addr.BaseType = Address::FrameIndexBase;
1043 Addr.Base.FI = MFI.CreateStackObject(8, 8, false);
1045 // Store the value from the FPR.
1046 if (!PPCEmitStore(MVT::f64, SrcReg, Addr))
1049 // Reload it into a GPR. If we want an i32, modify the address
1050 // to have a 4-byte offset so we load from the right place.
1054 // Look at the currently assigned register for this instruction
1055 // to determine the required register class.
1056 unsigned AssignedReg = FuncInfo.ValueMap[I];
1057 const TargetRegisterClass *RC =
1058 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr;
1060 unsigned ResultReg = 0;
1061 if (!PPCEmitLoad(VT, ResultReg, Addr, RC, !IsSigned))
1067 // Attempt to fast-select a floating-point-to-integer conversion.
1068 bool PPCFastISel::SelectFPToI(const Instruction *I, bool IsSigned) {
1070 Type *DstTy = I->getType();
1071 if (!isTypeLegal(DstTy, DstVT))
1074 if (DstVT != MVT::i32 && DstVT != MVT::i64)
1077 // If we don't have FCTIDUZ and we need it, punt to SelectionDAG.
1078 if (DstVT == MVT::i64 && !IsSigned && !PPCSubTarget->hasFPCVT())
1081 Value *Src = I->getOperand(0);
1082 Type *SrcTy = Src->getType();
1083 if (!isTypeLegal(SrcTy, SrcVT))
1086 if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1089 unsigned SrcReg = getRegForValue(Src);
1093 // Convert f32 to f64 if necessary. This is just a meaningless copy
1094 // to get the register class right. COPY_TO_REGCLASS is needed since
1095 // a COPY from F4RC to F8RC is converted to a F4RC-F4RC copy downstream.
1096 const TargetRegisterClass *InRC = MRI.getRegClass(SrcReg);
1097 if (InRC == &PPC::F4RCRegClass) {
1098 unsigned TmpReg = createResultReg(&PPC::F8RCRegClass);
1099 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1100 TII.get(TargetOpcode::COPY_TO_REGCLASS), TmpReg)
1101 .addReg(SrcReg).addImm(PPC::F8RCRegClassID);
1105 // Determine the opcode for the conversion, which takes place
1106 // entirely within FPRs.
1107 unsigned DestReg = createResultReg(&PPC::F8RCRegClass);
1110 if (DstVT == MVT::i32)
1114 Opc = PPCSubTarget->hasFPCVT() ? PPC::FCTIWUZ : PPC::FCTIDZ;
1116 Opc = IsSigned ? PPC::FCTIDZ : PPC::FCTIDUZ;
1118 // Generate the convert.
1119 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1122 // Now move the integer value from a float register to an integer register.
1123 unsigned IntReg = PPCMoveToIntReg(I, DstVT, DestReg, IsSigned);
1127 updateValueMap(I, IntReg);
1131 // Attempt to fast-select a binary integer operation that isn't already
1132 // handled automatically.
1133 bool PPCFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1134 EVT DestVT = TLI.getValueType(I->getType(), true);
1136 // We can get here in the case when we have a binary operation on a non-legal
1137 // type and the target independent selector doesn't know how to handle it.
1138 if (DestVT != MVT::i16 && DestVT != MVT::i8)
1141 // Look at the currently assigned register for this instruction
1142 // to determine the required register class. If there is no register,
1143 // make a conservative choice (don't assign R0).
1144 unsigned AssignedReg = FuncInfo.ValueMap[I];
1145 const TargetRegisterClass *RC =
1146 (AssignedReg ? MRI.getRegClass(AssignedReg) :
1147 &PPC::GPRC_and_GPRC_NOR0RegClass);
1148 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
1151 switch (ISDOpcode) {
1152 default: return false;
1154 Opc = IsGPRC ? PPC::ADD4 : PPC::ADD8;
1157 Opc = IsGPRC ? PPC::OR : PPC::OR8;
1160 Opc = IsGPRC ? PPC::SUBF : PPC::SUBF8;
1164 unsigned ResultReg = createResultReg(RC ? RC : &PPC::G8RCRegClass);
1165 unsigned SrcReg1 = getRegForValue(I->getOperand(0));
1166 if (SrcReg1 == 0) return false;
1168 // Handle case of small immediate operand.
1169 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(1))) {
1170 const APInt &CIVal = ConstInt->getValue();
1171 int Imm = (int)CIVal.getSExtValue();
1173 if (isInt<16>(Imm)) {
1176 llvm_unreachable("Missing case!");
1179 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1183 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
1196 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1205 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
1212 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
1216 updateValueMap(I, ResultReg);
1223 unsigned SrcReg2 = getRegForValue(I->getOperand(1));
1224 if (SrcReg2 == 0) return false;
1226 // Reverse operands for subtract-from.
1227 if (ISDOpcode == ISD::SUB)
1228 std::swap(SrcReg1, SrcReg2);
1230 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1231 .addReg(SrcReg1).addReg(SrcReg2);
1232 updateValueMap(I, ResultReg);
1236 // Handle arguments to a call that we're attempting to fast-select.
1237 // Return false if the arguments are too complex for us at the moment.
1238 bool PPCFastISel::processCallArgs(SmallVectorImpl<Value*> &Args,
1239 SmallVectorImpl<unsigned> &ArgRegs,
1240 SmallVectorImpl<MVT> &ArgVTs,
1241 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1242 SmallVectorImpl<unsigned> &RegArgs,
1246 SmallVector<CCValAssign, 16> ArgLocs;
1247 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, ArgLocs, *Context);
1249 // Reserve space for the linkage area on the stack.
1250 unsigned LinkageSize = PPCSubTarget->getFrameLowering()->getLinkageSize();
1251 CCInfo.AllocateStack(LinkageSize, 8);
1253 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CC_PPC64_ELF_FIS);
1255 // Bail out if we can't handle any of the arguments.
1256 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1257 CCValAssign &VA = ArgLocs[I];
1258 MVT ArgVT = ArgVTs[VA.getValNo()];
1260 // Skip vector arguments for now, as well as long double and
1261 // uint128_t, and anything that isn't passed in a register.
1262 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64 || ArgVT == MVT::i1 ||
1263 !VA.isRegLoc() || VA.needsCustom())
1266 // Skip bit-converted arguments for now.
1267 if (VA.getLocInfo() == CCValAssign::BCvt)
1271 // Get a count of how many bytes are to be pushed onto the stack.
1272 NumBytes = CCInfo.getNextStackOffset();
1274 // The prolog code of the callee may store up to 8 GPR argument registers to
1275 // the stack, allowing va_start to index over them in memory if its varargs.
1276 // Because we cannot tell if this is needed on the caller side, we have to
1277 // conservatively assume that it is needed. As such, make sure we have at
1278 // least enough stack space for the caller to store the 8 GPRs.
1279 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
1280 NumBytes = std::max(NumBytes, LinkageSize + 64);
1282 // Issue CALLSEQ_START.
1283 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1284 TII.get(TII.getCallFrameSetupOpcode()))
1287 // Prepare to assign register arguments. Every argument uses up a
1288 // GPR protocol register even if it's passed in a floating-point
1289 // register (unless we're using the fast calling convention).
1290 unsigned NextGPR = PPC::X3;
1291 unsigned NextFPR = PPC::F1;
1293 // Process arguments.
1294 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1295 CCValAssign &VA = ArgLocs[I];
1296 unsigned Arg = ArgRegs[VA.getValNo()];
1297 MVT ArgVT = ArgVTs[VA.getValNo()];
1299 // Handle argument promotion and bitcasts.
1300 switch (VA.getLocInfo()) {
1302 llvm_unreachable("Unknown loc info!");
1303 case CCValAssign::Full:
1305 case CCValAssign::SExt: {
1306 MVT DestVT = VA.getLocVT();
1307 const TargetRegisterClass *RC =
1308 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1309 unsigned TmpReg = createResultReg(RC);
1310 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/false))
1311 llvm_unreachable("Failed to emit a sext!");
1316 case CCValAssign::AExt:
1317 case CCValAssign::ZExt: {
1318 MVT DestVT = VA.getLocVT();
1319 const TargetRegisterClass *RC =
1320 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1321 unsigned TmpReg = createResultReg(RC);
1322 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/true))
1323 llvm_unreachable("Failed to emit a zext!");
1328 case CCValAssign::BCvt: {
1329 // FIXME: Not yet handled.
1330 llvm_unreachable("Should have bailed before getting here!");
1335 // Copy this argument to the appropriate register.
1337 if (ArgVT == MVT::f32 || ArgVT == MVT::f64) {
1339 if (CC != CallingConv::Fast)
1344 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1345 TII.get(TargetOpcode::COPY), ArgReg).addReg(Arg);
1346 RegArgs.push_back(ArgReg);
1352 // For a call that we've determined we can fast-select, finish the
1353 // call sequence and generate a copy to obtain the return value (if any).
1354 bool PPCFastISel::finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumBytes) {
1355 CallingConv::ID CC = CLI.CallConv;
1357 // Issue CallSEQ_END.
1358 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1359 TII.get(TII.getCallFrameDestroyOpcode()))
1360 .addImm(NumBytes).addImm(0);
1362 // Next, generate a copy to obtain the return value.
1363 // FIXME: No multi-register return values yet, though I don't foresee
1364 // any real difficulties there.
1365 if (RetVT != MVT::isVoid) {
1366 SmallVector<CCValAssign, 16> RVLocs;
1367 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1368 CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1369 CCValAssign &VA = RVLocs[0];
1370 assert(RVLocs.size() == 1 && "No support for multi-reg return values!");
1371 assert(VA.isRegLoc() && "Can only return in registers!");
1373 MVT DestVT = VA.getValVT();
1374 MVT CopyVT = DestVT;
1376 // Ints smaller than a register still arrive in a full 64-bit
1377 // register, so make sure we recognize this.
1378 if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32)
1381 unsigned SourcePhysReg = VA.getLocReg();
1382 unsigned ResultReg = 0;
1384 if (RetVT == CopyVT) {
1385 const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT);
1386 ResultReg = createResultReg(CpyRC);
1388 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1389 TII.get(TargetOpcode::COPY), ResultReg)
1390 .addReg(SourcePhysReg);
1392 // If necessary, round the floating result to single precision.
1393 } else if (CopyVT == MVT::f64) {
1394 ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1395 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::FRSP),
1396 ResultReg).addReg(SourcePhysReg);
1398 // If only the low half of a general register is needed, generate
1399 // a GPRC copy instead of a G8RC copy. (EXTRACT_SUBREG can't be
1400 // used along the fast-isel path (not lowered), and downstream logic
1401 // also doesn't like a direct subreg copy on a physical reg.)
1402 } else if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) {
1403 ResultReg = createResultReg(&PPC::GPRCRegClass);
1404 // Convert physical register from G8RC to GPRC.
1405 SourcePhysReg -= PPC::X0 - PPC::R0;
1406 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1407 TII.get(TargetOpcode::COPY), ResultReg)
1408 .addReg(SourcePhysReg);
1411 assert(ResultReg && "ResultReg unset!");
1412 CLI.InRegs.push_back(SourcePhysReg);
1413 CLI.ResultReg = ResultReg;
1414 CLI.NumResultRegs = 1;
1420 bool PPCFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1421 CallingConv::ID CC = CLI.CallConv;
1422 bool IsTailCall = CLI.IsTailCall;
1423 bool IsVarArg = CLI.IsVarArg;
1424 const Value *Callee = CLI.Callee;
1425 const char *SymName = CLI.SymName;
1427 if (!Callee && !SymName)
1430 // Allow SelectionDAG isel to handle tail calls.
1434 // Let SDISel handle vararg functions.
1438 // Handle simple calls for now, with legal return types and
1439 // those that can be extended.
1440 Type *RetTy = CLI.RetTy;
1442 if (RetTy->isVoidTy())
1443 RetVT = MVT::isVoid;
1444 else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
1448 // FIXME: No multi-register return values yet.
1449 if (RetVT != MVT::isVoid && RetVT != MVT::i8 && RetVT != MVT::i16 &&
1450 RetVT != MVT::i32 && RetVT != MVT::i64 && RetVT != MVT::f32 &&
1451 RetVT != MVT::f64) {
1452 SmallVector<CCValAssign, 16> RVLocs;
1453 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs, *Context);
1454 CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1455 if (RVLocs.size() > 1)
1459 // Bail early if more than 8 arguments, as we only currently
1460 // handle arguments passed in registers.
1461 unsigned NumArgs = CLI.OutVals.size();
1465 // Set up the argument vectors.
1466 SmallVector<Value*, 8> Args;
1467 SmallVector<unsigned, 8> ArgRegs;
1468 SmallVector<MVT, 8> ArgVTs;
1469 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1471 Args.reserve(NumArgs);
1472 ArgRegs.reserve(NumArgs);
1473 ArgVTs.reserve(NumArgs);
1474 ArgFlags.reserve(NumArgs);
1476 for (unsigned i = 0, ie = NumArgs; i != ie; ++i) {
1477 // Only handle easy calls for now. It would be reasonably easy
1478 // to handle <= 8-byte structures passed ByVal in registers, but we
1479 // have to ensure they are right-justified in the register.
1480 ISD::ArgFlagsTy Flags = CLI.OutFlags[i];
1481 if (Flags.isInReg() || Flags.isSRet() || Flags.isNest() || Flags.isByVal())
1484 Value *ArgValue = CLI.OutVals[i];
1485 Type *ArgTy = ArgValue->getType();
1487 if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8)
1490 if (ArgVT.isVector())
1493 unsigned Arg = getRegForValue(ArgValue);
1497 Args.push_back(ArgValue);
1498 ArgRegs.push_back(Arg);
1499 ArgVTs.push_back(ArgVT);
1500 ArgFlags.push_back(Flags);
1503 // Process the arguments.
1504 SmallVector<unsigned, 8> RegArgs;
1507 if (!processCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
1508 RegArgs, CC, NumBytes, IsVarArg))
1511 MachineInstrBuilder MIB;
1512 // FIXME: No handling for function pointers yet. This requires
1513 // implementing the function descriptor (OPD) setup.
1514 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1516 // patchpoints are a special case; they always dispatch to a pointer value.
1517 // However, we don't actually want to generate the indirect call sequence
1518 // here (that will be generated, as necessary, during asm printing), and
1519 // the call we generate here will be erased by FastISel::selectPatchpoint,
1520 // so don't try very hard...
1521 if (CLI.IsPatchPoint)
1522 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::NOP));
1526 // Build direct call with NOP for TOC restore.
1527 // FIXME: We can and should optimize away the NOP for local calls.
1528 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1529 TII.get(PPC::BL8_NOP));
1531 MIB.addGlobalAddress(GV);
1534 // Add implicit physical register uses to the call.
1535 for (unsigned II = 0, IE = RegArgs.size(); II != IE; ++II)
1536 MIB.addReg(RegArgs[II], RegState::Implicit);
1538 // Direct calls, in both the ELF V1 and V2 ABIs, need the TOC register live
1540 PPCFuncInfo->setUsesTOCBasePtr();
1541 MIB.addReg(PPC::X2, RegState::Implicit);
1543 // Add a register mask with the call-preserved registers. Proper
1544 // defs for return values will be added by setPhysRegsDeadExcept().
1545 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1549 // Finish off the call including any return values.
1550 return finishCall(RetVT, CLI, NumBytes);
1553 // Attempt to fast-select a return instruction.
1554 bool PPCFastISel::SelectRet(const Instruction *I) {
1556 if (!FuncInfo.CanLowerReturn)
1559 const ReturnInst *Ret = cast<ReturnInst>(I);
1560 const Function &F = *I->getParent()->getParent();
1562 // Build a list of return value registers.
1563 SmallVector<unsigned, 4> RetRegs;
1564 CallingConv::ID CC = F.getCallingConv();
1566 if (Ret->getNumOperands() > 0) {
1567 SmallVector<ISD::OutputArg, 4> Outs;
1568 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
1570 // Analyze operands of the call, assigning locations to each operand.
1571 SmallVector<CCValAssign, 16> ValLocs;
1572 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, *Context);
1573 CCInfo.AnalyzeReturn(Outs, RetCC_PPC64_ELF_FIS);
1574 const Value *RV = Ret->getOperand(0);
1576 // FIXME: Only one output register for now.
1577 if (ValLocs.size() > 1)
1580 // Special case for returning a constant integer of any size.
1581 // Materialize the constant as an i64 and copy it to the return
1582 // register. We still need to worry about properly extending the sign. E.g:
1583 // If the constant has only one bit, it means it is a boolean. Therefore
1584 // we can't use PPCMaterializeInt because it extends the sign which will
1585 // cause negations of the returned value to be incorrect as they are
1586 // implemented as the flip of the least significant bit.
1587 if (isa<ConstantInt>(*RV)) {
1588 const Constant *C = cast<Constant>(RV);
1590 CCValAssign &VA = ValLocs[0];
1592 unsigned RetReg = VA.getLocReg();
1593 unsigned SrcReg = PPCMaterializeInt(C, MVT::i64,
1594 VA.getLocInfo() == CCValAssign::SExt);
1596 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1597 TII.get(TargetOpcode::COPY), RetReg).addReg(SrcReg);
1599 RetRegs.push_back(RetReg);
1602 unsigned Reg = getRegForValue(RV);
1607 // Copy the result values into the output registers.
1608 for (unsigned i = 0; i < ValLocs.size(); ++i) {
1610 CCValAssign &VA = ValLocs[i];
1611 assert(VA.isRegLoc() && "Can only return in registers!");
1612 RetRegs.push_back(VA.getLocReg());
1613 unsigned SrcReg = Reg + VA.getValNo();
1615 EVT RVEVT = TLI.getValueType(RV->getType());
1616 if (!RVEVT.isSimple())
1618 MVT RVVT = RVEVT.getSimpleVT();
1619 MVT DestVT = VA.getLocVT();
1621 if (RVVT != DestVT && RVVT != MVT::i8 &&
1622 RVVT != MVT::i16 && RVVT != MVT::i32)
1625 if (RVVT != DestVT) {
1626 switch (VA.getLocInfo()) {
1628 llvm_unreachable("Unknown loc info!");
1629 case CCValAssign::Full:
1630 llvm_unreachable("Full value assign but types don't match?");
1631 case CCValAssign::AExt:
1632 case CCValAssign::ZExt: {
1633 const TargetRegisterClass *RC =
1634 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1635 unsigned TmpReg = createResultReg(RC);
1636 if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, true))
1641 case CCValAssign::SExt: {
1642 const TargetRegisterClass *RC =
1643 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1644 unsigned TmpReg = createResultReg(RC);
1645 if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, false))
1653 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1654 TII.get(TargetOpcode::COPY), RetRegs[i])
1660 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1661 TII.get(PPC::BLR8));
1663 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1664 MIB.addReg(RetRegs[i], RegState::Implicit);
1669 // Attempt to emit an integer extend of SrcReg into DestReg. Both
1670 // signed and zero extensions are supported. Return false if we
1672 bool PPCFastISel::PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1673 unsigned DestReg, bool IsZExt) {
1674 if (DestVT != MVT::i32 && DestVT != MVT::i64)
1676 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 && SrcVT != MVT::i32)
1679 // Signed extensions use EXTSB, EXTSH, EXTSW.
1682 if (SrcVT == MVT::i8)
1683 Opc = (DestVT == MVT::i32) ? PPC::EXTSB : PPC::EXTSB8_32_64;
1684 else if (SrcVT == MVT::i16)
1685 Opc = (DestVT == MVT::i32) ? PPC::EXTSH : PPC::EXTSH8_32_64;
1687 assert(DestVT == MVT::i64 && "Signed extend from i32 to i32??");
1688 Opc = PPC::EXTSW_32_64;
1690 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1693 // Unsigned 32-bit extensions use RLWINM.
1694 } else if (DestVT == MVT::i32) {
1696 if (SrcVT == MVT::i8)
1699 assert(SrcVT == MVT::i16 && "Unsigned extend from i32 to i32??");
1702 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::RLWINM),
1704 .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB).addImm(/*ME=*/31);
1706 // Unsigned 64-bit extensions use RLDICL (with a 32-bit source).
1709 if (SrcVT == MVT::i8)
1711 else if (SrcVT == MVT::i16)
1715 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1716 TII.get(PPC::RLDICL_32_64), DestReg)
1717 .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB);
1723 // Attempt to fast-select an indirect branch instruction.
1724 bool PPCFastISel::SelectIndirectBr(const Instruction *I) {
1725 unsigned AddrReg = getRegForValue(I->getOperand(0));
1729 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::MTCTR8))
1731 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCTR8));
1733 const IndirectBrInst *IB = cast<IndirectBrInst>(I);
1734 for (unsigned i = 0, e = IB->getNumSuccessors(); i != e; ++i)
1735 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[IB->getSuccessor(i)]);
1740 // Attempt to fast-select an integer truncate instruction.
1741 bool PPCFastISel::SelectTrunc(const Instruction *I) {
1742 Value *Src = I->getOperand(0);
1743 EVT SrcVT = TLI.getValueType(Src->getType(), true);
1744 EVT DestVT = TLI.getValueType(I->getType(), true);
1746 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16)
1749 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
1752 unsigned SrcReg = getRegForValue(Src);
1756 // The only interesting case is when we need to switch register classes.
1757 if (SrcVT == MVT::i64) {
1758 unsigned ResultReg = createResultReg(&PPC::GPRCRegClass);
1759 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1760 TII.get(TargetOpcode::COPY),
1761 ResultReg).addReg(SrcReg, 0, PPC::sub_32);
1765 updateValueMap(I, SrcReg);
1769 // Attempt to fast-select an integer extend instruction.
1770 bool PPCFastISel::SelectIntExt(const Instruction *I) {
1771 Type *DestTy = I->getType();
1772 Value *Src = I->getOperand(0);
1773 Type *SrcTy = Src->getType();
1775 bool IsZExt = isa<ZExtInst>(I);
1776 unsigned SrcReg = getRegForValue(Src);
1777 if (!SrcReg) return false;
1779 EVT SrcEVT, DestEVT;
1780 SrcEVT = TLI.getValueType(SrcTy, true);
1781 DestEVT = TLI.getValueType(DestTy, true);
1782 if (!SrcEVT.isSimple())
1784 if (!DestEVT.isSimple())
1787 MVT SrcVT = SrcEVT.getSimpleVT();
1788 MVT DestVT = DestEVT.getSimpleVT();
1790 // If we know the register class needed for the result of this
1791 // instruction, use it. Otherwise pick the register class of the
1792 // correct size that does not contain X0/R0, since we don't know
1793 // whether downstream uses permit that assignment.
1794 unsigned AssignedReg = FuncInfo.ValueMap[I];
1795 const TargetRegisterClass *RC =
1796 (AssignedReg ? MRI.getRegClass(AssignedReg) :
1797 (DestVT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
1798 &PPC::GPRC_and_GPRC_NOR0RegClass));
1799 unsigned ResultReg = createResultReg(RC);
1801 if (!PPCEmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, IsZExt))
1804 updateValueMap(I, ResultReg);
1808 // Attempt to fast-select an instruction that wasn't handled by
1809 // the table-generated machinery.
1810 bool PPCFastISel::fastSelectInstruction(const Instruction *I) {
1812 switch (I->getOpcode()) {
1813 case Instruction::Load:
1814 return SelectLoad(I);
1815 case Instruction::Store:
1816 return SelectStore(I);
1817 case Instruction::Br:
1818 return SelectBranch(I);
1819 case Instruction::IndirectBr:
1820 return SelectIndirectBr(I);
1821 case Instruction::FPExt:
1822 return SelectFPExt(I);
1823 case Instruction::FPTrunc:
1824 return SelectFPTrunc(I);
1825 case Instruction::SIToFP:
1826 return SelectIToFP(I, /*IsSigned*/ true);
1827 case Instruction::UIToFP:
1828 return SelectIToFP(I, /*IsSigned*/ false);
1829 case Instruction::FPToSI:
1830 return SelectFPToI(I, /*IsSigned*/ true);
1831 case Instruction::FPToUI:
1832 return SelectFPToI(I, /*IsSigned*/ false);
1833 case Instruction::Add:
1834 return SelectBinaryIntOp(I, ISD::ADD);
1835 case Instruction::Or:
1836 return SelectBinaryIntOp(I, ISD::OR);
1837 case Instruction::Sub:
1838 return SelectBinaryIntOp(I, ISD::SUB);
1839 case Instruction::Call:
1840 return selectCall(I);
1841 case Instruction::Ret:
1842 return SelectRet(I);
1843 case Instruction::Trunc:
1844 return SelectTrunc(I);
1845 case Instruction::ZExt:
1846 case Instruction::SExt:
1847 return SelectIntExt(I);
1848 // Here add other flavors of Instruction::XXX that automated
1849 // cases don't catch. For example, switches are terminators
1850 // that aren't yet handled.
1857 // Materialize a floating-point constant into a register, and return
1858 // the register number (or zero if we failed to handle it).
1859 unsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) {
1860 // No plans to handle long double here.
1861 if (VT != MVT::f32 && VT != MVT::f64)
1864 // All FP constants are loaded from the constant pool.
1865 unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
1866 assert(Align > 0 && "Unexpectedly missing alignment information!");
1867 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
1868 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
1869 CodeModel::Model CModel = TM.getCodeModel();
1871 MachineMemOperand *MMO =
1872 FuncInfo.MF->getMachineMemOperand(
1873 MachinePointerInfo::getConstantPool(), MachineMemOperand::MOLoad,
1874 (VT == MVT::f32) ? 4 : 8, Align);
1876 unsigned Opc = (VT == MVT::f32) ? PPC::LFS : PPC::LFD;
1877 unsigned TmpReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
1879 PPCFuncInfo->setUsesTOCBasePtr();
1880 // For small code model, generate a LF[SD](0, LDtocCPT(Idx, X2)).
1881 if (CModel == CodeModel::Small || CModel == CodeModel::JITDefault) {
1882 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocCPT),
1884 .addConstantPoolIndex(Idx).addReg(PPC::X2);
1885 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1886 .addImm(0).addReg(TmpReg).addMemOperand(MMO);
1888 // Otherwise we generate LF[SD](Idx[lo], ADDIStocHA(X2, Idx)).
1889 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA),
1890 TmpReg).addReg(PPC::X2).addConstantPoolIndex(Idx);
1891 // But for large code model, we must generate a LDtocL followed
1893 if (CModel == CodeModel::Large) {
1894 unsigned TmpReg2 = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
1895 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL),
1896 TmpReg2).addConstantPoolIndex(Idx).addReg(TmpReg);
1897 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1898 .addImm(0).addReg(TmpReg2);
1900 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1901 .addConstantPoolIndex(Idx, 0, PPCII::MO_TOC_LO)
1903 .addMemOperand(MMO);
1909 // Materialize the address of a global value into a register, and return
1910 // the register number (or zero if we failed to handle it).
1911 unsigned PPCFastISel::PPCMaterializeGV(const GlobalValue *GV, MVT VT) {
1912 assert(VT == MVT::i64 && "Non-address!");
1913 const TargetRegisterClass *RC = &PPC::G8RC_and_G8RC_NOX0RegClass;
1914 unsigned DestReg = createResultReg(RC);
1916 // Global values may be plain old object addresses, TLS object
1917 // addresses, constant pool entries, or jump tables. How we generate
1918 // code for these may depend on small, medium, or large code model.
1919 CodeModel::Model CModel = TM.getCodeModel();
1921 // FIXME: Jump tables are not yet required because fast-isel doesn't
1922 // handle switches; if that changes, we need them as well. For now,
1923 // what follows assumes everything's a generic (or TLS) global address.
1925 // FIXME: We don't yet handle the complexity of TLS.
1926 if (GV->isThreadLocal())
1929 PPCFuncInfo->setUsesTOCBasePtr();
1930 // For small code model, generate a simple TOC load.
1931 if (CModel == CodeModel::Small || CModel == CodeModel::JITDefault)
1932 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtoc),
1934 .addGlobalAddress(GV)
1937 // If the address is an externally defined symbol, a symbol with common
1938 // or externally available linkage, a non-local function address, or a
1939 // jump table address (not yet needed), or if we are generating code
1940 // for large code model, we generate:
1941 // LDtocL(GV, ADDIStocHA(%X2, GV))
1942 // Otherwise we generate:
1943 // ADDItocL(ADDIStocHA(%X2, GV), GV)
1944 // Either way, start with the ADDIStocHA:
1945 unsigned HighPartReg = createResultReg(RC);
1946 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA),
1947 HighPartReg).addReg(PPC::X2).addGlobalAddress(GV);
1949 // If/when switches are implemented, jump tables should be handled
1950 // on the "if" path here.
1951 if (CModel == CodeModel::Large ||
1952 (GV->getType()->getElementType()->isFunctionTy() &&
1953 (GV->isDeclaration() || GV->isWeakForLinker())) ||
1954 GV->isDeclaration() || GV->hasCommonLinkage() ||
1955 GV->hasAvailableExternallyLinkage())
1956 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL),
1957 DestReg).addGlobalAddress(GV).addReg(HighPartReg);
1959 // Otherwise generate the ADDItocL.
1960 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDItocL),
1961 DestReg).addReg(HighPartReg).addGlobalAddress(GV);
1967 // Materialize a 32-bit integer constant into a register, and return
1968 // the register number (or zero if we failed to handle it).
1969 unsigned PPCFastISel::PPCMaterialize32BitInt(int64_t Imm,
1970 const TargetRegisterClass *RC) {
1971 unsigned Lo = Imm & 0xFFFF;
1972 unsigned Hi = (Imm >> 16) & 0xFFFF;
1974 unsigned ResultReg = createResultReg(RC);
1975 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
1978 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1979 TII.get(IsGPRC ? PPC::LI : PPC::LI8), ResultReg)
1982 // Both Lo and Hi have nonzero bits.
1983 unsigned TmpReg = createResultReg(RC);
1984 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1985 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), TmpReg)
1987 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1988 TII.get(IsGPRC ? PPC::ORI : PPC::ORI8), ResultReg)
1989 .addReg(TmpReg).addImm(Lo);
1992 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1993 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), ResultReg)
1999 // Materialize a 64-bit integer constant into a register, and return
2000 // the register number (or zero if we failed to handle it).
2001 unsigned PPCFastISel::PPCMaterialize64BitInt(int64_t Imm,
2002 const TargetRegisterClass *RC) {
2003 unsigned Remainder = 0;
2006 // If the value doesn't fit in 32 bits, see if we can shift it
2007 // so that it fits in 32 bits.
2008 if (!isInt<32>(Imm)) {
2009 Shift = countTrailingZeros<uint64_t>(Imm);
2010 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
2012 if (isInt<32>(ImmSh))
2021 // Handle the high-order 32 bits (if shifted) or the whole 32 bits
2022 // (if not shifted).
2023 unsigned TmpReg1 = PPCMaterialize32BitInt(Imm, RC);
2027 // If upper 32 bits were not zero, we've built them and need to shift
2031 TmpReg2 = createResultReg(RC);
2032 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::RLDICR),
2033 TmpReg2).addReg(TmpReg1).addImm(Shift).addImm(63 - Shift);
2037 unsigned TmpReg3, Hi, Lo;
2038 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
2039 TmpReg3 = createResultReg(RC);
2040 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ORIS8),
2041 TmpReg3).addReg(TmpReg2).addImm(Hi);
2045 if ((Lo = Remainder & 0xFFFF)) {
2046 unsigned ResultReg = createResultReg(RC);
2047 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ORI8),
2048 ResultReg).addReg(TmpReg3).addImm(Lo);
2056 // Materialize an integer constant into a register, and return
2057 // the register number (or zero if we failed to handle it).
2058 unsigned PPCFastISel::PPCMaterializeInt(const Constant *C, MVT VT,
2060 // If we're using CR bit registers for i1 values, handle that as a special
2062 if (VT == MVT::i1 && PPCSubTarget->useCRBits()) {
2063 const ConstantInt *CI = cast<ConstantInt>(C);
2064 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass);
2065 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2066 TII.get(CI->isZero() ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2070 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 &&
2071 VT != MVT::i8 && VT != MVT::i1)
2074 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
2075 &PPC::GPRCRegClass);
2077 // If the constant is in range, use a load-immediate.
2078 const ConstantInt *CI = cast<ConstantInt>(C);
2079 if (isInt<16>(CI->getSExtValue())) {
2080 unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI;
2081 unsigned ImmReg = createResultReg(RC);
2082 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ImmReg)
2083 .addImm( (UseSExt) ? CI->getSExtValue() : CI->getZExtValue() );
2087 // Construct the constant piecewise.
2088 int64_t Imm = CI->getZExtValue();
2091 return PPCMaterialize64BitInt(Imm, RC);
2092 else if (VT == MVT::i32)
2093 return PPCMaterialize32BitInt(Imm, RC);
2098 // Materialize a constant into a register, and return the register
2099 // number (or zero if we failed to handle it).
2100 unsigned PPCFastISel::fastMaterializeConstant(const Constant *C) {
2101 EVT CEVT = TLI.getValueType(C->getType(), true);
2103 // Only handle simple types.
2104 if (!CEVT.isSimple()) return 0;
2105 MVT VT = CEVT.getSimpleVT();
2107 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
2108 return PPCMaterializeFP(CFP, VT);
2109 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
2110 return PPCMaterializeGV(GV, VT);
2111 else if (isa<ConstantInt>(C))
2112 return PPCMaterializeInt(C, VT, VT != MVT::i1);
2117 // Materialize the address created by an alloca into a register, and
2118 // return the register number (or zero if we failed to handle it).
2119 unsigned PPCFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
2120 // Don't handle dynamic allocas.
2121 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
2124 if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
2126 DenseMap<const AllocaInst*, int>::iterator SI =
2127 FuncInfo.StaticAllocaMap.find(AI);
2129 if (SI != FuncInfo.StaticAllocaMap.end()) {
2130 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
2131 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8),
2132 ResultReg).addFrameIndex(SI->second).addImm(0);
2139 // Fold loads into extends when possible.
2140 // FIXME: We can have multiple redundant extend/trunc instructions
2141 // following a load. The folding only picks up one. Extend this
2142 // to check subsequent instructions for the same pattern and remove
2143 // them. Thus ResultReg should be the def reg for the last redundant
2144 // instruction in a chain, and all intervening instructions can be
2145 // removed from parent. Change test/CodeGen/PowerPC/fast-isel-fold.ll
2146 // to add ELF64-NOT: rldicl to the appropriate tests when this works.
2147 bool PPCFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
2148 const LoadInst *LI) {
2149 // Verify we have a legal type before going any further.
2151 if (!isLoadTypeLegal(LI->getType(), VT))
2154 // Combine load followed by zero- or sign-extend.
2155 bool IsZExt = false;
2156 switch(MI->getOpcode()) {
2161 case PPC::RLDICL_32_64: {
2163 unsigned MB = MI->getOperand(3).getImm();
2164 if ((VT == MVT::i8 && MB <= 56) ||
2165 (VT == MVT::i16 && MB <= 48) ||
2166 (VT == MVT::i32 && MB <= 32))
2172 case PPC::RLWINM8: {
2174 unsigned MB = MI->getOperand(3).getImm();
2175 if ((VT == MVT::i8 && MB <= 24) ||
2176 (VT == MVT::i16 && MB <= 16))
2183 case PPC::EXTSB8_32_64:
2184 /* There is no sign-extending load-byte instruction. */
2189 case PPC::EXTSH8_32_64: {
2190 if (VT != MVT::i16 && VT != MVT::i8)
2196 case PPC::EXTSW_32_64: {
2197 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8)
2203 // See if we can handle this address.
2205 if (!PPCComputeAddress(LI->getOperand(0), Addr))
2208 unsigned ResultReg = MI->getOperand(0).getReg();
2210 if (!PPCEmitLoad(VT, ResultReg, Addr, nullptr, IsZExt))
2213 MI->eraseFromParent();
2217 // Attempt to lower call arguments in a faster way than done by
2218 // the selection DAG code.
2219 bool PPCFastISel::fastLowerArguments() {
2220 // Defer to normal argument lowering for now. It's reasonably
2221 // efficient. Consider doing something like ARM to handle the
2222 // case where all args fit in registers, no varargs, no float
2227 // Handle materializing integer constants into a register. This is not
2228 // automatically generated for PowerPC, so must be explicitly created here.
2229 unsigned PPCFastISel::fastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) {
2231 if (Opc != ISD::Constant)
2234 // If we're using CR bit registers for i1 values, handle that as a special
2236 if (VT == MVT::i1 && PPCSubTarget->useCRBits()) {
2237 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass);
2238 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2239 TII.get(Imm == 0 ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2243 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 &&
2244 VT != MVT::i8 && VT != MVT::i1)
2247 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
2248 &PPC::GPRCRegClass);
2250 return PPCMaterialize64BitInt(Imm, RC);
2252 return PPCMaterialize32BitInt(Imm, RC);
2255 // Override for ADDI and ADDI8 to set the correct register class
2256 // on RHS operand 0. The automatic infrastructure naively assumes
2257 // GPRC for i32 and G8RC for i64; the concept of "no R0" is lost
2258 // for these cases. At the moment, none of the other automatically
2259 // generated RI instructions require special treatment. However, once
2260 // SelectSelect is implemented, "isel" requires similar handling.
2262 // Also be conservative about the output register class. Avoid
2263 // assigning R0 or X0 to the output register for GPRC and G8RC
2264 // register classes, as any such result could be used in ADDI, etc.,
2265 // where those regs have another meaning.
2266 unsigned PPCFastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
2267 const TargetRegisterClass *RC,
2268 unsigned Op0, bool Op0IsKill,
2270 if (MachineInstOpcode == PPC::ADDI)
2271 MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass);
2272 else if (MachineInstOpcode == PPC::ADDI8)
2273 MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass);
2275 const TargetRegisterClass *UseRC =
2276 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2277 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2279 return FastISel::fastEmitInst_ri(MachineInstOpcode, UseRC,
2280 Op0, Op0IsKill, Imm);
2283 // Override for instructions with one register operand to avoid use of
2284 // R0/X0. The automatic infrastructure isn't aware of the context so
2285 // we must be conservative.
2286 unsigned PPCFastISel::fastEmitInst_r(unsigned MachineInstOpcode,
2287 const TargetRegisterClass* RC,
2288 unsigned Op0, bool Op0IsKill) {
2289 const TargetRegisterClass *UseRC =
2290 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2291 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2293 return FastISel::fastEmitInst_r(MachineInstOpcode, UseRC, Op0, Op0IsKill);
2296 // Override for instructions with two register operands to avoid use
2297 // of R0/X0. The automatic infrastructure isn't aware of the context
2298 // so we must be conservative.
2299 unsigned PPCFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
2300 const TargetRegisterClass* RC,
2301 unsigned Op0, bool Op0IsKill,
2302 unsigned Op1, bool Op1IsKill) {
2303 const TargetRegisterClass *UseRC =
2304 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2305 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2307 return FastISel::fastEmitInst_rr(MachineInstOpcode, UseRC, Op0, Op0IsKill,
2312 // Create the fast instruction selector for PowerPC64 ELF.
2313 FastISel *PPC::createFastISel(FunctionLoweringInfo &FuncInfo,
2314 const TargetLibraryInfo *LibInfo) {
2315 // Only available on 64-bit ELF for now.
2316 const PPCSubtarget &Subtarget = FuncInfo.MF->getSubtarget<PPCSubtarget>();
2317 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI())
2318 return new PPCFastISel(FuncInfo, LibInfo);