1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PPC implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCFrameLowering.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCInstrInfo.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCSubtarget.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineModuleInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/Target/TargetOptions.h"
30 /// VRRegNo - Map from a numbered VR register to its enum value.
32 static const uint16_t VRRegNo[] = {
33 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
34 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
35 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
36 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
39 PPCFrameLowering::PPCFrameLowering(const PPCSubtarget &STI)
40 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
41 (STI.hasQPX() || STI.isBGQ()) ? 32 : 16, 0),
44 // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
45 const PPCFrameLowering::SpillSlot *PPCFrameLowering::getCalleeSavedSpillSlots(
46 unsigned &NumEntries) const {
47 if (Subtarget.isDarwinABI()) {
49 if (Subtarget.isPPC64()) {
50 static const SpillSlot darwin64Offsets = {PPC::X31, -8};
51 return &darwin64Offsets;
53 static const SpillSlot darwinOffsets = {PPC::R31, -4};
54 return &darwinOffsets;
58 // Early exit if not using the SVR4 ABI.
59 if (!Subtarget.isSVR4ABI()) {
64 // Note that the offsets here overlap, but this is fixed up in
65 // processFunctionBeforeFrameFinalized.
67 static const SpillSlot Offsets[] = {
68 // Floating-point register save area offsets.
88 // General register save area offsets.
108 // CR save area offset. We map each of the nonvolatile CR fields
109 // to the slot for CR2, which is the first of the nonvolatile CR
110 // fields to be assigned, so that we only allocate one save slot.
111 // See PPCRegisterInfo::hasReservedSpillSlot() for more information.
114 // VRSAVE save area offset.
117 // Vector register save area
131 static const SpillSlot Offsets64[] = {
132 // Floating-point register save area offsets.
152 // General register save area offsets.
172 // VRSAVE save area offset.
175 // Vector register save area
189 if (Subtarget.isPPC64()) {
190 NumEntries = array_lengthof(Offsets64);
194 NumEntries = array_lengthof(Offsets);
200 /// RemoveVRSaveCode - We have found that this function does not need any code
201 /// to manipulate the VRSAVE register, even though it uses vector registers.
202 /// This can happen when the only registers used are known to be live in or out
203 /// of the function. Remove all of the VRSAVE related code from the function.
204 /// FIXME: The removal of the code results in a compile failure at -O0 when the
205 /// function contains a function call, as the GPR containing original VRSAVE
206 /// contents is spilled and reloaded around the call. Without the prolog code,
207 /// the spill instruction refers to an undefined register. This code needs
208 /// to account for all uses of that GPR.
209 static void RemoveVRSaveCode(MachineInstr *MI) {
210 MachineBasicBlock *Entry = MI->getParent();
211 MachineFunction *MF = Entry->getParent();
213 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
214 MachineBasicBlock::iterator MBBI = MI;
216 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
217 MBBI->eraseFromParent();
219 bool RemovedAllMTVRSAVEs = true;
220 // See if we can find and remove the MTVRSAVE instruction from all of the
222 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
223 // If last instruction is a return instruction, add an epilogue
224 if (!I->empty() && I->back().isReturn()) {
225 bool FoundIt = false;
226 for (MBBI = I->end(); MBBI != I->begin(); ) {
228 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
229 MBBI->eraseFromParent(); // remove it.
234 RemovedAllMTVRSAVEs &= FoundIt;
238 // If we found and removed all MTVRSAVE instructions, remove the read of
240 if (RemovedAllMTVRSAVEs) {
242 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
244 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
245 MBBI->eraseFromParent();
248 // Finally, nuke the UPDATE_VRSAVE.
249 MI->eraseFromParent();
252 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
253 // instruction selector. Based on the vector registers that have been used,
254 // transform this into the appropriate ORI instruction.
255 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
256 MachineFunction *MF = MI->getParent()->getParent();
257 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
258 DebugLoc dl = MI->getDebugLoc();
260 unsigned UsedRegMask = 0;
261 for (unsigned i = 0; i != 32; ++i)
262 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
263 UsedRegMask |= 1 << (31-i);
265 // Live in and live out values already must be in the mask, so don't bother
267 for (MachineRegisterInfo::livein_iterator
268 I = MF->getRegInfo().livein_begin(),
269 E = MF->getRegInfo().livein_end(); I != E; ++I) {
270 unsigned RegNo = TRI->getEncodingValue(I->first);
271 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
272 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
275 // Live out registers appear as use operands on return instructions.
276 for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end();
277 UsedRegMask != 0 && BI != BE; ++BI) {
278 const MachineBasicBlock &MBB = *BI;
279 if (MBB.empty() || !MBB.back().isReturn())
281 const MachineInstr &Ret = MBB.back();
282 for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) {
283 const MachineOperand &MO = Ret.getOperand(I);
284 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
286 unsigned RegNo = TRI->getEncodingValue(MO.getReg());
287 UsedRegMask &= ~(1 << (31-RegNo));
291 // If no registers are used, turn this into a copy.
292 if (UsedRegMask == 0) {
293 // Remove all VRSAVE code.
294 RemoveVRSaveCode(MI);
298 unsigned SrcReg = MI->getOperand(1).getReg();
299 unsigned DstReg = MI->getOperand(0).getReg();
301 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
302 if (DstReg != SrcReg)
303 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
305 .addImm(UsedRegMask);
307 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
308 .addReg(SrcReg, RegState::Kill)
309 .addImm(UsedRegMask);
310 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
311 if (DstReg != SrcReg)
312 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
314 .addImm(UsedRegMask >> 16);
316 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
317 .addReg(SrcReg, RegState::Kill)
318 .addImm(UsedRegMask >> 16);
320 if (DstReg != SrcReg)
321 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
323 .addImm(UsedRegMask >> 16);
325 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
326 .addReg(SrcReg, RegState::Kill)
327 .addImm(UsedRegMask >> 16);
329 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
330 .addReg(DstReg, RegState::Kill)
331 .addImm(UsedRegMask & 0xFFFF);
334 // Remove the old UPDATE_VRSAVE instruction.
335 MI->eraseFromParent();
338 static bool spillsCR(const MachineFunction &MF) {
339 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
340 return FuncInfo->isCRSpilled();
343 static bool spillsVRSAVE(const MachineFunction &MF) {
344 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
345 return FuncInfo->isVRSAVESpilled();
348 static bool hasSpills(const MachineFunction &MF) {
349 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
350 return FuncInfo->hasSpills();
353 static bool hasNonRISpills(const MachineFunction &MF) {
354 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
355 return FuncInfo->hasNonRISpills();
358 /// determineFrameLayout - Determine the size of the frame and maximum call
360 unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF,
362 bool UseEstimate) const {
363 MachineFrameInfo *MFI = MF.getFrameInfo();
365 // Get the number of bytes to allocate from the FrameInfo
367 UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize();
369 // Get stack alignments. The frame must be aligned to the greatest of these:
370 unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI
371 unsigned MaxAlign = MFI->getMaxAlignment(); // algmt required by data in frame
372 unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1;
374 const PPCRegisterInfo *RegInfo =
375 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
377 // If we are a leaf function, and use up to 224 bytes of stack space,
378 // don't have a frame pointer, calls, or dynamic alloca then we do not need
379 // to adjust the stack pointer (we fit in the Red Zone).
380 // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate
381 // stackless code if all local vars are reg-allocated.
382 bool DisableRedZone = MF.getFunction()->getAttributes().
383 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoRedZone);
384 if (!DisableRedZone &&
385 (Subtarget.isPPC64() || // 32-bit SVR4, no stack-
386 !Subtarget.isSVR4ABI() || // allocated locals.
388 FrameSize <= 224 && // Fits in red zone.
389 !MFI->hasVarSizedObjects() && // No dynamic alloca.
390 !MFI->adjustsStack() && // No calls.
391 !RegInfo->hasBasePointer(MF)) { // No special alignment.
394 MFI->setStackSize(0);
398 // Get the maximum call frame size of all the calls.
399 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
401 // Maximum call frame needs to be at least big enough for linkage area.
402 unsigned minCallFrameSize = getLinkageSize(Subtarget.isPPC64(),
403 Subtarget.isDarwinABI());
404 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
406 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
407 // that allocations will be aligned.
408 if (MFI->hasVarSizedObjects())
409 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
411 // Update maximum call frame size.
413 MFI->setMaxCallFrameSize(maxCallFrameSize);
415 // Include call frame size in total.
416 FrameSize += maxCallFrameSize;
418 // Make sure the frame is aligned.
419 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
421 // Update frame info.
423 MFI->setStackSize(FrameSize);
428 // hasFP - Return true if the specified function actually has a dedicated frame
430 bool PPCFrameLowering::hasFP(const MachineFunction &MF) const {
431 const MachineFrameInfo *MFI = MF.getFrameInfo();
432 // FIXME: This is pretty much broken by design: hasFP() might be called really
433 // early, before the stack layout was calculated and thus hasFP() might return
434 // true or false here depending on the time of call.
435 return (MFI->getStackSize()) && needsFP(MF);
438 // needsFP - Return true if the specified function should have a dedicated frame
439 // pointer register. This is true if the function has variable sized allocas or
440 // if frame pointer elimination is disabled.
441 bool PPCFrameLowering::needsFP(const MachineFunction &MF) const {
442 const MachineFrameInfo *MFI = MF.getFrameInfo();
444 // Naked functions have no stack frame pushed, so we don't have a frame
446 if (MF.getFunction()->getAttributes().hasAttribute(
447 AttributeSet::FunctionIndex, Attribute::Naked))
450 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
451 MFI->hasVarSizedObjects() ||
452 (MF.getTarget().Options.GuaranteedTailCallOpt &&
453 MF.getInfo<PPCFunctionInfo>()->hasFastCall());
456 void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const {
457 bool is31 = needsFP(MF);
458 unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
459 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
461 const PPCRegisterInfo *RegInfo =
462 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
463 bool HasBP = RegInfo->hasBasePointer(MF);
464 unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg;
465 unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg;
467 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
469 for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) {
471 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
472 MachineOperand &MO = MBBI->getOperand(I);
476 switch (MO.getReg()) {
495 void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
496 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
497 MachineBasicBlock::iterator MBBI = MBB.begin();
498 MachineFrameInfo *MFI = MF.getFrameInfo();
499 const PPCInstrInfo &TII =
500 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
501 const PPCRegisterInfo *RegInfo =
502 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
504 MachineModuleInfo &MMI = MF.getMMI();
505 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
507 bool needsFrameMoves = MMI.hasDebugInfo() ||
508 MF.getFunction()->needsUnwindTableEntry();
509 bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
511 // Get processor type.
512 bool isPPC64 = Subtarget.isPPC64();
514 bool isDarwinABI = Subtarget.isDarwinABI();
515 bool isSVR4ABI = Subtarget.isSVR4ABI();
516 assert((isDarwinABI || isSVR4ABI) &&
517 "Currently only Darwin and SVR4 ABIs are supported for PowerPC.");
519 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
522 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
523 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
524 HandleVRSaveUpdate(MBBI, TII);
529 // Move MBBI back to the beginning of the function.
532 // Work out frame sizes.
533 unsigned FrameSize = determineFrameLayout(MF);
534 int NegFrameSize = -FrameSize;
535 if (!isInt<32>(NegFrameSize))
536 llvm_unreachable("Unhandled stack size!");
538 if (MFI->isFrameAddressTaken())
539 replaceFPWithRealFP(MF);
541 // Check if the link register (LR) must be saved.
542 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
543 bool MustSaveLR = FI->mustSaveLR();
544 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
545 // Do we have a frame pointer and/or base pointer for this function?
546 bool HasFP = hasFP(MF);
547 bool HasBP = RegInfo->hasBasePointer(MF);
549 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
550 unsigned BPReg = RegInfo->getBaseRegister(MF);
551 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
552 unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR;
553 unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0;
554 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
555 // ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.)
556 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8
558 const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD
560 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU
562 const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX
564 const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8
566 const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8
568 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
570 const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8
572 const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8
575 // Regarding this assert: Even though LR is saved in the caller's frame (i.e.,
576 // LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no
577 // Red Zone, an asynchronous event (a form of "callee") could claim a frame &
578 // overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR.
579 assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) &&
580 "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
582 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
587 MachineFrameInfo *FFI = MF.getFrameInfo();
588 int FPIndex = FI->getFramePointerSaveIndex();
589 assert(FPIndex && "No Frame Pointer Save Slot!");
590 FPOffset = FFI->getObjectOffset(FPIndex);
593 PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
600 MachineFrameInfo *FFI = MF.getFrameInfo();
601 int BPIndex = FI->getBasePointerSaveIndex();
602 assert(BPIndex && "No Base Pointer Save Slot!");
603 BPOffset = FFI->getObjectOffset(BPIndex);
606 PPCFrameLowering::getBasePointerSaveOffset(isPPC64,
612 // Get stack alignments.
613 unsigned MaxAlign = MFI->getMaxAlignment();
614 if (HasBP && MaxAlign > 1)
615 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
616 "Invalid alignment!");
618 // Frames of 32KB & larger require special handling because they cannot be
619 // indexed into with a simple STDU/STWU/STD/STW immediate offset operand.
620 bool isLargeFrame = !isInt<16>(NegFrameSize);
623 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
625 assert((isPPC64 || MustSaveCRs.empty()) &&
626 "Prologue CR saving supported only in 64-bit mode");
628 if (!MustSaveCRs.empty()) { // will only occur for PPC64
629 MachineInstrBuilder MIB =
630 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg);
631 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
632 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill);
636 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
637 BuildMI(MBB, MBBI, dl, StoreInst)
643 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
644 BuildMI(MBB, MBBI, dl, StoreInst)
650 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
651 BuildMI(MBB, MBBI, dl, StoreInst)
656 if (!MustSaveCRs.empty()) // will only occur for PPC64
657 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
658 .addReg(TempReg, getKillRegState(true))
662 // Skip the rest if this is a leaf function & all spills fit in the Red Zone.
663 if (!FrameSize) return;
665 // Adjust stack pointer: r1 += NegFrameSize.
666 // If there is a preferred stack alignment, align R1 now
669 // Save a copy of r1 as the base pointer.
670 BuildMI(MBB, MBBI, dl, OrInst, BPReg)
675 if (HasBP && MaxAlign > 1) {
677 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)
680 .addImm(64 - Log2_32(MaxAlign));
682 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)
685 .addImm(32 - Log2_32(MaxAlign))
688 BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg)
689 .addReg(ScratchReg, RegState::Kill)
690 .addImm(NegFrameSize);
692 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg)
693 .addImm(NegFrameSize >> 16);
694 BuildMI(MBB, MBBI, dl, OrImmInst, TempReg)
695 .addReg(TempReg, RegState::Kill)
696 .addImm(NegFrameSize & 0xFFFF);
697 BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg)
698 .addReg(ScratchReg, RegState::Kill)
699 .addReg(TempReg, RegState::Kill);
701 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
702 .addReg(SPReg, RegState::Kill)
706 } else if (!isLargeFrame) {
707 BuildMI(MBB, MBBI, dl, StoreUpdtInst, SPReg)
709 .addImm(NegFrameSize)
713 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
714 .addImm(NegFrameSize >> 16);
715 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
716 .addReg(ScratchReg, RegState::Kill)
717 .addImm(NegFrameSize & 0xFFFF);
718 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
719 .addReg(SPReg, RegState::Kill)
724 // Add the "machine moves" for the instructions we generated above, but in
726 if (needsFrameMoves) {
727 // Show update of SP.
728 assert(NegFrameSize);
729 unsigned CFIIndex = MMI.addFrameInst(
730 MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize));
731 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
732 .addCFIIndex(CFIIndex);
735 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
736 CFIIndex = MMI.addFrameInst(
737 MCCFIInstruction::createOffset(nullptr, Reg, FPOffset));
738 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
739 .addCFIIndex(CFIIndex);
743 unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
744 CFIIndex = MMI.addFrameInst(
745 MCCFIInstruction::createOffset(nullptr, Reg, BPOffset));
746 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
747 .addCFIIndex(CFIIndex);
751 unsigned Reg = MRI->getDwarfRegNum(LRReg, true);
752 CFIIndex = MMI.addFrameInst(
753 MCCFIInstruction::createOffset(nullptr, Reg, LROffset));
754 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
755 .addCFIIndex(CFIIndex);
759 // If there is a frame pointer, copy R1 into R31
761 BuildMI(MBB, MBBI, dl, OrInst, FPReg)
765 if (needsFrameMoves) {
766 // Mark effective beginning of when frame pointer is ready.
767 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
768 unsigned CFIIndex = MMI.addFrameInst(
769 MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
771 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
772 .addCFIIndex(CFIIndex);
776 if (needsFrameMoves) {
777 // Add callee saved registers to move list.
778 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
779 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
780 unsigned Reg = CSI[I].getReg();
781 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
783 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
784 // subregisters of CR2. We just need to emit a move of CR2.
785 if (PPC::CRBITRCRegClass.contains(Reg))
788 // For SVR4, don't emit a move for the CR spill slot if we haven't
790 if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
791 && MustSaveCRs.empty())
794 // For 64-bit SVR4 when we have spilled CRs, the spill location
795 // is SP+8, not a frame-relative slot.
796 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
797 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
798 nullptr, MRI->getDwarfRegNum(PPC::CR2, true), 8));
799 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
800 .addCFIIndex(CFIIndex);
804 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
805 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
806 nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
807 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
808 .addCFIIndex(CFIIndex);
813 void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
814 MachineBasicBlock &MBB) const {
815 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
816 assert(MBBI != MBB.end() && "Returning block has no terminator");
817 const PPCInstrInfo &TII =
818 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
819 const PPCRegisterInfo *RegInfo =
820 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
822 unsigned RetOpcode = MBBI->getOpcode();
825 assert((RetOpcode == PPC::BLR ||
826 RetOpcode == PPC::TCRETURNri ||
827 RetOpcode == PPC::TCRETURNdi ||
828 RetOpcode == PPC::TCRETURNai ||
829 RetOpcode == PPC::TCRETURNri8 ||
830 RetOpcode == PPC::TCRETURNdi8 ||
831 RetOpcode == PPC::TCRETURNai8) &&
832 "Can only insert epilog into returning blocks");
834 // Get alignment info so we know how to restore the SP.
835 const MachineFrameInfo *MFI = MF.getFrameInfo();
837 // Get the number of bytes allocated from the FrameInfo.
838 int FrameSize = MFI->getStackSize();
840 // Get processor type.
841 bool isPPC64 = Subtarget.isPPC64();
843 bool isDarwinABI = Subtarget.isDarwinABI();
844 bool isSVR4ABI = Subtarget.isSVR4ABI();
845 bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
847 // Check if the link register (LR) has been saved.
848 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
849 bool MustSaveLR = FI->mustSaveLR();
850 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
851 // Do we have a frame pointer and/or base pointer for this function?
852 bool HasFP = hasFP(MF);
853 bool HasBP = RegInfo->hasBasePointer(MF);
855 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
856 unsigned BPReg = RegInfo->getBaseRegister(MF);
857 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
858 unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0;
859 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
860 const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8
862 const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD
864 const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8
866 const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8
868 const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8
870 const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8
873 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
878 MachineFrameInfo *FFI = MF.getFrameInfo();
879 int FPIndex = FI->getFramePointerSaveIndex();
880 assert(FPIndex && "No Frame Pointer Save Slot!");
881 FPOffset = FFI->getObjectOffset(FPIndex);
884 PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
891 MachineFrameInfo *FFI = MF.getFrameInfo();
892 int BPIndex = FI->getBasePointerSaveIndex();
893 assert(BPIndex && "No Base Pointer Save Slot!");
894 BPOffset = FFI->getObjectOffset(BPIndex);
897 PPCFrameLowering::getBasePointerSaveOffset(isPPC64,
903 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
904 RetOpcode == PPC::TCRETURNdi ||
905 RetOpcode == PPC::TCRETURNai ||
906 RetOpcode == PPC::TCRETURNri8 ||
907 RetOpcode == PPC::TCRETURNdi8 ||
908 RetOpcode == PPC::TCRETURNai8;
911 int MaxTCRetDelta = FI->getTailCallSPDelta();
912 MachineOperand &StackAdjust = MBBI->getOperand(1);
913 assert(StackAdjust.isImm() && "Expecting immediate value.");
914 // Adjust stack pointer.
915 int StackAdj = StackAdjust.getImm();
916 int Delta = StackAdj - MaxTCRetDelta;
917 assert((Delta >= 0) && "Delta must be positive");
919 FrameSize += (StackAdj +Delta);
921 FrameSize += StackAdj;
924 // Frames of 32KB & larger require special handling because they cannot be
925 // indexed into with a simple LD/LWZ immediate offset operand.
926 bool isLargeFrame = !isInt<16>(FrameSize);
929 // In the prologue, the loaded (or persistent) stack pointer value is offset
930 // by the STDU/STDUX/STWU/STWUX instruction. Add this offset back now.
932 // If this function contained a fastcc call and GuaranteedTailCallOpt is
933 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
934 // call which invalidates the stack pointer value in SP(0). So we use the
935 // value of R31 in this case.
936 if (FI->hasFastCall()) {
937 assert(HasFP && "Expecting a valid frame pointer.");
939 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
940 .addReg(FPReg).addImm(FrameSize);
942 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
943 .addImm(FrameSize >> 16);
944 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
945 .addReg(ScratchReg, RegState::Kill)
946 .addImm(FrameSize & 0xFFFF);
947 BuildMI(MBB, MBBI, dl, AddInst)
952 } else if (!isLargeFrame && !HasBP && !MFI->hasVarSizedObjects()) {
953 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
957 BuildMI(MBB, MBBI, dl, LoadInst, SPReg)
965 BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
969 assert((isPPC64 || MustSaveCRs.empty()) &&
970 "Epilogue CR restoring supported only in 64-bit mode");
972 if (!MustSaveCRs.empty()) // will only occur for PPC64
973 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
978 BuildMI(MBB, MBBI, dl, LoadInst, FPReg)
983 BuildMI(MBB, MBBI, dl, LoadInst, BPReg)
987 if (!MustSaveCRs.empty()) // will only occur for PPC64
988 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
989 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
990 .addReg(TempReg, getKillRegState(i == e-1));
993 BuildMI(MBB, MBBI, dl, MTLRInst).addReg(ScratchReg);
995 // Callee pop calling convention. Pop parameter/linkage area. Used for tail
997 if (MF.getTarget().Options.GuaranteedTailCallOpt && RetOpcode == PPC::BLR &&
998 MF.getFunction()->getCallingConv() == CallingConv::Fast) {
999 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1000 unsigned CallerAllocatedAmt = FI->getMinReservedArea();
1002 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
1003 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1004 .addReg(SPReg).addImm(CallerAllocatedAmt);
1006 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1007 .addImm(CallerAllocatedAmt >> 16);
1008 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1009 .addReg(ScratchReg, RegState::Kill)
1010 .addImm(CallerAllocatedAmt & 0xFFFF);
1011 BuildMI(MBB, MBBI, dl, AddInst)
1014 .addReg(ScratchReg);
1016 } else if (RetOpcode == PPC::TCRETURNdi) {
1017 MBBI = MBB.getLastNonDebugInstr();
1018 MachineOperand &JumpTarget = MBBI->getOperand(0);
1019 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
1020 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1021 } else if (RetOpcode == PPC::TCRETURNri) {
1022 MBBI = MBB.getLastNonDebugInstr();
1023 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1024 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
1025 } else if (RetOpcode == PPC::TCRETURNai) {
1026 MBBI = MBB.getLastNonDebugInstr();
1027 MachineOperand &JumpTarget = MBBI->getOperand(0);
1028 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
1029 } else if (RetOpcode == PPC::TCRETURNdi8) {
1030 MBBI = MBB.getLastNonDebugInstr();
1031 MachineOperand &JumpTarget = MBBI->getOperand(0);
1032 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
1033 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1034 } else if (RetOpcode == PPC::TCRETURNri8) {
1035 MBBI = MBB.getLastNonDebugInstr();
1036 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1037 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
1038 } else if (RetOpcode == PPC::TCRETURNai8) {
1039 MBBI = MBB.getLastNonDebugInstr();
1040 MachineOperand &JumpTarget = MBBI->getOperand(0);
1041 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
1045 /// MustSaveLR - Return true if this function requires that we save the LR
1046 /// register onto the stack in the prolog and restore it in the epilog of the
1048 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
1049 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
1051 // We need a save/restore of LR if there is any def of LR (which is
1052 // defined by calls, including the PIC setup sequence), or if there is
1053 // some use of the LR stack slot (e.g. for builtin_return_address).
1054 // (LR comes in 32 and 64 bit versions.)
1055 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
1056 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
1060 PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1061 RegScavenger *) const {
1062 const PPCRegisterInfo *RegInfo =
1063 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
1065 // Save and clear the LR state.
1066 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1067 unsigned LR = RegInfo->getRARegister();
1068 FI->setMustSaveLR(MustSaveLR(MF, LR));
1069 MachineRegisterInfo &MRI = MF.getRegInfo();
1070 MRI.setPhysRegUnused(LR);
1072 // Save R31 if necessary
1073 int FPSI = FI->getFramePointerSaveIndex();
1074 bool isPPC64 = Subtarget.isPPC64();
1075 bool isDarwinABI = Subtarget.isDarwinABI();
1076 bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
1077 MachineFrameInfo *MFI = MF.getFrameInfo();
1079 // If the frame pointer save index hasn't been defined yet.
1080 if (!FPSI && needsFP(MF)) {
1081 // Find out what the fix offset of the frame pointer save area.
1082 int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI);
1083 // Allocate the frame index for frame pointer save area.
1084 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
1086 FI->setFramePointerSaveIndex(FPSI);
1089 int BPSI = FI->getBasePointerSaveIndex();
1090 if (!BPSI && RegInfo->hasBasePointer(MF)) {
1091 int BPOffset = getBasePointerSaveOffset(isPPC64, isDarwinABI, isPIC);
1092 // Allocate the frame index for the base pointer save area.
1093 BPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, BPOffset, true);
1095 FI->setBasePointerSaveIndex(BPSI);
1098 // Reserve stack space to move the linkage area to in case of a tail call.
1100 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1101 (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
1102 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
1105 // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
1106 // function uses CR 2, 3, or 4.
1107 if (!isPPC64 && !isDarwinABI &&
1108 (MRI.isPhysRegUsed(PPC::CR2) ||
1109 MRI.isPhysRegUsed(PPC::CR3) ||
1110 MRI.isPhysRegUsed(PPC::CR4))) {
1111 int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true);
1112 FI->setCRSpillFrameIndex(FrameIdx);
1116 void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
1117 RegScavenger *RS) const {
1118 // Early exit if not using the SVR4 ABI.
1119 if (!Subtarget.isSVR4ABI()) {
1120 addScavengingSpillSlot(MF, RS);
1124 // Get callee saved register information.
1125 MachineFrameInfo *FFI = MF.getFrameInfo();
1126 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
1128 // Early exit if no callee saved registers are modified!
1129 if (CSI.empty() && !needsFP(MF)) {
1130 addScavengingSpillSlot(MF, RS);
1134 unsigned MinGPR = PPC::R31;
1135 unsigned MinG8R = PPC::X31;
1136 unsigned MinFPR = PPC::F31;
1137 unsigned MinVR = PPC::V31;
1139 bool HasGPSaveArea = false;
1140 bool HasG8SaveArea = false;
1141 bool HasFPSaveArea = false;
1142 bool HasVRSAVESaveArea = false;
1143 bool HasVRSaveArea = false;
1145 SmallVector<CalleeSavedInfo, 18> GPRegs;
1146 SmallVector<CalleeSavedInfo, 18> G8Regs;
1147 SmallVector<CalleeSavedInfo, 18> FPRegs;
1148 SmallVector<CalleeSavedInfo, 18> VRegs;
1150 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1151 unsigned Reg = CSI[i].getReg();
1152 if (PPC::GPRCRegClass.contains(Reg)) {
1153 HasGPSaveArea = true;
1155 GPRegs.push_back(CSI[i]);
1160 } else if (PPC::G8RCRegClass.contains(Reg)) {
1161 HasG8SaveArea = true;
1163 G8Regs.push_back(CSI[i]);
1168 } else if (PPC::F8RCRegClass.contains(Reg)) {
1169 HasFPSaveArea = true;
1171 FPRegs.push_back(CSI[i]);
1176 } else if (PPC::CRBITRCRegClass.contains(Reg) ||
1177 PPC::CRRCRegClass.contains(Reg)) {
1178 ; // do nothing, as we already know whether CRs are spilled
1179 } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1180 HasVRSAVESaveArea = true;
1181 } else if (PPC::VRRCRegClass.contains(Reg)) {
1182 HasVRSaveArea = true;
1184 VRegs.push_back(CSI[i]);
1190 llvm_unreachable("Unknown RegisterClass!");
1194 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>();
1195 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
1197 int64_t LowerBound = 0;
1199 // Take into account stack space reserved for tail calls.
1201 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1202 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
1203 LowerBound = TCSPDelta;
1206 // The Floating-point register save area is right below the back chain word
1207 // of the previous stack frame.
1208 if (HasFPSaveArea) {
1209 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
1210 int FI = FPRegs[i].getFrameIdx();
1212 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1215 LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8;
1218 // Check whether the frame pointer register is allocated. If so, make sure it
1219 // is spilled to the correct offset.
1221 HasGPSaveArea = true;
1223 int FI = PFI->getFramePointerSaveIndex();
1224 assert(FI && "No Frame Pointer Save Slot!");
1226 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1229 const PPCRegisterInfo *RegInfo =
1230 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
1231 if (RegInfo->hasBasePointer(MF)) {
1232 HasGPSaveArea = true;
1234 int FI = PFI->getBasePointerSaveIndex();
1235 assert(FI && "No Base Pointer Save Slot!");
1237 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1240 // General register save area starts right below the Floating-point
1241 // register save area.
1242 if (HasGPSaveArea || HasG8SaveArea) {
1243 // Move general register save area spill slots down, taking into account
1244 // the size of the Floating-point register save area.
1245 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
1246 int FI = GPRegs[i].getFrameIdx();
1248 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1251 // Move general register save area spill slots down, taking into account
1252 // the size of the Floating-point register save area.
1253 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
1254 int FI = G8Regs[i].getFrameIdx();
1256 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1260 std::min<unsigned>(TRI->getEncodingValue(MinGPR),
1261 TRI->getEncodingValue(MinG8R));
1263 if (Subtarget.isPPC64()) {
1264 LowerBound -= (31 - MinReg + 1) * 8;
1266 LowerBound -= (31 - MinReg + 1) * 4;
1270 // For 32-bit only, the CR save area is below the general register
1271 // save area. For 64-bit SVR4, the CR save area is addressed relative
1272 // to the stack pointer and hence does not need an adjustment here.
1273 // Only CR2 (the first nonvolatile spilled) has an associated frame
1274 // index so that we have a single uniform save area.
1275 if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) {
1276 // Adjust the frame index of the CR spill slot.
1277 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1278 unsigned Reg = CSI[i].getReg();
1280 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
1281 // Leave Darwin logic as-is.
1282 || (!Subtarget.isSVR4ABI() &&
1283 (PPC::CRBITRCRegClass.contains(Reg) ||
1284 PPC::CRRCRegClass.contains(Reg)))) {
1285 int FI = CSI[i].getFrameIdx();
1287 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1291 LowerBound -= 4; // The CR save area is always 4 bytes long.
1294 if (HasVRSAVESaveArea) {
1295 // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1296 // which have the VRSAVE register class?
1297 // Adjust the frame index of the VRSAVE spill slot.
1298 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1299 unsigned Reg = CSI[i].getReg();
1301 if (PPC::VRSAVERCRegClass.contains(Reg)) {
1302 int FI = CSI[i].getFrameIdx();
1304 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1308 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
1311 if (HasVRSaveArea) {
1312 // Insert alignment padding, we need 16-byte alignment.
1313 LowerBound = (LowerBound - 15) & ~(15);
1315 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
1316 int FI = VRegs[i].getFrameIdx();
1318 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1322 addScavengingSpillSlot(MF, RS);
1326 PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
1327 RegScavenger *RS) const {
1328 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
1329 // a large stack, which will require scavenging a register to materialize a
1332 // We need to have a scavenger spill slot for spills if the frame size is
1333 // large. In case there is no free register for large-offset addressing,
1334 // this slot is used for the necessary emergency spill. Also, we need the
1335 // slot for dynamic stack allocations.
1337 // The scavenger might be invoked if the frame offset does not fit into
1338 // the 16-bit immediate. We don't know the complete frame size here
1339 // because we've not yet computed callee-saved register spills or the
1340 // needed alignment padding.
1341 unsigned StackSize = determineFrameLayout(MF, false, true);
1342 MachineFrameInfo *MFI = MF.getFrameInfo();
1343 if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) ||
1344 hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) {
1345 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1346 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1347 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
1348 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1352 // Might we have over-aligned allocas?
1353 bool HasAlVars = MFI->hasVarSizedObjects() &&
1354 MFI->getMaxAlignment() > getStackAlignment();
1356 // These kinds of spills might need two registers.
1357 if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars)
1358 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1366 PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1367 MachineBasicBlock::iterator MI,
1368 const std::vector<CalleeSavedInfo> &CSI,
1369 const TargetRegisterInfo *TRI) const {
1371 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1372 // Return false otherwise to maintain pre-existing behavior.
1373 if (!Subtarget.isSVR4ABI())
1376 MachineFunction *MF = MBB.getParent();
1377 const PPCInstrInfo &TII =
1378 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1380 bool CRSpilled = false;
1381 MachineInstrBuilder CRMIB;
1383 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1384 unsigned Reg = CSI[i].getReg();
1385 // Only Darwin actually uses the VRSAVE register, but it can still appear
1386 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1387 // Darwin, ignore it.
1388 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1391 // CR2 through CR4 are the nonvolatile CR fields.
1392 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
1394 // Add the callee-saved register as live-in; it's killed at the spill.
1397 if (CRSpilled && IsCRField) {
1398 CRMIB.addReg(Reg, RegState::ImplicitKill);
1402 // Insert the spill to the stack frame.
1404 PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
1405 if (Subtarget.isPPC64()) {
1406 // The actual spill will happen at the start of the prologue.
1407 FuncInfo->addMustSaveCR(Reg);
1410 FuncInfo->setSpillsCR();
1412 // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have
1413 // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
1414 CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
1415 .addReg(Reg, RegState::ImplicitKill);
1417 MBB.insert(MI, CRMIB);
1418 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
1420 getKillRegState(true)),
1421 CSI[i].getFrameIdx()));
1424 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1425 TII.storeRegToStackSlot(MBB, MI, Reg, true,
1426 CSI[i].getFrameIdx(), RC, TRI);
1433 restoreCRs(bool isPPC64, bool is31,
1434 bool CR2Spilled, bool CR3Spilled, bool CR4Spilled,
1435 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1436 const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
1438 MachineFunction *MF = MBB.getParent();
1439 const PPCInstrInfo &TII =
1440 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1442 unsigned RestoreOp, MoveReg;
1445 // This is handled during epilogue generation.
1448 // 32-bit: FP-relative
1449 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
1451 CSI[CSIIndex].getFrameIdx()));
1452 RestoreOp = PPC::MTOCRF;
1457 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
1458 .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled)));
1461 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
1462 .addReg(MoveReg, getKillRegState(!CR4Spilled)));
1465 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
1466 .addReg(MoveReg, getKillRegState(true)));
1469 void PPCFrameLowering::
1470 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1471 MachineBasicBlock::iterator I) const {
1472 const PPCInstrInfo &TII =
1473 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
1474 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1475 I->getOpcode() == PPC::ADJCALLSTACKUP) {
1476 // Add (actually subtract) back the amount the callee popped on return.
1477 if (int CalleeAmt = I->getOperand(1).getImm()) {
1478 bool is64Bit = Subtarget.isPPC64();
1480 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
1481 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
1482 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
1483 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
1484 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
1485 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
1486 MachineInstr *MI = I;
1487 DebugLoc dl = MI->getDebugLoc();
1489 if (isInt<16>(CalleeAmt)) {
1490 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
1491 .addReg(StackReg, RegState::Kill)
1494 MachineBasicBlock::iterator MBBI = I;
1495 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
1496 .addImm(CalleeAmt >> 16);
1497 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
1498 .addReg(TmpReg, RegState::Kill)
1499 .addImm(CalleeAmt & 0xFFFF);
1500 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
1501 .addReg(StackReg, RegState::Kill)
1506 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
1511 PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1512 MachineBasicBlock::iterator MI,
1513 const std::vector<CalleeSavedInfo> &CSI,
1514 const TargetRegisterInfo *TRI) const {
1516 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1517 // Return false otherwise to maintain pre-existing behavior.
1518 if (!Subtarget.isSVR4ABI())
1521 MachineFunction *MF = MBB.getParent();
1522 const PPCInstrInfo &TII =
1523 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1524 bool CR2Spilled = false;
1525 bool CR3Spilled = false;
1526 bool CR4Spilled = false;
1527 unsigned CSIIndex = 0;
1529 // Initialize insertion-point logic; we will be restoring in reverse
1531 MachineBasicBlock::iterator I = MI, BeforeI = I;
1532 bool AtStart = I == MBB.begin();
1537 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1538 unsigned Reg = CSI[i].getReg();
1540 // Only Darwin actually uses the VRSAVE register, but it can still appear
1541 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1542 // Darwin, ignore it.
1543 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1546 if (Reg == PPC::CR2) {
1548 // The spill slot is associated only with CR2, which is the
1549 // first nonvolatile spilled. Save it here.
1552 } else if (Reg == PPC::CR3) {
1555 } else if (Reg == PPC::CR4) {
1559 // When we first encounter a non-CR register after seeing at
1560 // least one CR register, restore all spilled CRs together.
1561 if ((CR2Spilled || CR3Spilled || CR4Spilled)
1562 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1563 bool is31 = needsFP(*MF);
1564 restoreCRs(Subtarget.isPPC64(), is31,
1565 CR2Spilled, CR3Spilled, CR4Spilled,
1566 MBB, I, CSI, CSIIndex);
1567 CR2Spilled = CR3Spilled = CR4Spilled = false;
1570 // Default behavior for non-CR saves.
1571 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1572 TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(),
1574 assert(I != MBB.begin() &&
1575 "loadRegFromStackSlot didn't insert any code!");
1578 // Insert in reverse order.
1587 // If we haven't yet spilled the CRs, do so now.
1588 if (CR2Spilled || CR3Spilled || CR4Spilled) {
1589 bool is31 = needsFP(*MF);
1590 restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled,
1591 MBB, I, CSI, CSIIndex);