1 //=====- PPCFrameLowering.cpp - PPC Frame Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PPC implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCFrameLowering.h"
15 #include "PPCInstrInfo.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "llvm/Function.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/Target/TargetOptions.h"
28 // FIXME This disables some code that aligns the stack to a boundary bigger than
29 // the default (16 bytes on Darwin) when there is a stack local of greater
30 // alignment. This does not currently work, because the delta between old and
31 // new stack pointers is added to offsets that reference incoming parameters
32 // after the prolog is generated, and the code that does that doesn't handle a
33 // variable delta. You don't want to do that anyway; a better approach is to
34 // reserve another register that retains to the incoming stack pointer, and
35 // reference parameters relative to that.
39 /// VRRegNo - Map from a numbered VR register to its enum value.
41 static const unsigned short VRRegNo[] = {
42 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
43 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
44 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
45 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
48 /// RemoveVRSaveCode - We have found that this function does not need any code
49 /// to manipulate the VRSAVE register, even though it uses vector registers.
50 /// This can happen when the only registers used are known to be live in or out
51 /// of the function. Remove all of the VRSAVE related code from the function.
52 static void RemoveVRSaveCode(MachineInstr *MI) {
53 MachineBasicBlock *Entry = MI->getParent();
54 MachineFunction *MF = Entry->getParent();
56 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
57 MachineBasicBlock::iterator MBBI = MI;
59 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
60 MBBI->eraseFromParent();
62 bool RemovedAllMTVRSAVEs = true;
63 // See if we can find and remove the MTVRSAVE instruction from all of the
65 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
66 // If last instruction is a return instruction, add an epilogue
67 if (!I->empty() && I->back().getDesc().isReturn()) {
69 for (MBBI = I->end(); MBBI != I->begin(); ) {
71 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
72 MBBI->eraseFromParent(); // remove it.
77 RemovedAllMTVRSAVEs &= FoundIt;
81 // If we found and removed all MTVRSAVE instructions, remove the read of
83 if (RemovedAllMTVRSAVEs) {
85 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
87 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
88 MBBI->eraseFromParent();
91 // Finally, nuke the UPDATE_VRSAVE.
92 MI->eraseFromParent();
95 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
96 // instruction selector. Based on the vector registers that have been used,
97 // transform this into the appropriate ORI instruction.
98 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
99 MachineFunction *MF = MI->getParent()->getParent();
100 DebugLoc dl = MI->getDebugLoc();
102 unsigned UsedRegMask = 0;
103 for (unsigned i = 0; i != 32; ++i)
104 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
105 UsedRegMask |= 1 << (31-i);
107 // Live in and live out values already must be in the mask, so don't bother
109 for (MachineRegisterInfo::livein_iterator
110 I = MF->getRegInfo().livein_begin(),
111 E = MF->getRegInfo().livein_end(); I != E; ++I) {
112 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
113 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
114 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
116 for (MachineRegisterInfo::liveout_iterator
117 I = MF->getRegInfo().liveout_begin(),
118 E = MF->getRegInfo().liveout_end(); I != E; ++I) {
119 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
120 if (VRRegNo[RegNo] == *I) // If this really is a vector reg.
121 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
124 // If no registers are used, turn this into a copy.
125 if (UsedRegMask == 0) {
126 // Remove all VRSAVE code.
127 RemoveVRSaveCode(MI);
131 unsigned SrcReg = MI->getOperand(1).getReg();
132 unsigned DstReg = MI->getOperand(0).getReg();
134 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
135 if (DstReg != SrcReg)
136 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
138 .addImm(UsedRegMask);
140 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
141 .addReg(SrcReg, RegState::Kill)
142 .addImm(UsedRegMask);
143 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
144 if (DstReg != SrcReg)
145 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
147 .addImm(UsedRegMask >> 16);
149 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
150 .addReg(SrcReg, RegState::Kill)
151 .addImm(UsedRegMask >> 16);
153 if (DstReg != SrcReg)
154 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
156 .addImm(UsedRegMask >> 16);
158 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
159 .addReg(SrcReg, RegState::Kill)
160 .addImm(UsedRegMask >> 16);
162 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
163 .addReg(DstReg, RegState::Kill)
164 .addImm(UsedRegMask & 0xFFFF);
167 // Remove the old UPDATE_VRSAVE instruction.
168 MI->eraseFromParent();
171 /// determineFrameLayout - Determine the size of the frame and maximum call
173 void PPCFrameLowering::determineFrameLayout(MachineFunction &MF) const {
174 MachineFrameInfo *MFI = MF.getFrameInfo();
176 // Get the number of bytes to allocate from the FrameInfo
177 unsigned FrameSize = MFI->getStackSize();
179 // Get the alignments provided by the target, and the maximum alignment
180 // (if any) of the fixed frame objects.
181 unsigned MaxAlign = MFI->getMaxAlignment();
182 unsigned TargetAlign = getStackAlignment();
183 unsigned AlignMask = TargetAlign - 1; //
185 // If we are a leaf function, and use up to 224 bytes of stack space,
186 // don't have a frame pointer, calls, or dynamic alloca then we do not need
187 // to adjust the stack pointer (we fit in the Red Zone).
188 bool DisableRedZone = MF.getFunction()->hasFnAttr(Attribute::NoRedZone);
189 // FIXME SVR4 The 32-bit SVR4 ABI has no red zone.
190 if (!DisableRedZone &&
191 FrameSize <= 224 && // Fits in red zone.
192 !MFI->hasVarSizedObjects() && // No dynamic alloca.
193 !MFI->adjustsStack() && // No calls.
194 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment.
196 MFI->setStackSize(0);
200 // Get the maximum call frame size of all the calls.
201 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
203 // Maximum call frame needs to be at least big enough for linkage and 8 args.
204 unsigned minCallFrameSize = getMinCallFrameSize(Subtarget.isPPC64(),
205 Subtarget.isDarwinABI());
206 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
208 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
209 // that allocations will be aligned.
210 if (MFI->hasVarSizedObjects())
211 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
213 // Update maximum call frame size.
214 MFI->setMaxCallFrameSize(maxCallFrameSize);
216 // Include call frame size in total.
217 FrameSize += maxCallFrameSize;
219 // Make sure the frame is aligned.
220 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
222 // Update frame info.
223 MFI->setStackSize(FrameSize);
226 // hasFP - Return true if the specified function actually has a dedicated frame
228 bool PPCFrameLowering::hasFP(const MachineFunction &MF) const {
229 const MachineFrameInfo *MFI = MF.getFrameInfo();
230 // FIXME: This is pretty much broken by design: hasFP() might be called really
231 // early, before the stack layout was calculated and thus hasFP() might return
232 // true or false here depending on the time of call.
233 return (MFI->getStackSize()) && needsFP(MF);
236 // needsFP - Return true if the specified function should have a dedicated frame
237 // pointer register. This is true if the function has variable sized allocas or
238 // if frame pointer elimination is disabled.
239 bool PPCFrameLowering::needsFP(const MachineFunction &MF) const {
240 const MachineFrameInfo *MFI = MF.getFrameInfo();
242 // Naked functions have no stack frame pushed, so we don't have a frame
244 if (MF.getFunction()->hasFnAttr(Attribute::Naked))
247 return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects() ||
248 (GuaranteedTailCallOpt && MF.getInfo<PPCFunctionInfo>()->hasFastCall());
252 void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
253 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
254 MachineBasicBlock::iterator MBBI = MBB.begin();
255 MachineFrameInfo *MFI = MF.getFrameInfo();
256 const PPCInstrInfo &TII =
257 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
259 MachineModuleInfo &MMI = MF.getMMI();
261 bool needsFrameMoves = MMI.hasDebugInfo() ||
262 MF.getFunction()->needsUnwindTableEntry();
264 // Prepare for frame info.
265 MCSymbol *FrameLabel = 0;
267 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
269 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
270 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
271 HandleVRSaveUpdate(MBBI, TII);
276 // Move MBBI back to the beginning of the function.
279 // Work out frame sizes.
280 // FIXME: determineFrameLayout() may change the frame size. This should be
281 // moved upper, to some hook.
282 determineFrameLayout(MF);
283 unsigned FrameSize = MFI->getStackSize();
285 int NegFrameSize = -FrameSize;
287 // Get processor type.
288 bool isPPC64 = Subtarget.isPPC64();
289 // Get operating system
290 bool isDarwinABI = Subtarget.isDarwinABI();
291 // Check if the link register (LR) must be saved.
292 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
293 bool MustSaveLR = FI->mustSaveLR();
294 // Do we have a frame pointer for this function?
295 bool HasFP = hasFP(MF);
297 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
301 if (Subtarget.isSVR4ABI()) {
302 MachineFrameInfo *FFI = MF.getFrameInfo();
303 int FPIndex = FI->getFramePointerSaveIndex();
304 assert(FPIndex && "No Frame Pointer Save Slot!");
305 FPOffset = FFI->getObjectOffset(FPIndex);
307 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
313 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0);
316 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
322 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
324 .addImm(LROffset / 4)
328 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0);
331 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
337 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
343 // Skip if a leaf routine.
344 if (!FrameSize) return;
346 // Get stack alignments.
347 unsigned TargetAlign = getStackAlignment();
348 unsigned MaxAlign = MFI->getMaxAlignment();
350 // Adjust stack pointer: r1 += NegFrameSize.
351 // If there is a preferred stack alignment, align R1 now
354 if (ALIGN_STACK && MaxAlign > TargetAlign) {
355 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
356 "Invalid alignment!");
357 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!");
359 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0)
362 .addImm(32 - Log2_32(MaxAlign))
364 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0)
365 .addReg(PPC::R0, RegState::Kill)
366 .addImm(NegFrameSize);
367 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX))
371 } else if (isInt<16>(NegFrameSize)) {
372 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1)
374 .addImm(NegFrameSize)
377 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
378 .addImm(NegFrameSize >> 16);
379 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
380 .addReg(PPC::R0, RegState::Kill)
381 .addImm(NegFrameSize & 0xFFFF);
382 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX))
388 if (ALIGN_STACK && MaxAlign > TargetAlign) {
389 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
390 "Invalid alignment!");
391 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!");
393 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0)
396 .addImm(64 - Log2_32(MaxAlign));
397 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0)
399 .addImm(NegFrameSize);
400 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX))
404 } else if (isInt<16>(NegFrameSize)) {
405 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1)
407 .addImm(NegFrameSize / 4)
410 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
411 .addImm(NegFrameSize >> 16);
412 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
413 .addReg(PPC::X0, RegState::Kill)
414 .addImm(NegFrameSize & 0xFFFF);
415 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX))
422 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
424 // Add the "machine moves" for the instructions we generated above, but in
426 if (needsFrameMoves) {
427 // Mark effective beginning of when frame pointer becomes valid.
428 FrameLabel = MMI.getContext().CreateTempSymbol();
429 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(FrameLabel);
431 // Show update of SP.
433 MachineLocation SPDst(MachineLocation::VirtualFP);
434 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
435 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
437 MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31);
438 Moves.push_back(MachineMove(FrameLabel, SP, SP));
442 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
443 MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31);
444 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
448 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
449 MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR);
450 Moves.push_back(MachineMove(FrameLabel, LRDst, LRSrc));
454 MCSymbol *ReadyLabel = 0;
456 // If there is a frame pointer, copy R1 into R31
459 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31)
463 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31)
468 if (needsFrameMoves) {
469 ReadyLabel = MMI.getContext().CreateTempSymbol();
471 // Mark effective beginning of when frame pointer is ready.
472 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(ReadyLabel);
474 MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) :
475 (isPPC64 ? PPC::X1 : PPC::R1));
476 MachineLocation FPSrc(MachineLocation::VirtualFP);
477 Moves.push_back(MachineMove(ReadyLabel, FPDst, FPSrc));
481 if (needsFrameMoves) {
482 MCSymbol *Label = HasFP ? ReadyLabel : FrameLabel;
484 // Add callee saved registers to move list.
485 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
486 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
487 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
488 unsigned Reg = CSI[I].getReg();
489 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
491 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
492 // subregisters of CR2. We just need to emit a move of CR2.
493 if (Reg == PPC::CR2LT || Reg == PPC::CR2GT || Reg == PPC::CR2EQ)
495 if (Reg == PPC::CR2UN)
498 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
499 MachineLocation CSSrc(Reg);
500 Moves.push_back(MachineMove(Label, CSDst, CSSrc));
505 void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
506 MachineBasicBlock &MBB) const {
507 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
508 assert(MBBI != MBB.end() && "Returning block has no terminator");
509 const PPCInstrInfo &TII =
510 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
512 unsigned RetOpcode = MBBI->getOpcode();
515 assert((RetOpcode == PPC::BLR ||
516 RetOpcode == PPC::TCRETURNri ||
517 RetOpcode == PPC::TCRETURNdi ||
518 RetOpcode == PPC::TCRETURNai ||
519 RetOpcode == PPC::TCRETURNri8 ||
520 RetOpcode == PPC::TCRETURNdi8 ||
521 RetOpcode == PPC::TCRETURNai8) &&
522 "Can only insert epilog into returning blocks");
524 // Get alignment info so we know how to restore r1
525 const MachineFrameInfo *MFI = MF.getFrameInfo();
526 unsigned TargetAlign = getStackAlignment();
527 unsigned MaxAlign = MFI->getMaxAlignment();
529 // Get the number of bytes allocated from the FrameInfo.
530 int FrameSize = MFI->getStackSize();
532 // Get processor type.
533 bool isPPC64 = Subtarget.isPPC64();
534 // Get operating system
535 bool isDarwinABI = Subtarget.isDarwinABI();
536 // Check if the link register (LR) has been saved.
537 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
538 bool MustSaveLR = FI->mustSaveLR();
539 // Do we have a frame pointer for this function?
540 bool HasFP = hasFP(MF);
542 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
546 if (Subtarget.isSVR4ABI()) {
547 MachineFrameInfo *FFI = MF.getFrameInfo();
548 int FPIndex = FI->getFramePointerSaveIndex();
549 assert(FPIndex && "No Frame Pointer Save Slot!");
550 FPOffset = FFI->getObjectOffset(FPIndex);
552 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
556 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
557 RetOpcode == PPC::TCRETURNdi ||
558 RetOpcode == PPC::TCRETURNai ||
559 RetOpcode == PPC::TCRETURNri8 ||
560 RetOpcode == PPC::TCRETURNdi8 ||
561 RetOpcode == PPC::TCRETURNai8;
564 int MaxTCRetDelta = FI->getTailCallSPDelta();
565 MachineOperand &StackAdjust = MBBI->getOperand(1);
566 assert(StackAdjust.isImm() && "Expecting immediate value.");
567 // Adjust stack pointer.
568 int StackAdj = StackAdjust.getImm();
569 int Delta = StackAdj - MaxTCRetDelta;
570 assert((Delta >= 0) && "Delta must be positive");
572 FrameSize += (StackAdj +Delta);
574 FrameSize += StackAdj;
578 // The loaded (or persistent) stack pointer value is offset by the 'stwu'
579 // on entry to the function. Add this offset back now.
581 // If this function contained a fastcc call and GuaranteedTailCallOpt is
582 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
583 // call which invalidates the stack pointer value in SP(0). So we use the
584 // value of R31 in this case.
585 if (FI->hasFastCall() && isInt<16>(FrameSize)) {
586 assert(hasFP(MF) && "Expecting a valid the frame pointer.");
587 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
588 .addReg(PPC::R31).addImm(FrameSize);
589 } else if(FI->hasFastCall()) {
590 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
591 .addImm(FrameSize >> 16);
592 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
593 .addReg(PPC::R0, RegState::Kill)
594 .addImm(FrameSize & 0xFFFF);
595 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4))
599 } else if (isInt<16>(FrameSize) &&
600 (!ALIGN_STACK || TargetAlign >= MaxAlign) &&
601 !MFI->hasVarSizedObjects()) {
602 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
603 .addReg(PPC::R1).addImm(FrameSize);
605 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1)
606 .addImm(0).addReg(PPC::R1);
609 if (FI->hasFastCall() && isInt<16>(FrameSize)) {
610 assert(hasFP(MF) && "Expecting a valid the frame pointer.");
611 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
612 .addReg(PPC::X31).addImm(FrameSize);
613 } else if(FI->hasFastCall()) {
614 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
615 .addImm(FrameSize >> 16);
616 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
617 .addReg(PPC::X0, RegState::Kill)
618 .addImm(FrameSize & 0xFFFF);
619 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8))
623 } else if (isInt<16>(FrameSize) && TargetAlign >= MaxAlign &&
624 !MFI->hasVarSizedObjects()) {
625 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
626 .addReg(PPC::X1).addImm(FrameSize);
628 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1)
629 .addImm(0).addReg(PPC::X1);
636 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0)
637 .addImm(LROffset/4).addReg(PPC::X1);
640 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31)
641 .addImm(FPOffset/4).addReg(PPC::X1);
644 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0);
647 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0)
648 .addImm(LROffset).addReg(PPC::R1);
651 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31)
652 .addImm(FPOffset).addReg(PPC::R1);
655 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0);
658 // Callee pop calling convention. Pop parameter/linkage area. Used for tail
660 if (GuaranteedTailCallOpt && RetOpcode == PPC::BLR &&
661 MF.getFunction()->getCallingConv() == CallingConv::Fast) {
662 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
663 unsigned CallerAllocatedAmt = FI->getMinReservedArea();
664 unsigned StackReg = isPPC64 ? PPC::X1 : PPC::R1;
665 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
666 unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0;
667 unsigned ADDIInstr = isPPC64 ? PPC::ADDI8 : PPC::ADDI;
668 unsigned ADDInstr = isPPC64 ? PPC::ADD8 : PPC::ADD4;
669 unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS;
670 unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI;
672 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
673 BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg)
674 .addReg(StackReg).addImm(CallerAllocatedAmt);
676 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
677 .addImm(CallerAllocatedAmt >> 16);
678 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
679 .addReg(TmpReg, RegState::Kill)
680 .addImm(CallerAllocatedAmt & 0xFFFF);
681 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
686 } else if (RetOpcode == PPC::TCRETURNdi) {
687 MBBI = MBB.getLastNonDebugInstr();
688 MachineOperand &JumpTarget = MBBI->getOperand(0);
689 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
690 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
691 } else if (RetOpcode == PPC::TCRETURNri) {
692 MBBI = MBB.getLastNonDebugInstr();
693 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
694 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
695 } else if (RetOpcode == PPC::TCRETURNai) {
696 MBBI = MBB.getLastNonDebugInstr();
697 MachineOperand &JumpTarget = MBBI->getOperand(0);
698 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
699 } else if (RetOpcode == PPC::TCRETURNdi8) {
700 MBBI = MBB.getLastNonDebugInstr();
701 MachineOperand &JumpTarget = MBBI->getOperand(0);
702 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
703 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
704 } else if (RetOpcode == PPC::TCRETURNri8) {
705 MBBI = MBB.getLastNonDebugInstr();
706 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
707 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
708 } else if (RetOpcode == PPC::TCRETURNai8) {
709 MBBI = MBB.getLastNonDebugInstr();
710 MachineOperand &JumpTarget = MBBI->getOperand(0);
711 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
715 void PPCFrameLowering::getInitialFrameState(std::vector<MachineMove> &Moves) const {
716 // Initial state of the frame pointer is R1.
717 MachineLocation Dst(MachineLocation::VirtualFP);
718 MachineLocation Src(PPC::R1, 0);
719 Moves.push_back(MachineMove(0, Dst, Src));
722 static bool spillsCR(const MachineFunction &MF) {
723 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
724 return FuncInfo->isCRSpilled();
727 /// MustSaveLR - Return true if this function requires that we save the LR
728 /// register onto the stack in the prolog and restore it in the epilog of the
730 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
731 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
733 // We need a save/restore of LR if there is any def of LR (which is
734 // defined by calls, including the PIC setup sequence), or if there is
735 // some use of the LR stack slot (e.g. for builtin_return_address).
736 // (LR comes in 32 and 64 bit versions.)
737 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
738 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
742 PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
743 RegScavenger *RS) const {
744 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
746 // Save and clear the LR state.
747 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
748 unsigned LR = RegInfo->getRARegister();
749 FI->setMustSaveLR(MustSaveLR(MF, LR));
750 MF.getRegInfo().setPhysRegUnused(LR);
752 // Save R31 if necessary
753 int FPSI = FI->getFramePointerSaveIndex();
754 bool isPPC64 = Subtarget.isPPC64();
755 bool isDarwinABI = Subtarget.isDarwinABI();
756 MachineFrameInfo *MFI = MF.getFrameInfo();
758 // If the frame pointer save index hasn't been defined yet.
759 if (!FPSI && needsFP(MF)) {
760 // Find out what the fix offset of the frame pointer save area.
761 int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI);
762 // Allocate the frame index for frame pointer save area.
763 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
765 FI->setFramePointerSaveIndex(FPSI);
768 // Reserve stack space to move the linkage area to in case of a tail call.
770 if (GuaranteedTailCallOpt && (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
771 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
774 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
775 // a large stack, which will require scavenging a register to materialize a
777 // FIXME: this doesn't actually check stack size, so is a bit pessimistic
778 // FIXME: doesn't detect whether or not we need to spill vXX, which requires
781 if (RegInfo->requiresRegisterScavenging(MF)) // FIXME (64-bit): Enable.
782 if (needsFP(MF) || spillsCR(MF)) {
783 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
784 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
785 const TargetRegisterClass *RC = isPPC64 ? G8RC : GPRC;
786 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
792 void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF)
794 // Early exit if not using the SVR4 ABI.
795 if (!Subtarget.isSVR4ABI())
798 // Get callee saved register information.
799 MachineFrameInfo *FFI = MF.getFrameInfo();
800 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
802 // Early exit if no callee saved registers are modified!
803 if (CSI.empty() && !needsFP(MF)) {
807 unsigned MinGPR = PPC::R31;
808 unsigned MinG8R = PPC::X31;
809 unsigned MinFPR = PPC::F31;
810 unsigned MinVR = PPC::V31;
812 bool HasGPSaveArea = false;
813 bool HasG8SaveArea = false;
814 bool HasFPSaveArea = false;
815 bool HasCRSaveArea = false;
816 bool HasVRSAVESaveArea = false;
817 bool HasVRSaveArea = false;
819 SmallVector<CalleeSavedInfo, 18> GPRegs;
820 SmallVector<CalleeSavedInfo, 18> G8Regs;
821 SmallVector<CalleeSavedInfo, 18> FPRegs;
822 SmallVector<CalleeSavedInfo, 18> VRegs;
824 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
825 unsigned Reg = CSI[i].getReg();
826 if (PPC::GPRCRegisterClass->contains(Reg)) {
827 HasGPSaveArea = true;
829 GPRegs.push_back(CSI[i]);
834 } else if (PPC::G8RCRegisterClass->contains(Reg)) {
835 HasG8SaveArea = true;
837 G8Regs.push_back(CSI[i]);
842 } else if (PPC::F8RCRegisterClass->contains(Reg)) {
843 HasFPSaveArea = true;
845 FPRegs.push_back(CSI[i]);
850 // FIXME SVR4: Disable CR save area for now.
851 } else if (PPC::CRBITRCRegisterClass->contains(Reg)
852 || PPC::CRRCRegisterClass->contains(Reg)) {
853 // HasCRSaveArea = true;
854 } else if (PPC::VRSAVERCRegisterClass->contains(Reg)) {
855 HasVRSAVESaveArea = true;
856 } else if (PPC::VRRCRegisterClass->contains(Reg)) {
857 HasVRSaveArea = true;
859 VRegs.push_back(CSI[i]);
865 llvm_unreachable("Unknown RegisterClass!");
869 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>();
871 int64_t LowerBound = 0;
873 // Take into account stack space reserved for tail calls.
875 if (GuaranteedTailCallOpt && (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
876 LowerBound = TCSPDelta;
879 // The Floating-point register save area is right below the back chain word
880 // of the previous stack frame.
882 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
883 int FI = FPRegs[i].getFrameIdx();
885 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
888 LowerBound -= (31 - PPCRegisterInfo::getRegisterNumbering(MinFPR) + 1) * 8;
891 // Check whether the frame pointer register is allocated. If so, make sure it
892 // is spilled to the correct offset.
894 HasGPSaveArea = true;
896 int FI = PFI->getFramePointerSaveIndex();
897 assert(FI && "No Frame Pointer Save Slot!");
899 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
902 // General register save area starts right below the Floating-point
903 // register save area.
904 if (HasGPSaveArea || HasG8SaveArea) {
905 // Move general register save area spill slots down, taking into account
906 // the size of the Floating-point register save area.
907 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
908 int FI = GPRegs[i].getFrameIdx();
910 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
913 // Move general register save area spill slots down, taking into account
914 // the size of the Floating-point register save area.
915 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
916 int FI = G8Regs[i].getFrameIdx();
918 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
922 std::min<unsigned>(PPCRegisterInfo::getRegisterNumbering(MinGPR),
923 PPCRegisterInfo::getRegisterNumbering(MinG8R));
925 if (Subtarget.isPPC64()) {
926 LowerBound -= (31 - MinReg + 1) * 8;
928 LowerBound -= (31 - MinReg + 1) * 4;
932 // The CR save area is below the general register save area.
934 // FIXME SVR4: Is it actually possible to have multiple elements in CSI
935 // which have the CR/CRBIT register class?
936 // Adjust the frame index of the CR spill slot.
937 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
938 unsigned Reg = CSI[i].getReg();
940 if (PPC::CRBITRCRegisterClass->contains(Reg) ||
941 PPC::CRRCRegisterClass->contains(Reg)) {
942 int FI = CSI[i].getFrameIdx();
944 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
948 LowerBound -= 4; // The CR save area is always 4 bytes long.
951 if (HasVRSAVESaveArea) {
952 // FIXME SVR4: Is it actually possible to have multiple elements in CSI
953 // which have the VRSAVE register class?
954 // Adjust the frame index of the VRSAVE spill slot.
955 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
956 unsigned Reg = CSI[i].getReg();
958 if (PPC::VRSAVERCRegisterClass->contains(Reg)) {
959 int FI = CSI[i].getFrameIdx();
961 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
965 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
969 // Insert alignment padding, we need 16-byte alignment.
970 LowerBound = (LowerBound - 15) & ~(15);
972 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
973 int FI = VRegs[i].getFrameIdx();
975 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));