1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PPC implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCFrameLowering.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCInstrInfo.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/IR/Function.h"
25 #include "llvm/Target/TargetOptions.h"
29 // FIXME This disables some code that aligns the stack to a boundary bigger than
30 // the default (16 bytes on Darwin) when there is a stack local of greater
31 // alignment. This does not currently work, because the delta between old and
32 // new stack pointers is added to offsets that reference incoming parameters
33 // after the prolog is generated, and the code that does that doesn't handle a
34 // variable delta. You don't want to do that anyway; a better approach is to
35 // reserve another register that retains to the incoming stack pointer, and
36 // reference parameters relative to that.
40 /// VRRegNo - Map from a numbered VR register to its enum value.
42 static const uint16_t VRRegNo[] = {
43 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
44 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
45 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
46 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
49 /// RemoveVRSaveCode - We have found that this function does not need any code
50 /// to manipulate the VRSAVE register, even though it uses vector registers.
51 /// This can happen when the only registers used are known to be live in or out
52 /// of the function. Remove all of the VRSAVE related code from the function.
53 /// FIXME: The removal of the code results in a compile failure at -O0 when the
54 /// function contains a function call, as the GPR containing original VRSAVE
55 /// contents is spilled and reloaded around the call. Without the prolog code,
56 /// the spill instruction refers to an undefined register. This code needs
57 /// to account for all uses of that GPR.
58 static void RemoveVRSaveCode(MachineInstr *MI) {
59 MachineBasicBlock *Entry = MI->getParent();
60 MachineFunction *MF = Entry->getParent();
62 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
63 MachineBasicBlock::iterator MBBI = MI;
65 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
66 MBBI->eraseFromParent();
68 bool RemovedAllMTVRSAVEs = true;
69 // See if we can find and remove the MTVRSAVE instruction from all of the
71 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
72 // If last instruction is a return instruction, add an epilogue
73 if (!I->empty() && I->back().isReturn()) {
75 for (MBBI = I->end(); MBBI != I->begin(); ) {
77 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
78 MBBI->eraseFromParent(); // remove it.
83 RemovedAllMTVRSAVEs &= FoundIt;
87 // If we found and removed all MTVRSAVE instructions, remove the read of
89 if (RemovedAllMTVRSAVEs) {
91 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
93 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
94 MBBI->eraseFromParent();
97 // Finally, nuke the UPDATE_VRSAVE.
98 MI->eraseFromParent();
101 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
102 // instruction selector. Based on the vector registers that have been used,
103 // transform this into the appropriate ORI instruction.
104 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
105 MachineFunction *MF = MI->getParent()->getParent();
106 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
107 DebugLoc dl = MI->getDebugLoc();
109 unsigned UsedRegMask = 0;
110 for (unsigned i = 0; i != 32; ++i)
111 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
112 UsedRegMask |= 1 << (31-i);
114 // Live in and live out values already must be in the mask, so don't bother
116 for (MachineRegisterInfo::livein_iterator
117 I = MF->getRegInfo().livein_begin(),
118 E = MF->getRegInfo().livein_end(); I != E; ++I) {
119 unsigned RegNo = TRI->getEncodingValue(I->first);
120 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
121 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
124 // Live out registers appear as use operands on return instructions.
125 for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end();
126 UsedRegMask != 0 && BI != BE; ++BI) {
127 const MachineBasicBlock &MBB = *BI;
128 if (MBB.empty() || !MBB.back().isReturn())
130 const MachineInstr &Ret = MBB.back();
131 for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) {
132 const MachineOperand &MO = Ret.getOperand(I);
133 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
135 unsigned RegNo = TRI->getEncodingValue(MO.getReg());
136 UsedRegMask &= ~(1 << (31-RegNo));
140 // If no registers are used, turn this into a copy.
141 if (UsedRegMask == 0) {
142 // Remove all VRSAVE code.
143 RemoveVRSaveCode(MI);
147 unsigned SrcReg = MI->getOperand(1).getReg();
148 unsigned DstReg = MI->getOperand(0).getReg();
150 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
151 if (DstReg != SrcReg)
152 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
154 .addImm(UsedRegMask);
156 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
157 .addReg(SrcReg, RegState::Kill)
158 .addImm(UsedRegMask);
159 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
160 if (DstReg != SrcReg)
161 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
163 .addImm(UsedRegMask >> 16);
165 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
166 .addReg(SrcReg, RegState::Kill)
167 .addImm(UsedRegMask >> 16);
169 if (DstReg != SrcReg)
170 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
172 .addImm(UsedRegMask >> 16);
174 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
175 .addReg(SrcReg, RegState::Kill)
176 .addImm(UsedRegMask >> 16);
178 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
179 .addReg(DstReg, RegState::Kill)
180 .addImm(UsedRegMask & 0xFFFF);
183 // Remove the old UPDATE_VRSAVE instruction.
184 MI->eraseFromParent();
187 static bool spillsCR(const MachineFunction &MF) {
188 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
189 return FuncInfo->isCRSpilled();
192 static bool spillsVRSAVE(const MachineFunction &MF) {
193 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
194 return FuncInfo->isVRSAVESpilled();
197 static bool hasSpills(const MachineFunction &MF) {
198 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
199 return FuncInfo->hasSpills();
202 static bool hasNonRISpills(const MachineFunction &MF) {
203 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
204 return FuncInfo->hasNonRISpills();
207 /// determineFrameLayout - Determine the size of the frame and maximum call
209 unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF,
211 bool UseEstimate) const {
212 MachineFrameInfo *MFI = MF.getFrameInfo();
214 // Get the number of bytes to allocate from the FrameInfo
216 UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize();
218 // Get the alignments provided by the target, and the maximum alignment
219 // (if any) of the fixed frame objects.
220 unsigned MaxAlign = MFI->getMaxAlignment();
221 unsigned TargetAlign = getStackAlignment();
222 unsigned AlignMask = TargetAlign - 1; //
224 // If we are a leaf function, and use up to 224 bytes of stack space,
225 // don't have a frame pointer, calls, or dynamic alloca then we do not need
226 // to adjust the stack pointer (we fit in the Red Zone). For 64-bit
227 // SVR4, we also require a stack frame if we need to spill the CR,
228 // since this spill area is addressed relative to the stack pointer.
229 // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate
230 // stackless code if all local vars are reg-allocated.
231 bool DisableRedZone = MF.getFunction()->getAttributes().
232 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoRedZone);
233 if (!DisableRedZone &&
234 (Subtarget.isPPC64() || // 32-bit SVR4, no stack-
235 !Subtarget.isSVR4ABI() || // allocated locals.
237 FrameSize <= 224 && // Fits in red zone.
238 !MFI->hasVarSizedObjects() && // No dynamic alloca.
239 !MFI->adjustsStack() && // No calls.
240 !(Subtarget.isPPC64() && // No 64-bit SVR4 CRsave.
241 Subtarget.isSVR4ABI()
243 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment.
246 MFI->setStackSize(0);
250 // Get the maximum call frame size of all the calls.
251 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
253 // Maximum call frame needs to be at least big enough for linkage and 8 args.
254 unsigned minCallFrameSize = getMinCallFrameSize(Subtarget.isPPC64(),
255 Subtarget.isDarwinABI());
256 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
258 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
259 // that allocations will be aligned.
260 if (MFI->hasVarSizedObjects())
261 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
263 // Update maximum call frame size.
265 MFI->setMaxCallFrameSize(maxCallFrameSize);
267 // Include call frame size in total.
268 FrameSize += maxCallFrameSize;
270 // Make sure the frame is aligned.
271 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
273 // Update frame info.
275 MFI->setStackSize(FrameSize);
280 // hasFP - Return true if the specified function actually has a dedicated frame
282 bool PPCFrameLowering::hasFP(const MachineFunction &MF) const {
283 const MachineFrameInfo *MFI = MF.getFrameInfo();
284 // FIXME: This is pretty much broken by design: hasFP() might be called really
285 // early, before the stack layout was calculated and thus hasFP() might return
286 // true or false here depending on the time of call.
287 return (MFI->getStackSize()) && needsFP(MF);
290 // needsFP - Return true if the specified function should have a dedicated frame
291 // pointer register. This is true if the function has variable sized allocas or
292 // if frame pointer elimination is disabled.
293 bool PPCFrameLowering::needsFP(const MachineFunction &MF) const {
294 const MachineFrameInfo *MFI = MF.getFrameInfo();
296 // Naked functions have no stack frame pushed, so we don't have a frame
298 if (MF.getFunction()->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
302 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
303 MFI->hasVarSizedObjects() ||
304 (MF.getTarget().Options.GuaranteedTailCallOpt &&
305 MF.getInfo<PPCFunctionInfo>()->hasFastCall());
308 void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const {
309 bool is31 = needsFP(MF);
310 unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
311 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
313 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
315 for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) {
317 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
318 MachineOperand &MO = MBBI->getOperand(I);
322 switch (MO.getReg()) {
334 void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
335 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
336 MachineBasicBlock::iterator MBBI = MBB.begin();
337 MachineFrameInfo *MFI = MF.getFrameInfo();
338 const PPCInstrInfo &TII =
339 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
341 MachineModuleInfo &MMI = MF.getMMI();
343 bool needsFrameMoves = MMI.hasDebugInfo() ||
344 MF.getFunction()->needsUnwindTableEntry();
346 // Prepare for frame info.
347 MCSymbol *FrameLabel = 0;
349 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
351 if (!Subtarget.isSVR4ABI())
352 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
353 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
354 HandleVRSaveUpdate(MBBI, TII);
359 // Move MBBI back to the beginning of the function.
362 // Work out frame sizes.
363 unsigned FrameSize = determineFrameLayout(MF);
364 int NegFrameSize = -FrameSize;
366 if (MFI->isFrameAddressTaken())
367 replaceFPWithRealFP(MF);
369 // Get processor type.
370 bool isPPC64 = Subtarget.isPPC64();
371 // Get operating system
372 bool isDarwinABI = Subtarget.isDarwinABI();
373 // Check if the link register (LR) must be saved.
374 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
375 bool MustSaveLR = FI->mustSaveLR();
376 // Do we have a frame pointer for this function?
377 bool HasFP = hasFP(MF);
379 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
383 if (Subtarget.isSVR4ABI()) {
384 MachineFrameInfo *FFI = MF.getFrameInfo();
385 int FPIndex = FI->getFramePointerSaveIndex();
386 assert(FPIndex && "No Frame Pointer Save Slot!");
387 FPOffset = FFI->getObjectOffset(FPIndex);
389 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
395 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0);
398 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
404 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
406 .addImm(LROffset / 4)
410 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0);
413 // FIXME: On PPC32 SVR4, FPOffset is negative and access to negative
414 // offsets of R1 is not allowed.
415 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
421 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
427 // Skip if a leaf routine.
428 if (!FrameSize) return;
430 // Get stack alignments.
431 unsigned TargetAlign = getStackAlignment();
432 unsigned MaxAlign = MFI->getMaxAlignment();
434 // Adjust stack pointer: r1 += NegFrameSize.
435 // If there is a preferred stack alignment, align R1 now
438 if (ALIGN_STACK && MaxAlign > TargetAlign) {
439 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
440 "Invalid alignment!");
441 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!");
443 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0)
446 .addImm(32 - Log2_32(MaxAlign))
448 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0)
449 .addReg(PPC::R0, RegState::Kill)
450 .addImm(NegFrameSize);
451 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1)
452 .addReg(PPC::R1, RegState::Kill)
455 } else if (isInt<16>(NegFrameSize)) {
456 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1)
458 .addImm(NegFrameSize)
461 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
462 .addImm(NegFrameSize >> 16);
463 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
464 .addReg(PPC::R0, RegState::Kill)
465 .addImm(NegFrameSize & 0xFFFF);
466 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1)
467 .addReg(PPC::R1, RegState::Kill)
472 if (ALIGN_STACK && MaxAlign > TargetAlign) {
473 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
474 "Invalid alignment!");
475 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!");
477 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0)
480 .addImm(64 - Log2_32(MaxAlign));
481 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0)
483 .addImm(NegFrameSize);
484 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1)
485 .addReg(PPC::X1, RegState::Kill)
488 } else if (isInt<16>(NegFrameSize)) {
489 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1)
491 .addImm(NegFrameSize / 4)
494 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
495 .addImm(NegFrameSize >> 16);
496 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
497 .addReg(PPC::X0, RegState::Kill)
498 .addImm(NegFrameSize & 0xFFFF);
499 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1)
500 .addReg(PPC::X1, RegState::Kill)
506 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
508 // Add the "machine moves" for the instructions we generated above, but in
510 if (needsFrameMoves) {
511 // Mark effective beginning of when frame pointer becomes valid.
512 FrameLabel = MMI.getContext().CreateTempSymbol();
513 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(FrameLabel);
515 // Show update of SP.
517 MachineLocation SPDst(MachineLocation::VirtualFP);
518 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
519 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
521 MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31);
522 Moves.push_back(MachineMove(FrameLabel, SP, SP));
526 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
527 MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31);
528 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
532 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
533 MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR);
534 Moves.push_back(MachineMove(FrameLabel, LRDst, LRSrc));
538 MCSymbol *ReadyLabel = 0;
540 // If there is a frame pointer, copy R1 into R31
543 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31)
547 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31)
552 if (needsFrameMoves) {
553 ReadyLabel = MMI.getContext().CreateTempSymbol();
555 // Mark effective beginning of when frame pointer is ready.
556 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(ReadyLabel);
558 MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) :
559 (isPPC64 ? PPC::X1 : PPC::R1));
560 MachineLocation FPSrc(MachineLocation::VirtualFP);
561 Moves.push_back(MachineMove(ReadyLabel, FPDst, FPSrc));
565 if (needsFrameMoves) {
566 MCSymbol *Label = HasFP ? ReadyLabel : FrameLabel;
568 // Add callee saved registers to move list.
569 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
570 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
571 unsigned Reg = CSI[I].getReg();
572 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
574 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
575 // subregisters of CR2. We just need to emit a move of CR2.
576 if (PPC::CRBITRCRegClass.contains(Reg))
579 // For SVR4, don't emit a move for the CR spill slot if we haven't
581 if (Subtarget.isSVR4ABI()
582 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
586 // For 64-bit SVR4 when we have spilled CRs, the spill location
587 // is SP+8, not a frame-relative slot.
588 if (Subtarget.isSVR4ABI()
589 && Subtarget.isPPC64()
590 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
591 MachineLocation CSDst(PPC::X1, 8);
592 MachineLocation CSSrc(PPC::CR2);
593 Moves.push_back(MachineMove(Label, CSDst, CSSrc));
597 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
598 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
599 MachineLocation CSSrc(Reg);
600 Moves.push_back(MachineMove(Label, CSDst, CSSrc));
605 void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
606 MachineBasicBlock &MBB) const {
607 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
608 assert(MBBI != MBB.end() && "Returning block has no terminator");
609 const PPCInstrInfo &TII =
610 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
612 unsigned RetOpcode = MBBI->getOpcode();
615 assert((RetOpcode == PPC::BLR ||
616 RetOpcode == PPC::TCRETURNri ||
617 RetOpcode == PPC::TCRETURNdi ||
618 RetOpcode == PPC::TCRETURNai ||
619 RetOpcode == PPC::TCRETURNri8 ||
620 RetOpcode == PPC::TCRETURNdi8 ||
621 RetOpcode == PPC::TCRETURNai8) &&
622 "Can only insert epilog into returning blocks");
624 // Get alignment info so we know how to restore r1
625 const MachineFrameInfo *MFI = MF.getFrameInfo();
626 unsigned TargetAlign = getStackAlignment();
627 unsigned MaxAlign = MFI->getMaxAlignment();
629 // Get the number of bytes allocated from the FrameInfo.
630 int FrameSize = MFI->getStackSize();
632 // Get processor type.
633 bool isPPC64 = Subtarget.isPPC64();
634 // Get operating system
635 bool isDarwinABI = Subtarget.isDarwinABI();
636 // Check if the link register (LR) has been saved.
637 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
638 bool MustSaveLR = FI->mustSaveLR();
639 // Do we have a frame pointer for this function?
640 bool HasFP = hasFP(MF);
642 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
646 if (Subtarget.isSVR4ABI()) {
647 MachineFrameInfo *FFI = MF.getFrameInfo();
648 int FPIndex = FI->getFramePointerSaveIndex();
649 assert(FPIndex && "No Frame Pointer Save Slot!");
650 FPOffset = FFI->getObjectOffset(FPIndex);
652 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
656 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
657 RetOpcode == PPC::TCRETURNdi ||
658 RetOpcode == PPC::TCRETURNai ||
659 RetOpcode == PPC::TCRETURNri8 ||
660 RetOpcode == PPC::TCRETURNdi8 ||
661 RetOpcode == PPC::TCRETURNai8;
664 int MaxTCRetDelta = FI->getTailCallSPDelta();
665 MachineOperand &StackAdjust = MBBI->getOperand(1);
666 assert(StackAdjust.isImm() && "Expecting immediate value.");
667 // Adjust stack pointer.
668 int StackAdj = StackAdjust.getImm();
669 int Delta = StackAdj - MaxTCRetDelta;
670 assert((Delta >= 0) && "Delta must be positive");
672 FrameSize += (StackAdj +Delta);
674 FrameSize += StackAdj;
678 // The loaded (or persistent) stack pointer value is offset by the 'stwu'
679 // on entry to the function. Add this offset back now.
681 // If this function contained a fastcc call and GuaranteedTailCallOpt is
682 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
683 // call which invalidates the stack pointer value in SP(0). So we use the
684 // value of R31 in this case.
685 if (FI->hasFastCall() && isInt<16>(FrameSize)) {
686 assert(hasFP(MF) && "Expecting a valid the frame pointer.");
687 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
688 .addReg(PPC::R31).addImm(FrameSize);
689 } else if(FI->hasFastCall()) {
690 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
691 .addImm(FrameSize >> 16);
692 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
693 .addReg(PPC::R0, RegState::Kill)
694 .addImm(FrameSize & 0xFFFF);
695 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4))
699 } else if (isInt<16>(FrameSize) &&
700 (!ALIGN_STACK || TargetAlign >= MaxAlign) &&
701 !MFI->hasVarSizedObjects()) {
702 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
703 .addReg(PPC::R1).addImm(FrameSize);
705 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1)
706 .addImm(0).addReg(PPC::R1);
709 if (FI->hasFastCall() && isInt<16>(FrameSize)) {
710 assert(hasFP(MF) && "Expecting a valid the frame pointer.");
711 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
712 .addReg(PPC::X31).addImm(FrameSize);
713 } else if(FI->hasFastCall()) {
714 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
715 .addImm(FrameSize >> 16);
716 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
717 .addReg(PPC::X0, RegState::Kill)
718 .addImm(FrameSize & 0xFFFF);
719 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8))
723 } else if (isInt<16>(FrameSize) && TargetAlign >= MaxAlign &&
724 !MFI->hasVarSizedObjects()) {
725 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
726 .addReg(PPC::X1).addImm(FrameSize);
728 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1)
729 .addImm(0).addReg(PPC::X1);
736 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0)
737 .addImm(LROffset/4).addReg(PPC::X1);
740 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31)
741 .addImm(FPOffset/4).addReg(PPC::X1);
744 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0);
747 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0)
748 .addImm(LROffset).addReg(PPC::R1);
751 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31)
752 .addImm(FPOffset).addReg(PPC::R1);
755 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0);
758 // Callee pop calling convention. Pop parameter/linkage area. Used for tail
760 if (MF.getTarget().Options.GuaranteedTailCallOpt && RetOpcode == PPC::BLR &&
761 MF.getFunction()->getCallingConv() == CallingConv::Fast) {
762 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
763 unsigned CallerAllocatedAmt = FI->getMinReservedArea();
764 unsigned StackReg = isPPC64 ? PPC::X1 : PPC::R1;
765 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
766 unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0;
767 unsigned ADDIInstr = isPPC64 ? PPC::ADDI8 : PPC::ADDI;
768 unsigned ADDInstr = isPPC64 ? PPC::ADD8 : PPC::ADD4;
769 unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS;
770 unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI;
772 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
773 BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg)
774 .addReg(StackReg).addImm(CallerAllocatedAmt);
776 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
777 .addImm(CallerAllocatedAmt >> 16);
778 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
779 .addReg(TmpReg, RegState::Kill)
780 .addImm(CallerAllocatedAmt & 0xFFFF);
781 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
786 } else if (RetOpcode == PPC::TCRETURNdi) {
787 MBBI = MBB.getLastNonDebugInstr();
788 MachineOperand &JumpTarget = MBBI->getOperand(0);
789 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
790 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
791 } else if (RetOpcode == PPC::TCRETURNri) {
792 MBBI = MBB.getLastNonDebugInstr();
793 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
794 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
795 } else if (RetOpcode == PPC::TCRETURNai) {
796 MBBI = MBB.getLastNonDebugInstr();
797 MachineOperand &JumpTarget = MBBI->getOperand(0);
798 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
799 } else if (RetOpcode == PPC::TCRETURNdi8) {
800 MBBI = MBB.getLastNonDebugInstr();
801 MachineOperand &JumpTarget = MBBI->getOperand(0);
802 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
803 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
804 } else if (RetOpcode == PPC::TCRETURNri8) {
805 MBBI = MBB.getLastNonDebugInstr();
806 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
807 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
808 } else if (RetOpcode == PPC::TCRETURNai8) {
809 MBBI = MBB.getLastNonDebugInstr();
810 MachineOperand &JumpTarget = MBBI->getOperand(0);
811 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
815 /// MustSaveLR - Return true if this function requires that we save the LR
816 /// register onto the stack in the prolog and restore it in the epilog of the
818 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
819 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
821 // We need a save/restore of LR if there is any def of LR (which is
822 // defined by calls, including the PIC setup sequence), or if there is
823 // some use of the LR stack slot (e.g. for builtin_return_address).
824 // (LR comes in 32 and 64 bit versions.)
825 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
826 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
830 PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
831 RegScavenger *) const {
832 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
834 // Save and clear the LR state.
835 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
836 unsigned LR = RegInfo->getRARegister();
837 FI->setMustSaveLR(MustSaveLR(MF, LR));
838 MachineRegisterInfo &MRI = MF.getRegInfo();
839 MRI.setPhysRegUnused(LR);
841 // Save R31 if necessary
842 int FPSI = FI->getFramePointerSaveIndex();
843 bool isPPC64 = Subtarget.isPPC64();
844 bool isDarwinABI = Subtarget.isDarwinABI();
845 MachineFrameInfo *MFI = MF.getFrameInfo();
847 // If the frame pointer save index hasn't been defined yet.
848 if (!FPSI && needsFP(MF)) {
849 // Find out what the fix offset of the frame pointer save area.
850 int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI);
851 // Allocate the frame index for frame pointer save area.
852 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
854 FI->setFramePointerSaveIndex(FPSI);
857 // Reserve stack space to move the linkage area to in case of a tail call.
859 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
860 (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
861 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
864 // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
865 // function uses CR 2, 3, or 4.
866 if (!isPPC64 && !isDarwinABI &&
867 (MRI.isPhysRegUsed(PPC::CR2) ||
868 MRI.isPhysRegUsed(PPC::CR3) ||
869 MRI.isPhysRegUsed(PPC::CR4))) {
870 int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true);
871 FI->setCRSpillFrameIndex(FrameIdx);
875 void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
876 RegScavenger *RS) const {
877 // Early exit if not using the SVR4 ABI.
878 if (!Subtarget.isSVR4ABI()) {
879 addScavengingSpillSlot(MF, RS);
883 // Get callee saved register information.
884 MachineFrameInfo *FFI = MF.getFrameInfo();
885 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
887 // Early exit if no callee saved registers are modified!
888 if (CSI.empty() && !needsFP(MF)) {
889 addScavengingSpillSlot(MF, RS);
893 unsigned MinGPR = PPC::R31;
894 unsigned MinG8R = PPC::X31;
895 unsigned MinFPR = PPC::F31;
896 unsigned MinVR = PPC::V31;
898 bool HasGPSaveArea = false;
899 bool HasG8SaveArea = false;
900 bool HasFPSaveArea = false;
901 bool HasVRSAVESaveArea = false;
902 bool HasVRSaveArea = false;
904 SmallVector<CalleeSavedInfo, 18> GPRegs;
905 SmallVector<CalleeSavedInfo, 18> G8Regs;
906 SmallVector<CalleeSavedInfo, 18> FPRegs;
907 SmallVector<CalleeSavedInfo, 18> VRegs;
909 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
910 unsigned Reg = CSI[i].getReg();
911 if (PPC::GPRCRegClass.contains(Reg)) {
912 HasGPSaveArea = true;
914 GPRegs.push_back(CSI[i]);
919 } else if (PPC::G8RCRegClass.contains(Reg)) {
920 HasG8SaveArea = true;
922 G8Regs.push_back(CSI[i]);
927 } else if (PPC::F8RCRegClass.contains(Reg)) {
928 HasFPSaveArea = true;
930 FPRegs.push_back(CSI[i]);
935 } else if (PPC::CRBITRCRegClass.contains(Reg) ||
936 PPC::CRRCRegClass.contains(Reg)) {
937 ; // do nothing, as we already know whether CRs are spilled
938 } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
939 HasVRSAVESaveArea = true;
940 } else if (PPC::VRRCRegClass.contains(Reg)) {
941 HasVRSaveArea = true;
943 VRegs.push_back(CSI[i]);
949 llvm_unreachable("Unknown RegisterClass!");
953 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>();
954 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
956 int64_t LowerBound = 0;
958 // Take into account stack space reserved for tail calls.
960 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
961 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
962 LowerBound = TCSPDelta;
965 // The Floating-point register save area is right below the back chain word
966 // of the previous stack frame.
968 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
969 int FI = FPRegs[i].getFrameIdx();
971 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
974 LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8;
977 // Check whether the frame pointer register is allocated. If so, make sure it
978 // is spilled to the correct offset.
980 HasGPSaveArea = true;
982 int FI = PFI->getFramePointerSaveIndex();
983 assert(FI && "No Frame Pointer Save Slot!");
985 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
988 // General register save area starts right below the Floating-point
989 // register save area.
990 if (HasGPSaveArea || HasG8SaveArea) {
991 // Move general register save area spill slots down, taking into account
992 // the size of the Floating-point register save area.
993 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
994 int FI = GPRegs[i].getFrameIdx();
996 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
999 // Move general register save area spill slots down, taking into account
1000 // the size of the Floating-point register save area.
1001 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
1002 int FI = G8Regs[i].getFrameIdx();
1004 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1008 std::min<unsigned>(TRI->getEncodingValue(MinGPR),
1009 TRI->getEncodingValue(MinG8R));
1011 if (Subtarget.isPPC64()) {
1012 LowerBound -= (31 - MinReg + 1) * 8;
1014 LowerBound -= (31 - MinReg + 1) * 4;
1018 // For 32-bit only, the CR save area is below the general register
1019 // save area. For 64-bit SVR4, the CR save area is addressed relative
1020 // to the stack pointer and hence does not need an adjustment here.
1021 // Only CR2 (the first nonvolatile spilled) has an associated frame
1022 // index so that we have a single uniform save area.
1023 if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) {
1024 // Adjust the frame index of the CR spill slot.
1025 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1026 unsigned Reg = CSI[i].getReg();
1028 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
1029 // Leave Darwin logic as-is.
1030 || (!Subtarget.isSVR4ABI() &&
1031 (PPC::CRBITRCRegClass.contains(Reg) ||
1032 PPC::CRRCRegClass.contains(Reg)))) {
1033 int FI = CSI[i].getFrameIdx();
1035 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1039 LowerBound -= 4; // The CR save area is always 4 bytes long.
1042 if (HasVRSAVESaveArea) {
1043 // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1044 // which have the VRSAVE register class?
1045 // Adjust the frame index of the VRSAVE spill slot.
1046 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1047 unsigned Reg = CSI[i].getReg();
1049 if (PPC::VRSAVERCRegClass.contains(Reg)) {
1050 int FI = CSI[i].getFrameIdx();
1052 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1056 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
1059 if (HasVRSaveArea) {
1060 // Insert alignment padding, we need 16-byte alignment.
1061 LowerBound = (LowerBound - 15) & ~(15);
1063 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
1064 int FI = VRegs[i].getFrameIdx();
1066 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1070 addScavengingSpillSlot(MF, RS);
1074 PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
1075 RegScavenger *RS) const {
1076 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
1077 // a large stack, which will require scavenging a register to materialize a
1080 // We need to have a scavenger spill slot for spills if the frame size is
1081 // large. In case there is no free register for large-offset addressing,
1082 // this slot is used for the necessary emergency spill. Also, we need the
1083 // slot for dynamic stack allocations.
1085 // The scavenger might be invoked if the frame offset does not fit into
1086 // the 16-bit immediate. We don't know the complete frame size here
1087 // because we've not yet computed callee-saved register spills or the
1088 // needed alignment padding.
1089 unsigned StackSize = determineFrameLayout(MF, false, true);
1090 MachineFrameInfo *MFI = MF.getFrameInfo();
1091 if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) ||
1092 hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) {
1093 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1094 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1095 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
1096 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1100 // These kinds of spills might need two registers.
1101 if (spillsCR(MF) || spillsVRSAVE(MF))
1102 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1110 PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1111 MachineBasicBlock::iterator MI,
1112 const std::vector<CalleeSavedInfo> &CSI,
1113 const TargetRegisterInfo *TRI) const {
1115 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1116 // Return false otherwise to maintain pre-existing behavior.
1117 if (!Subtarget.isSVR4ABI())
1120 MachineFunction *MF = MBB.getParent();
1121 const PPCInstrInfo &TII =
1122 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1124 bool CRSpilled = false;
1126 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1127 unsigned Reg = CSI[i].getReg();
1128 // CR2 through CR4 are the nonvolatile CR fields.
1129 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
1131 if (CRSpilled && IsCRField)
1134 // Add the callee-saved register as live-in; it's killed at the spill.
1137 // Insert the spill to the stack frame.
1140 // The first time we see a CR field, store the whole CR into the
1141 // save slot via GPR12 (available in the prolog for 32- and 64-bit).
1142 if (Subtarget.isPPC64()) {
1144 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::X12));
1145 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::STW))
1147 getKillRegState(true))
1151 // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have
1152 // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
1153 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12));
1154 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
1156 getKillRegState(true)),
1157 CSI[i].getFrameIdx()));
1160 // Record that we spill the CR in this function.
1161 PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
1162 FuncInfo->setSpillsCR();
1164 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1165 TII.storeRegToStackSlot(MBB, MI, Reg, true,
1166 CSI[i].getFrameIdx(), RC, TRI);
1173 restoreCRs(bool isPPC64, bool CR2Spilled, bool CR3Spilled, bool CR4Spilled,
1174 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1175 const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
1177 MachineFunction *MF = MBB.getParent();
1178 const PPCInstrInfo &TII =
1179 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1181 unsigned RestoreOp, MoveReg;
1185 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::LWZ), PPC::X12)
1188 RestoreOp = PPC::MTCRF8;
1191 // 32-bit: FP-relative
1192 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
1194 CSI[CSIIndex].getFrameIdx()));
1195 RestoreOp = PPC::MTCRF;
1200 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
1204 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
1208 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
1212 void PPCFrameLowering::
1213 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1214 MachineBasicBlock::iterator I) const {
1215 const PPCInstrInfo &TII =
1216 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
1217 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1218 I->getOpcode() == PPC::ADJCALLSTACKUP) {
1219 // Add (actually subtract) back the amount the callee popped on return.
1220 if (int CalleeAmt = I->getOperand(1).getImm()) {
1221 bool is64Bit = Subtarget.isPPC64();
1223 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
1224 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
1225 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
1226 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
1227 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
1228 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
1229 MachineInstr *MI = I;
1230 DebugLoc dl = MI->getDebugLoc();
1232 if (isInt<16>(CalleeAmt)) {
1233 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
1234 .addReg(StackReg, RegState::Kill)
1237 MachineBasicBlock::iterator MBBI = I;
1238 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
1239 .addImm(CalleeAmt >> 16);
1240 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
1241 .addReg(TmpReg, RegState::Kill)
1242 .addImm(CalleeAmt & 0xFFFF);
1243 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
1244 .addReg(StackReg, RegState::Kill)
1249 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
1254 PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1255 MachineBasicBlock::iterator MI,
1256 const std::vector<CalleeSavedInfo> &CSI,
1257 const TargetRegisterInfo *TRI) const {
1259 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1260 // Return false otherwise to maintain pre-existing behavior.
1261 if (!Subtarget.isSVR4ABI())
1264 MachineFunction *MF = MBB.getParent();
1265 const PPCInstrInfo &TII =
1266 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1267 bool CR2Spilled = false;
1268 bool CR3Spilled = false;
1269 bool CR4Spilled = false;
1270 unsigned CSIIndex = 0;
1272 // Initialize insertion-point logic; we will be restoring in reverse
1274 MachineBasicBlock::iterator I = MI, BeforeI = I;
1275 bool AtStart = I == MBB.begin();
1280 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1281 unsigned Reg = CSI[i].getReg();
1283 if (Reg == PPC::CR2) {
1285 // The spill slot is associated only with CR2, which is the
1286 // first nonvolatile spilled. Save it here.
1289 } else if (Reg == PPC::CR3) {
1292 } else if (Reg == PPC::CR4) {
1296 // When we first encounter a non-CR register after seeing at
1297 // least one CR register, restore all spilled CRs together.
1298 if ((CR2Spilled || CR3Spilled || CR4Spilled)
1299 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1300 restoreCRs(Subtarget.isPPC64(), CR2Spilled, CR3Spilled, CR4Spilled,
1301 MBB, I, CSI, CSIIndex);
1302 CR2Spilled = CR3Spilled = CR4Spilled = false;
1305 // Default behavior for non-CR saves.
1306 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1307 TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(),
1309 assert(I != MBB.begin() &&
1310 "loadRegFromStackSlot didn't insert any code!");
1313 // Insert in reverse order.
1322 // If we haven't yet spilled the CRs, do so now.
1323 if (CR2Spilled || CR3Spilled || CR4Spilled)
1324 restoreCRs(Subtarget.isPPC64(), CR2Spilled, CR3Spilled, CR4Spilled,
1325 MBB, I, CSI, CSIIndex);