1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PPC implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCFrameLowering.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCInstrInfo.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCSubtarget.h"
19 #include "PPCTargetMachine.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineModuleInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/RegisterScavenging.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/Target/TargetOptions.h"
31 /// VRRegNo - Map from a numbered VR register to its enum value.
33 static const uint16_t VRRegNo[] = {
34 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
35 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
36 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
37 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
40 static unsigned computeReturnSaveOffset(const PPCSubtarget &STI) {
41 if (STI.isDarwinABI())
42 return STI.isPPC64() ? 16 : 8;
44 return STI.isPPC64() ? 16 : 4;
47 static unsigned computeTOCSaveOffset(const PPCSubtarget &STI) {
48 return STI.isELFv2ABI() ? 24 : 40;
51 static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI) {
52 // For the Darwin ABI:
53 // We cannot use the TOC save slot (offset +20) in the PowerPC linkage area
54 // for saving the frame pointer (if needed.) While the published ABI has
55 // not used this slot since at least MacOSX 10.2, there is older code
56 // around that does use it, and that needs to continue to work.
57 if (STI.isDarwinABI())
58 return STI.isPPC64() ? -8U : -4U;
60 // SVR4 ABI: First slot in the general register save area.
61 return STI.isPPC64() ? -8U : -4U;
64 static unsigned computeLinkageSize(const PPCSubtarget &STI) {
65 if (STI.isDarwinABI() || STI.isPPC64())
66 return (STI.isELFv2ABI() ? 4 : 6) * (STI.isPPC64() ? 8 : 4);
72 static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI) {
73 if (STI.isDarwinABI())
74 return STI.isPPC64() ? -16U : -8U;
76 // SVR4 ABI: First slot in the general register save area.
79 : (STI.getTargetMachine().getRelocationModel() == Reloc::PIC_)
84 PPCFrameLowering::PPCFrameLowering(const PPCSubtarget &STI)
85 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
86 STI.getPlatformStackAlignment(), 0),
87 Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)),
88 TOCSaveOffset(computeTOCSaveOffset(Subtarget)),
89 FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)),
90 LinkageSize(computeLinkageSize(Subtarget)),
91 BasePointerSaveOffset(computeBasePointerSaveOffset(STI)) {}
93 // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
94 const PPCFrameLowering::SpillSlot *PPCFrameLowering::getCalleeSavedSpillSlots(
95 unsigned &NumEntries) const {
96 if (Subtarget.isDarwinABI()) {
98 if (Subtarget.isPPC64()) {
99 static const SpillSlot darwin64Offsets = {PPC::X31, -8};
100 return &darwin64Offsets;
102 static const SpillSlot darwinOffsets = {PPC::R31, -4};
103 return &darwinOffsets;
107 // Early exit if not using the SVR4 ABI.
108 if (!Subtarget.isSVR4ABI()) {
113 // Note that the offsets here overlap, but this is fixed up in
114 // processFunctionBeforeFrameFinalized.
116 static const SpillSlot Offsets[] = {
117 // Floating-point register save area offsets.
137 // General register save area offsets.
157 // CR save area offset. We map each of the nonvolatile CR fields
158 // to the slot for CR2, which is the first of the nonvolatile CR
159 // fields to be assigned, so that we only allocate one save slot.
160 // See PPCRegisterInfo::hasReservedSpillSlot() for more information.
163 // VRSAVE save area offset.
166 // Vector register save area
180 static const SpillSlot Offsets64[] = {
181 // Floating-point register save area offsets.
201 // General register save area offsets.
221 // VRSAVE save area offset.
224 // Vector register save area
238 if (Subtarget.isPPC64()) {
239 NumEntries = array_lengthof(Offsets64);
243 NumEntries = array_lengthof(Offsets);
249 /// RemoveVRSaveCode - We have found that this function does not need any code
250 /// to manipulate the VRSAVE register, even though it uses vector registers.
251 /// This can happen when the only registers used are known to be live in or out
252 /// of the function. Remove all of the VRSAVE related code from the function.
253 /// FIXME: The removal of the code results in a compile failure at -O0 when the
254 /// function contains a function call, as the GPR containing original VRSAVE
255 /// contents is spilled and reloaded around the call. Without the prolog code,
256 /// the spill instruction refers to an undefined register. This code needs
257 /// to account for all uses of that GPR.
258 static void RemoveVRSaveCode(MachineInstr *MI) {
259 MachineBasicBlock *Entry = MI->getParent();
260 MachineFunction *MF = Entry->getParent();
262 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
263 MachineBasicBlock::iterator MBBI = MI;
265 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
266 MBBI->eraseFromParent();
268 bool RemovedAllMTVRSAVEs = true;
269 // See if we can find and remove the MTVRSAVE instruction from all of the
271 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
272 // If last instruction is a return instruction, add an epilogue
273 if (!I->empty() && I->back().isReturn()) {
274 bool FoundIt = false;
275 for (MBBI = I->end(); MBBI != I->begin(); ) {
277 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
278 MBBI->eraseFromParent(); // remove it.
283 RemovedAllMTVRSAVEs &= FoundIt;
287 // If we found and removed all MTVRSAVE instructions, remove the read of
289 if (RemovedAllMTVRSAVEs) {
291 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
293 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
294 MBBI->eraseFromParent();
297 // Finally, nuke the UPDATE_VRSAVE.
298 MI->eraseFromParent();
301 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
302 // instruction selector. Based on the vector registers that have been used,
303 // transform this into the appropriate ORI instruction.
304 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
305 MachineFunction *MF = MI->getParent()->getParent();
306 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
307 DebugLoc dl = MI->getDebugLoc();
309 const MachineRegisterInfo &MRI = MF->getRegInfo();
310 unsigned UsedRegMask = 0;
311 for (unsigned i = 0; i != 32; ++i)
312 if (MRI.isPhysRegModified(VRRegNo[i]))
313 UsedRegMask |= 1 << (31-i);
315 // Live in and live out values already must be in the mask, so don't bother
317 for (MachineRegisterInfo::livein_iterator
318 I = MF->getRegInfo().livein_begin(),
319 E = MF->getRegInfo().livein_end(); I != E; ++I) {
320 unsigned RegNo = TRI->getEncodingValue(I->first);
321 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
322 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
325 // Live out registers appear as use operands on return instructions.
326 for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end();
327 UsedRegMask != 0 && BI != BE; ++BI) {
328 const MachineBasicBlock &MBB = *BI;
329 if (MBB.empty() || !MBB.back().isReturn())
331 const MachineInstr &Ret = MBB.back();
332 for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) {
333 const MachineOperand &MO = Ret.getOperand(I);
334 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
336 unsigned RegNo = TRI->getEncodingValue(MO.getReg());
337 UsedRegMask &= ~(1 << (31-RegNo));
341 // If no registers are used, turn this into a copy.
342 if (UsedRegMask == 0) {
343 // Remove all VRSAVE code.
344 RemoveVRSaveCode(MI);
348 unsigned SrcReg = MI->getOperand(1).getReg();
349 unsigned DstReg = MI->getOperand(0).getReg();
351 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
352 if (DstReg != SrcReg)
353 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
355 .addImm(UsedRegMask);
357 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
358 .addReg(SrcReg, RegState::Kill)
359 .addImm(UsedRegMask);
360 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
361 if (DstReg != SrcReg)
362 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
364 .addImm(UsedRegMask >> 16);
366 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
367 .addReg(SrcReg, RegState::Kill)
368 .addImm(UsedRegMask >> 16);
370 if (DstReg != SrcReg)
371 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
373 .addImm(UsedRegMask >> 16);
375 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
376 .addReg(SrcReg, RegState::Kill)
377 .addImm(UsedRegMask >> 16);
379 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
380 .addReg(DstReg, RegState::Kill)
381 .addImm(UsedRegMask & 0xFFFF);
384 // Remove the old UPDATE_VRSAVE instruction.
385 MI->eraseFromParent();
388 static bool spillsCR(const MachineFunction &MF) {
389 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
390 return FuncInfo->isCRSpilled();
393 static bool spillsVRSAVE(const MachineFunction &MF) {
394 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
395 return FuncInfo->isVRSAVESpilled();
398 static bool hasSpills(const MachineFunction &MF) {
399 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
400 return FuncInfo->hasSpills();
403 static bool hasNonRISpills(const MachineFunction &MF) {
404 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
405 return FuncInfo->hasNonRISpills();
408 /// MustSaveLR - Return true if this function requires that we save the LR
409 /// register onto the stack in the prolog and restore it in the epilog of the
411 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
412 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
414 // We need a save/restore of LR if there is any def of LR (which is
415 // defined by calls, including the PIC setup sequence), or if there is
416 // some use of the LR stack slot (e.g. for builtin_return_address).
417 // (LR comes in 32 and 64 bit versions.)
418 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
419 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
422 /// determineFrameLayout - Determine the size of the frame and maximum call
424 unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF,
426 bool UseEstimate) const {
427 MachineFrameInfo *MFI = MF.getFrameInfo();
429 // Get the number of bytes to allocate from the FrameInfo
431 UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize();
433 // Get stack alignments. The frame must be aligned to the greatest of these:
434 unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI
435 unsigned MaxAlign = MFI->getMaxAlignment(); // algmt required by data in frame
436 unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1;
438 const PPCRegisterInfo *RegInfo =
439 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
441 // If we are a leaf function, and use up to 224 bytes of stack space,
442 // don't have a frame pointer, calls, or dynamic alloca then we do not need
443 // to adjust the stack pointer (we fit in the Red Zone).
444 // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate
445 // stackless code if all local vars are reg-allocated.
446 bool DisableRedZone = MF.getFunction()->hasFnAttribute(Attribute::NoRedZone);
447 unsigned LR = RegInfo->getRARegister();
448 if (!DisableRedZone &&
449 (Subtarget.isPPC64() || // 32-bit SVR4, no stack-
450 !Subtarget.isSVR4ABI() || // allocated locals.
452 FrameSize <= 224 && // Fits in red zone.
453 !MFI->hasVarSizedObjects() && // No dynamic alloca.
454 !MFI->adjustsStack() && // No calls.
455 !MustSaveLR(MF, LR) &&
456 !RegInfo->hasBasePointer(MF)) { // No special alignment.
459 MFI->setStackSize(0);
463 // Get the maximum call frame size of all the calls.
464 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
466 // Maximum call frame needs to be at least big enough for linkage area.
467 unsigned minCallFrameSize = getLinkageSize();
468 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
470 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
471 // that allocations will be aligned.
472 if (MFI->hasVarSizedObjects())
473 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
475 // Update maximum call frame size.
477 MFI->setMaxCallFrameSize(maxCallFrameSize);
479 // Include call frame size in total.
480 FrameSize += maxCallFrameSize;
482 // Make sure the frame is aligned.
483 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
485 // Update frame info.
487 MFI->setStackSize(FrameSize);
492 // hasFP - Return true if the specified function actually has a dedicated frame
494 bool PPCFrameLowering::hasFP(const MachineFunction &MF) const {
495 const MachineFrameInfo *MFI = MF.getFrameInfo();
496 // FIXME: This is pretty much broken by design: hasFP() might be called really
497 // early, before the stack layout was calculated and thus hasFP() might return
498 // true or false here depending on the time of call.
499 return (MFI->getStackSize()) && needsFP(MF);
502 // needsFP - Return true if the specified function should have a dedicated frame
503 // pointer register. This is true if the function has variable sized allocas or
504 // if frame pointer elimination is disabled.
505 bool PPCFrameLowering::needsFP(const MachineFunction &MF) const {
506 const MachineFrameInfo *MFI = MF.getFrameInfo();
508 // Naked functions have no stack frame pushed, so we don't have a frame
510 if (MF.getFunction()->hasFnAttribute(Attribute::Naked))
513 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
514 MFI->hasVarSizedObjects() ||
515 MFI->hasStackMap() || MFI->hasPatchPoint() ||
516 (MF.getTarget().Options.GuaranteedTailCallOpt &&
517 MF.getInfo<PPCFunctionInfo>()->hasFastCall());
520 void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const {
521 bool is31 = needsFP(MF);
522 unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
523 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
525 const PPCRegisterInfo *RegInfo =
526 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
527 bool HasBP = RegInfo->hasBasePointer(MF);
528 unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg;
529 unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg;
531 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
533 for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) {
535 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
536 MachineOperand &MO = MBBI->getOperand(I);
540 switch (MO.getReg()) {
559 void PPCFrameLowering::emitPrologue(MachineFunction &MF,
560 MachineBasicBlock &MBB) const {
561 assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
562 MachineBasicBlock::iterator MBBI = MBB.begin();
563 MachineFrameInfo *MFI = MF.getFrameInfo();
564 const PPCInstrInfo &TII =
565 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
566 const PPCRegisterInfo *RegInfo =
567 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
569 MachineModuleInfo &MMI = MF.getMMI();
570 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
572 bool needsCFI = MMI.hasDebugInfo() ||
573 MF.getFunction()->needsUnwindTableEntry();
575 // Get processor type.
576 bool isPPC64 = Subtarget.isPPC64();
578 bool isSVR4ABI = Subtarget.isSVR4ABI();
579 bool isELFv2ABI = Subtarget.isELFv2ABI();
580 assert((Subtarget.isDarwinABI() || isSVR4ABI) &&
581 "Currently only Darwin and SVR4 ABIs are supported for PowerPC.");
583 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
586 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
587 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
588 HandleVRSaveUpdate(MBBI, TII);
593 // Move MBBI back to the beginning of the function.
596 // Work out frame sizes.
597 unsigned FrameSize = determineFrameLayout(MF);
598 int NegFrameSize = -FrameSize;
599 if (!isInt<32>(NegFrameSize))
600 llvm_unreachable("Unhandled stack size!");
602 if (MFI->isFrameAddressTaken())
603 replaceFPWithRealFP(MF);
605 // Check if the link register (LR) must be saved.
606 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
607 bool MustSaveLR = FI->mustSaveLR();
608 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
609 // Do we have a frame pointer and/or base pointer for this function?
610 bool HasFP = hasFP(MF);
611 bool HasBP = RegInfo->hasBasePointer(MF);
613 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
614 unsigned BPReg = RegInfo->getBaseRegister(MF);
615 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
616 unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR;
617 unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0;
618 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
619 // ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.)
620 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8
622 const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD
624 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU
626 const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX
628 const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8
630 const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8
632 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
634 const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8
636 const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8
639 // Regarding this assert: Even though LR is saved in the caller's frame (i.e.,
640 // LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no
641 // Red Zone, an asynchronous event (a form of "callee") could claim a frame &
642 // overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR.
643 assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) &&
644 "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
646 int LROffset = getReturnSaveOffset();
651 MachineFrameInfo *FFI = MF.getFrameInfo();
652 int FPIndex = FI->getFramePointerSaveIndex();
653 assert(FPIndex && "No Frame Pointer Save Slot!");
654 FPOffset = FFI->getObjectOffset(FPIndex);
656 FPOffset = getFramePointerSaveOffset();
663 MachineFrameInfo *FFI = MF.getFrameInfo();
664 int BPIndex = FI->getBasePointerSaveIndex();
665 assert(BPIndex && "No Base Pointer Save Slot!");
666 BPOffset = FFI->getObjectOffset(BPIndex);
668 BPOffset = getBasePointerSaveOffset();
673 if (FI->usesPICBase()) {
674 MachineFrameInfo *FFI = MF.getFrameInfo();
675 int PBPIndex = FI->getPICBasePointerSaveIndex();
676 assert(PBPIndex && "No PIC Base Pointer Save Slot!");
677 PBPOffset = FFI->getObjectOffset(PBPIndex);
680 // Get stack alignments.
681 unsigned MaxAlign = MFI->getMaxAlignment();
682 if (HasBP && MaxAlign > 1)
683 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
684 "Invalid alignment!");
686 // Frames of 32KB & larger require special handling because they cannot be
687 // indexed into with a simple STDU/STWU/STD/STW immediate offset operand.
688 bool isLargeFrame = !isInt<16>(NegFrameSize);
691 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
693 assert((isPPC64 || MustSaveCRs.empty()) &&
694 "Prologue CR saving supported only in 64-bit mode");
696 if (!MustSaveCRs.empty()) { // will only occur for PPC64
697 // FIXME: In the ELFv2 ABI, we are not required to save all CR fields.
698 // If only one or two CR fields are clobbered, it could be more
699 // efficient to use mfocrf to selectively save just those fields.
700 MachineInstrBuilder MIB =
701 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg);
702 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
703 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill);
707 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
708 BuildMI(MBB, MBBI, dl, StoreInst)
713 if (FI->usesPICBase())
714 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
715 BuildMI(MBB, MBBI, dl, StoreInst)
721 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
722 BuildMI(MBB, MBBI, dl, StoreInst)
728 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
729 BuildMI(MBB, MBBI, dl, StoreInst)
734 if (!MustSaveCRs.empty()) // will only occur for PPC64
735 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
736 .addReg(TempReg, getKillRegState(true))
740 // Skip the rest if this is a leaf function & all spills fit in the Red Zone.
741 if (!FrameSize) return;
743 // Adjust stack pointer: r1 += NegFrameSize.
744 // If there is a preferred stack alignment, align R1 now
747 // Save a copy of r1 as the base pointer.
748 BuildMI(MBB, MBBI, dl, OrInst, BPReg)
753 if (HasBP && MaxAlign > 1) {
755 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)
758 .addImm(64 - Log2_32(MaxAlign));
760 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)
763 .addImm(32 - Log2_32(MaxAlign))
766 BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg)
767 .addReg(ScratchReg, RegState::Kill)
768 .addImm(NegFrameSize);
770 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg)
771 .addImm(NegFrameSize >> 16);
772 BuildMI(MBB, MBBI, dl, OrImmInst, TempReg)
773 .addReg(TempReg, RegState::Kill)
774 .addImm(NegFrameSize & 0xFFFF);
775 BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg)
776 .addReg(ScratchReg, RegState::Kill)
777 .addReg(TempReg, RegState::Kill);
779 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
780 .addReg(SPReg, RegState::Kill)
784 } else if (!isLargeFrame) {
785 BuildMI(MBB, MBBI, dl, StoreUpdtInst, SPReg)
787 .addImm(NegFrameSize)
791 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
792 .addImm(NegFrameSize >> 16);
793 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
794 .addReg(ScratchReg, RegState::Kill)
795 .addImm(NegFrameSize & 0xFFFF);
796 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
797 .addReg(SPReg, RegState::Kill)
802 // Add Call Frame Information for the instructions we generated above.
807 // Define CFA in terms of BP. Do this in preference to using FP/SP,
808 // because if the stack needed aligning then CFA won't be at a fixed
809 // offset from FP/SP.
810 unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
811 CFIIndex = MMI.addFrameInst(
812 MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
814 // Adjust the definition of CFA to account for the change in SP.
815 assert(NegFrameSize);
816 CFIIndex = MMI.addFrameInst(
817 MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize));
819 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
820 .addCFIIndex(CFIIndex);
823 // Describe where FP was saved, at a fixed offset from CFA.
824 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
825 CFIIndex = MMI.addFrameInst(
826 MCCFIInstruction::createOffset(nullptr, Reg, FPOffset));
827 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
828 .addCFIIndex(CFIIndex);
831 if (FI->usesPICBase()) {
832 // Describe where FP was saved, at a fixed offset from CFA.
833 unsigned Reg = MRI->getDwarfRegNum(PPC::R30, true);
834 CFIIndex = MMI.addFrameInst(
835 MCCFIInstruction::createOffset(nullptr, Reg, PBPOffset));
836 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
837 .addCFIIndex(CFIIndex);
841 // Describe where BP was saved, at a fixed offset from CFA.
842 unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
843 CFIIndex = MMI.addFrameInst(
844 MCCFIInstruction::createOffset(nullptr, Reg, BPOffset));
845 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
846 .addCFIIndex(CFIIndex);
850 // Describe where LR was saved, at a fixed offset from CFA.
851 unsigned Reg = MRI->getDwarfRegNum(LRReg, true);
852 CFIIndex = MMI.addFrameInst(
853 MCCFIInstruction::createOffset(nullptr, Reg, LROffset));
854 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
855 .addCFIIndex(CFIIndex);
859 // If there is a frame pointer, copy R1 into R31
861 BuildMI(MBB, MBBI, dl, OrInst, FPReg)
865 if (!HasBP && needsCFI) {
866 // Change the definition of CFA from SP+offset to FP+offset, because SP
867 // will change at every alloca.
868 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
869 unsigned CFIIndex = MMI.addFrameInst(
870 MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
872 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
873 .addCFIIndex(CFIIndex);
878 // Describe where callee saved registers were saved, at fixed offsets from
880 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
881 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
882 unsigned Reg = CSI[I].getReg();
883 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
885 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
886 // subregisters of CR2. We just need to emit a move of CR2.
887 if (PPC::CRBITRCRegClass.contains(Reg))
890 // For SVR4, don't emit a move for the CR spill slot if we haven't
892 if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
893 && MustSaveCRs.empty())
896 // For 64-bit SVR4 when we have spilled CRs, the spill location
897 // is SP+8, not a frame-relative slot.
898 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
899 // In the ELFv1 ABI, only CR2 is noted in CFI and stands in for
900 // the whole CR word. In the ELFv2 ABI, every CR that was
901 // actually saved gets its own CFI record.
902 unsigned CRReg = isELFv2ABI? Reg : (unsigned) PPC::CR2;
903 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
904 nullptr, MRI->getDwarfRegNum(CRReg, true), 8));
905 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
906 .addCFIIndex(CFIIndex);
910 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
911 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
912 nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
913 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
914 .addCFIIndex(CFIIndex);
919 void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
920 MachineBasicBlock &MBB) const {
921 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
922 assert(MBBI != MBB.end() && "Returning block has no terminator");
923 const PPCInstrInfo &TII =
924 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
925 const PPCRegisterInfo *RegInfo =
926 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
928 unsigned RetOpcode = MBBI->getOpcode();
931 assert((RetOpcode == PPC::BLR ||
932 RetOpcode == PPC::BLR8 ||
933 RetOpcode == PPC::TCRETURNri ||
934 RetOpcode == PPC::TCRETURNdi ||
935 RetOpcode == PPC::TCRETURNai ||
936 RetOpcode == PPC::TCRETURNri8 ||
937 RetOpcode == PPC::TCRETURNdi8 ||
938 RetOpcode == PPC::TCRETURNai8) &&
939 "Can only insert epilog into returning blocks");
941 // Get alignment info so we know how to restore the SP.
942 const MachineFrameInfo *MFI = MF.getFrameInfo();
944 // Get the number of bytes allocated from the FrameInfo.
945 int FrameSize = MFI->getStackSize();
947 // Get processor type.
948 bool isPPC64 = Subtarget.isPPC64();
950 bool isSVR4ABI = Subtarget.isSVR4ABI();
952 // Check if the link register (LR) has been saved.
953 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
954 bool MustSaveLR = FI->mustSaveLR();
955 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
956 // Do we have a frame pointer and/or base pointer for this function?
957 bool HasFP = hasFP(MF);
958 bool HasBP = RegInfo->hasBasePointer(MF);
960 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
961 unsigned BPReg = RegInfo->getBaseRegister(MF);
962 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
963 unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0;
964 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
965 const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8
967 const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD
969 const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8
971 const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8
973 const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8
975 const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8
978 int LROffset = getReturnSaveOffset();
983 MachineFrameInfo *FFI = MF.getFrameInfo();
984 int FPIndex = FI->getFramePointerSaveIndex();
985 assert(FPIndex && "No Frame Pointer Save Slot!");
986 FPOffset = FFI->getObjectOffset(FPIndex);
988 FPOffset = getFramePointerSaveOffset();
995 MachineFrameInfo *FFI = MF.getFrameInfo();
996 int BPIndex = FI->getBasePointerSaveIndex();
997 assert(BPIndex && "No Base Pointer Save Slot!");
998 BPOffset = FFI->getObjectOffset(BPIndex);
1000 BPOffset = getBasePointerSaveOffset();
1005 if (FI->usesPICBase()) {
1006 MachineFrameInfo *FFI = MF.getFrameInfo();
1007 int PBPIndex = FI->getPICBasePointerSaveIndex();
1008 assert(PBPIndex && "No PIC Base Pointer Save Slot!");
1009 PBPOffset = FFI->getObjectOffset(PBPIndex);
1012 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
1013 RetOpcode == PPC::TCRETURNdi ||
1014 RetOpcode == PPC::TCRETURNai ||
1015 RetOpcode == PPC::TCRETURNri8 ||
1016 RetOpcode == PPC::TCRETURNdi8 ||
1017 RetOpcode == PPC::TCRETURNai8;
1020 int MaxTCRetDelta = FI->getTailCallSPDelta();
1021 MachineOperand &StackAdjust = MBBI->getOperand(1);
1022 assert(StackAdjust.isImm() && "Expecting immediate value.");
1023 // Adjust stack pointer.
1024 int StackAdj = StackAdjust.getImm();
1025 int Delta = StackAdj - MaxTCRetDelta;
1026 assert((Delta >= 0) && "Delta must be positive");
1027 if (MaxTCRetDelta>0)
1028 FrameSize += (StackAdj +Delta);
1030 FrameSize += StackAdj;
1033 // Frames of 32KB & larger require special handling because they cannot be
1034 // indexed into with a simple LD/LWZ immediate offset operand.
1035 bool isLargeFrame = !isInt<16>(FrameSize);
1038 // In the prologue, the loaded (or persistent) stack pointer value is offset
1039 // by the STDU/STDUX/STWU/STWUX instruction. Add this offset back now.
1041 // If this function contained a fastcc call and GuaranteedTailCallOpt is
1042 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
1043 // call which invalidates the stack pointer value in SP(0). So we use the
1044 // value of R31 in this case.
1045 if (FI->hasFastCall()) {
1046 assert(HasFP && "Expecting a valid frame pointer.");
1047 if (!isLargeFrame) {
1048 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1049 .addReg(FPReg).addImm(FrameSize);
1051 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1052 .addImm(FrameSize >> 16);
1053 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1054 .addReg(ScratchReg, RegState::Kill)
1055 .addImm(FrameSize & 0xFFFF);
1056 BuildMI(MBB, MBBI, dl, AddInst)
1059 .addReg(ScratchReg);
1061 } else if (!isLargeFrame && !HasBP && !MFI->hasVarSizedObjects()) {
1062 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1066 BuildMI(MBB, MBBI, dl, LoadInst, SPReg)
1074 BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
1078 assert((isPPC64 || MustSaveCRs.empty()) &&
1079 "Epilogue CR restoring supported only in 64-bit mode");
1081 if (!MustSaveCRs.empty()) // will only occur for PPC64
1082 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
1087 BuildMI(MBB, MBBI, dl, LoadInst, FPReg)
1091 if (FI->usesPICBase())
1092 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
1093 BuildMI(MBB, MBBI, dl, LoadInst)
1099 BuildMI(MBB, MBBI, dl, LoadInst, BPReg)
1103 if (!MustSaveCRs.empty()) // will only occur for PPC64
1104 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
1105 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
1106 .addReg(TempReg, getKillRegState(i == e-1));
1109 BuildMI(MBB, MBBI, dl, MTLRInst).addReg(ScratchReg);
1111 // Callee pop calling convention. Pop parameter/linkage area. Used for tail
1112 // call optimization
1113 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1114 (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) &&
1115 MF.getFunction()->getCallingConv() == CallingConv::Fast) {
1116 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1117 unsigned CallerAllocatedAmt = FI->getMinReservedArea();
1119 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
1120 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1121 .addReg(SPReg).addImm(CallerAllocatedAmt);
1123 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1124 .addImm(CallerAllocatedAmt >> 16);
1125 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1126 .addReg(ScratchReg, RegState::Kill)
1127 .addImm(CallerAllocatedAmt & 0xFFFF);
1128 BuildMI(MBB, MBBI, dl, AddInst)
1131 .addReg(ScratchReg);
1133 } else if (RetOpcode == PPC::TCRETURNdi) {
1134 MBBI = MBB.getLastNonDebugInstr();
1135 MachineOperand &JumpTarget = MBBI->getOperand(0);
1136 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
1137 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1138 } else if (RetOpcode == PPC::TCRETURNri) {
1139 MBBI = MBB.getLastNonDebugInstr();
1140 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1141 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
1142 } else if (RetOpcode == PPC::TCRETURNai) {
1143 MBBI = MBB.getLastNonDebugInstr();
1144 MachineOperand &JumpTarget = MBBI->getOperand(0);
1145 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
1146 } else if (RetOpcode == PPC::TCRETURNdi8) {
1147 MBBI = MBB.getLastNonDebugInstr();
1148 MachineOperand &JumpTarget = MBBI->getOperand(0);
1149 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
1150 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1151 } else if (RetOpcode == PPC::TCRETURNri8) {
1152 MBBI = MBB.getLastNonDebugInstr();
1153 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1154 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
1155 } else if (RetOpcode == PPC::TCRETURNai8) {
1156 MBBI = MBB.getLastNonDebugInstr();
1157 MachineOperand &JumpTarget = MBBI->getOperand(0);
1158 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
1162 void PPCFrameLowering::determineCalleeSaves(MachineFunction &MF,
1163 BitVector &SavedRegs,
1164 RegScavenger *RS) const {
1165 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
1167 const PPCRegisterInfo *RegInfo =
1168 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
1170 // Save and clear the LR state.
1171 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1172 unsigned LR = RegInfo->getRARegister();
1173 FI->setMustSaveLR(MustSaveLR(MF, LR));
1174 SavedRegs.reset(LR);
1176 // Save R31 if necessary
1177 int FPSI = FI->getFramePointerSaveIndex();
1178 bool isPPC64 = Subtarget.isPPC64();
1179 bool isDarwinABI = Subtarget.isDarwinABI();
1180 MachineFrameInfo *MFI = MF.getFrameInfo();
1182 // If the frame pointer save index hasn't been defined yet.
1183 if (!FPSI && needsFP(MF)) {
1184 // Find out what the fix offset of the frame pointer save area.
1185 int FPOffset = getFramePointerSaveOffset();
1186 // Allocate the frame index for frame pointer save area.
1187 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
1189 FI->setFramePointerSaveIndex(FPSI);
1192 int BPSI = FI->getBasePointerSaveIndex();
1193 if (!BPSI && RegInfo->hasBasePointer(MF)) {
1194 int BPOffset = getBasePointerSaveOffset();
1195 // Allocate the frame index for the base pointer save area.
1196 BPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, BPOffset, true);
1198 FI->setBasePointerSaveIndex(BPSI);
1201 // Reserve stack space for the PIC Base register (R30).
1202 // Only used in SVR4 32-bit.
1203 if (FI->usesPICBase()) {
1204 int PBPSI = FI->getPICBasePointerSaveIndex();
1205 PBPSI = MFI->CreateFixedObject(4, -8, true);
1206 FI->setPICBasePointerSaveIndex(PBPSI);
1209 // Reserve stack space to move the linkage area to in case of a tail call.
1211 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1212 (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
1213 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
1216 // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
1217 // function uses CR 2, 3, or 4.
1218 if (!isPPC64 && !isDarwinABI &&
1219 (SavedRegs.test(PPC::CR2) ||
1220 SavedRegs.test(PPC::CR3) ||
1221 SavedRegs.test(PPC::CR4))) {
1222 int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true);
1223 FI->setCRSpillFrameIndex(FrameIdx);
1227 void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
1228 RegScavenger *RS) const {
1229 // Early exit if not using the SVR4 ABI.
1230 if (!Subtarget.isSVR4ABI()) {
1231 addScavengingSpillSlot(MF, RS);
1235 // Get callee saved register information.
1236 MachineFrameInfo *FFI = MF.getFrameInfo();
1237 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
1239 // Early exit if no callee saved registers are modified!
1240 if (CSI.empty() && !needsFP(MF)) {
1241 addScavengingSpillSlot(MF, RS);
1245 unsigned MinGPR = PPC::R31;
1246 unsigned MinG8R = PPC::X31;
1247 unsigned MinFPR = PPC::F31;
1248 unsigned MinVR = PPC::V31;
1250 bool HasGPSaveArea = false;
1251 bool HasG8SaveArea = false;
1252 bool HasFPSaveArea = false;
1253 bool HasVRSAVESaveArea = false;
1254 bool HasVRSaveArea = false;
1256 SmallVector<CalleeSavedInfo, 18> GPRegs;
1257 SmallVector<CalleeSavedInfo, 18> G8Regs;
1258 SmallVector<CalleeSavedInfo, 18> FPRegs;
1259 SmallVector<CalleeSavedInfo, 18> VRegs;
1261 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1262 unsigned Reg = CSI[i].getReg();
1263 if (PPC::GPRCRegClass.contains(Reg)) {
1264 HasGPSaveArea = true;
1266 GPRegs.push_back(CSI[i]);
1271 } else if (PPC::G8RCRegClass.contains(Reg)) {
1272 HasG8SaveArea = true;
1274 G8Regs.push_back(CSI[i]);
1279 } else if (PPC::F8RCRegClass.contains(Reg)) {
1280 HasFPSaveArea = true;
1282 FPRegs.push_back(CSI[i]);
1287 } else if (PPC::CRBITRCRegClass.contains(Reg) ||
1288 PPC::CRRCRegClass.contains(Reg)) {
1289 ; // do nothing, as we already know whether CRs are spilled
1290 } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1291 HasVRSAVESaveArea = true;
1292 } else if (PPC::VRRCRegClass.contains(Reg)) {
1293 HasVRSaveArea = true;
1295 VRegs.push_back(CSI[i]);
1301 llvm_unreachable("Unknown RegisterClass!");
1305 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>();
1306 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1308 int64_t LowerBound = 0;
1310 // Take into account stack space reserved for tail calls.
1312 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1313 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
1314 LowerBound = TCSPDelta;
1317 // The Floating-point register save area is right below the back chain word
1318 // of the previous stack frame.
1319 if (HasFPSaveArea) {
1320 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
1321 int FI = FPRegs[i].getFrameIdx();
1323 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1326 LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8;
1329 // Check whether the frame pointer register is allocated. If so, make sure it
1330 // is spilled to the correct offset.
1332 HasGPSaveArea = true;
1334 int FI = PFI->getFramePointerSaveIndex();
1335 assert(FI && "No Frame Pointer Save Slot!");
1337 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1340 if (PFI->usesPICBase()) {
1341 HasGPSaveArea = true;
1343 int FI = PFI->getPICBasePointerSaveIndex();
1344 assert(FI && "No PIC Base Pointer Save Slot!");
1346 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1349 const PPCRegisterInfo *RegInfo =
1350 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
1351 if (RegInfo->hasBasePointer(MF)) {
1352 HasGPSaveArea = true;
1354 int FI = PFI->getBasePointerSaveIndex();
1355 assert(FI && "No Base Pointer Save Slot!");
1357 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1360 // General register save area starts right below the Floating-point
1361 // register save area.
1362 if (HasGPSaveArea || HasG8SaveArea) {
1363 // Move general register save area spill slots down, taking into account
1364 // the size of the Floating-point register save area.
1365 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
1366 int FI = GPRegs[i].getFrameIdx();
1368 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1371 // Move general register save area spill slots down, taking into account
1372 // the size of the Floating-point register save area.
1373 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
1374 int FI = G8Regs[i].getFrameIdx();
1376 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1380 std::min<unsigned>(TRI->getEncodingValue(MinGPR),
1381 TRI->getEncodingValue(MinG8R));
1383 if (Subtarget.isPPC64()) {
1384 LowerBound -= (31 - MinReg + 1) * 8;
1386 LowerBound -= (31 - MinReg + 1) * 4;
1390 // For 32-bit only, the CR save area is below the general register
1391 // save area. For 64-bit SVR4, the CR save area is addressed relative
1392 // to the stack pointer and hence does not need an adjustment here.
1393 // Only CR2 (the first nonvolatile spilled) has an associated frame
1394 // index so that we have a single uniform save area.
1395 if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) {
1396 // Adjust the frame index of the CR spill slot.
1397 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1398 unsigned Reg = CSI[i].getReg();
1400 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
1401 // Leave Darwin logic as-is.
1402 || (!Subtarget.isSVR4ABI() &&
1403 (PPC::CRBITRCRegClass.contains(Reg) ||
1404 PPC::CRRCRegClass.contains(Reg)))) {
1405 int FI = CSI[i].getFrameIdx();
1407 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1411 LowerBound -= 4; // The CR save area is always 4 bytes long.
1414 if (HasVRSAVESaveArea) {
1415 // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1416 // which have the VRSAVE register class?
1417 // Adjust the frame index of the VRSAVE spill slot.
1418 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1419 unsigned Reg = CSI[i].getReg();
1421 if (PPC::VRSAVERCRegClass.contains(Reg)) {
1422 int FI = CSI[i].getFrameIdx();
1424 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1428 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
1431 if (HasVRSaveArea) {
1432 // Insert alignment padding, we need 16-byte alignment.
1433 LowerBound = (LowerBound - 15) & ~(15);
1435 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
1436 int FI = VRegs[i].getFrameIdx();
1438 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1442 addScavengingSpillSlot(MF, RS);
1446 PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
1447 RegScavenger *RS) const {
1448 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
1449 // a large stack, which will require scavenging a register to materialize a
1452 // We need to have a scavenger spill slot for spills if the frame size is
1453 // large. In case there is no free register for large-offset addressing,
1454 // this slot is used for the necessary emergency spill. Also, we need the
1455 // slot for dynamic stack allocations.
1457 // The scavenger might be invoked if the frame offset does not fit into
1458 // the 16-bit immediate. We don't know the complete frame size here
1459 // because we've not yet computed callee-saved register spills or the
1460 // needed alignment padding.
1461 unsigned StackSize = determineFrameLayout(MF, false, true);
1462 MachineFrameInfo *MFI = MF.getFrameInfo();
1463 if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) ||
1464 hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) {
1465 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1466 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1467 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
1468 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1472 // Might we have over-aligned allocas?
1473 bool HasAlVars = MFI->hasVarSizedObjects() &&
1474 MFI->getMaxAlignment() > getStackAlignment();
1476 // These kinds of spills might need two registers.
1477 if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars)
1478 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1486 PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1487 MachineBasicBlock::iterator MI,
1488 const std::vector<CalleeSavedInfo> &CSI,
1489 const TargetRegisterInfo *TRI) const {
1491 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1492 // Return false otherwise to maintain pre-existing behavior.
1493 if (!Subtarget.isSVR4ABI())
1496 MachineFunction *MF = MBB.getParent();
1497 const PPCInstrInfo &TII =
1498 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
1500 bool CRSpilled = false;
1501 MachineInstrBuilder CRMIB;
1503 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1504 unsigned Reg = CSI[i].getReg();
1505 // Only Darwin actually uses the VRSAVE register, but it can still appear
1506 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1507 // Darwin, ignore it.
1508 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1511 // CR2 through CR4 are the nonvolatile CR fields.
1512 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
1514 // Add the callee-saved register as live-in; it's killed at the spill.
1517 if (CRSpilled && IsCRField) {
1518 CRMIB.addReg(Reg, RegState::ImplicitKill);
1522 // Insert the spill to the stack frame.
1524 PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
1525 if (Subtarget.isPPC64()) {
1526 // The actual spill will happen at the start of the prologue.
1527 FuncInfo->addMustSaveCR(Reg);
1530 FuncInfo->setSpillsCR();
1532 // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have
1533 // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
1534 CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
1535 .addReg(Reg, RegState::ImplicitKill);
1537 MBB.insert(MI, CRMIB);
1538 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
1540 getKillRegState(true)),
1541 CSI[i].getFrameIdx()));
1544 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1545 TII.storeRegToStackSlot(MBB, MI, Reg, true,
1546 CSI[i].getFrameIdx(), RC, TRI);
1553 restoreCRs(bool isPPC64, bool is31,
1554 bool CR2Spilled, bool CR3Spilled, bool CR4Spilled,
1555 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1556 const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
1558 MachineFunction *MF = MBB.getParent();
1559 const PPCInstrInfo &TII = *MF->getSubtarget<PPCSubtarget>().getInstrInfo();
1561 unsigned RestoreOp, MoveReg;
1564 // This is handled during epilogue generation.
1567 // 32-bit: FP-relative
1568 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
1570 CSI[CSIIndex].getFrameIdx()));
1571 RestoreOp = PPC::MTOCRF;
1576 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
1577 .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled)));
1580 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
1581 .addReg(MoveReg, getKillRegState(!CR4Spilled)));
1584 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
1585 .addReg(MoveReg, getKillRegState(true)));
1588 void PPCFrameLowering::
1589 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1590 MachineBasicBlock::iterator I) const {
1591 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1592 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1593 I->getOpcode() == PPC::ADJCALLSTACKUP) {
1594 // Add (actually subtract) back the amount the callee popped on return.
1595 if (int CalleeAmt = I->getOperand(1).getImm()) {
1596 bool is64Bit = Subtarget.isPPC64();
1598 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
1599 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
1600 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
1601 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
1602 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
1603 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
1604 MachineInstr *MI = I;
1605 DebugLoc dl = MI->getDebugLoc();
1607 if (isInt<16>(CalleeAmt)) {
1608 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
1609 .addReg(StackReg, RegState::Kill)
1612 MachineBasicBlock::iterator MBBI = I;
1613 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
1614 .addImm(CalleeAmt >> 16);
1615 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
1616 .addReg(TmpReg, RegState::Kill)
1617 .addImm(CalleeAmt & 0xFFFF);
1618 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
1619 .addReg(StackReg, RegState::Kill)
1624 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
1629 PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1630 MachineBasicBlock::iterator MI,
1631 const std::vector<CalleeSavedInfo> &CSI,
1632 const TargetRegisterInfo *TRI) const {
1634 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1635 // Return false otherwise to maintain pre-existing behavior.
1636 if (!Subtarget.isSVR4ABI())
1639 MachineFunction *MF = MBB.getParent();
1640 const PPCInstrInfo &TII =
1641 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
1642 bool CR2Spilled = false;
1643 bool CR3Spilled = false;
1644 bool CR4Spilled = false;
1645 unsigned CSIIndex = 0;
1647 // Initialize insertion-point logic; we will be restoring in reverse
1649 MachineBasicBlock::iterator I = MI, BeforeI = I;
1650 bool AtStart = I == MBB.begin();
1655 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1656 unsigned Reg = CSI[i].getReg();
1658 // Only Darwin actually uses the VRSAVE register, but it can still appear
1659 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1660 // Darwin, ignore it.
1661 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1664 if (Reg == PPC::CR2) {
1666 // The spill slot is associated only with CR2, which is the
1667 // first nonvolatile spilled. Save it here.
1670 } else if (Reg == PPC::CR3) {
1673 } else if (Reg == PPC::CR4) {
1677 // When we first encounter a non-CR register after seeing at
1678 // least one CR register, restore all spilled CRs together.
1679 if ((CR2Spilled || CR3Spilled || CR4Spilled)
1680 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1681 bool is31 = needsFP(*MF);
1682 restoreCRs(Subtarget.isPPC64(), is31,
1683 CR2Spilled, CR3Spilled, CR4Spilled,
1684 MBB, I, CSI, CSIIndex);
1685 CR2Spilled = CR3Spilled = CR4Spilled = false;
1688 // Default behavior for non-CR saves.
1689 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1690 TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(),
1692 assert(I != MBB.begin() &&
1693 "loadRegFromStackSlot didn't insert any code!");
1696 // Insert in reverse order.
1705 // If we haven't yet spilled the CRs, do so now.
1706 if (CR2Spilled || CR3Spilled || CR4Spilled) {
1707 bool is31 = needsFP(*MF);
1708 restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled,
1709 MBB, I, CSI, CSIIndex);