1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PPC implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCFrameLowering.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCInstrInfo.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/IR/Function.h"
25 #include "llvm/Target/TargetOptions.h"
29 // FIXME This disables some code that aligns the stack to a boundary bigger than
30 // the default (16 bytes on Darwin) when there is a stack local of greater
31 // alignment. This does not currently work, because the delta between old and
32 // new stack pointers is added to offsets that reference incoming parameters
33 // after the prolog is generated, and the code that does that doesn't handle a
34 // variable delta. You don't want to do that anyway; a better approach is to
35 // reserve another register that retains to the incoming stack pointer, and
36 // reference parameters relative to that.
40 /// VRRegNo - Map from a numbered VR register to its enum value.
42 static const uint16_t VRRegNo[] = {
43 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
44 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
45 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
46 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
49 /// RemoveVRSaveCode - We have found that this function does not need any code
50 /// to manipulate the VRSAVE register, even though it uses vector registers.
51 /// This can happen when the only registers used are known to be live in or out
52 /// of the function. Remove all of the VRSAVE related code from the function.
53 /// FIXME: The removal of the code results in a compile failure at -O0 when the
54 /// function contains a function call, as the GPR containing original VRSAVE
55 /// contents is spilled and reloaded around the call. Without the prolog code,
56 /// the spill instruction refers to an undefined register. This code needs
57 /// to account for all uses of that GPR.
58 static void RemoveVRSaveCode(MachineInstr *MI) {
59 MachineBasicBlock *Entry = MI->getParent();
60 MachineFunction *MF = Entry->getParent();
62 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
63 MachineBasicBlock::iterator MBBI = MI;
65 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
66 MBBI->eraseFromParent();
68 bool RemovedAllMTVRSAVEs = true;
69 // See if we can find and remove the MTVRSAVE instruction from all of the
71 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
72 // If last instruction is a return instruction, add an epilogue
73 if (!I->empty() && I->back().isReturn()) {
75 for (MBBI = I->end(); MBBI != I->begin(); ) {
77 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
78 MBBI->eraseFromParent(); // remove it.
83 RemovedAllMTVRSAVEs &= FoundIt;
87 // If we found and removed all MTVRSAVE instructions, remove the read of
89 if (RemovedAllMTVRSAVEs) {
91 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
93 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
94 MBBI->eraseFromParent();
97 // Finally, nuke the UPDATE_VRSAVE.
98 MI->eraseFromParent();
101 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
102 // instruction selector. Based on the vector registers that have been used,
103 // transform this into the appropriate ORI instruction.
104 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
105 MachineFunction *MF = MI->getParent()->getParent();
106 DebugLoc dl = MI->getDebugLoc();
108 unsigned UsedRegMask = 0;
109 for (unsigned i = 0; i != 32; ++i)
110 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
111 UsedRegMask |= 1 << (31-i);
113 // Live in and live out values already must be in the mask, so don't bother
115 for (MachineRegisterInfo::livein_iterator
116 I = MF->getRegInfo().livein_begin(),
117 E = MF->getRegInfo().livein_end(); I != E; ++I) {
118 unsigned RegNo = getPPCRegisterNumbering(I->first);
119 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
120 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
123 // Live out registers appear as use operands on return instructions.
124 for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end();
125 UsedRegMask != 0 && BI != BE; ++BI) {
126 const MachineBasicBlock &MBB = *BI;
127 if (MBB.empty() || !MBB.back().isReturn())
129 const MachineInstr &Ret = MBB.back();
130 for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) {
131 const MachineOperand &MO = Ret.getOperand(I);
132 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
134 unsigned RegNo = getPPCRegisterNumbering(MO.getReg());
135 UsedRegMask &= ~(1 << (31-RegNo));
139 // If no registers are used, turn this into a copy.
140 if (UsedRegMask == 0) {
141 // Remove all VRSAVE code.
142 RemoveVRSaveCode(MI);
146 unsigned SrcReg = MI->getOperand(1).getReg();
147 unsigned DstReg = MI->getOperand(0).getReg();
149 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
150 if (DstReg != SrcReg)
151 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
153 .addImm(UsedRegMask);
155 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
156 .addReg(SrcReg, RegState::Kill)
157 .addImm(UsedRegMask);
158 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
159 if (DstReg != SrcReg)
160 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
162 .addImm(UsedRegMask >> 16);
164 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
165 .addReg(SrcReg, RegState::Kill)
166 .addImm(UsedRegMask >> 16);
168 if (DstReg != SrcReg)
169 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
171 .addImm(UsedRegMask >> 16);
173 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
174 .addReg(SrcReg, RegState::Kill)
175 .addImm(UsedRegMask >> 16);
177 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
178 .addReg(DstReg, RegState::Kill)
179 .addImm(UsedRegMask & 0xFFFF);
182 // Remove the old UPDATE_VRSAVE instruction.
183 MI->eraseFromParent();
186 static bool spillsCR(const MachineFunction &MF) {
187 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
188 return FuncInfo->isCRSpilled();
191 /// determineFrameLayout - Determine the size of the frame and maximum call
193 void PPCFrameLowering::determineFrameLayout(MachineFunction &MF) const {
194 MachineFrameInfo *MFI = MF.getFrameInfo();
196 // Get the number of bytes to allocate from the FrameInfo
197 unsigned FrameSize = MFI->getStackSize();
199 // Get the alignments provided by the target, and the maximum alignment
200 // (if any) of the fixed frame objects.
201 unsigned MaxAlign = MFI->getMaxAlignment();
202 unsigned TargetAlign = getStackAlignment();
203 unsigned AlignMask = TargetAlign - 1; //
205 // If we are a leaf function, and use up to 224 bytes of stack space,
206 // don't have a frame pointer, calls, or dynamic alloca then we do not need
207 // to adjust the stack pointer (we fit in the Red Zone). For 64-bit
208 // SVR4, we also require a stack frame if we need to spill the CR,
209 // since this spill area is addressed relative to the stack pointer.
210 bool DisableRedZone = MF.getFunction()->getAttributes().
211 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoRedZone);
212 // FIXME SVR4 The 32-bit SVR4 ABI has no red zone. However, it can
213 // still generate stackless code if all local vars are reg-allocated.
214 // Try: (FrameSize <= 224
215 // || (FrameSize == 0 && Subtarget.isPPC32 && Subtarget.isSVR4ABI()))
216 if (!DisableRedZone &&
217 FrameSize <= 224 && // Fits in red zone.
218 !MFI->hasVarSizedObjects() && // No dynamic alloca.
219 !MFI->adjustsStack() && // No calls.
220 !(Subtarget.isPPC64() && // No 64-bit SVR4 CRsave.
221 Subtarget.isSVR4ABI()
223 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment.
225 MFI->setStackSize(0);
229 // Get the maximum call frame size of all the calls.
230 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
232 // Maximum call frame needs to be at least big enough for linkage and 8 args.
233 unsigned minCallFrameSize = getMinCallFrameSize(Subtarget.isPPC64(),
234 Subtarget.isDarwinABI());
235 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
237 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
238 // that allocations will be aligned.
239 if (MFI->hasVarSizedObjects())
240 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
242 // Update maximum call frame size.
243 MFI->setMaxCallFrameSize(maxCallFrameSize);
245 // Include call frame size in total.
246 FrameSize += maxCallFrameSize;
248 // Make sure the frame is aligned.
249 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
251 // Update frame info.
252 MFI->setStackSize(FrameSize);
255 // hasFP - Return true if the specified function actually has a dedicated frame
257 bool PPCFrameLowering::hasFP(const MachineFunction &MF) const {
258 const MachineFrameInfo *MFI = MF.getFrameInfo();
259 // FIXME: This is pretty much broken by design: hasFP() might be called really
260 // early, before the stack layout was calculated and thus hasFP() might return
261 // true or false here depending on the time of call.
262 return (MFI->getStackSize()) && needsFP(MF);
265 // needsFP - Return true if the specified function should have a dedicated frame
266 // pointer register. This is true if the function has variable sized allocas or
267 // if frame pointer elimination is disabled.
268 bool PPCFrameLowering::needsFP(const MachineFunction &MF) const {
269 const MachineFrameInfo *MFI = MF.getFrameInfo();
271 // Naked functions have no stack frame pushed, so we don't have a frame
273 if (MF.getFunction()->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
277 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
278 MFI->hasVarSizedObjects() ||
279 (MF.getTarget().Options.GuaranteedTailCallOpt &&
280 MF.getInfo<PPCFunctionInfo>()->hasFastCall());
284 void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
285 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
286 MachineBasicBlock::iterator MBBI = MBB.begin();
287 MachineFrameInfo *MFI = MF.getFrameInfo();
288 const PPCInstrInfo &TII =
289 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
291 MachineModuleInfo &MMI = MF.getMMI();
293 bool needsFrameMoves = MMI.hasDebugInfo() ||
294 MF.getFunction()->needsUnwindTableEntry();
296 // Prepare for frame info.
297 MCSymbol *FrameLabel = 0;
299 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
301 if (!Subtarget.isSVR4ABI())
302 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
303 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
304 HandleVRSaveUpdate(MBBI, TII);
309 // Move MBBI back to the beginning of the function.
312 // Work out frame sizes.
313 // FIXME: determineFrameLayout() may change the frame size. This should be
314 // moved upper, to some hook.
315 determineFrameLayout(MF);
316 unsigned FrameSize = MFI->getStackSize();
318 int NegFrameSize = -FrameSize;
320 // Get processor type.
321 bool isPPC64 = Subtarget.isPPC64();
322 // Get operating system
323 bool isDarwinABI = Subtarget.isDarwinABI();
324 // Check if the link register (LR) must be saved.
325 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
326 bool MustSaveLR = FI->mustSaveLR();
327 // Do we have a frame pointer for this function?
328 bool HasFP = hasFP(MF);
330 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
334 if (Subtarget.isSVR4ABI()) {
335 MachineFrameInfo *FFI = MF.getFrameInfo();
336 int FPIndex = FI->getFramePointerSaveIndex();
337 assert(FPIndex && "No Frame Pointer Save Slot!");
338 FPOffset = FFI->getObjectOffset(FPIndex);
340 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
346 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0);
349 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
355 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
357 .addImm(LROffset / 4)
361 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0);
364 // FIXME: On PPC32 SVR4, FPOffset is negative and access to negative
365 // offsets of R1 is not allowed.
366 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
372 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
378 // Skip if a leaf routine.
379 if (!FrameSize) return;
381 // Get stack alignments.
382 unsigned TargetAlign = getStackAlignment();
383 unsigned MaxAlign = MFI->getMaxAlignment();
385 // Adjust stack pointer: r1 += NegFrameSize.
386 // If there is a preferred stack alignment, align R1 now
389 if (ALIGN_STACK && MaxAlign > TargetAlign) {
390 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
391 "Invalid alignment!");
392 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!");
394 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0)
397 .addImm(32 - Log2_32(MaxAlign))
399 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0)
400 .addReg(PPC::R0, RegState::Kill)
401 .addImm(NegFrameSize);
402 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1)
403 .addReg(PPC::R1, RegState::Kill)
406 } else if (isInt<16>(NegFrameSize)) {
407 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1)
409 .addImm(NegFrameSize)
412 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
413 .addImm(NegFrameSize >> 16);
414 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
415 .addReg(PPC::R0, RegState::Kill)
416 .addImm(NegFrameSize & 0xFFFF);
417 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1)
418 .addReg(PPC::R1, RegState::Kill)
423 if (ALIGN_STACK && MaxAlign > TargetAlign) {
424 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
425 "Invalid alignment!");
426 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!");
428 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0)
431 .addImm(64 - Log2_32(MaxAlign));
432 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0)
434 .addImm(NegFrameSize);
435 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1)
436 .addReg(PPC::X1, RegState::Kill)
439 } else if (isInt<16>(NegFrameSize)) {
440 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1)
442 .addImm(NegFrameSize / 4)
445 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
446 .addImm(NegFrameSize >> 16);
447 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
448 .addReg(PPC::X0, RegState::Kill)
449 .addImm(NegFrameSize & 0xFFFF);
450 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1)
451 .addReg(PPC::X1, RegState::Kill)
457 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
459 // Add the "machine moves" for the instructions we generated above, but in
461 if (needsFrameMoves) {
462 // Mark effective beginning of when frame pointer becomes valid.
463 FrameLabel = MMI.getContext().CreateTempSymbol();
464 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(FrameLabel);
466 // Show update of SP.
468 MachineLocation SPDst(MachineLocation::VirtualFP);
469 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
470 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
472 MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31);
473 Moves.push_back(MachineMove(FrameLabel, SP, SP));
477 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
478 MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31);
479 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
483 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
484 MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR);
485 Moves.push_back(MachineMove(FrameLabel, LRDst, LRSrc));
489 MCSymbol *ReadyLabel = 0;
491 // If there is a frame pointer, copy R1 into R31
494 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31)
498 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31)
503 if (needsFrameMoves) {
504 ReadyLabel = MMI.getContext().CreateTempSymbol();
506 // Mark effective beginning of when frame pointer is ready.
507 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(ReadyLabel);
509 MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) :
510 (isPPC64 ? PPC::X1 : PPC::R1));
511 MachineLocation FPSrc(MachineLocation::VirtualFP);
512 Moves.push_back(MachineMove(ReadyLabel, FPDst, FPSrc));
516 if (needsFrameMoves) {
517 MCSymbol *Label = HasFP ? ReadyLabel : FrameLabel;
519 // Add callee saved registers to move list.
520 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
521 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
522 unsigned Reg = CSI[I].getReg();
523 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
525 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
526 // subregisters of CR2. We just need to emit a move of CR2.
527 if (PPC::CRBITRCRegClass.contains(Reg))
530 // For SVR4, don't emit a move for the CR spill slot if we haven't
532 if (Subtarget.isSVR4ABI()
533 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
537 // For 64-bit SVR4 when we have spilled CRs, the spill location
538 // is SP+8, not a frame-relative slot.
539 if (Subtarget.isSVR4ABI()
540 && Subtarget.isPPC64()
541 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
542 MachineLocation CSDst(PPC::X1, 8);
543 MachineLocation CSSrc(PPC::CR2);
544 Moves.push_back(MachineMove(Label, CSDst, CSSrc));
548 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
549 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
550 MachineLocation CSSrc(Reg);
551 Moves.push_back(MachineMove(Label, CSDst, CSSrc));
556 void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
557 MachineBasicBlock &MBB) const {
558 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
559 assert(MBBI != MBB.end() && "Returning block has no terminator");
560 const PPCInstrInfo &TII =
561 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
563 unsigned RetOpcode = MBBI->getOpcode();
566 assert((RetOpcode == PPC::BLR ||
567 RetOpcode == PPC::TCRETURNri ||
568 RetOpcode == PPC::TCRETURNdi ||
569 RetOpcode == PPC::TCRETURNai ||
570 RetOpcode == PPC::TCRETURNri8 ||
571 RetOpcode == PPC::TCRETURNdi8 ||
572 RetOpcode == PPC::TCRETURNai8) &&
573 "Can only insert epilog into returning blocks");
575 // Get alignment info so we know how to restore r1
576 const MachineFrameInfo *MFI = MF.getFrameInfo();
577 unsigned TargetAlign = getStackAlignment();
578 unsigned MaxAlign = MFI->getMaxAlignment();
580 // Get the number of bytes allocated from the FrameInfo.
581 int FrameSize = MFI->getStackSize();
583 // Get processor type.
584 bool isPPC64 = Subtarget.isPPC64();
585 // Get operating system
586 bool isDarwinABI = Subtarget.isDarwinABI();
587 // Check if the link register (LR) has been saved.
588 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
589 bool MustSaveLR = FI->mustSaveLR();
590 // Do we have a frame pointer for this function?
591 bool HasFP = hasFP(MF);
593 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
597 if (Subtarget.isSVR4ABI()) {
598 MachineFrameInfo *FFI = MF.getFrameInfo();
599 int FPIndex = FI->getFramePointerSaveIndex();
600 assert(FPIndex && "No Frame Pointer Save Slot!");
601 FPOffset = FFI->getObjectOffset(FPIndex);
603 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
607 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
608 RetOpcode == PPC::TCRETURNdi ||
609 RetOpcode == PPC::TCRETURNai ||
610 RetOpcode == PPC::TCRETURNri8 ||
611 RetOpcode == PPC::TCRETURNdi8 ||
612 RetOpcode == PPC::TCRETURNai8;
615 int MaxTCRetDelta = FI->getTailCallSPDelta();
616 MachineOperand &StackAdjust = MBBI->getOperand(1);
617 assert(StackAdjust.isImm() && "Expecting immediate value.");
618 // Adjust stack pointer.
619 int StackAdj = StackAdjust.getImm();
620 int Delta = StackAdj - MaxTCRetDelta;
621 assert((Delta >= 0) && "Delta must be positive");
623 FrameSize += (StackAdj +Delta);
625 FrameSize += StackAdj;
629 // The loaded (or persistent) stack pointer value is offset by the 'stwu'
630 // on entry to the function. Add this offset back now.
632 // If this function contained a fastcc call and GuaranteedTailCallOpt is
633 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
634 // call which invalidates the stack pointer value in SP(0). So we use the
635 // value of R31 in this case.
636 if (FI->hasFastCall() && isInt<16>(FrameSize)) {
637 assert(hasFP(MF) && "Expecting a valid the frame pointer.");
638 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
639 .addReg(PPC::R31).addImm(FrameSize);
640 } else if(FI->hasFastCall()) {
641 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
642 .addImm(FrameSize >> 16);
643 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
644 .addReg(PPC::R0, RegState::Kill)
645 .addImm(FrameSize & 0xFFFF);
646 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4))
650 } else if (isInt<16>(FrameSize) &&
651 (!ALIGN_STACK || TargetAlign >= MaxAlign) &&
652 !MFI->hasVarSizedObjects()) {
653 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
654 .addReg(PPC::R1).addImm(FrameSize);
656 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1)
657 .addImm(0).addReg(PPC::R1);
660 if (FI->hasFastCall() && isInt<16>(FrameSize)) {
661 assert(hasFP(MF) && "Expecting a valid the frame pointer.");
662 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
663 .addReg(PPC::X31).addImm(FrameSize);
664 } else if(FI->hasFastCall()) {
665 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
666 .addImm(FrameSize >> 16);
667 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
668 .addReg(PPC::X0, RegState::Kill)
669 .addImm(FrameSize & 0xFFFF);
670 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8))
674 } else if (isInt<16>(FrameSize) && TargetAlign >= MaxAlign &&
675 !MFI->hasVarSizedObjects()) {
676 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
677 .addReg(PPC::X1).addImm(FrameSize);
679 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1)
680 .addImm(0).addReg(PPC::X1);
687 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0)
688 .addImm(LROffset/4).addReg(PPC::X1);
691 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31)
692 .addImm(FPOffset/4).addReg(PPC::X1);
695 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0);
698 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0)
699 .addImm(LROffset).addReg(PPC::R1);
702 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31)
703 .addImm(FPOffset).addReg(PPC::R1);
706 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0);
709 // Callee pop calling convention. Pop parameter/linkage area. Used for tail
711 if (MF.getTarget().Options.GuaranteedTailCallOpt && RetOpcode == PPC::BLR &&
712 MF.getFunction()->getCallingConv() == CallingConv::Fast) {
713 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
714 unsigned CallerAllocatedAmt = FI->getMinReservedArea();
715 unsigned StackReg = isPPC64 ? PPC::X1 : PPC::R1;
716 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
717 unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0;
718 unsigned ADDIInstr = isPPC64 ? PPC::ADDI8 : PPC::ADDI;
719 unsigned ADDInstr = isPPC64 ? PPC::ADD8 : PPC::ADD4;
720 unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS;
721 unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI;
723 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
724 BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg)
725 .addReg(StackReg).addImm(CallerAllocatedAmt);
727 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
728 .addImm(CallerAllocatedAmt >> 16);
729 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
730 .addReg(TmpReg, RegState::Kill)
731 .addImm(CallerAllocatedAmt & 0xFFFF);
732 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
737 } else if (RetOpcode == PPC::TCRETURNdi) {
738 MBBI = MBB.getLastNonDebugInstr();
739 MachineOperand &JumpTarget = MBBI->getOperand(0);
740 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
741 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
742 } else if (RetOpcode == PPC::TCRETURNri) {
743 MBBI = MBB.getLastNonDebugInstr();
744 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
745 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
746 } else if (RetOpcode == PPC::TCRETURNai) {
747 MBBI = MBB.getLastNonDebugInstr();
748 MachineOperand &JumpTarget = MBBI->getOperand(0);
749 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
750 } else if (RetOpcode == PPC::TCRETURNdi8) {
751 MBBI = MBB.getLastNonDebugInstr();
752 MachineOperand &JumpTarget = MBBI->getOperand(0);
753 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
754 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
755 } else if (RetOpcode == PPC::TCRETURNri8) {
756 MBBI = MBB.getLastNonDebugInstr();
757 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
758 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
759 } else if (RetOpcode == PPC::TCRETURNai8) {
760 MBBI = MBB.getLastNonDebugInstr();
761 MachineOperand &JumpTarget = MBBI->getOperand(0);
762 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
766 /// MustSaveLR - Return true if this function requires that we save the LR
767 /// register onto the stack in the prolog and restore it in the epilog of the
769 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
770 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
772 // We need a save/restore of LR if there is any def of LR (which is
773 // defined by calls, including the PIC setup sequence), or if there is
774 // some use of the LR stack slot (e.g. for builtin_return_address).
775 // (LR comes in 32 and 64 bit versions.)
776 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
777 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
781 PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
782 RegScavenger *RS) const {
783 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
785 // Save and clear the LR state.
786 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
787 unsigned LR = RegInfo->getRARegister();
788 FI->setMustSaveLR(MustSaveLR(MF, LR));
789 MF.getRegInfo().setPhysRegUnused(LR);
791 // Save R31 if necessary
792 int FPSI = FI->getFramePointerSaveIndex();
793 bool isPPC64 = Subtarget.isPPC64();
794 bool isDarwinABI = Subtarget.isDarwinABI();
795 MachineFrameInfo *MFI = MF.getFrameInfo();
797 // If the frame pointer save index hasn't been defined yet.
798 if (!FPSI && needsFP(MF)) {
799 // Find out what the fix offset of the frame pointer save area.
800 int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI);
801 // Allocate the frame index for frame pointer save area.
802 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
804 FI->setFramePointerSaveIndex(FPSI);
807 // Reserve stack space to move the linkage area to in case of a tail call.
809 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
810 (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
811 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
814 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
815 // a large stack, which will require scavenging a register to materialize a
817 // FIXME: this doesn't actually check stack size, so is a bit pessimistic
818 // FIXME: doesn't detect whether or not we need to spill vXX, which requires
821 if (RegInfo->requiresRegisterScavenging(MF))
822 if (needsFP(MF) || spillsCR(MF)) {
823 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
824 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
825 const TargetRegisterClass *RC = isPPC64 ? G8RC : GPRC;
826 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
832 void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF)
834 // Early exit if not using the SVR4 ABI.
835 if (!Subtarget.isSVR4ABI())
838 // Get callee saved register information.
839 MachineFrameInfo *FFI = MF.getFrameInfo();
840 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
842 // Early exit if no callee saved registers are modified!
843 if (CSI.empty() && !needsFP(MF)) {
847 unsigned MinGPR = PPC::R31;
848 unsigned MinG8R = PPC::X31;
849 unsigned MinFPR = PPC::F31;
850 unsigned MinVR = PPC::V31;
852 bool HasGPSaveArea = false;
853 bool HasG8SaveArea = false;
854 bool HasFPSaveArea = false;
855 bool HasVRSAVESaveArea = false;
856 bool HasVRSaveArea = false;
858 SmallVector<CalleeSavedInfo, 18> GPRegs;
859 SmallVector<CalleeSavedInfo, 18> G8Regs;
860 SmallVector<CalleeSavedInfo, 18> FPRegs;
861 SmallVector<CalleeSavedInfo, 18> VRegs;
863 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
864 unsigned Reg = CSI[i].getReg();
865 if (PPC::GPRCRegClass.contains(Reg)) {
866 HasGPSaveArea = true;
868 GPRegs.push_back(CSI[i]);
873 } else if (PPC::G8RCRegClass.contains(Reg)) {
874 HasG8SaveArea = true;
876 G8Regs.push_back(CSI[i]);
881 } else if (PPC::F8RCRegClass.contains(Reg)) {
882 HasFPSaveArea = true;
884 FPRegs.push_back(CSI[i]);
889 } else if (PPC::CRBITRCRegClass.contains(Reg) ||
890 PPC::CRRCRegClass.contains(Reg)) {
891 ; // do nothing, as we already know whether CRs are spilled
892 } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
893 HasVRSAVESaveArea = true;
894 } else if (PPC::VRRCRegClass.contains(Reg)) {
895 HasVRSaveArea = true;
897 VRegs.push_back(CSI[i]);
903 llvm_unreachable("Unknown RegisterClass!");
907 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>();
909 int64_t LowerBound = 0;
911 // Take into account stack space reserved for tail calls.
913 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
914 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
915 LowerBound = TCSPDelta;
918 // The Floating-point register save area is right below the back chain word
919 // of the previous stack frame.
921 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
922 int FI = FPRegs[i].getFrameIdx();
924 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
927 LowerBound -= (31 - getPPCRegisterNumbering(MinFPR) + 1) * 8;
930 // Check whether the frame pointer register is allocated. If so, make sure it
931 // is spilled to the correct offset.
933 HasGPSaveArea = true;
935 int FI = PFI->getFramePointerSaveIndex();
936 assert(FI && "No Frame Pointer Save Slot!");
938 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
941 // General register save area starts right below the Floating-point
942 // register save area.
943 if (HasGPSaveArea || HasG8SaveArea) {
944 // Move general register save area spill slots down, taking into account
945 // the size of the Floating-point register save area.
946 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
947 int FI = GPRegs[i].getFrameIdx();
949 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
952 // Move general register save area spill slots down, taking into account
953 // the size of the Floating-point register save area.
954 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
955 int FI = G8Regs[i].getFrameIdx();
957 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
961 std::min<unsigned>(getPPCRegisterNumbering(MinGPR),
962 getPPCRegisterNumbering(MinG8R));
964 if (Subtarget.isPPC64()) {
965 LowerBound -= (31 - MinReg + 1) * 8;
967 LowerBound -= (31 - MinReg + 1) * 4;
971 // For 32-bit only, the CR save area is below the general register
972 // save area. For 64-bit SVR4, the CR save area is addressed relative
973 // to the stack pointer and hence does not need an adjustment here.
974 // Only CR2 (the first nonvolatile spilled) has an associated frame
975 // index so that we have a single uniform save area.
976 if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) {
977 // Adjust the frame index of the CR spill slot.
978 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
979 unsigned Reg = CSI[i].getReg();
981 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
982 // Leave Darwin logic as-is.
983 || (!Subtarget.isSVR4ABI() &&
984 (PPC::CRBITRCRegClass.contains(Reg) ||
985 PPC::CRRCRegClass.contains(Reg)))) {
986 int FI = CSI[i].getFrameIdx();
988 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
992 LowerBound -= 4; // The CR save area is always 4 bytes long.
995 if (HasVRSAVESaveArea) {
996 // FIXME SVR4: Is it actually possible to have multiple elements in CSI
997 // which have the VRSAVE register class?
998 // Adjust the frame index of the VRSAVE spill slot.
999 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1000 unsigned Reg = CSI[i].getReg();
1002 if (PPC::VRSAVERCRegClass.contains(Reg)) {
1003 int FI = CSI[i].getFrameIdx();
1005 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1009 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
1012 if (HasVRSaveArea) {
1013 // Insert alignment padding, we need 16-byte alignment.
1014 LowerBound = (LowerBound - 15) & ~(15);
1016 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
1017 int FI = VRegs[i].getFrameIdx();
1019 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1025 PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1026 MachineBasicBlock::iterator MI,
1027 const std::vector<CalleeSavedInfo> &CSI,
1028 const TargetRegisterInfo *TRI) const {
1030 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1031 // Return false otherwise to maintain pre-existing behavior.
1032 if (!Subtarget.isSVR4ABI())
1035 MachineFunction *MF = MBB.getParent();
1036 const PPCInstrInfo &TII =
1037 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1039 bool CRSpilled = false;
1041 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1042 unsigned Reg = CSI[i].getReg();
1043 // CR2 through CR4 are the nonvolatile CR fields.
1044 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
1046 if (CRSpilled && IsCRField)
1049 // Add the callee-saved register as live-in; it's killed at the spill.
1052 // Insert the spill to the stack frame.
1055 // The first time we see a CR field, store the whole CR into the
1056 // save slot via GPR12 (available in the prolog for 32- and 64-bit).
1057 if (Subtarget.isPPC64()) {
1059 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::X12));
1060 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::STW))
1062 getKillRegState(true))
1066 // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have
1067 // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
1068 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12));
1069 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
1071 getKillRegState(true)),
1072 CSI[i].getFrameIdx()));
1075 // Record that we spill the CR in this function.
1076 PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
1077 FuncInfo->setSpillsCR();
1079 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1080 TII.storeRegToStackSlot(MBB, MI, Reg, true,
1081 CSI[i].getFrameIdx(), RC, TRI);
1088 restoreCRs(bool isPPC64, bool CR2Spilled, bool CR3Spilled, bool CR4Spilled,
1089 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1090 const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
1092 MachineFunction *MF = MBB.getParent();
1093 const PPCInstrInfo &TII =
1094 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1096 unsigned RestoreOp, MoveReg;
1100 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::LWZ), PPC::X12)
1103 RestoreOp = PPC::MTCRF8;
1106 // 32-bit: FP-relative
1107 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
1109 CSI[CSIIndex].getFrameIdx()));
1110 RestoreOp = PPC::MTCRF;
1115 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
1119 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
1123 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
1128 PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1129 MachineBasicBlock::iterator MI,
1130 const std::vector<CalleeSavedInfo> &CSI,
1131 const TargetRegisterInfo *TRI) const {
1133 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1134 // Return false otherwise to maintain pre-existing behavior.
1135 if (!Subtarget.isSVR4ABI())
1138 MachineFunction *MF = MBB.getParent();
1139 const PPCInstrInfo &TII =
1140 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1141 bool CR2Spilled = false;
1142 bool CR3Spilled = false;
1143 bool CR4Spilled = false;
1144 unsigned CSIIndex = 0;
1146 // Initialize insertion-point logic; we will be restoring in reverse
1148 MachineBasicBlock::iterator I = MI, BeforeI = I;
1149 bool AtStart = I == MBB.begin();
1154 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1155 unsigned Reg = CSI[i].getReg();
1157 if (Reg == PPC::CR2) {
1159 // The spill slot is associated only with CR2, which is the
1160 // first nonvolatile spilled. Save it here.
1163 } else if (Reg == PPC::CR3) {
1166 } else if (Reg == PPC::CR4) {
1170 // When we first encounter a non-CR register after seeing at
1171 // least one CR register, restore all spilled CRs together.
1172 if ((CR2Spilled || CR3Spilled || CR4Spilled)
1173 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1174 restoreCRs(Subtarget.isPPC64(), CR2Spilled, CR3Spilled, CR4Spilled,
1175 MBB, I, CSI, CSIIndex);
1176 CR2Spilled = CR3Spilled = CR4Spilled = false;
1179 // Default behavior for non-CR saves.
1180 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1181 TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(),
1183 assert(I != MBB.begin() &&
1184 "loadRegFromStackSlot didn't insert any code!");
1187 // Insert in reverse order.
1196 // If we haven't yet spilled the CRs, do so now.
1197 if (CR2Spilled || CR3Spilled || CR4Spilled)
1198 restoreCRs(Subtarget.isPPC64(), CR2Spilled, CR3Spilled, CR4Spilled,
1199 MBB, I, CSI, CSIIndex);