1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PPC implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCFrameLowering.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCInstrInfo.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/IR/Function.h"
25 #include "llvm/Target/TargetOptions.h"
29 // FIXME This disables some code that aligns the stack to a boundary bigger than
30 // the default (16 bytes on Darwin) when there is a stack local of greater
31 // alignment. This does not currently work, because the delta between old and
32 // new stack pointers is added to offsets that reference incoming parameters
33 // after the prolog is generated, and the code that does that doesn't handle a
34 // variable delta. You don't want to do that anyway; a better approach is to
35 // reserve another register that retains to the incoming stack pointer, and
36 // reference parameters relative to that.
40 /// VRRegNo - Map from a numbered VR register to its enum value.
42 static const uint16_t VRRegNo[] = {
43 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
44 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
45 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
46 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
49 /// RemoveVRSaveCode - We have found that this function does not need any code
50 /// to manipulate the VRSAVE register, even though it uses vector registers.
51 /// This can happen when the only registers used are known to be live in or out
52 /// of the function. Remove all of the VRSAVE related code from the function.
53 /// FIXME: The removal of the code results in a compile failure at -O0 when the
54 /// function contains a function call, as the GPR containing original VRSAVE
55 /// contents is spilled and reloaded around the call. Without the prolog code,
56 /// the spill instruction refers to an undefined register. This code needs
57 /// to account for all uses of that GPR.
58 static void RemoveVRSaveCode(MachineInstr *MI) {
59 MachineBasicBlock *Entry = MI->getParent();
60 MachineFunction *MF = Entry->getParent();
62 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
63 MachineBasicBlock::iterator MBBI = MI;
65 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
66 MBBI->eraseFromParent();
68 bool RemovedAllMTVRSAVEs = true;
69 // See if we can find and remove the MTVRSAVE instruction from all of the
71 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
72 // If last instruction is a return instruction, add an epilogue
73 if (!I->empty() && I->back().isReturn()) {
75 for (MBBI = I->end(); MBBI != I->begin(); ) {
77 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
78 MBBI->eraseFromParent(); // remove it.
83 RemovedAllMTVRSAVEs &= FoundIt;
87 // If we found and removed all MTVRSAVE instructions, remove the read of
89 if (RemovedAllMTVRSAVEs) {
91 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
93 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
94 MBBI->eraseFromParent();
97 // Finally, nuke the UPDATE_VRSAVE.
98 MI->eraseFromParent();
101 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
102 // instruction selector. Based on the vector registers that have been used,
103 // transform this into the appropriate ORI instruction.
104 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
105 MachineFunction *MF = MI->getParent()->getParent();
106 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
107 DebugLoc dl = MI->getDebugLoc();
109 unsigned UsedRegMask = 0;
110 for (unsigned i = 0; i != 32; ++i)
111 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
112 UsedRegMask |= 1 << (31-i);
114 // Live in and live out values already must be in the mask, so don't bother
116 for (MachineRegisterInfo::livein_iterator
117 I = MF->getRegInfo().livein_begin(),
118 E = MF->getRegInfo().livein_end(); I != E; ++I) {
119 unsigned RegNo = TRI->getEncodingValue(I->first);
120 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
121 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
124 // Live out registers appear as use operands on return instructions.
125 for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end();
126 UsedRegMask != 0 && BI != BE; ++BI) {
127 const MachineBasicBlock &MBB = *BI;
128 if (MBB.empty() || !MBB.back().isReturn())
130 const MachineInstr &Ret = MBB.back();
131 for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) {
132 const MachineOperand &MO = Ret.getOperand(I);
133 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
135 unsigned RegNo = TRI->getEncodingValue(MO.getReg());
136 UsedRegMask &= ~(1 << (31-RegNo));
140 // If no registers are used, turn this into a copy.
141 if (UsedRegMask == 0) {
142 // Remove all VRSAVE code.
143 RemoveVRSaveCode(MI);
147 unsigned SrcReg = MI->getOperand(1).getReg();
148 unsigned DstReg = MI->getOperand(0).getReg();
150 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
151 if (DstReg != SrcReg)
152 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
154 .addImm(UsedRegMask);
156 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
157 .addReg(SrcReg, RegState::Kill)
158 .addImm(UsedRegMask);
159 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
160 if (DstReg != SrcReg)
161 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
163 .addImm(UsedRegMask >> 16);
165 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
166 .addReg(SrcReg, RegState::Kill)
167 .addImm(UsedRegMask >> 16);
169 if (DstReg != SrcReg)
170 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
172 .addImm(UsedRegMask >> 16);
174 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
175 .addReg(SrcReg, RegState::Kill)
176 .addImm(UsedRegMask >> 16);
178 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
179 .addReg(DstReg, RegState::Kill)
180 .addImm(UsedRegMask & 0xFFFF);
183 // Remove the old UPDATE_VRSAVE instruction.
184 MI->eraseFromParent();
187 static bool spillsCR(const MachineFunction &MF) {
188 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
189 return FuncInfo->isCRSpilled();
192 static bool spillsVRSAVE(const MachineFunction &MF) {
193 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
194 return FuncInfo->isVRSAVESpilled();
197 static bool hasSpills(const MachineFunction &MF) {
198 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
199 return FuncInfo->hasSpills();
202 static bool hasNonRISpills(const MachineFunction &MF) {
203 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
204 return FuncInfo->hasNonRISpills();
207 /// determineFrameLayout - Determine the size of the frame and maximum call
209 unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF,
211 bool UseEstimate) const {
212 MachineFrameInfo *MFI = MF.getFrameInfo();
214 // Get the number of bytes to allocate from the FrameInfo
216 UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize();
218 // Get the alignments provided by the target, and the maximum alignment
219 // (if any) of the fixed frame objects.
220 unsigned MaxAlign = MFI->getMaxAlignment();
221 unsigned TargetAlign = getStackAlignment();
222 unsigned AlignMask = TargetAlign - 1; //
224 // If we are a leaf function, and use up to 224 bytes of stack space,
225 // don't have a frame pointer, calls, or dynamic alloca then we do not need
226 // to adjust the stack pointer (we fit in the Red Zone).
227 // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate
228 // stackless code if all local vars are reg-allocated.
229 bool DisableRedZone = MF.getFunction()->getAttributes().
230 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoRedZone);
231 if (!DisableRedZone &&
232 (Subtarget.isPPC64() || // 32-bit SVR4, no stack-
233 !Subtarget.isSVR4ABI() || // allocated locals.
235 FrameSize <= 224 && // Fits in red zone.
236 !MFI->hasVarSizedObjects() && // No dynamic alloca.
237 !MFI->adjustsStack() && // No calls.
238 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment.
241 MFI->setStackSize(0);
245 // Get the maximum call frame size of all the calls.
246 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
248 // Maximum call frame needs to be at least big enough for linkage and 8 args.
249 unsigned minCallFrameSize = getMinCallFrameSize(Subtarget.isPPC64(),
250 Subtarget.isDarwinABI());
251 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
253 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
254 // that allocations will be aligned.
255 if (MFI->hasVarSizedObjects())
256 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
258 // Update maximum call frame size.
260 MFI->setMaxCallFrameSize(maxCallFrameSize);
262 // Include call frame size in total.
263 FrameSize += maxCallFrameSize;
265 // Make sure the frame is aligned.
266 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
268 // Update frame info.
270 MFI->setStackSize(FrameSize);
275 // hasFP - Return true if the specified function actually has a dedicated frame
277 bool PPCFrameLowering::hasFP(const MachineFunction &MF) const {
278 const MachineFrameInfo *MFI = MF.getFrameInfo();
279 // FIXME: This is pretty much broken by design: hasFP() might be called really
280 // early, before the stack layout was calculated and thus hasFP() might return
281 // true or false here depending on the time of call.
282 return (MFI->getStackSize()) && needsFP(MF);
285 // needsFP - Return true if the specified function should have a dedicated frame
286 // pointer register. This is true if the function has variable sized allocas or
287 // if frame pointer elimination is disabled.
288 bool PPCFrameLowering::needsFP(const MachineFunction &MF) const {
289 const MachineFrameInfo *MFI = MF.getFrameInfo();
291 // Naked functions have no stack frame pushed, so we don't have a frame
293 if (MF.getFunction()->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
297 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
298 MFI->hasVarSizedObjects() ||
299 (MF.getTarget().Options.GuaranteedTailCallOpt &&
300 MF.getInfo<PPCFunctionInfo>()->hasFastCall());
303 void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const {
304 bool is31 = needsFP(MF);
305 unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
306 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
308 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
310 for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) {
312 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
313 MachineOperand &MO = MBBI->getOperand(I);
317 switch (MO.getReg()) {
329 void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
330 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
331 MachineBasicBlock::iterator MBBI = MBB.begin();
332 MachineFrameInfo *MFI = MF.getFrameInfo();
333 const PPCInstrInfo &TII =
334 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
336 MachineModuleInfo &MMI = MF.getMMI();
337 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
339 bool needsFrameMoves = MMI.hasDebugInfo() ||
340 MF.getFunction()->needsUnwindTableEntry();
342 // Prepare for frame info.
343 MCSymbol *FrameLabel = 0;
345 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
347 if (!Subtarget.isSVR4ABI())
348 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
349 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
350 HandleVRSaveUpdate(MBBI, TII);
355 // Move MBBI back to the beginning of the function.
358 // Work out frame sizes.
359 unsigned FrameSize = determineFrameLayout(MF);
360 int NegFrameSize = -FrameSize;
362 if (MFI->isFrameAddressTaken())
363 replaceFPWithRealFP(MF);
365 // Get processor type.
366 bool isPPC64 = Subtarget.isPPC64();
367 // Get operating system
368 bool isDarwinABI = Subtarget.isDarwinABI();
369 // Check if the link register (LR) must be saved.
370 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
371 bool MustSaveLR = FI->mustSaveLR();
372 const SmallVector<unsigned, 3> &MustSaveCRs = FI->getMustSaveCRs();
373 // Do we have a frame pointer for this function?
374 bool HasFP = hasFP(MF);
376 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
380 if (Subtarget.isSVR4ABI()) {
381 MachineFrameInfo *FFI = MF.getFrameInfo();
382 int FPIndex = FI->getFramePointerSaveIndex();
383 assert(FPIndex && "No Frame Pointer Save Slot!");
384 FPOffset = FFI->getObjectOffset(FPIndex);
386 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
392 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0);
394 if (!MustSaveCRs.empty()) {
395 MachineInstrBuilder MIB =
396 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), PPC::X12);
397 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
398 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill);
402 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
408 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
413 if (!MustSaveCRs.empty())
414 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
415 .addReg(PPC::X12, getKillRegState(true))
420 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0);
423 // FIXME: On PPC32 SVR4, FPOffset is negative and access to negative
424 // offsets of R1 is not allowed.
425 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
430 assert(MustSaveCRs.empty() &&
431 "Prologue CR saving supported only in 64-bit mode");
434 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
440 // Skip if a leaf routine.
441 if (!FrameSize) return;
443 // Get stack alignments.
444 unsigned TargetAlign = getStackAlignment();
445 unsigned MaxAlign = MFI->getMaxAlignment();
447 // Adjust stack pointer: r1 += NegFrameSize.
448 // If there is a preferred stack alignment, align R1 now
451 if (ALIGN_STACK && MaxAlign > TargetAlign) {
452 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
453 "Invalid alignment!");
454 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!");
456 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0)
459 .addImm(32 - Log2_32(MaxAlign))
461 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0)
462 .addReg(PPC::R0, RegState::Kill)
463 .addImm(NegFrameSize);
464 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1)
465 .addReg(PPC::R1, RegState::Kill)
468 } else if (isInt<16>(NegFrameSize)) {
469 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1)
471 .addImm(NegFrameSize)
474 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
475 .addImm(NegFrameSize >> 16);
476 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
477 .addReg(PPC::R0, RegState::Kill)
478 .addImm(NegFrameSize & 0xFFFF);
479 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1)
480 .addReg(PPC::R1, RegState::Kill)
485 if (ALIGN_STACK && MaxAlign > TargetAlign) {
486 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
487 "Invalid alignment!");
488 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!");
490 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0)
493 .addImm(64 - Log2_32(MaxAlign));
494 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0)
496 .addImm(NegFrameSize);
497 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1)
498 .addReg(PPC::X1, RegState::Kill)
501 } else if (isInt<16>(NegFrameSize)) {
502 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1)
504 .addImm(NegFrameSize)
507 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
508 .addImm(NegFrameSize >> 16);
509 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
510 .addReg(PPC::X0, RegState::Kill)
511 .addImm(NegFrameSize & 0xFFFF);
512 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1)
513 .addReg(PPC::X1, RegState::Kill)
519 // Add the "machine moves" for the instructions we generated above, but in
521 if (needsFrameMoves) {
522 // Mark effective beginning of when frame pointer becomes valid.
523 FrameLabel = MMI.getContext().CreateTempSymbol();
524 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(FrameLabel);
526 // Show update of SP.
527 assert(NegFrameSize);
529 MCCFIInstruction::createDefCfaOffset(FrameLabel, NegFrameSize));
532 unsigned Reg = isPPC64 ? PPC::X31 : PPC::R31;
533 Reg = MRI->getDwarfRegNum(Reg, true);
535 MCCFIInstruction::createOffset(FrameLabel, Reg, FPOffset));
539 unsigned Reg = isPPC64 ? PPC::LR8 : PPC::LR;
540 Reg = MRI->getDwarfRegNum(Reg, true);
542 MCCFIInstruction::createOffset(FrameLabel, Reg, LROffset));
546 MCSymbol *ReadyLabel = 0;
548 // If there is a frame pointer, copy R1 into R31
551 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31)
555 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31)
560 if (needsFrameMoves) {
561 ReadyLabel = MMI.getContext().CreateTempSymbol();
563 // Mark effective beginning of when frame pointer is ready.
564 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(ReadyLabel);
566 unsigned Reg = HasFP ? (isPPC64 ? PPC::X31 : PPC::R31)
567 : (isPPC64 ? PPC::X1 : PPC::R1);
568 Reg = MRI->getDwarfRegNum(Reg, true);
569 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(ReadyLabel, Reg));
573 if (needsFrameMoves) {
574 MCSymbol *Label = HasFP ? ReadyLabel : FrameLabel;
576 // Add callee saved registers to move list.
577 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
578 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
579 unsigned Reg = CSI[I].getReg();
580 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
582 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
583 // subregisters of CR2. We just need to emit a move of CR2.
584 if (PPC::CRBITRCRegClass.contains(Reg))
587 // For SVR4, don't emit a move for the CR spill slot if we haven't
589 if (Subtarget.isSVR4ABI()
590 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
591 && MustSaveCRs.empty())
594 // For 64-bit SVR4 when we have spilled CRs, the spill location
595 // is SP+8, not a frame-relative slot.
596 if (Subtarget.isSVR4ABI()
597 && Subtarget.isPPC64()
598 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
599 MMI.addFrameInst(MCCFIInstruction::createOffset(
600 Label, MRI->getDwarfRegNum(PPC::CR2, true), 8));
604 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
605 MMI.addFrameInst(MCCFIInstruction::createOffset(
606 Label, MRI->getDwarfRegNum(Reg, true), Offset));
611 void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
612 MachineBasicBlock &MBB) const {
613 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
614 assert(MBBI != MBB.end() && "Returning block has no terminator");
615 const PPCInstrInfo &TII =
616 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
618 unsigned RetOpcode = MBBI->getOpcode();
621 assert((RetOpcode == PPC::BLR ||
622 RetOpcode == PPC::TCRETURNri ||
623 RetOpcode == PPC::TCRETURNdi ||
624 RetOpcode == PPC::TCRETURNai ||
625 RetOpcode == PPC::TCRETURNri8 ||
626 RetOpcode == PPC::TCRETURNdi8 ||
627 RetOpcode == PPC::TCRETURNai8) &&
628 "Can only insert epilog into returning blocks");
630 // Get alignment info so we know how to restore r1
631 const MachineFrameInfo *MFI = MF.getFrameInfo();
632 unsigned TargetAlign = getStackAlignment();
633 unsigned MaxAlign = MFI->getMaxAlignment();
635 // Get the number of bytes allocated from the FrameInfo.
636 int FrameSize = MFI->getStackSize();
638 // Get processor type.
639 bool isPPC64 = Subtarget.isPPC64();
640 // Get operating system
641 bool isDarwinABI = Subtarget.isDarwinABI();
642 // Check if the link register (LR) has been saved.
643 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
644 bool MustSaveLR = FI->mustSaveLR();
645 const SmallVector<unsigned, 3> &MustSaveCRs = FI->getMustSaveCRs();
646 // Do we have a frame pointer for this function?
647 bool HasFP = hasFP(MF);
649 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
653 if (Subtarget.isSVR4ABI()) {
654 MachineFrameInfo *FFI = MF.getFrameInfo();
655 int FPIndex = FI->getFramePointerSaveIndex();
656 assert(FPIndex && "No Frame Pointer Save Slot!");
657 FPOffset = FFI->getObjectOffset(FPIndex);
659 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
663 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
664 RetOpcode == PPC::TCRETURNdi ||
665 RetOpcode == PPC::TCRETURNai ||
666 RetOpcode == PPC::TCRETURNri8 ||
667 RetOpcode == PPC::TCRETURNdi8 ||
668 RetOpcode == PPC::TCRETURNai8;
671 int MaxTCRetDelta = FI->getTailCallSPDelta();
672 MachineOperand &StackAdjust = MBBI->getOperand(1);
673 assert(StackAdjust.isImm() && "Expecting immediate value.");
674 // Adjust stack pointer.
675 int StackAdj = StackAdjust.getImm();
676 int Delta = StackAdj - MaxTCRetDelta;
677 assert((Delta >= 0) && "Delta must be positive");
679 FrameSize += (StackAdj +Delta);
681 FrameSize += StackAdj;
685 // The loaded (or persistent) stack pointer value is offset by the 'stwu'
686 // on entry to the function. Add this offset back now.
688 // If this function contained a fastcc call and GuaranteedTailCallOpt is
689 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
690 // call which invalidates the stack pointer value in SP(0). So we use the
691 // value of R31 in this case.
692 if (FI->hasFastCall() && isInt<16>(FrameSize)) {
693 assert(hasFP(MF) && "Expecting a valid the frame pointer.");
694 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
695 .addReg(PPC::R31).addImm(FrameSize);
696 } else if(FI->hasFastCall()) {
697 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
698 .addImm(FrameSize >> 16);
699 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
700 .addReg(PPC::R0, RegState::Kill)
701 .addImm(FrameSize & 0xFFFF);
702 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4))
706 } else if (isInt<16>(FrameSize) &&
707 (!ALIGN_STACK || TargetAlign >= MaxAlign) &&
708 !MFI->hasVarSizedObjects()) {
709 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
710 .addReg(PPC::R1).addImm(FrameSize);
712 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1)
713 .addImm(0).addReg(PPC::R1);
716 if (FI->hasFastCall() && isInt<16>(FrameSize)) {
717 assert(hasFP(MF) && "Expecting a valid the frame pointer.");
718 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
719 .addReg(PPC::X31).addImm(FrameSize);
720 } else if(FI->hasFastCall()) {
721 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
722 .addImm(FrameSize >> 16);
723 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
724 .addReg(PPC::X0, RegState::Kill)
725 .addImm(FrameSize & 0xFFFF);
726 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8))
730 } else if (isInt<16>(FrameSize) && TargetAlign >= MaxAlign &&
731 !MFI->hasVarSizedObjects()) {
732 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
733 .addReg(PPC::X1).addImm(FrameSize);
735 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1)
736 .addImm(0).addReg(PPC::X1);
743 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0)
744 .addImm(LROffset).addReg(PPC::X1);
746 if (!MustSaveCRs.empty())
747 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), PPC::X12)
748 .addImm(8).addReg(PPC::X1);
751 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31)
752 .addImm(FPOffset).addReg(PPC::X1);
754 if (!MustSaveCRs.empty())
755 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
756 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
757 .addReg(PPC::X12, getKillRegState(i == e-1));
760 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0);
763 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0)
764 .addImm(LROffset).addReg(PPC::R1);
766 assert(MustSaveCRs.empty() &&
767 "Epilogue CR restoring supported only in 64-bit mode");
770 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31)
771 .addImm(FPOffset).addReg(PPC::R1);
774 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0);
777 // Callee pop calling convention. Pop parameter/linkage area. Used for tail
779 if (MF.getTarget().Options.GuaranteedTailCallOpt && RetOpcode == PPC::BLR &&
780 MF.getFunction()->getCallingConv() == CallingConv::Fast) {
781 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
782 unsigned CallerAllocatedAmt = FI->getMinReservedArea();
783 unsigned StackReg = isPPC64 ? PPC::X1 : PPC::R1;
784 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
785 unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0;
786 unsigned ADDIInstr = isPPC64 ? PPC::ADDI8 : PPC::ADDI;
787 unsigned ADDInstr = isPPC64 ? PPC::ADD8 : PPC::ADD4;
788 unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS;
789 unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI;
791 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
792 BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg)
793 .addReg(StackReg).addImm(CallerAllocatedAmt);
795 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
796 .addImm(CallerAllocatedAmt >> 16);
797 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
798 .addReg(TmpReg, RegState::Kill)
799 .addImm(CallerAllocatedAmt & 0xFFFF);
800 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
805 } else if (RetOpcode == PPC::TCRETURNdi) {
806 MBBI = MBB.getLastNonDebugInstr();
807 MachineOperand &JumpTarget = MBBI->getOperand(0);
808 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
809 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
810 } else if (RetOpcode == PPC::TCRETURNri) {
811 MBBI = MBB.getLastNonDebugInstr();
812 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
813 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
814 } else if (RetOpcode == PPC::TCRETURNai) {
815 MBBI = MBB.getLastNonDebugInstr();
816 MachineOperand &JumpTarget = MBBI->getOperand(0);
817 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
818 } else if (RetOpcode == PPC::TCRETURNdi8) {
819 MBBI = MBB.getLastNonDebugInstr();
820 MachineOperand &JumpTarget = MBBI->getOperand(0);
821 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
822 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
823 } else if (RetOpcode == PPC::TCRETURNri8) {
824 MBBI = MBB.getLastNonDebugInstr();
825 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
826 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
827 } else if (RetOpcode == PPC::TCRETURNai8) {
828 MBBI = MBB.getLastNonDebugInstr();
829 MachineOperand &JumpTarget = MBBI->getOperand(0);
830 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
834 /// MustSaveLR - Return true if this function requires that we save the LR
835 /// register onto the stack in the prolog and restore it in the epilog of the
837 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
838 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
840 // We need a save/restore of LR if there is any def of LR (which is
841 // defined by calls, including the PIC setup sequence), or if there is
842 // some use of the LR stack slot (e.g. for builtin_return_address).
843 // (LR comes in 32 and 64 bit versions.)
844 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
845 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
849 PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
850 RegScavenger *) const {
851 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
853 // Save and clear the LR state.
854 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
855 unsigned LR = RegInfo->getRARegister();
856 FI->setMustSaveLR(MustSaveLR(MF, LR));
857 MachineRegisterInfo &MRI = MF.getRegInfo();
858 MRI.setPhysRegUnused(LR);
860 // Save R31 if necessary
861 int FPSI = FI->getFramePointerSaveIndex();
862 bool isPPC64 = Subtarget.isPPC64();
863 bool isDarwinABI = Subtarget.isDarwinABI();
864 MachineFrameInfo *MFI = MF.getFrameInfo();
866 // If the frame pointer save index hasn't been defined yet.
867 if (!FPSI && needsFP(MF)) {
868 // Find out what the fix offset of the frame pointer save area.
869 int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI);
870 // Allocate the frame index for frame pointer save area.
871 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
873 FI->setFramePointerSaveIndex(FPSI);
876 // Reserve stack space to move the linkage area to in case of a tail call.
878 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
879 (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
880 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
883 // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
884 // function uses CR 2, 3, or 4.
885 if (!isPPC64 && !isDarwinABI &&
886 (MRI.isPhysRegUsed(PPC::CR2) ||
887 MRI.isPhysRegUsed(PPC::CR3) ||
888 MRI.isPhysRegUsed(PPC::CR4))) {
889 int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true);
890 FI->setCRSpillFrameIndex(FrameIdx);
894 void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
895 RegScavenger *RS) const {
896 // Early exit if not using the SVR4 ABI.
897 if (!Subtarget.isSVR4ABI()) {
898 addScavengingSpillSlot(MF, RS);
902 // Get callee saved register information.
903 MachineFrameInfo *FFI = MF.getFrameInfo();
904 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
906 // Early exit if no callee saved registers are modified!
907 if (CSI.empty() && !needsFP(MF)) {
908 addScavengingSpillSlot(MF, RS);
912 unsigned MinGPR = PPC::R31;
913 unsigned MinG8R = PPC::X31;
914 unsigned MinFPR = PPC::F31;
915 unsigned MinVR = PPC::V31;
917 bool HasGPSaveArea = false;
918 bool HasG8SaveArea = false;
919 bool HasFPSaveArea = false;
920 bool HasVRSAVESaveArea = false;
921 bool HasVRSaveArea = false;
923 SmallVector<CalleeSavedInfo, 18> GPRegs;
924 SmallVector<CalleeSavedInfo, 18> G8Regs;
925 SmallVector<CalleeSavedInfo, 18> FPRegs;
926 SmallVector<CalleeSavedInfo, 18> VRegs;
928 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
929 unsigned Reg = CSI[i].getReg();
930 if (PPC::GPRCRegClass.contains(Reg)) {
931 HasGPSaveArea = true;
933 GPRegs.push_back(CSI[i]);
938 } else if (PPC::G8RCRegClass.contains(Reg)) {
939 HasG8SaveArea = true;
941 G8Regs.push_back(CSI[i]);
946 } else if (PPC::F8RCRegClass.contains(Reg)) {
947 HasFPSaveArea = true;
949 FPRegs.push_back(CSI[i]);
954 } else if (PPC::CRBITRCRegClass.contains(Reg) ||
955 PPC::CRRCRegClass.contains(Reg)) {
956 ; // do nothing, as we already know whether CRs are spilled
957 } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
958 HasVRSAVESaveArea = true;
959 } else if (PPC::VRRCRegClass.contains(Reg)) {
960 HasVRSaveArea = true;
962 VRegs.push_back(CSI[i]);
968 llvm_unreachable("Unknown RegisterClass!");
972 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>();
973 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
975 int64_t LowerBound = 0;
977 // Take into account stack space reserved for tail calls.
979 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
980 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
981 LowerBound = TCSPDelta;
984 // The Floating-point register save area is right below the back chain word
985 // of the previous stack frame.
987 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
988 int FI = FPRegs[i].getFrameIdx();
990 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
993 LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8;
996 // Check whether the frame pointer register is allocated. If so, make sure it
997 // is spilled to the correct offset.
999 HasGPSaveArea = true;
1001 int FI = PFI->getFramePointerSaveIndex();
1002 assert(FI && "No Frame Pointer Save Slot!");
1004 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1007 // General register save area starts right below the Floating-point
1008 // register save area.
1009 if (HasGPSaveArea || HasG8SaveArea) {
1010 // Move general register save area spill slots down, taking into account
1011 // the size of the Floating-point register save area.
1012 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
1013 int FI = GPRegs[i].getFrameIdx();
1015 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1018 // Move general register save area spill slots down, taking into account
1019 // the size of the Floating-point register save area.
1020 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
1021 int FI = G8Regs[i].getFrameIdx();
1023 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1027 std::min<unsigned>(TRI->getEncodingValue(MinGPR),
1028 TRI->getEncodingValue(MinG8R));
1030 if (Subtarget.isPPC64()) {
1031 LowerBound -= (31 - MinReg + 1) * 8;
1033 LowerBound -= (31 - MinReg + 1) * 4;
1037 // For 32-bit only, the CR save area is below the general register
1038 // save area. For 64-bit SVR4, the CR save area is addressed relative
1039 // to the stack pointer and hence does not need an adjustment here.
1040 // Only CR2 (the first nonvolatile spilled) has an associated frame
1041 // index so that we have a single uniform save area.
1042 if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) {
1043 // Adjust the frame index of the CR spill slot.
1044 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1045 unsigned Reg = CSI[i].getReg();
1047 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
1048 // Leave Darwin logic as-is.
1049 || (!Subtarget.isSVR4ABI() &&
1050 (PPC::CRBITRCRegClass.contains(Reg) ||
1051 PPC::CRRCRegClass.contains(Reg)))) {
1052 int FI = CSI[i].getFrameIdx();
1054 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1058 LowerBound -= 4; // The CR save area is always 4 bytes long.
1061 if (HasVRSAVESaveArea) {
1062 // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1063 // which have the VRSAVE register class?
1064 // Adjust the frame index of the VRSAVE spill slot.
1065 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1066 unsigned Reg = CSI[i].getReg();
1068 if (PPC::VRSAVERCRegClass.contains(Reg)) {
1069 int FI = CSI[i].getFrameIdx();
1071 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1075 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
1078 if (HasVRSaveArea) {
1079 // Insert alignment padding, we need 16-byte alignment.
1080 LowerBound = (LowerBound - 15) & ~(15);
1082 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
1083 int FI = VRegs[i].getFrameIdx();
1085 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1089 addScavengingSpillSlot(MF, RS);
1093 PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
1094 RegScavenger *RS) const {
1095 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
1096 // a large stack, which will require scavenging a register to materialize a
1099 // We need to have a scavenger spill slot for spills if the frame size is
1100 // large. In case there is no free register for large-offset addressing,
1101 // this slot is used for the necessary emergency spill. Also, we need the
1102 // slot for dynamic stack allocations.
1104 // The scavenger might be invoked if the frame offset does not fit into
1105 // the 16-bit immediate. We don't know the complete frame size here
1106 // because we've not yet computed callee-saved register spills or the
1107 // needed alignment padding.
1108 unsigned StackSize = determineFrameLayout(MF, false, true);
1109 MachineFrameInfo *MFI = MF.getFrameInfo();
1110 if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) ||
1111 hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) {
1112 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1113 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1114 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
1115 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1119 // These kinds of spills might need two registers.
1120 if (spillsCR(MF) || spillsVRSAVE(MF))
1121 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1129 PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1130 MachineBasicBlock::iterator MI,
1131 const std::vector<CalleeSavedInfo> &CSI,
1132 const TargetRegisterInfo *TRI) const {
1134 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1135 // Return false otherwise to maintain pre-existing behavior.
1136 if (!Subtarget.isSVR4ABI())
1139 MachineFunction *MF = MBB.getParent();
1140 const PPCInstrInfo &TII =
1141 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1143 bool CRSpilled = false;
1144 MachineInstrBuilder CRMIB;
1146 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1147 unsigned Reg = CSI[i].getReg();
1148 // Only Darwin actually uses the VRSAVE register, but it can still appear
1149 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1150 // Darwin, ignore it.
1151 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1154 // CR2 through CR4 are the nonvolatile CR fields.
1155 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
1157 // Add the callee-saved register as live-in; it's killed at the spill.
1160 if (CRSpilled && IsCRField) {
1161 CRMIB.addReg(Reg, RegState::ImplicitKill);
1165 // Insert the spill to the stack frame.
1167 PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
1168 if (Subtarget.isPPC64()) {
1169 // The actual spill will happen at the start of the prologue.
1170 FuncInfo->addMustSaveCR(Reg);
1173 FuncInfo->setSpillsCR();
1175 // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have
1176 // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
1177 CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
1178 .addReg(Reg, RegState::ImplicitKill);
1180 MBB.insert(MI, CRMIB);
1181 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
1183 getKillRegState(true)),
1184 CSI[i].getFrameIdx()));
1187 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1188 TII.storeRegToStackSlot(MBB, MI, Reg, true,
1189 CSI[i].getFrameIdx(), RC, TRI);
1196 restoreCRs(bool isPPC64, bool is31,
1197 bool CR2Spilled, bool CR3Spilled, bool CR4Spilled,
1198 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1199 const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
1201 MachineFunction *MF = MBB.getParent();
1202 const PPCInstrInfo &TII =
1203 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1205 unsigned RestoreOp, MoveReg;
1208 // This is handled during epilogue generation.
1211 // 32-bit: FP-relative
1212 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
1214 CSI[CSIIndex].getFrameIdx()));
1215 RestoreOp = PPC::MTOCRF;
1220 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
1221 .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled)));
1224 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
1225 .addReg(MoveReg, getKillRegState(!CR4Spilled)));
1228 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
1229 .addReg(MoveReg, getKillRegState(true)));
1232 void PPCFrameLowering::
1233 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1234 MachineBasicBlock::iterator I) const {
1235 const PPCInstrInfo &TII =
1236 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
1237 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1238 I->getOpcode() == PPC::ADJCALLSTACKUP) {
1239 // Add (actually subtract) back the amount the callee popped on return.
1240 if (int CalleeAmt = I->getOperand(1).getImm()) {
1241 bool is64Bit = Subtarget.isPPC64();
1243 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
1244 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
1245 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
1246 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
1247 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
1248 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
1249 MachineInstr *MI = I;
1250 DebugLoc dl = MI->getDebugLoc();
1252 if (isInt<16>(CalleeAmt)) {
1253 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
1254 .addReg(StackReg, RegState::Kill)
1257 MachineBasicBlock::iterator MBBI = I;
1258 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
1259 .addImm(CalleeAmt >> 16);
1260 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
1261 .addReg(TmpReg, RegState::Kill)
1262 .addImm(CalleeAmt & 0xFFFF);
1263 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
1264 .addReg(StackReg, RegState::Kill)
1269 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
1274 PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1275 MachineBasicBlock::iterator MI,
1276 const std::vector<CalleeSavedInfo> &CSI,
1277 const TargetRegisterInfo *TRI) const {
1279 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1280 // Return false otherwise to maintain pre-existing behavior.
1281 if (!Subtarget.isSVR4ABI())
1284 MachineFunction *MF = MBB.getParent();
1285 const PPCInstrInfo &TII =
1286 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1287 bool CR2Spilled = false;
1288 bool CR3Spilled = false;
1289 bool CR4Spilled = false;
1290 unsigned CSIIndex = 0;
1292 // Initialize insertion-point logic; we will be restoring in reverse
1294 MachineBasicBlock::iterator I = MI, BeforeI = I;
1295 bool AtStart = I == MBB.begin();
1300 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1301 unsigned Reg = CSI[i].getReg();
1303 // Only Darwin actually uses the VRSAVE register, but it can still appear
1304 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1305 // Darwin, ignore it.
1306 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1309 if (Reg == PPC::CR2) {
1311 // The spill slot is associated only with CR2, which is the
1312 // first nonvolatile spilled. Save it here.
1315 } else if (Reg == PPC::CR3) {
1318 } else if (Reg == PPC::CR4) {
1322 // When we first encounter a non-CR register after seeing at
1323 // least one CR register, restore all spilled CRs together.
1324 if ((CR2Spilled || CR3Spilled || CR4Spilled)
1325 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1326 bool is31 = needsFP(*MF);
1327 restoreCRs(Subtarget.isPPC64(), is31,
1328 CR2Spilled, CR3Spilled, CR4Spilled,
1329 MBB, I, CSI, CSIIndex);
1330 CR2Spilled = CR3Spilled = CR4Spilled = false;
1333 // Default behavior for non-CR saves.
1334 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1335 TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(),
1337 assert(I != MBB.begin() &&
1338 "loadRegFromStackSlot didn't insert any code!");
1341 // Insert in reverse order.
1350 // If we haven't yet spilled the CRs, do so now.
1351 if (CR2Spilled || CR3Spilled || CR4Spilled) {
1352 bool is31 = needsFP(*MF);
1353 restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled,
1354 MBB, I, CSI, CSIIndex);