1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PPC implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCFrameLowering.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCInstrInfo.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/IR/Function.h"
25 #include "llvm/Target/TargetOptions.h"
29 // FIXME This disables some code that aligns the stack to a boundary bigger than
30 // the default (16 bytes on Darwin) when there is a stack local of greater
31 // alignment. This does not currently work, because the delta between old and
32 // new stack pointers is added to offsets that reference incoming parameters
33 // after the prolog is generated, and the code that does that doesn't handle a
34 // variable delta. You don't want to do that anyway; a better approach is to
35 // reserve another register that retains to the incoming stack pointer, and
36 // reference parameters relative to that.
40 /// VRRegNo - Map from a numbered VR register to its enum value.
42 static const uint16_t VRRegNo[] = {
43 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
44 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
45 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
46 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
49 /// RemoveVRSaveCode - We have found that this function does not need any code
50 /// to manipulate the VRSAVE register, even though it uses vector registers.
51 /// This can happen when the only registers used are known to be live in or out
52 /// of the function. Remove all of the VRSAVE related code from the function.
53 /// FIXME: The removal of the code results in a compile failure at -O0 when the
54 /// function contains a function call, as the GPR containing original VRSAVE
55 /// contents is spilled and reloaded around the call. Without the prolog code,
56 /// the spill instruction refers to an undefined register. This code needs
57 /// to account for all uses of that GPR.
58 static void RemoveVRSaveCode(MachineInstr *MI) {
59 MachineBasicBlock *Entry = MI->getParent();
60 MachineFunction *MF = Entry->getParent();
62 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
63 MachineBasicBlock::iterator MBBI = MI;
65 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
66 MBBI->eraseFromParent();
68 bool RemovedAllMTVRSAVEs = true;
69 // See if we can find and remove the MTVRSAVE instruction from all of the
71 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
72 // If last instruction is a return instruction, add an epilogue
73 if (!I->empty() && I->back().isReturn()) {
75 for (MBBI = I->end(); MBBI != I->begin(); ) {
77 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
78 MBBI->eraseFromParent(); // remove it.
83 RemovedAllMTVRSAVEs &= FoundIt;
87 // If we found and removed all MTVRSAVE instructions, remove the read of
89 if (RemovedAllMTVRSAVEs) {
91 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
93 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
94 MBBI->eraseFromParent();
97 // Finally, nuke the UPDATE_VRSAVE.
98 MI->eraseFromParent();
101 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
102 // instruction selector. Based on the vector registers that have been used,
103 // transform this into the appropriate ORI instruction.
104 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
105 MachineFunction *MF = MI->getParent()->getParent();
106 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
107 DebugLoc dl = MI->getDebugLoc();
109 unsigned UsedRegMask = 0;
110 for (unsigned i = 0; i != 32; ++i)
111 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
112 UsedRegMask |= 1 << (31-i);
114 // Live in and live out values already must be in the mask, so don't bother
116 for (MachineRegisterInfo::livein_iterator
117 I = MF->getRegInfo().livein_begin(),
118 E = MF->getRegInfo().livein_end(); I != E; ++I) {
119 unsigned RegNo = TRI->getEncodingValue(I->first);
120 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
121 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
124 // Live out registers appear as use operands on return instructions.
125 for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end();
126 UsedRegMask != 0 && BI != BE; ++BI) {
127 const MachineBasicBlock &MBB = *BI;
128 if (MBB.empty() || !MBB.back().isReturn())
130 const MachineInstr &Ret = MBB.back();
131 for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) {
132 const MachineOperand &MO = Ret.getOperand(I);
133 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
135 unsigned RegNo = TRI->getEncodingValue(MO.getReg());
136 UsedRegMask &= ~(1 << (31-RegNo));
140 // If no registers are used, turn this into a copy.
141 if (UsedRegMask == 0) {
142 // Remove all VRSAVE code.
143 RemoveVRSaveCode(MI);
147 unsigned SrcReg = MI->getOperand(1).getReg();
148 unsigned DstReg = MI->getOperand(0).getReg();
150 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
151 if (DstReg != SrcReg)
152 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
154 .addImm(UsedRegMask);
156 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
157 .addReg(SrcReg, RegState::Kill)
158 .addImm(UsedRegMask);
159 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
160 if (DstReg != SrcReg)
161 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
163 .addImm(UsedRegMask >> 16);
165 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
166 .addReg(SrcReg, RegState::Kill)
167 .addImm(UsedRegMask >> 16);
169 if (DstReg != SrcReg)
170 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
172 .addImm(UsedRegMask >> 16);
174 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
175 .addReg(SrcReg, RegState::Kill)
176 .addImm(UsedRegMask >> 16);
178 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
179 .addReg(DstReg, RegState::Kill)
180 .addImm(UsedRegMask & 0xFFFF);
183 // Remove the old UPDATE_VRSAVE instruction.
184 MI->eraseFromParent();
187 static bool spillsCR(const MachineFunction &MF) {
188 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
189 return FuncInfo->isCRSpilled();
192 static bool spillsVRSAVE(const MachineFunction &MF) {
193 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
194 return FuncInfo->isVRSAVESpilled();
197 static bool hasSpills(const MachineFunction &MF) {
198 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
199 return FuncInfo->hasSpills();
202 static bool hasNonRISpills(const MachineFunction &MF) {
203 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
204 return FuncInfo->hasNonRISpills();
207 /// determineFrameLayout - Determine the size of the frame and maximum call
209 unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF,
211 bool UseEstimate) const {
212 MachineFrameInfo *MFI = MF.getFrameInfo();
214 // Get the number of bytes to allocate from the FrameInfo
216 UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize();
218 // Get the alignments provided by the target, and the maximum alignment
219 // (if any) of the fixed frame objects.
220 unsigned MaxAlign = MFI->getMaxAlignment();
221 unsigned TargetAlign = getStackAlignment();
222 unsigned AlignMask = TargetAlign - 1; //
224 // If we are a leaf function, and use up to 224 bytes of stack space,
225 // don't have a frame pointer, calls, or dynamic alloca then we do not need
226 // to adjust the stack pointer (we fit in the Red Zone).
227 // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate
228 // stackless code if all local vars are reg-allocated.
229 bool DisableRedZone = MF.getFunction()->getAttributes().
230 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoRedZone);
231 if (!DisableRedZone &&
232 (Subtarget.isPPC64() || // 32-bit SVR4, no stack-
233 !Subtarget.isSVR4ABI() || // allocated locals.
235 FrameSize <= 224 && // Fits in red zone.
236 !MFI->hasVarSizedObjects() && // No dynamic alloca.
237 !MFI->adjustsStack() && // No calls.
238 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment.
241 MFI->setStackSize(0);
245 // Get the maximum call frame size of all the calls.
246 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
248 // Maximum call frame needs to be at least big enough for linkage and 8 args.
249 unsigned minCallFrameSize = getMinCallFrameSize(Subtarget.isPPC64(),
250 Subtarget.isDarwinABI());
251 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
253 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
254 // that allocations will be aligned.
255 if (MFI->hasVarSizedObjects())
256 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
258 // Update maximum call frame size.
260 MFI->setMaxCallFrameSize(maxCallFrameSize);
262 // Include call frame size in total.
263 FrameSize += maxCallFrameSize;
265 // Make sure the frame is aligned.
266 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
268 // Update frame info.
270 MFI->setStackSize(FrameSize);
275 // hasFP - Return true if the specified function actually has a dedicated frame
277 bool PPCFrameLowering::hasFP(const MachineFunction &MF) const {
278 const MachineFrameInfo *MFI = MF.getFrameInfo();
279 // FIXME: This is pretty much broken by design: hasFP() might be called really
280 // early, before the stack layout was calculated and thus hasFP() might return
281 // true or false here depending on the time of call.
282 return (MFI->getStackSize()) && needsFP(MF);
285 // needsFP - Return true if the specified function should have a dedicated frame
286 // pointer register. This is true if the function has variable sized allocas or
287 // if frame pointer elimination is disabled.
288 bool PPCFrameLowering::needsFP(const MachineFunction &MF) const {
289 const MachineFrameInfo *MFI = MF.getFrameInfo();
291 // Naked functions have no stack frame pushed, so we don't have a frame
293 if (MF.getFunction()->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
297 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
298 MFI->hasVarSizedObjects() ||
299 (MF.getTarget().Options.GuaranteedTailCallOpt &&
300 MF.getInfo<PPCFunctionInfo>()->hasFastCall());
303 void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const {
304 bool is31 = needsFP(MF);
305 unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
306 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
308 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
310 for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) {
312 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
313 MachineOperand &MO = MBBI->getOperand(I);
317 switch (MO.getReg()) {
329 void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
330 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
331 MachineBasicBlock::iterator MBBI = MBB.begin();
332 MachineFrameInfo *MFI = MF.getFrameInfo();
333 const PPCInstrInfo &TII =
334 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
336 MachineModuleInfo &MMI = MF.getMMI();
338 bool needsFrameMoves = MMI.hasDebugInfo() ||
339 MF.getFunction()->needsUnwindTableEntry();
341 // Prepare for frame info.
342 MCSymbol *FrameLabel = 0;
344 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
346 if (!Subtarget.isSVR4ABI())
347 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
348 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
349 HandleVRSaveUpdate(MBBI, TII);
354 // Move MBBI back to the beginning of the function.
357 // Work out frame sizes.
358 unsigned FrameSize = determineFrameLayout(MF);
359 int NegFrameSize = -FrameSize;
361 if (MFI->isFrameAddressTaken())
362 replaceFPWithRealFP(MF);
364 // Get processor type.
365 bool isPPC64 = Subtarget.isPPC64();
366 // Get operating system
367 bool isDarwinABI = Subtarget.isDarwinABI();
368 // Check if the link register (LR) must be saved.
369 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
370 bool MustSaveLR = FI->mustSaveLR();
371 const SmallVector<unsigned, 3> &MustSaveCRs = FI->getMustSaveCRs();
372 // Do we have a frame pointer for this function?
373 bool HasFP = hasFP(MF);
375 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
379 if (Subtarget.isSVR4ABI()) {
380 MachineFrameInfo *FFI = MF.getFrameInfo();
381 int FPIndex = FI->getFramePointerSaveIndex();
382 assert(FPIndex && "No Frame Pointer Save Slot!");
383 FPOffset = FFI->getObjectOffset(FPIndex);
385 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
391 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0);
393 if (!MustSaveCRs.empty()) {
394 MachineInstrBuilder MIB =
395 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), PPC::X12);
396 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
397 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill);
401 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
407 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
409 .addImm(LROffset / 4)
412 if (!MustSaveCRs.empty())
413 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
414 .addReg(PPC::X12, getKillRegState(true))
419 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0);
422 // FIXME: On PPC32 SVR4, FPOffset is negative and access to negative
423 // offsets of R1 is not allowed.
424 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
429 assert(MustSaveCRs.empty() &&
430 "Prologue CR saving supported only in 64-bit mode");
433 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
439 // Skip if a leaf routine.
440 if (!FrameSize) return;
442 // Get stack alignments.
443 unsigned TargetAlign = getStackAlignment();
444 unsigned MaxAlign = MFI->getMaxAlignment();
446 // Adjust stack pointer: r1 += NegFrameSize.
447 // If there is a preferred stack alignment, align R1 now
450 if (ALIGN_STACK && MaxAlign > TargetAlign) {
451 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
452 "Invalid alignment!");
453 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!");
455 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0)
458 .addImm(32 - Log2_32(MaxAlign))
460 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0)
461 .addReg(PPC::R0, RegState::Kill)
462 .addImm(NegFrameSize);
463 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1)
464 .addReg(PPC::R1, RegState::Kill)
467 } else if (isInt<16>(NegFrameSize)) {
468 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1)
470 .addImm(NegFrameSize)
473 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
474 .addImm(NegFrameSize >> 16);
475 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
476 .addReg(PPC::R0, RegState::Kill)
477 .addImm(NegFrameSize & 0xFFFF);
478 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1)
479 .addReg(PPC::R1, RegState::Kill)
484 if (ALIGN_STACK && MaxAlign > TargetAlign) {
485 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
486 "Invalid alignment!");
487 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!");
489 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0)
492 .addImm(64 - Log2_32(MaxAlign));
493 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0)
495 .addImm(NegFrameSize);
496 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1)
497 .addReg(PPC::X1, RegState::Kill)
500 } else if (isInt<16>(NegFrameSize)) {
501 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1)
503 .addImm(NegFrameSize / 4)
506 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
507 .addImm(NegFrameSize >> 16);
508 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
509 .addReg(PPC::X0, RegState::Kill)
510 .addImm(NegFrameSize & 0xFFFF);
511 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1)
512 .addReg(PPC::X1, RegState::Kill)
518 // Add the "machine moves" for the instructions we generated above, but in
520 if (needsFrameMoves) {
521 // Mark effective beginning of when frame pointer becomes valid.
522 FrameLabel = MMI.getContext().CreateTempSymbol();
523 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(FrameLabel);
525 // Show update of SP.
527 MachineLocation SPDst(MachineLocation::VirtualFP);
528 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
529 MMI.addFrameMove(FrameLabel, SPDst, SPSrc);
531 MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31);
532 MMI.addFrameMove(FrameLabel, SP, SP);
536 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
537 MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31);
538 MMI.addFrameMove(FrameLabel, FPDst, FPSrc);
542 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
543 MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR);
544 MMI.addFrameMove(FrameLabel, LRDst, LRSrc);
548 MCSymbol *ReadyLabel = 0;
550 // If there is a frame pointer, copy R1 into R31
553 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31)
557 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31)
562 if (needsFrameMoves) {
563 ReadyLabel = MMI.getContext().CreateTempSymbol();
565 // Mark effective beginning of when frame pointer is ready.
566 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(ReadyLabel);
568 MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) :
569 (isPPC64 ? PPC::X1 : PPC::R1));
570 MachineLocation FPSrc(MachineLocation::VirtualFP);
571 MMI.addFrameMove(ReadyLabel, FPDst, FPSrc);
575 if (needsFrameMoves) {
576 MCSymbol *Label = HasFP ? ReadyLabel : FrameLabel;
578 // Add callee saved registers to move list.
579 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
580 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
581 unsigned Reg = CSI[I].getReg();
582 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
584 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
585 // subregisters of CR2. We just need to emit a move of CR2.
586 if (PPC::CRBITRCRegClass.contains(Reg))
589 // For SVR4, don't emit a move for the CR spill slot if we haven't
591 if (Subtarget.isSVR4ABI()
592 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
593 && MustSaveCRs.empty())
596 // For 64-bit SVR4 when we have spilled CRs, the spill location
597 // is SP+8, not a frame-relative slot.
598 if (Subtarget.isSVR4ABI()
599 && Subtarget.isPPC64()
600 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
601 MachineLocation CSDst(PPC::X1, 8);
602 MachineLocation CSSrc(PPC::CR2);
603 MMI.addFrameMove(Label, CSDst, CSSrc);
607 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
608 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
609 MachineLocation CSSrc(Reg);
610 MMI.addFrameMove(Label, CSDst, CSSrc);
615 void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
616 MachineBasicBlock &MBB) const {
617 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
618 assert(MBBI != MBB.end() && "Returning block has no terminator");
619 const PPCInstrInfo &TII =
620 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
622 unsigned RetOpcode = MBBI->getOpcode();
625 assert((RetOpcode == PPC::BLR ||
626 RetOpcode == PPC::TCRETURNri ||
627 RetOpcode == PPC::TCRETURNdi ||
628 RetOpcode == PPC::TCRETURNai ||
629 RetOpcode == PPC::TCRETURNri8 ||
630 RetOpcode == PPC::TCRETURNdi8 ||
631 RetOpcode == PPC::TCRETURNai8) &&
632 "Can only insert epilog into returning blocks");
634 // Get alignment info so we know how to restore r1
635 const MachineFrameInfo *MFI = MF.getFrameInfo();
636 unsigned TargetAlign = getStackAlignment();
637 unsigned MaxAlign = MFI->getMaxAlignment();
639 // Get the number of bytes allocated from the FrameInfo.
640 int FrameSize = MFI->getStackSize();
642 // Get processor type.
643 bool isPPC64 = Subtarget.isPPC64();
644 // Get operating system
645 bool isDarwinABI = Subtarget.isDarwinABI();
646 // Check if the link register (LR) has been saved.
647 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
648 bool MustSaveLR = FI->mustSaveLR();
649 const SmallVector<unsigned, 3> &MustSaveCRs = FI->getMustSaveCRs();
650 // Do we have a frame pointer for this function?
651 bool HasFP = hasFP(MF);
653 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
657 if (Subtarget.isSVR4ABI()) {
658 MachineFrameInfo *FFI = MF.getFrameInfo();
659 int FPIndex = FI->getFramePointerSaveIndex();
660 assert(FPIndex && "No Frame Pointer Save Slot!");
661 FPOffset = FFI->getObjectOffset(FPIndex);
663 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
667 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
668 RetOpcode == PPC::TCRETURNdi ||
669 RetOpcode == PPC::TCRETURNai ||
670 RetOpcode == PPC::TCRETURNri8 ||
671 RetOpcode == PPC::TCRETURNdi8 ||
672 RetOpcode == PPC::TCRETURNai8;
675 int MaxTCRetDelta = FI->getTailCallSPDelta();
676 MachineOperand &StackAdjust = MBBI->getOperand(1);
677 assert(StackAdjust.isImm() && "Expecting immediate value.");
678 // Adjust stack pointer.
679 int StackAdj = StackAdjust.getImm();
680 int Delta = StackAdj - MaxTCRetDelta;
681 assert((Delta >= 0) && "Delta must be positive");
683 FrameSize += (StackAdj +Delta);
685 FrameSize += StackAdj;
689 // The loaded (or persistent) stack pointer value is offset by the 'stwu'
690 // on entry to the function. Add this offset back now.
692 // If this function contained a fastcc call and GuaranteedTailCallOpt is
693 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
694 // call which invalidates the stack pointer value in SP(0). So we use the
695 // value of R31 in this case.
696 if (FI->hasFastCall() && isInt<16>(FrameSize)) {
697 assert(hasFP(MF) && "Expecting a valid the frame pointer.");
698 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
699 .addReg(PPC::R31).addImm(FrameSize);
700 } else if(FI->hasFastCall()) {
701 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
702 .addImm(FrameSize >> 16);
703 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
704 .addReg(PPC::R0, RegState::Kill)
705 .addImm(FrameSize & 0xFFFF);
706 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4))
710 } else if (isInt<16>(FrameSize) &&
711 (!ALIGN_STACK || TargetAlign >= MaxAlign) &&
712 !MFI->hasVarSizedObjects()) {
713 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
714 .addReg(PPC::R1).addImm(FrameSize);
716 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1)
717 .addImm(0).addReg(PPC::R1);
720 if (FI->hasFastCall() && isInt<16>(FrameSize)) {
721 assert(hasFP(MF) && "Expecting a valid the frame pointer.");
722 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
723 .addReg(PPC::X31).addImm(FrameSize);
724 } else if(FI->hasFastCall()) {
725 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
726 .addImm(FrameSize >> 16);
727 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
728 .addReg(PPC::X0, RegState::Kill)
729 .addImm(FrameSize & 0xFFFF);
730 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8))
734 } else if (isInt<16>(FrameSize) && TargetAlign >= MaxAlign &&
735 !MFI->hasVarSizedObjects()) {
736 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
737 .addReg(PPC::X1).addImm(FrameSize);
739 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1)
740 .addImm(0).addReg(PPC::X1);
747 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0)
748 .addImm(LROffset/4).addReg(PPC::X1);
750 if (!MustSaveCRs.empty())
751 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), PPC::X12)
752 .addImm(8).addReg(PPC::X1);
755 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31)
756 .addImm(FPOffset/4).addReg(PPC::X1);
758 if (!MustSaveCRs.empty())
759 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
760 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTCRF8), MustSaveCRs[i])
761 .addReg(PPC::X12, getKillRegState(i == e-1));
764 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0);
767 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0)
768 .addImm(LROffset).addReg(PPC::R1);
770 assert(MustSaveCRs.empty() &&
771 "Epilogue CR restoring supported only in 64-bit mode");
774 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31)
775 .addImm(FPOffset).addReg(PPC::R1);
778 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0);
781 // Callee pop calling convention. Pop parameter/linkage area. Used for tail
783 if (MF.getTarget().Options.GuaranteedTailCallOpt && RetOpcode == PPC::BLR &&
784 MF.getFunction()->getCallingConv() == CallingConv::Fast) {
785 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
786 unsigned CallerAllocatedAmt = FI->getMinReservedArea();
787 unsigned StackReg = isPPC64 ? PPC::X1 : PPC::R1;
788 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
789 unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0;
790 unsigned ADDIInstr = isPPC64 ? PPC::ADDI8 : PPC::ADDI;
791 unsigned ADDInstr = isPPC64 ? PPC::ADD8 : PPC::ADD4;
792 unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS;
793 unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI;
795 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
796 BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg)
797 .addReg(StackReg).addImm(CallerAllocatedAmt);
799 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
800 .addImm(CallerAllocatedAmt >> 16);
801 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
802 .addReg(TmpReg, RegState::Kill)
803 .addImm(CallerAllocatedAmt & 0xFFFF);
804 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
809 } else if (RetOpcode == PPC::TCRETURNdi) {
810 MBBI = MBB.getLastNonDebugInstr();
811 MachineOperand &JumpTarget = MBBI->getOperand(0);
812 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
813 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
814 } else if (RetOpcode == PPC::TCRETURNri) {
815 MBBI = MBB.getLastNonDebugInstr();
816 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
817 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
818 } else if (RetOpcode == PPC::TCRETURNai) {
819 MBBI = MBB.getLastNonDebugInstr();
820 MachineOperand &JumpTarget = MBBI->getOperand(0);
821 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
822 } else if (RetOpcode == PPC::TCRETURNdi8) {
823 MBBI = MBB.getLastNonDebugInstr();
824 MachineOperand &JumpTarget = MBBI->getOperand(0);
825 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
826 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
827 } else if (RetOpcode == PPC::TCRETURNri8) {
828 MBBI = MBB.getLastNonDebugInstr();
829 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
830 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
831 } else if (RetOpcode == PPC::TCRETURNai8) {
832 MBBI = MBB.getLastNonDebugInstr();
833 MachineOperand &JumpTarget = MBBI->getOperand(0);
834 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
838 /// MustSaveLR - Return true if this function requires that we save the LR
839 /// register onto the stack in the prolog and restore it in the epilog of the
841 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
842 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
844 // We need a save/restore of LR if there is any def of LR (which is
845 // defined by calls, including the PIC setup sequence), or if there is
846 // some use of the LR stack slot (e.g. for builtin_return_address).
847 // (LR comes in 32 and 64 bit versions.)
848 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
849 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
853 PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
854 RegScavenger *) const {
855 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
857 // Save and clear the LR state.
858 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
859 unsigned LR = RegInfo->getRARegister();
860 FI->setMustSaveLR(MustSaveLR(MF, LR));
861 MachineRegisterInfo &MRI = MF.getRegInfo();
862 MRI.setPhysRegUnused(LR);
864 // Save R31 if necessary
865 int FPSI = FI->getFramePointerSaveIndex();
866 bool isPPC64 = Subtarget.isPPC64();
867 bool isDarwinABI = Subtarget.isDarwinABI();
868 MachineFrameInfo *MFI = MF.getFrameInfo();
870 // If the frame pointer save index hasn't been defined yet.
871 if (!FPSI && needsFP(MF)) {
872 // Find out what the fix offset of the frame pointer save area.
873 int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI);
874 // Allocate the frame index for frame pointer save area.
875 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
877 FI->setFramePointerSaveIndex(FPSI);
880 // Reserve stack space to move the linkage area to in case of a tail call.
882 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
883 (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
884 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
887 // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
888 // function uses CR 2, 3, or 4.
889 if (!isPPC64 && !isDarwinABI &&
890 (MRI.isPhysRegUsed(PPC::CR2) ||
891 MRI.isPhysRegUsed(PPC::CR3) ||
892 MRI.isPhysRegUsed(PPC::CR4))) {
893 int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true);
894 FI->setCRSpillFrameIndex(FrameIdx);
898 void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
899 RegScavenger *RS) const {
900 // Early exit if not using the SVR4 ABI.
901 if (!Subtarget.isSVR4ABI()) {
902 addScavengingSpillSlot(MF, RS);
906 // Get callee saved register information.
907 MachineFrameInfo *FFI = MF.getFrameInfo();
908 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
910 // Early exit if no callee saved registers are modified!
911 if (CSI.empty() && !needsFP(MF)) {
912 addScavengingSpillSlot(MF, RS);
916 unsigned MinGPR = PPC::R31;
917 unsigned MinG8R = PPC::X31;
918 unsigned MinFPR = PPC::F31;
919 unsigned MinVR = PPC::V31;
921 bool HasGPSaveArea = false;
922 bool HasG8SaveArea = false;
923 bool HasFPSaveArea = false;
924 bool HasVRSAVESaveArea = false;
925 bool HasVRSaveArea = false;
927 SmallVector<CalleeSavedInfo, 18> GPRegs;
928 SmallVector<CalleeSavedInfo, 18> G8Regs;
929 SmallVector<CalleeSavedInfo, 18> FPRegs;
930 SmallVector<CalleeSavedInfo, 18> VRegs;
932 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
933 unsigned Reg = CSI[i].getReg();
934 if (PPC::GPRCRegClass.contains(Reg)) {
935 HasGPSaveArea = true;
937 GPRegs.push_back(CSI[i]);
942 } else if (PPC::G8RCRegClass.contains(Reg)) {
943 HasG8SaveArea = true;
945 G8Regs.push_back(CSI[i]);
950 } else if (PPC::F8RCRegClass.contains(Reg)) {
951 HasFPSaveArea = true;
953 FPRegs.push_back(CSI[i]);
958 } else if (PPC::CRBITRCRegClass.contains(Reg) ||
959 PPC::CRRCRegClass.contains(Reg)) {
960 ; // do nothing, as we already know whether CRs are spilled
961 } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
962 HasVRSAVESaveArea = true;
963 } else if (PPC::VRRCRegClass.contains(Reg)) {
964 HasVRSaveArea = true;
966 VRegs.push_back(CSI[i]);
972 llvm_unreachable("Unknown RegisterClass!");
976 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>();
977 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
979 int64_t LowerBound = 0;
981 // Take into account stack space reserved for tail calls.
983 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
984 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
985 LowerBound = TCSPDelta;
988 // The Floating-point register save area is right below the back chain word
989 // of the previous stack frame.
991 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
992 int FI = FPRegs[i].getFrameIdx();
994 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
997 LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8;
1000 // Check whether the frame pointer register is allocated. If so, make sure it
1001 // is spilled to the correct offset.
1003 HasGPSaveArea = true;
1005 int FI = PFI->getFramePointerSaveIndex();
1006 assert(FI && "No Frame Pointer Save Slot!");
1008 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1011 // General register save area starts right below the Floating-point
1012 // register save area.
1013 if (HasGPSaveArea || HasG8SaveArea) {
1014 // Move general register save area spill slots down, taking into account
1015 // the size of the Floating-point register save area.
1016 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
1017 int FI = GPRegs[i].getFrameIdx();
1019 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1022 // Move general register save area spill slots down, taking into account
1023 // the size of the Floating-point register save area.
1024 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
1025 int FI = G8Regs[i].getFrameIdx();
1027 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1031 std::min<unsigned>(TRI->getEncodingValue(MinGPR),
1032 TRI->getEncodingValue(MinG8R));
1034 if (Subtarget.isPPC64()) {
1035 LowerBound -= (31 - MinReg + 1) * 8;
1037 LowerBound -= (31 - MinReg + 1) * 4;
1041 // For 32-bit only, the CR save area is below the general register
1042 // save area. For 64-bit SVR4, the CR save area is addressed relative
1043 // to the stack pointer and hence does not need an adjustment here.
1044 // Only CR2 (the first nonvolatile spilled) has an associated frame
1045 // index so that we have a single uniform save area.
1046 if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) {
1047 // Adjust the frame index of the CR spill slot.
1048 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1049 unsigned Reg = CSI[i].getReg();
1051 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
1052 // Leave Darwin logic as-is.
1053 || (!Subtarget.isSVR4ABI() &&
1054 (PPC::CRBITRCRegClass.contains(Reg) ||
1055 PPC::CRRCRegClass.contains(Reg)))) {
1056 int FI = CSI[i].getFrameIdx();
1058 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1062 LowerBound -= 4; // The CR save area is always 4 bytes long.
1065 if (HasVRSAVESaveArea) {
1066 // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1067 // which have the VRSAVE register class?
1068 // Adjust the frame index of the VRSAVE spill slot.
1069 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1070 unsigned Reg = CSI[i].getReg();
1072 if (PPC::VRSAVERCRegClass.contains(Reg)) {
1073 int FI = CSI[i].getFrameIdx();
1075 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1079 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
1082 if (HasVRSaveArea) {
1083 // Insert alignment padding, we need 16-byte alignment.
1084 LowerBound = (LowerBound - 15) & ~(15);
1086 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
1087 int FI = VRegs[i].getFrameIdx();
1089 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1093 addScavengingSpillSlot(MF, RS);
1097 PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
1098 RegScavenger *RS) const {
1099 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
1100 // a large stack, which will require scavenging a register to materialize a
1103 // We need to have a scavenger spill slot for spills if the frame size is
1104 // large. In case there is no free register for large-offset addressing,
1105 // this slot is used for the necessary emergency spill. Also, we need the
1106 // slot for dynamic stack allocations.
1108 // The scavenger might be invoked if the frame offset does not fit into
1109 // the 16-bit immediate. We don't know the complete frame size here
1110 // because we've not yet computed callee-saved register spills or the
1111 // needed alignment padding.
1112 unsigned StackSize = determineFrameLayout(MF, false, true);
1113 MachineFrameInfo *MFI = MF.getFrameInfo();
1114 if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) ||
1115 hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) {
1116 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1117 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1118 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
1119 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1123 // These kinds of spills might need two registers.
1124 if (spillsCR(MF) || spillsVRSAVE(MF))
1125 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1133 PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1134 MachineBasicBlock::iterator MI,
1135 const std::vector<CalleeSavedInfo> &CSI,
1136 const TargetRegisterInfo *TRI) const {
1138 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1139 // Return false otherwise to maintain pre-existing behavior.
1140 if (!Subtarget.isSVR4ABI())
1143 MachineFunction *MF = MBB.getParent();
1144 const PPCInstrInfo &TII =
1145 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1147 bool CRSpilled = false;
1148 MachineInstrBuilder CRMIB;
1150 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1151 unsigned Reg = CSI[i].getReg();
1152 // CR2 through CR4 are the nonvolatile CR fields.
1153 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
1155 // Add the callee-saved register as live-in; it's killed at the spill.
1158 if (CRSpilled && IsCRField) {
1159 CRMIB.addReg(Reg, RegState::ImplicitKill);
1163 // Insert the spill to the stack frame.
1165 PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
1166 if (Subtarget.isPPC64()) {
1167 // The actual spill will happen at the start of the prologue.
1168 FuncInfo->addMustSaveCR(Reg);
1172 // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have
1173 // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
1174 CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
1175 .addReg(Reg, RegState::ImplicitKill);
1177 MBB.insert(MI, CRMIB);
1178 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
1180 getKillRegState(true)),
1181 CSI[i].getFrameIdx()));
1184 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1185 TII.storeRegToStackSlot(MBB, MI, Reg, true,
1186 CSI[i].getFrameIdx(), RC, TRI);
1193 restoreCRs(bool isPPC64, bool is31,
1194 bool CR2Spilled, bool CR3Spilled, bool CR4Spilled,
1195 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1196 const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
1198 MachineFunction *MF = MBB.getParent();
1199 const PPCInstrInfo &TII =
1200 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1202 unsigned RestoreOp, MoveReg;
1205 // This is handled during epilogue generation.
1208 // 32-bit: FP-relative
1209 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
1211 CSI[CSIIndex].getFrameIdx()));
1212 RestoreOp = PPC::MTCRF;
1217 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
1218 .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled)));
1221 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
1222 .addReg(MoveReg, getKillRegState(!CR4Spilled)));
1225 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
1226 .addReg(MoveReg, getKillRegState(true)));
1229 void PPCFrameLowering::
1230 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1231 MachineBasicBlock::iterator I) const {
1232 const PPCInstrInfo &TII =
1233 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
1234 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1235 I->getOpcode() == PPC::ADJCALLSTACKUP) {
1236 // Add (actually subtract) back the amount the callee popped on return.
1237 if (int CalleeAmt = I->getOperand(1).getImm()) {
1238 bool is64Bit = Subtarget.isPPC64();
1240 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
1241 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
1242 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
1243 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
1244 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
1245 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
1246 MachineInstr *MI = I;
1247 DebugLoc dl = MI->getDebugLoc();
1249 if (isInt<16>(CalleeAmt)) {
1250 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
1251 .addReg(StackReg, RegState::Kill)
1254 MachineBasicBlock::iterator MBBI = I;
1255 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
1256 .addImm(CalleeAmt >> 16);
1257 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
1258 .addReg(TmpReg, RegState::Kill)
1259 .addImm(CalleeAmt & 0xFFFF);
1260 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
1261 .addReg(StackReg, RegState::Kill)
1266 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
1271 PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1272 MachineBasicBlock::iterator MI,
1273 const std::vector<CalleeSavedInfo> &CSI,
1274 const TargetRegisterInfo *TRI) const {
1276 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1277 // Return false otherwise to maintain pre-existing behavior.
1278 if (!Subtarget.isSVR4ABI())
1281 MachineFunction *MF = MBB.getParent();
1282 const PPCInstrInfo &TII =
1283 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1284 bool CR2Spilled = false;
1285 bool CR3Spilled = false;
1286 bool CR4Spilled = false;
1287 unsigned CSIIndex = 0;
1289 // Initialize insertion-point logic; we will be restoring in reverse
1291 MachineBasicBlock::iterator I = MI, BeforeI = I;
1292 bool AtStart = I == MBB.begin();
1297 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1298 unsigned Reg = CSI[i].getReg();
1300 if (Reg == PPC::CR2) {
1302 // The spill slot is associated only with CR2, which is the
1303 // first nonvolatile spilled. Save it here.
1306 } else if (Reg == PPC::CR3) {
1309 } else if (Reg == PPC::CR4) {
1313 // When we first encounter a non-CR register after seeing at
1314 // least one CR register, restore all spilled CRs together.
1315 if ((CR2Spilled || CR3Spilled || CR4Spilled)
1316 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1317 bool is31 = needsFP(*MF);
1318 restoreCRs(Subtarget.isPPC64(), is31,
1319 CR2Spilled, CR3Spilled, CR4Spilled,
1320 MBB, I, CSI, CSIIndex);
1321 CR2Spilled = CR3Spilled = CR4Spilled = false;
1324 // Default behavior for non-CR saves.
1325 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1326 TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(),
1328 assert(I != MBB.begin() &&
1329 "loadRegFromStackSlot didn't insert any code!");
1332 // Insert in reverse order.
1341 // If we haven't yet spilled the CRs, do so now.
1342 if (CR2Spilled || CR3Spilled || CR4Spilled) {
1343 bool is31 = needsFP(*MF);
1344 restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled,
1345 MBB, I, CSI, CSIIndex);