1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PPC implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCFrameLowering.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCInstrInfo.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCSubtarget.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineModuleInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/Target/TargetOptions.h"
30 /// VRRegNo - Map from a numbered VR register to its enum value.
32 static const uint16_t VRRegNo[] = {
33 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
34 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
35 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
36 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
39 PPCFrameLowering::PPCFrameLowering(const PPCSubtarget &STI)
40 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
41 (STI.hasQPX() || STI.isBGQ()) ? 32 : 16, 0),
44 // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
45 const PPCFrameLowering::SpillSlot *PPCFrameLowering::getCalleeSavedSpillSlots(
46 unsigned &NumEntries) const {
47 if (Subtarget.isDarwinABI()) {
49 if (Subtarget.isPPC64()) {
50 static const SpillSlot darwin64Offsets = {PPC::X31, -8};
51 return &darwin64Offsets;
53 static const SpillSlot darwinOffsets = {PPC::R31, -4};
54 return &darwinOffsets;
58 // Early exit if not using the SVR4 ABI.
59 if (!Subtarget.isSVR4ABI()) {
64 // Note that the offsets here overlap, but this is fixed up in
65 // processFunctionBeforeFrameFinalized.
67 static const SpillSlot Offsets[] = {
68 // Floating-point register save area offsets.
88 // General register save area offsets.
108 // CR save area offset. We map each of the nonvolatile CR fields
109 // to the slot for CR2, which is the first of the nonvolatile CR
110 // fields to be assigned, so that we only allocate one save slot.
111 // See PPCRegisterInfo::hasReservedSpillSlot() for more information.
114 // VRSAVE save area offset.
117 // Vector register save area
131 static const SpillSlot Offsets64[] = {
132 // Floating-point register save area offsets.
152 // General register save area offsets.
172 // VRSAVE save area offset.
175 // Vector register save area
189 if (Subtarget.isPPC64()) {
190 NumEntries = array_lengthof(Offsets64);
194 NumEntries = array_lengthof(Offsets);
200 /// RemoveVRSaveCode - We have found that this function does not need any code
201 /// to manipulate the VRSAVE register, even though it uses vector registers.
202 /// This can happen when the only registers used are known to be live in or out
203 /// of the function. Remove all of the VRSAVE related code from the function.
204 /// FIXME: The removal of the code results in a compile failure at -O0 when the
205 /// function contains a function call, as the GPR containing original VRSAVE
206 /// contents is spilled and reloaded around the call. Without the prolog code,
207 /// the spill instruction refers to an undefined register. This code needs
208 /// to account for all uses of that GPR.
209 static void RemoveVRSaveCode(MachineInstr *MI) {
210 MachineBasicBlock *Entry = MI->getParent();
211 MachineFunction *MF = Entry->getParent();
213 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
214 MachineBasicBlock::iterator MBBI = MI;
216 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
217 MBBI->eraseFromParent();
219 bool RemovedAllMTVRSAVEs = true;
220 // See if we can find and remove the MTVRSAVE instruction from all of the
222 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
223 // If last instruction is a return instruction, add an epilogue
224 if (!I->empty() && I->back().isReturn()) {
225 bool FoundIt = false;
226 for (MBBI = I->end(); MBBI != I->begin(); ) {
228 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
229 MBBI->eraseFromParent(); // remove it.
234 RemovedAllMTVRSAVEs &= FoundIt;
238 // If we found and removed all MTVRSAVE instructions, remove the read of
240 if (RemovedAllMTVRSAVEs) {
242 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
244 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
245 MBBI->eraseFromParent();
248 // Finally, nuke the UPDATE_VRSAVE.
249 MI->eraseFromParent();
252 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
253 // instruction selector. Based on the vector registers that have been used,
254 // transform this into the appropriate ORI instruction.
255 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
256 MachineFunction *MF = MI->getParent()->getParent();
257 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
258 DebugLoc dl = MI->getDebugLoc();
260 unsigned UsedRegMask = 0;
261 for (unsigned i = 0; i != 32; ++i)
262 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
263 UsedRegMask |= 1 << (31-i);
265 // Live in and live out values already must be in the mask, so don't bother
267 for (MachineRegisterInfo::livein_iterator
268 I = MF->getRegInfo().livein_begin(),
269 E = MF->getRegInfo().livein_end(); I != E; ++I) {
270 unsigned RegNo = TRI->getEncodingValue(I->first);
271 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
272 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
275 // Live out registers appear as use operands on return instructions.
276 for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end();
277 UsedRegMask != 0 && BI != BE; ++BI) {
278 const MachineBasicBlock &MBB = *BI;
279 if (MBB.empty() || !MBB.back().isReturn())
281 const MachineInstr &Ret = MBB.back();
282 for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) {
283 const MachineOperand &MO = Ret.getOperand(I);
284 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
286 unsigned RegNo = TRI->getEncodingValue(MO.getReg());
287 UsedRegMask &= ~(1 << (31-RegNo));
291 // If no registers are used, turn this into a copy.
292 if (UsedRegMask == 0) {
293 // Remove all VRSAVE code.
294 RemoveVRSaveCode(MI);
298 unsigned SrcReg = MI->getOperand(1).getReg();
299 unsigned DstReg = MI->getOperand(0).getReg();
301 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
302 if (DstReg != SrcReg)
303 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
305 .addImm(UsedRegMask);
307 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
308 .addReg(SrcReg, RegState::Kill)
309 .addImm(UsedRegMask);
310 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
311 if (DstReg != SrcReg)
312 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
314 .addImm(UsedRegMask >> 16);
316 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
317 .addReg(SrcReg, RegState::Kill)
318 .addImm(UsedRegMask >> 16);
320 if (DstReg != SrcReg)
321 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
323 .addImm(UsedRegMask >> 16);
325 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
326 .addReg(SrcReg, RegState::Kill)
327 .addImm(UsedRegMask >> 16);
329 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
330 .addReg(DstReg, RegState::Kill)
331 .addImm(UsedRegMask & 0xFFFF);
334 // Remove the old UPDATE_VRSAVE instruction.
335 MI->eraseFromParent();
338 static bool spillsCR(const MachineFunction &MF) {
339 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
340 return FuncInfo->isCRSpilled();
343 static bool spillsVRSAVE(const MachineFunction &MF) {
344 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
345 return FuncInfo->isVRSAVESpilled();
348 static bool hasSpills(const MachineFunction &MF) {
349 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
350 return FuncInfo->hasSpills();
353 static bool hasNonRISpills(const MachineFunction &MF) {
354 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
355 return FuncInfo->hasNonRISpills();
358 /// determineFrameLayout - Determine the size of the frame and maximum call
360 unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF,
362 bool UseEstimate) const {
363 MachineFrameInfo *MFI = MF.getFrameInfo();
365 // Get the number of bytes to allocate from the FrameInfo
367 UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize();
369 // Get stack alignments. The frame must be aligned to the greatest of these:
370 unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI
371 unsigned MaxAlign = MFI->getMaxAlignment(); // algmt required by data in frame
372 unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1;
374 const PPCRegisterInfo *RegInfo =
375 static_cast<const PPCRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
377 // If we are a leaf function, and use up to 224 bytes of stack space,
378 // don't have a frame pointer, calls, or dynamic alloca then we do not need
379 // to adjust the stack pointer (we fit in the Red Zone).
380 // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate
381 // stackless code if all local vars are reg-allocated.
382 bool DisableRedZone = MF.getFunction()->getAttributes().
383 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoRedZone);
384 if (!DisableRedZone &&
385 (Subtarget.isPPC64() || // 32-bit SVR4, no stack-
386 !Subtarget.isSVR4ABI() || // allocated locals.
388 FrameSize <= 224 && // Fits in red zone.
389 !MFI->hasVarSizedObjects() && // No dynamic alloca.
390 !MFI->adjustsStack() && // No calls.
391 !RegInfo->hasBasePointer(MF)) { // No special alignment.
394 MFI->setStackSize(0);
398 // Get the maximum call frame size of all the calls.
399 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
401 // Maximum call frame needs to be at least big enough for linkage area.
402 unsigned minCallFrameSize = getLinkageSize(Subtarget.isPPC64(),
403 Subtarget.isDarwinABI(),
404 Subtarget.isELFv2ABI());
405 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
407 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
408 // that allocations will be aligned.
409 if (MFI->hasVarSizedObjects())
410 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
412 // Update maximum call frame size.
414 MFI->setMaxCallFrameSize(maxCallFrameSize);
416 // Include call frame size in total.
417 FrameSize += maxCallFrameSize;
419 // Make sure the frame is aligned.
420 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
422 // Update frame info.
424 MFI->setStackSize(FrameSize);
429 // hasFP - Return true if the specified function actually has a dedicated frame
431 bool PPCFrameLowering::hasFP(const MachineFunction &MF) const {
432 const MachineFrameInfo *MFI = MF.getFrameInfo();
433 // FIXME: This is pretty much broken by design: hasFP() might be called really
434 // early, before the stack layout was calculated and thus hasFP() might return
435 // true or false here depending on the time of call.
436 return (MFI->getStackSize()) && needsFP(MF);
439 // needsFP - Return true if the specified function should have a dedicated frame
440 // pointer register. This is true if the function has variable sized allocas or
441 // if frame pointer elimination is disabled.
442 bool PPCFrameLowering::needsFP(const MachineFunction &MF) const {
443 const MachineFrameInfo *MFI = MF.getFrameInfo();
445 // Naked functions have no stack frame pushed, so we don't have a frame
447 if (MF.getFunction()->getAttributes().hasAttribute(
448 AttributeSet::FunctionIndex, Attribute::Naked))
451 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
452 MFI->hasVarSizedObjects() ||
453 (MF.getTarget().Options.GuaranteedTailCallOpt &&
454 MF.getInfo<PPCFunctionInfo>()->hasFastCall());
457 void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const {
458 bool is31 = needsFP(MF);
459 unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
460 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
462 const PPCRegisterInfo *RegInfo =
463 static_cast<const PPCRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
464 bool HasBP = RegInfo->hasBasePointer(MF);
465 unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg;
466 unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg;
468 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
470 for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) {
472 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
473 MachineOperand &MO = MBBI->getOperand(I);
477 switch (MO.getReg()) {
496 void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
497 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
498 MachineBasicBlock::iterator MBBI = MBB.begin();
499 MachineFrameInfo *MFI = MF.getFrameInfo();
500 const PPCInstrInfo &TII =
501 *static_cast<const PPCInstrInfo *>(MF.getSubtarget().getInstrInfo());
502 const PPCRegisterInfo *RegInfo =
503 static_cast<const PPCRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
505 MachineModuleInfo &MMI = MF.getMMI();
506 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
508 bool needsCFI = MMI.hasDebugInfo() ||
509 MF.getFunction()->needsUnwindTableEntry();
510 bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
512 // Get processor type.
513 bool isPPC64 = Subtarget.isPPC64();
515 bool isDarwinABI = Subtarget.isDarwinABI();
516 bool isSVR4ABI = Subtarget.isSVR4ABI();
517 bool isELFv2ABI = Subtarget.isELFv2ABI();
518 assert((isDarwinABI || isSVR4ABI) &&
519 "Currently only Darwin and SVR4 ABIs are supported for PowerPC.");
521 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
524 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
525 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
526 HandleVRSaveUpdate(MBBI, TII);
531 // Move MBBI back to the beginning of the function.
534 // Work out frame sizes.
535 unsigned FrameSize = determineFrameLayout(MF);
536 int NegFrameSize = -FrameSize;
537 if (!isInt<32>(NegFrameSize))
538 llvm_unreachable("Unhandled stack size!");
540 if (MFI->isFrameAddressTaken())
541 replaceFPWithRealFP(MF);
543 // Check if the link register (LR) must be saved.
544 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
545 bool MustSaveLR = FI->mustSaveLR();
546 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
547 // Do we have a frame pointer and/or base pointer for this function?
548 bool HasFP = hasFP(MF);
549 bool HasBP = RegInfo->hasBasePointer(MF);
551 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
552 unsigned BPReg = RegInfo->getBaseRegister(MF);
553 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
554 unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR;
555 unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0;
556 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
557 // ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.)
558 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8
560 const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD
562 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU
564 const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX
566 const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8
568 const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8
570 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
572 const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8
574 const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8
577 // Regarding this assert: Even though LR is saved in the caller's frame (i.e.,
578 // LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no
579 // Red Zone, an asynchronous event (a form of "callee") could claim a frame &
580 // overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR.
581 assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) &&
582 "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
584 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
589 MachineFrameInfo *FFI = MF.getFrameInfo();
590 int FPIndex = FI->getFramePointerSaveIndex();
591 assert(FPIndex && "No Frame Pointer Save Slot!");
592 FPOffset = FFI->getObjectOffset(FPIndex);
595 PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
602 MachineFrameInfo *FFI = MF.getFrameInfo();
603 int BPIndex = FI->getBasePointerSaveIndex();
604 assert(BPIndex && "No Base Pointer Save Slot!");
605 BPOffset = FFI->getObjectOffset(BPIndex);
608 PPCFrameLowering::getBasePointerSaveOffset(isPPC64,
615 if (FI->usesPICBase()) {
616 MachineFrameInfo *FFI = MF.getFrameInfo();
617 int PBPIndex = FI->getPICBasePointerSaveIndex();
618 assert(PBPIndex && "No PIC Base Pointer Save Slot!");
619 PBPOffset = FFI->getObjectOffset(PBPIndex);
622 // Get stack alignments.
623 unsigned MaxAlign = MFI->getMaxAlignment();
624 if (HasBP && MaxAlign > 1)
625 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
626 "Invalid alignment!");
628 // Frames of 32KB & larger require special handling because they cannot be
629 // indexed into with a simple STDU/STWU/STD/STW immediate offset operand.
630 bool isLargeFrame = !isInt<16>(NegFrameSize);
633 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
635 assert((isPPC64 || MustSaveCRs.empty()) &&
636 "Prologue CR saving supported only in 64-bit mode");
638 if (!MustSaveCRs.empty()) { // will only occur for PPC64
639 // FIXME: In the ELFv2 ABI, we are not required to save all CR fields.
640 // If only one or two CR fields are clobbered, it could be more
641 // efficient to use mfocrf to selectively save just those fields.
642 MachineInstrBuilder MIB =
643 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg);
644 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
645 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill);
649 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
650 BuildMI(MBB, MBBI, dl, StoreInst)
655 if (FI->usesPICBase())
656 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
657 BuildMI(MBB, MBBI, dl, StoreInst)
663 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
664 BuildMI(MBB, MBBI, dl, StoreInst)
670 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
671 BuildMI(MBB, MBBI, dl, StoreInst)
676 if (!MustSaveCRs.empty()) // will only occur for PPC64
677 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
678 .addReg(TempReg, getKillRegState(true))
682 // Skip the rest if this is a leaf function & all spills fit in the Red Zone.
683 if (!FrameSize) return;
685 // Adjust stack pointer: r1 += NegFrameSize.
686 // If there is a preferred stack alignment, align R1 now
689 // Save a copy of r1 as the base pointer.
690 BuildMI(MBB, MBBI, dl, OrInst, BPReg)
695 if (HasBP && MaxAlign > 1) {
697 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)
700 .addImm(64 - Log2_32(MaxAlign));
702 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)
705 .addImm(32 - Log2_32(MaxAlign))
708 BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg)
709 .addReg(ScratchReg, RegState::Kill)
710 .addImm(NegFrameSize);
712 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg)
713 .addImm(NegFrameSize >> 16);
714 BuildMI(MBB, MBBI, dl, OrImmInst, TempReg)
715 .addReg(TempReg, RegState::Kill)
716 .addImm(NegFrameSize & 0xFFFF);
717 BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg)
718 .addReg(ScratchReg, RegState::Kill)
719 .addReg(TempReg, RegState::Kill);
721 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
722 .addReg(SPReg, RegState::Kill)
726 } else if (!isLargeFrame) {
727 BuildMI(MBB, MBBI, dl, StoreUpdtInst, SPReg)
729 .addImm(NegFrameSize)
733 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
734 .addImm(NegFrameSize >> 16);
735 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
736 .addReg(ScratchReg, RegState::Kill)
737 .addImm(NegFrameSize & 0xFFFF);
738 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
739 .addReg(SPReg, RegState::Kill)
744 // Add Call Frame Information for the instructions we generated above.
749 // Define CFA in terms of BP. Do this in preference to using FP/SP,
750 // because if the stack needed aligning then CFA won't be at a fixed
751 // offset from FP/SP.
752 unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
753 CFIIndex = MMI.addFrameInst(
754 MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
756 // Adjust the definition of CFA to account for the change in SP.
757 assert(NegFrameSize);
758 CFIIndex = MMI.addFrameInst(
759 MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize));
761 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
762 .addCFIIndex(CFIIndex);
765 // Describe where FP was saved, at a fixed offset from CFA.
766 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
767 CFIIndex = MMI.addFrameInst(
768 MCCFIInstruction::createOffset(nullptr, Reg, FPOffset));
769 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
770 .addCFIIndex(CFIIndex);
773 if (FI->usesPICBase()) {
774 // Describe where FP was saved, at a fixed offset from CFA.
775 unsigned Reg = MRI->getDwarfRegNum(PPC::R30, true);
776 CFIIndex = MMI.addFrameInst(
777 MCCFIInstruction::createOffset(nullptr, Reg, PBPOffset));
778 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
779 .addCFIIndex(CFIIndex);
783 // Describe where BP was saved, at a fixed offset from CFA.
784 unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
785 CFIIndex = MMI.addFrameInst(
786 MCCFIInstruction::createOffset(nullptr, Reg, BPOffset));
787 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
788 .addCFIIndex(CFIIndex);
792 // Describe where LR was saved, at a fixed offset from CFA.
793 unsigned Reg = MRI->getDwarfRegNum(LRReg, true);
794 CFIIndex = MMI.addFrameInst(
795 MCCFIInstruction::createOffset(nullptr, Reg, LROffset));
796 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
797 .addCFIIndex(CFIIndex);
801 // If there is a frame pointer, copy R1 into R31
803 BuildMI(MBB, MBBI, dl, OrInst, FPReg)
807 if (!HasBP && needsCFI) {
808 // Change the definition of CFA from SP+offset to FP+offset, because SP
809 // will change at every alloca.
810 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
811 unsigned CFIIndex = MMI.addFrameInst(
812 MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
814 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
815 .addCFIIndex(CFIIndex);
820 // Describe where callee saved registers were saved, at fixed offsets from
822 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
823 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
824 unsigned Reg = CSI[I].getReg();
825 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
827 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
828 // subregisters of CR2. We just need to emit a move of CR2.
829 if (PPC::CRBITRCRegClass.contains(Reg))
832 // For SVR4, don't emit a move for the CR spill slot if we haven't
834 if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
835 && MustSaveCRs.empty())
838 // For 64-bit SVR4 when we have spilled CRs, the spill location
839 // is SP+8, not a frame-relative slot.
840 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
841 // In the ELFv1 ABI, only CR2 is noted in CFI and stands in for
842 // the whole CR word. In the ELFv2 ABI, every CR that was
843 // actually saved gets its own CFI record.
844 unsigned CRReg = isELFv2ABI? Reg : (unsigned) PPC::CR2;
845 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
846 nullptr, MRI->getDwarfRegNum(CRReg, true), 8));
847 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
848 .addCFIIndex(CFIIndex);
852 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
853 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
854 nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
855 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
856 .addCFIIndex(CFIIndex);
861 void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
862 MachineBasicBlock &MBB) const {
863 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
864 assert(MBBI != MBB.end() && "Returning block has no terminator");
865 const PPCInstrInfo &TII =
866 *static_cast<const PPCInstrInfo *>(MF.getSubtarget().getInstrInfo());
867 const PPCRegisterInfo *RegInfo =
868 static_cast<const PPCRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
870 unsigned RetOpcode = MBBI->getOpcode();
873 assert((RetOpcode == PPC::BLR ||
874 RetOpcode == PPC::BLR8 ||
875 RetOpcode == PPC::TCRETURNri ||
876 RetOpcode == PPC::TCRETURNdi ||
877 RetOpcode == PPC::TCRETURNai ||
878 RetOpcode == PPC::TCRETURNri8 ||
879 RetOpcode == PPC::TCRETURNdi8 ||
880 RetOpcode == PPC::TCRETURNai8) &&
881 "Can only insert epilog into returning blocks");
883 // Get alignment info so we know how to restore the SP.
884 const MachineFrameInfo *MFI = MF.getFrameInfo();
886 // Get the number of bytes allocated from the FrameInfo.
887 int FrameSize = MFI->getStackSize();
889 // Get processor type.
890 bool isPPC64 = Subtarget.isPPC64();
892 bool isDarwinABI = Subtarget.isDarwinABI();
893 bool isSVR4ABI = Subtarget.isSVR4ABI();
894 bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
896 // Check if the link register (LR) has been saved.
897 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
898 bool MustSaveLR = FI->mustSaveLR();
899 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
900 // Do we have a frame pointer and/or base pointer for this function?
901 bool HasFP = hasFP(MF);
902 bool HasBP = RegInfo->hasBasePointer(MF);
904 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
905 unsigned BPReg = RegInfo->getBaseRegister(MF);
906 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
907 unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0;
908 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
909 const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8
911 const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD
913 const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8
915 const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8
917 const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8
919 const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8
922 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
927 MachineFrameInfo *FFI = MF.getFrameInfo();
928 int FPIndex = FI->getFramePointerSaveIndex();
929 assert(FPIndex && "No Frame Pointer Save Slot!");
930 FPOffset = FFI->getObjectOffset(FPIndex);
933 PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
940 MachineFrameInfo *FFI = MF.getFrameInfo();
941 int BPIndex = FI->getBasePointerSaveIndex();
942 assert(BPIndex && "No Base Pointer Save Slot!");
943 BPOffset = FFI->getObjectOffset(BPIndex);
946 PPCFrameLowering::getBasePointerSaveOffset(isPPC64,
953 if (FI->usesPICBase()) {
954 MachineFrameInfo *FFI = MF.getFrameInfo();
955 int PBPIndex = FI->getPICBasePointerSaveIndex();
956 assert(PBPIndex && "No PIC Base Pointer Save Slot!");
957 PBPOffset = FFI->getObjectOffset(PBPIndex);
960 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
961 RetOpcode == PPC::TCRETURNdi ||
962 RetOpcode == PPC::TCRETURNai ||
963 RetOpcode == PPC::TCRETURNri8 ||
964 RetOpcode == PPC::TCRETURNdi8 ||
965 RetOpcode == PPC::TCRETURNai8;
968 int MaxTCRetDelta = FI->getTailCallSPDelta();
969 MachineOperand &StackAdjust = MBBI->getOperand(1);
970 assert(StackAdjust.isImm() && "Expecting immediate value.");
971 // Adjust stack pointer.
972 int StackAdj = StackAdjust.getImm();
973 int Delta = StackAdj - MaxTCRetDelta;
974 assert((Delta >= 0) && "Delta must be positive");
976 FrameSize += (StackAdj +Delta);
978 FrameSize += StackAdj;
981 // Frames of 32KB & larger require special handling because they cannot be
982 // indexed into with a simple LD/LWZ immediate offset operand.
983 bool isLargeFrame = !isInt<16>(FrameSize);
986 // In the prologue, the loaded (or persistent) stack pointer value is offset
987 // by the STDU/STDUX/STWU/STWUX instruction. Add this offset back now.
989 // If this function contained a fastcc call and GuaranteedTailCallOpt is
990 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
991 // call which invalidates the stack pointer value in SP(0). So we use the
992 // value of R31 in this case.
993 if (FI->hasFastCall()) {
994 assert(HasFP && "Expecting a valid frame pointer.");
996 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
997 .addReg(FPReg).addImm(FrameSize);
999 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1000 .addImm(FrameSize >> 16);
1001 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1002 .addReg(ScratchReg, RegState::Kill)
1003 .addImm(FrameSize & 0xFFFF);
1004 BuildMI(MBB, MBBI, dl, AddInst)
1007 .addReg(ScratchReg);
1009 } else if (!isLargeFrame && !HasBP && !MFI->hasVarSizedObjects()) {
1010 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1014 BuildMI(MBB, MBBI, dl, LoadInst, SPReg)
1022 BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
1026 assert((isPPC64 || MustSaveCRs.empty()) &&
1027 "Epilogue CR restoring supported only in 64-bit mode");
1029 if (!MustSaveCRs.empty()) // will only occur for PPC64
1030 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
1035 BuildMI(MBB, MBBI, dl, LoadInst, FPReg)
1039 if (FI->usesPICBase())
1040 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
1041 BuildMI(MBB, MBBI, dl, LoadInst)
1047 BuildMI(MBB, MBBI, dl, LoadInst, BPReg)
1051 if (!MustSaveCRs.empty()) // will only occur for PPC64
1052 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
1053 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
1054 .addReg(TempReg, getKillRegState(i == e-1));
1057 BuildMI(MBB, MBBI, dl, MTLRInst).addReg(ScratchReg);
1059 // Callee pop calling convention. Pop parameter/linkage area. Used for tail
1060 // call optimization
1061 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1062 (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) &&
1063 MF.getFunction()->getCallingConv() == CallingConv::Fast) {
1064 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1065 unsigned CallerAllocatedAmt = FI->getMinReservedArea();
1067 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
1068 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1069 .addReg(SPReg).addImm(CallerAllocatedAmt);
1071 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1072 .addImm(CallerAllocatedAmt >> 16);
1073 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1074 .addReg(ScratchReg, RegState::Kill)
1075 .addImm(CallerAllocatedAmt & 0xFFFF);
1076 BuildMI(MBB, MBBI, dl, AddInst)
1079 .addReg(ScratchReg);
1081 } else if (RetOpcode == PPC::TCRETURNdi) {
1082 MBBI = MBB.getLastNonDebugInstr();
1083 MachineOperand &JumpTarget = MBBI->getOperand(0);
1084 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
1085 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1086 } else if (RetOpcode == PPC::TCRETURNri) {
1087 MBBI = MBB.getLastNonDebugInstr();
1088 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1089 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
1090 } else if (RetOpcode == PPC::TCRETURNai) {
1091 MBBI = MBB.getLastNonDebugInstr();
1092 MachineOperand &JumpTarget = MBBI->getOperand(0);
1093 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
1094 } else if (RetOpcode == PPC::TCRETURNdi8) {
1095 MBBI = MBB.getLastNonDebugInstr();
1096 MachineOperand &JumpTarget = MBBI->getOperand(0);
1097 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
1098 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1099 } else if (RetOpcode == PPC::TCRETURNri8) {
1100 MBBI = MBB.getLastNonDebugInstr();
1101 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1102 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
1103 } else if (RetOpcode == PPC::TCRETURNai8) {
1104 MBBI = MBB.getLastNonDebugInstr();
1105 MachineOperand &JumpTarget = MBBI->getOperand(0);
1106 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
1110 /// MustSaveLR - Return true if this function requires that we save the LR
1111 /// register onto the stack in the prolog and restore it in the epilog of the
1113 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
1114 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
1116 // We need a save/restore of LR if there is any def of LR (which is
1117 // defined by calls, including the PIC setup sequence), or if there is
1118 // some use of the LR stack slot (e.g. for builtin_return_address).
1119 // (LR comes in 32 and 64 bit versions.)
1120 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
1121 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
1125 PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1126 RegScavenger *) const {
1127 const PPCRegisterInfo *RegInfo =
1128 static_cast<const PPCRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
1130 // Save and clear the LR state.
1131 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1132 unsigned LR = RegInfo->getRARegister();
1133 FI->setMustSaveLR(MustSaveLR(MF, LR));
1134 MachineRegisterInfo &MRI = MF.getRegInfo();
1135 MRI.setPhysRegUnused(LR);
1137 // Save R31 if necessary
1138 int FPSI = FI->getFramePointerSaveIndex();
1139 bool isPPC64 = Subtarget.isPPC64();
1140 bool isDarwinABI = Subtarget.isDarwinABI();
1141 bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
1142 MachineFrameInfo *MFI = MF.getFrameInfo();
1144 // If the frame pointer save index hasn't been defined yet.
1145 if (!FPSI && needsFP(MF)) {
1146 // Find out what the fix offset of the frame pointer save area.
1147 int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI);
1148 // Allocate the frame index for frame pointer save area.
1149 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
1151 FI->setFramePointerSaveIndex(FPSI);
1154 int BPSI = FI->getBasePointerSaveIndex();
1155 if (!BPSI && RegInfo->hasBasePointer(MF)) {
1156 int BPOffset = getBasePointerSaveOffset(isPPC64, isDarwinABI, isPIC);
1157 // Allocate the frame index for the base pointer save area.
1158 BPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, BPOffset, true);
1160 FI->setBasePointerSaveIndex(BPSI);
1163 // Reserve stack space for the PIC Base register (R30).
1164 // Only used in SVR4 32-bit.
1165 if (FI->usesPICBase()) {
1166 int PBPSI = FI->getPICBasePointerSaveIndex();
1167 PBPSI = MFI->CreateFixedObject(4, -8, true);
1168 FI->setPICBasePointerSaveIndex(PBPSI);
1171 // Reserve stack space to move the linkage area to in case of a tail call.
1173 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1174 (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
1175 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
1178 // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
1179 // function uses CR 2, 3, or 4.
1180 if (!isPPC64 && !isDarwinABI &&
1181 (MRI.isPhysRegUsed(PPC::CR2) ||
1182 MRI.isPhysRegUsed(PPC::CR3) ||
1183 MRI.isPhysRegUsed(PPC::CR4))) {
1184 int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true);
1185 FI->setCRSpillFrameIndex(FrameIdx);
1189 void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
1190 RegScavenger *RS) const {
1191 // Early exit if not using the SVR4 ABI.
1192 if (!Subtarget.isSVR4ABI()) {
1193 addScavengingSpillSlot(MF, RS);
1197 // Get callee saved register information.
1198 MachineFrameInfo *FFI = MF.getFrameInfo();
1199 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
1201 // Early exit if no callee saved registers are modified!
1202 if (CSI.empty() && !needsFP(MF)) {
1203 addScavengingSpillSlot(MF, RS);
1207 unsigned MinGPR = PPC::R31;
1208 unsigned MinG8R = PPC::X31;
1209 unsigned MinFPR = PPC::F31;
1210 unsigned MinVR = PPC::V31;
1212 bool HasGPSaveArea = false;
1213 bool HasG8SaveArea = false;
1214 bool HasFPSaveArea = false;
1215 bool HasVRSAVESaveArea = false;
1216 bool HasVRSaveArea = false;
1218 SmallVector<CalleeSavedInfo, 18> GPRegs;
1219 SmallVector<CalleeSavedInfo, 18> G8Regs;
1220 SmallVector<CalleeSavedInfo, 18> FPRegs;
1221 SmallVector<CalleeSavedInfo, 18> VRegs;
1223 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1224 unsigned Reg = CSI[i].getReg();
1225 if (PPC::GPRCRegClass.contains(Reg)) {
1226 HasGPSaveArea = true;
1228 GPRegs.push_back(CSI[i]);
1233 } else if (PPC::G8RCRegClass.contains(Reg)) {
1234 HasG8SaveArea = true;
1236 G8Regs.push_back(CSI[i]);
1241 } else if (PPC::F8RCRegClass.contains(Reg)) {
1242 HasFPSaveArea = true;
1244 FPRegs.push_back(CSI[i]);
1249 } else if (PPC::CRBITRCRegClass.contains(Reg) ||
1250 PPC::CRRCRegClass.contains(Reg)) {
1251 ; // do nothing, as we already know whether CRs are spilled
1252 } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1253 HasVRSAVESaveArea = true;
1254 } else if (PPC::VRRCRegClass.contains(Reg)) {
1255 HasVRSaveArea = true;
1257 VRegs.push_back(CSI[i]);
1263 llvm_unreachable("Unknown RegisterClass!");
1267 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>();
1268 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
1270 int64_t LowerBound = 0;
1272 // Take into account stack space reserved for tail calls.
1274 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1275 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
1276 LowerBound = TCSPDelta;
1279 // The Floating-point register save area is right below the back chain word
1280 // of the previous stack frame.
1281 if (HasFPSaveArea) {
1282 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
1283 int FI = FPRegs[i].getFrameIdx();
1285 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1288 LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8;
1291 // Check whether the frame pointer register is allocated. If so, make sure it
1292 // is spilled to the correct offset.
1294 HasGPSaveArea = true;
1296 int FI = PFI->getFramePointerSaveIndex();
1297 assert(FI && "No Frame Pointer Save Slot!");
1299 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1302 if (PFI->usesPICBase()) {
1303 HasGPSaveArea = true;
1305 int FI = PFI->getPICBasePointerSaveIndex();
1306 assert(FI && "No PIC Base Pointer Save Slot!");
1308 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1311 const PPCRegisterInfo *RegInfo =
1312 static_cast<const PPCRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
1313 if (RegInfo->hasBasePointer(MF)) {
1314 HasGPSaveArea = true;
1316 int FI = PFI->getBasePointerSaveIndex();
1317 assert(FI && "No Base Pointer Save Slot!");
1319 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1322 // General register save area starts right below the Floating-point
1323 // register save area.
1324 if (HasGPSaveArea || HasG8SaveArea) {
1325 // Move general register save area spill slots down, taking into account
1326 // the size of the Floating-point register save area.
1327 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
1328 int FI = GPRegs[i].getFrameIdx();
1330 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1333 // Move general register save area spill slots down, taking into account
1334 // the size of the Floating-point register save area.
1335 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
1336 int FI = G8Regs[i].getFrameIdx();
1338 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1342 std::min<unsigned>(TRI->getEncodingValue(MinGPR),
1343 TRI->getEncodingValue(MinG8R));
1345 if (Subtarget.isPPC64()) {
1346 LowerBound -= (31 - MinReg + 1) * 8;
1348 LowerBound -= (31 - MinReg + 1) * 4;
1352 // For 32-bit only, the CR save area is below the general register
1353 // save area. For 64-bit SVR4, the CR save area is addressed relative
1354 // to the stack pointer and hence does not need an adjustment here.
1355 // Only CR2 (the first nonvolatile spilled) has an associated frame
1356 // index so that we have a single uniform save area.
1357 if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) {
1358 // Adjust the frame index of the CR spill slot.
1359 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1360 unsigned Reg = CSI[i].getReg();
1362 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
1363 // Leave Darwin logic as-is.
1364 || (!Subtarget.isSVR4ABI() &&
1365 (PPC::CRBITRCRegClass.contains(Reg) ||
1366 PPC::CRRCRegClass.contains(Reg)))) {
1367 int FI = CSI[i].getFrameIdx();
1369 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1373 LowerBound -= 4; // The CR save area is always 4 bytes long.
1376 if (HasVRSAVESaveArea) {
1377 // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1378 // which have the VRSAVE register class?
1379 // Adjust the frame index of the VRSAVE spill slot.
1380 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1381 unsigned Reg = CSI[i].getReg();
1383 if (PPC::VRSAVERCRegClass.contains(Reg)) {
1384 int FI = CSI[i].getFrameIdx();
1386 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1390 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
1393 if (HasVRSaveArea) {
1394 // Insert alignment padding, we need 16-byte alignment.
1395 LowerBound = (LowerBound - 15) & ~(15);
1397 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
1398 int FI = VRegs[i].getFrameIdx();
1400 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1404 addScavengingSpillSlot(MF, RS);
1408 PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
1409 RegScavenger *RS) const {
1410 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
1411 // a large stack, which will require scavenging a register to materialize a
1414 // We need to have a scavenger spill slot for spills if the frame size is
1415 // large. In case there is no free register for large-offset addressing,
1416 // this slot is used for the necessary emergency spill. Also, we need the
1417 // slot for dynamic stack allocations.
1419 // The scavenger might be invoked if the frame offset does not fit into
1420 // the 16-bit immediate. We don't know the complete frame size here
1421 // because we've not yet computed callee-saved register spills or the
1422 // needed alignment padding.
1423 unsigned StackSize = determineFrameLayout(MF, false, true);
1424 MachineFrameInfo *MFI = MF.getFrameInfo();
1425 if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) ||
1426 hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) {
1427 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1428 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1429 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
1430 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1434 // Might we have over-aligned allocas?
1435 bool HasAlVars = MFI->hasVarSizedObjects() &&
1436 MFI->getMaxAlignment() > getStackAlignment();
1438 // These kinds of spills might need two registers.
1439 if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars)
1440 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1448 PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1449 MachineBasicBlock::iterator MI,
1450 const std::vector<CalleeSavedInfo> &CSI,
1451 const TargetRegisterInfo *TRI) const {
1453 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1454 // Return false otherwise to maintain pre-existing behavior.
1455 if (!Subtarget.isSVR4ABI())
1458 MachineFunction *MF = MBB.getParent();
1459 const PPCInstrInfo &TII =
1460 *static_cast<const PPCInstrInfo *>(MF->getSubtarget().getInstrInfo());
1462 bool CRSpilled = false;
1463 MachineInstrBuilder CRMIB;
1465 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1466 unsigned Reg = CSI[i].getReg();
1467 // Only Darwin actually uses the VRSAVE register, but it can still appear
1468 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1469 // Darwin, ignore it.
1470 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1473 // CR2 through CR4 are the nonvolatile CR fields.
1474 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
1476 // Add the callee-saved register as live-in; it's killed at the spill.
1479 if (CRSpilled && IsCRField) {
1480 CRMIB.addReg(Reg, RegState::ImplicitKill);
1484 // Insert the spill to the stack frame.
1486 PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
1487 if (Subtarget.isPPC64()) {
1488 // The actual spill will happen at the start of the prologue.
1489 FuncInfo->addMustSaveCR(Reg);
1492 FuncInfo->setSpillsCR();
1494 // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have
1495 // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
1496 CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
1497 .addReg(Reg, RegState::ImplicitKill);
1499 MBB.insert(MI, CRMIB);
1500 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
1502 getKillRegState(true)),
1503 CSI[i].getFrameIdx()));
1506 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1507 TII.storeRegToStackSlot(MBB, MI, Reg, true,
1508 CSI[i].getFrameIdx(), RC, TRI);
1515 restoreCRs(bool isPPC64, bool is31,
1516 bool CR2Spilled, bool CR3Spilled, bool CR4Spilled,
1517 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1518 const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
1520 MachineFunction *MF = MBB.getParent();
1521 const PPCInstrInfo &TII =
1522 *static_cast<const PPCInstrInfo *>(MF->getSubtarget().getInstrInfo());
1524 unsigned RestoreOp, MoveReg;
1527 // This is handled during epilogue generation.
1530 // 32-bit: FP-relative
1531 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
1533 CSI[CSIIndex].getFrameIdx()));
1534 RestoreOp = PPC::MTOCRF;
1539 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
1540 .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled)));
1543 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
1544 .addReg(MoveReg, getKillRegState(!CR4Spilled)));
1547 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
1548 .addReg(MoveReg, getKillRegState(true)));
1551 void PPCFrameLowering::
1552 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1553 MachineBasicBlock::iterator I) const {
1554 const PPCInstrInfo &TII =
1555 *static_cast<const PPCInstrInfo *>(MF.getSubtarget().getInstrInfo());
1556 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1557 I->getOpcode() == PPC::ADJCALLSTACKUP) {
1558 // Add (actually subtract) back the amount the callee popped on return.
1559 if (int CalleeAmt = I->getOperand(1).getImm()) {
1560 bool is64Bit = Subtarget.isPPC64();
1562 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
1563 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
1564 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
1565 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
1566 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
1567 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
1568 MachineInstr *MI = I;
1569 DebugLoc dl = MI->getDebugLoc();
1571 if (isInt<16>(CalleeAmt)) {
1572 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
1573 .addReg(StackReg, RegState::Kill)
1576 MachineBasicBlock::iterator MBBI = I;
1577 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
1578 .addImm(CalleeAmt >> 16);
1579 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
1580 .addReg(TmpReg, RegState::Kill)
1581 .addImm(CalleeAmt & 0xFFFF);
1582 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
1583 .addReg(StackReg, RegState::Kill)
1588 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
1593 PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1594 MachineBasicBlock::iterator MI,
1595 const std::vector<CalleeSavedInfo> &CSI,
1596 const TargetRegisterInfo *TRI) const {
1598 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1599 // Return false otherwise to maintain pre-existing behavior.
1600 if (!Subtarget.isSVR4ABI())
1603 MachineFunction *MF = MBB.getParent();
1604 const PPCInstrInfo &TII =
1605 *static_cast<const PPCInstrInfo *>(MF->getSubtarget().getInstrInfo());
1606 bool CR2Spilled = false;
1607 bool CR3Spilled = false;
1608 bool CR4Spilled = false;
1609 unsigned CSIIndex = 0;
1611 // Initialize insertion-point logic; we will be restoring in reverse
1613 MachineBasicBlock::iterator I = MI, BeforeI = I;
1614 bool AtStart = I == MBB.begin();
1619 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1620 unsigned Reg = CSI[i].getReg();
1622 // Only Darwin actually uses the VRSAVE register, but it can still appear
1623 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1624 // Darwin, ignore it.
1625 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1628 if (Reg == PPC::CR2) {
1630 // The spill slot is associated only with CR2, which is the
1631 // first nonvolatile spilled. Save it here.
1634 } else if (Reg == PPC::CR3) {
1637 } else if (Reg == PPC::CR4) {
1641 // When we first encounter a non-CR register after seeing at
1642 // least one CR register, restore all spilled CRs together.
1643 if ((CR2Spilled || CR3Spilled || CR4Spilled)
1644 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1645 bool is31 = needsFP(*MF);
1646 restoreCRs(Subtarget.isPPC64(), is31,
1647 CR2Spilled, CR3Spilled, CR4Spilled,
1648 MBB, I, CSI, CSIIndex);
1649 CR2Spilled = CR3Spilled = CR4Spilled = false;
1652 // Default behavior for non-CR saves.
1653 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1654 TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(),
1656 assert(I != MBB.begin() &&
1657 "loadRegFromStackSlot didn't insert any code!");
1660 // Insert in reverse order.
1669 // If we haven't yet spilled the CRs, do so now.
1670 if (CR2Spilled || CR3Spilled || CR4Spilled) {
1671 bool is31 = needsFP(*MF);
1672 restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled,
1673 MBB, I, CSI, CSIIndex);