1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PPC implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCFrameLowering.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCInstrInfo.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/IR/Function.h"
25 #include "llvm/Target/TargetOptions.h"
29 // FIXME This disables some code that aligns the stack to a boundary bigger than
30 // the default (16 bytes on Darwin) when there is a stack local of greater
31 // alignment. This does not currently work, because the delta between old and
32 // new stack pointers is added to offsets that reference incoming parameters
33 // after the prolog is generated, and the code that does that doesn't handle a
34 // variable delta. You don't want to do that anyway; a better approach is to
35 // reserve another register that retains to the incoming stack pointer, and
36 // reference parameters relative to that.
40 /// VRRegNo - Map from a numbered VR register to its enum value.
42 static const uint16_t VRRegNo[] = {
43 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
44 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
45 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
46 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
49 /// RemoveVRSaveCode - We have found that this function does not need any code
50 /// to manipulate the VRSAVE register, even though it uses vector registers.
51 /// This can happen when the only registers used are known to be live in or out
52 /// of the function. Remove all of the VRSAVE related code from the function.
53 /// FIXME: The removal of the code results in a compile failure at -O0 when the
54 /// function contains a function call, as the GPR containing original VRSAVE
55 /// contents is spilled and reloaded around the call. Without the prolog code,
56 /// the spill instruction refers to an undefined register. This code needs
57 /// to account for all uses of that GPR.
58 static void RemoveVRSaveCode(MachineInstr *MI) {
59 MachineBasicBlock *Entry = MI->getParent();
60 MachineFunction *MF = Entry->getParent();
62 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
63 MachineBasicBlock::iterator MBBI = MI;
65 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
66 MBBI->eraseFromParent();
68 bool RemovedAllMTVRSAVEs = true;
69 // See if we can find and remove the MTVRSAVE instruction from all of the
71 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
72 // If last instruction is a return instruction, add an epilogue
73 if (!I->empty() && I->back().isReturn()) {
75 for (MBBI = I->end(); MBBI != I->begin(); ) {
77 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
78 MBBI->eraseFromParent(); // remove it.
83 RemovedAllMTVRSAVEs &= FoundIt;
87 // If we found and removed all MTVRSAVE instructions, remove the read of
89 if (RemovedAllMTVRSAVEs) {
91 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
93 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
94 MBBI->eraseFromParent();
97 // Finally, nuke the UPDATE_VRSAVE.
98 MI->eraseFromParent();
101 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
102 // instruction selector. Based on the vector registers that have been used,
103 // transform this into the appropriate ORI instruction.
104 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
105 MachineFunction *MF = MI->getParent()->getParent();
106 DebugLoc dl = MI->getDebugLoc();
108 unsigned UsedRegMask = 0;
109 for (unsigned i = 0; i != 32; ++i)
110 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
111 UsedRegMask |= 1 << (31-i);
113 // Live in and live out values already must be in the mask, so don't bother
115 for (MachineRegisterInfo::livein_iterator
116 I = MF->getRegInfo().livein_begin(),
117 E = MF->getRegInfo().livein_end(); I != E; ++I) {
118 unsigned RegNo = getPPCRegisterNumbering(I->first);
119 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
120 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
123 // Live out registers appear as use operands on return instructions.
124 for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end();
125 UsedRegMask != 0 && BI != BE; ++BI) {
126 const MachineBasicBlock &MBB = *BI;
127 if (MBB.empty() || !MBB.back().isReturn())
129 const MachineInstr &Ret = MBB.back();
130 for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) {
131 const MachineOperand &MO = Ret.getOperand(I);
132 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
134 unsigned RegNo = getPPCRegisterNumbering(MO.getReg());
135 UsedRegMask &= ~(1 << (31-RegNo));
139 // If no registers are used, turn this into a copy.
140 if (UsedRegMask == 0) {
141 // Remove all VRSAVE code.
142 RemoveVRSaveCode(MI);
146 unsigned SrcReg = MI->getOperand(1).getReg();
147 unsigned DstReg = MI->getOperand(0).getReg();
149 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
150 if (DstReg != SrcReg)
151 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
153 .addImm(UsedRegMask);
155 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
156 .addReg(SrcReg, RegState::Kill)
157 .addImm(UsedRegMask);
158 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
159 if (DstReg != SrcReg)
160 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
162 .addImm(UsedRegMask >> 16);
164 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
165 .addReg(SrcReg, RegState::Kill)
166 .addImm(UsedRegMask >> 16);
168 if (DstReg != SrcReg)
169 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
171 .addImm(UsedRegMask >> 16);
173 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
174 .addReg(SrcReg, RegState::Kill)
175 .addImm(UsedRegMask >> 16);
177 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
178 .addReg(DstReg, RegState::Kill)
179 .addImm(UsedRegMask & 0xFFFF);
182 // Remove the old UPDATE_VRSAVE instruction.
183 MI->eraseFromParent();
186 static bool spillsCR(const MachineFunction &MF) {
187 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
188 return FuncInfo->isCRSpilled();
191 static bool spillsVRSAVE(const MachineFunction &MF) {
192 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
193 return FuncInfo->isVRSAVESpilled();
196 static bool hasSpills(const MachineFunction &MF) {
197 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
198 return FuncInfo->hasSpills();
201 static bool hasNonRISpills(const MachineFunction &MF) {
202 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
203 return FuncInfo->hasNonRISpills();
206 /// determineFrameLayout - Determine the size of the frame and maximum call
208 unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF,
210 bool UseEstimate) const {
211 MachineFrameInfo *MFI = MF.getFrameInfo();
213 // Get the number of bytes to allocate from the FrameInfo
215 UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize();
217 // Get the alignments provided by the target, and the maximum alignment
218 // (if any) of the fixed frame objects.
219 unsigned MaxAlign = MFI->getMaxAlignment();
220 unsigned TargetAlign = getStackAlignment();
221 unsigned AlignMask = TargetAlign - 1; //
223 // If we are a leaf function, and use up to 224 bytes of stack space,
224 // don't have a frame pointer, calls, or dynamic alloca then we do not need
225 // to adjust the stack pointer (we fit in the Red Zone). For 64-bit
226 // SVR4, we also require a stack frame if we need to spill the CR,
227 // since this spill area is addressed relative to the stack pointer.
228 // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate
229 // stackless code if all local vars are reg-allocated.
230 bool DisableRedZone = MF.getFunction()->getAttributes().
231 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoRedZone);
232 if (!DisableRedZone &&
233 (Subtarget.isPPC64() || // 32-bit SVR4, no stack-
234 !Subtarget.isSVR4ABI() || // allocated locals.
236 FrameSize <= 224 && // Fits in red zone.
237 !MFI->hasVarSizedObjects() && // No dynamic alloca.
238 !MFI->adjustsStack() && // No calls.
239 !(Subtarget.isPPC64() && // No 64-bit SVR4 CRsave.
240 Subtarget.isSVR4ABI()
242 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment.
245 MFI->setStackSize(0);
249 // Get the maximum call frame size of all the calls.
250 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
252 // Maximum call frame needs to be at least big enough for linkage and 8 args.
253 unsigned minCallFrameSize = getMinCallFrameSize(Subtarget.isPPC64(),
254 Subtarget.isDarwinABI());
255 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
257 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
258 // that allocations will be aligned.
259 if (MFI->hasVarSizedObjects())
260 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
262 // Update maximum call frame size.
264 MFI->setMaxCallFrameSize(maxCallFrameSize);
266 // Include call frame size in total.
267 FrameSize += maxCallFrameSize;
269 // Make sure the frame is aligned.
270 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
272 // Update frame info.
274 MFI->setStackSize(FrameSize);
279 // hasFP - Return true if the specified function actually has a dedicated frame
281 bool PPCFrameLowering::hasFP(const MachineFunction &MF) const {
282 const MachineFrameInfo *MFI = MF.getFrameInfo();
283 // FIXME: This is pretty much broken by design: hasFP() might be called really
284 // early, before the stack layout was calculated and thus hasFP() might return
285 // true or false here depending on the time of call.
286 return (MFI->getStackSize()) && needsFP(MF);
289 // needsFP - Return true if the specified function should have a dedicated frame
290 // pointer register. This is true if the function has variable sized allocas or
291 // if frame pointer elimination is disabled.
292 bool PPCFrameLowering::needsFP(const MachineFunction &MF) const {
293 const MachineFrameInfo *MFI = MF.getFrameInfo();
295 // Naked functions have no stack frame pushed, so we don't have a frame
297 if (MF.getFunction()->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
301 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
302 MFI->hasVarSizedObjects() ||
303 (MF.getTarget().Options.GuaranteedTailCallOpt &&
304 MF.getInfo<PPCFunctionInfo>()->hasFastCall());
307 void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const {
308 bool is31 = needsFP(MF);
309 unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
310 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
312 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
314 for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) {
316 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
317 MachineOperand &MO = MBBI->getOperand(I);
321 switch (MO.getReg()) {
333 void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
334 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
335 MachineBasicBlock::iterator MBBI = MBB.begin();
336 MachineFrameInfo *MFI = MF.getFrameInfo();
337 const PPCInstrInfo &TII =
338 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
340 MachineModuleInfo &MMI = MF.getMMI();
342 bool needsFrameMoves = MMI.hasDebugInfo() ||
343 MF.getFunction()->needsUnwindTableEntry();
345 // Prepare for frame info.
346 MCSymbol *FrameLabel = 0;
348 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
350 if (!Subtarget.isSVR4ABI())
351 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
352 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
353 HandleVRSaveUpdate(MBBI, TII);
358 // Move MBBI back to the beginning of the function.
361 // Work out frame sizes.
362 unsigned FrameSize = determineFrameLayout(MF);
363 int NegFrameSize = -FrameSize;
365 if (MFI->isFrameAddressTaken())
366 replaceFPWithRealFP(MF);
368 // Get processor type.
369 bool isPPC64 = Subtarget.isPPC64();
370 // Get operating system
371 bool isDarwinABI = Subtarget.isDarwinABI();
372 // Check if the link register (LR) must be saved.
373 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
374 bool MustSaveLR = FI->mustSaveLR();
375 // Do we have a frame pointer for this function?
376 bool HasFP = hasFP(MF);
378 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
382 if (Subtarget.isSVR4ABI()) {
383 MachineFrameInfo *FFI = MF.getFrameInfo();
384 int FPIndex = FI->getFramePointerSaveIndex();
385 assert(FPIndex && "No Frame Pointer Save Slot!");
386 FPOffset = FFI->getObjectOffset(FPIndex);
388 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
394 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0);
397 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
403 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
405 .addImm(LROffset / 4)
409 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0);
412 // FIXME: On PPC32 SVR4, FPOffset is negative and access to negative
413 // offsets of R1 is not allowed.
414 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
420 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
426 // Skip if a leaf routine.
427 if (!FrameSize) return;
429 // Get stack alignments.
430 unsigned TargetAlign = getStackAlignment();
431 unsigned MaxAlign = MFI->getMaxAlignment();
433 // Adjust stack pointer: r1 += NegFrameSize.
434 // If there is a preferred stack alignment, align R1 now
437 if (ALIGN_STACK && MaxAlign > TargetAlign) {
438 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
439 "Invalid alignment!");
440 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!");
442 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0)
445 .addImm(32 - Log2_32(MaxAlign))
447 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0)
448 .addReg(PPC::R0, RegState::Kill)
449 .addImm(NegFrameSize);
450 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1)
451 .addReg(PPC::R1, RegState::Kill)
454 } else if (isInt<16>(NegFrameSize)) {
455 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1)
457 .addImm(NegFrameSize)
460 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
461 .addImm(NegFrameSize >> 16);
462 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
463 .addReg(PPC::R0, RegState::Kill)
464 .addImm(NegFrameSize & 0xFFFF);
465 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1)
466 .addReg(PPC::R1, RegState::Kill)
471 if (ALIGN_STACK && MaxAlign > TargetAlign) {
472 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
473 "Invalid alignment!");
474 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!");
476 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0)
479 .addImm(64 - Log2_32(MaxAlign));
480 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0)
482 .addImm(NegFrameSize);
483 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1)
484 .addReg(PPC::X1, RegState::Kill)
487 } else if (isInt<16>(NegFrameSize)) {
488 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1)
490 .addImm(NegFrameSize / 4)
493 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
494 .addImm(NegFrameSize >> 16);
495 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
496 .addReg(PPC::X0, RegState::Kill)
497 .addImm(NegFrameSize & 0xFFFF);
498 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1)
499 .addReg(PPC::X1, RegState::Kill)
505 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
507 // Add the "machine moves" for the instructions we generated above, but in
509 if (needsFrameMoves) {
510 // Mark effective beginning of when frame pointer becomes valid.
511 FrameLabel = MMI.getContext().CreateTempSymbol();
512 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(FrameLabel);
514 // Show update of SP.
516 MachineLocation SPDst(MachineLocation::VirtualFP);
517 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
518 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
520 MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31);
521 Moves.push_back(MachineMove(FrameLabel, SP, SP));
525 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
526 MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31);
527 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
531 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
532 MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR);
533 Moves.push_back(MachineMove(FrameLabel, LRDst, LRSrc));
537 MCSymbol *ReadyLabel = 0;
539 // If there is a frame pointer, copy R1 into R31
542 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31)
546 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31)
551 if (needsFrameMoves) {
552 ReadyLabel = MMI.getContext().CreateTempSymbol();
554 // Mark effective beginning of when frame pointer is ready.
555 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(ReadyLabel);
557 MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) :
558 (isPPC64 ? PPC::X1 : PPC::R1));
559 MachineLocation FPSrc(MachineLocation::VirtualFP);
560 Moves.push_back(MachineMove(ReadyLabel, FPDst, FPSrc));
564 if (needsFrameMoves) {
565 MCSymbol *Label = HasFP ? ReadyLabel : FrameLabel;
567 // Add callee saved registers to move list.
568 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
569 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
570 unsigned Reg = CSI[I].getReg();
571 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
573 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
574 // subregisters of CR2. We just need to emit a move of CR2.
575 if (PPC::CRBITRCRegClass.contains(Reg))
578 // For SVR4, don't emit a move for the CR spill slot if we haven't
580 if (Subtarget.isSVR4ABI()
581 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
585 // For 64-bit SVR4 when we have spilled CRs, the spill location
586 // is SP+8, not a frame-relative slot.
587 if (Subtarget.isSVR4ABI()
588 && Subtarget.isPPC64()
589 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
590 MachineLocation CSDst(PPC::X1, 8);
591 MachineLocation CSSrc(PPC::CR2);
592 Moves.push_back(MachineMove(Label, CSDst, CSSrc));
596 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
597 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
598 MachineLocation CSSrc(Reg);
599 Moves.push_back(MachineMove(Label, CSDst, CSSrc));
604 void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
605 MachineBasicBlock &MBB) const {
606 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
607 assert(MBBI != MBB.end() && "Returning block has no terminator");
608 const PPCInstrInfo &TII =
609 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
611 unsigned RetOpcode = MBBI->getOpcode();
614 assert((RetOpcode == PPC::BLR ||
615 RetOpcode == PPC::TCRETURNri ||
616 RetOpcode == PPC::TCRETURNdi ||
617 RetOpcode == PPC::TCRETURNai ||
618 RetOpcode == PPC::TCRETURNri8 ||
619 RetOpcode == PPC::TCRETURNdi8 ||
620 RetOpcode == PPC::TCRETURNai8) &&
621 "Can only insert epilog into returning blocks");
623 // Get alignment info so we know how to restore r1
624 const MachineFrameInfo *MFI = MF.getFrameInfo();
625 unsigned TargetAlign = getStackAlignment();
626 unsigned MaxAlign = MFI->getMaxAlignment();
628 // Get the number of bytes allocated from the FrameInfo.
629 int FrameSize = MFI->getStackSize();
631 // Get processor type.
632 bool isPPC64 = Subtarget.isPPC64();
633 // Get operating system
634 bool isDarwinABI = Subtarget.isDarwinABI();
635 // Check if the link register (LR) has been saved.
636 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
637 bool MustSaveLR = FI->mustSaveLR();
638 // Do we have a frame pointer for this function?
639 bool HasFP = hasFP(MF);
641 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
645 if (Subtarget.isSVR4ABI()) {
646 MachineFrameInfo *FFI = MF.getFrameInfo();
647 int FPIndex = FI->getFramePointerSaveIndex();
648 assert(FPIndex && "No Frame Pointer Save Slot!");
649 FPOffset = FFI->getObjectOffset(FPIndex);
651 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
655 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
656 RetOpcode == PPC::TCRETURNdi ||
657 RetOpcode == PPC::TCRETURNai ||
658 RetOpcode == PPC::TCRETURNri8 ||
659 RetOpcode == PPC::TCRETURNdi8 ||
660 RetOpcode == PPC::TCRETURNai8;
663 int MaxTCRetDelta = FI->getTailCallSPDelta();
664 MachineOperand &StackAdjust = MBBI->getOperand(1);
665 assert(StackAdjust.isImm() && "Expecting immediate value.");
666 // Adjust stack pointer.
667 int StackAdj = StackAdjust.getImm();
668 int Delta = StackAdj - MaxTCRetDelta;
669 assert((Delta >= 0) && "Delta must be positive");
671 FrameSize += (StackAdj +Delta);
673 FrameSize += StackAdj;
677 // The loaded (or persistent) stack pointer value is offset by the 'stwu'
678 // on entry to the function. Add this offset back now.
680 // If this function contained a fastcc call and GuaranteedTailCallOpt is
681 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
682 // call which invalidates the stack pointer value in SP(0). So we use the
683 // value of R31 in this case.
684 if (FI->hasFastCall() && isInt<16>(FrameSize)) {
685 assert(hasFP(MF) && "Expecting a valid the frame pointer.");
686 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
687 .addReg(PPC::R31).addImm(FrameSize);
688 } else if(FI->hasFastCall()) {
689 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
690 .addImm(FrameSize >> 16);
691 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
692 .addReg(PPC::R0, RegState::Kill)
693 .addImm(FrameSize & 0xFFFF);
694 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4))
698 } else if (isInt<16>(FrameSize) &&
699 (!ALIGN_STACK || TargetAlign >= MaxAlign) &&
700 !MFI->hasVarSizedObjects()) {
701 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
702 .addReg(PPC::R1).addImm(FrameSize);
704 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1)
705 .addImm(0).addReg(PPC::R1);
708 if (FI->hasFastCall() && isInt<16>(FrameSize)) {
709 assert(hasFP(MF) && "Expecting a valid the frame pointer.");
710 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
711 .addReg(PPC::X31).addImm(FrameSize);
712 } else if(FI->hasFastCall()) {
713 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
714 .addImm(FrameSize >> 16);
715 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
716 .addReg(PPC::X0, RegState::Kill)
717 .addImm(FrameSize & 0xFFFF);
718 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8))
722 } else if (isInt<16>(FrameSize) && TargetAlign >= MaxAlign &&
723 !MFI->hasVarSizedObjects()) {
724 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
725 .addReg(PPC::X1).addImm(FrameSize);
727 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1)
728 .addImm(0).addReg(PPC::X1);
735 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0)
736 .addImm(LROffset/4).addReg(PPC::X1);
739 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31)
740 .addImm(FPOffset/4).addReg(PPC::X1);
743 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0);
746 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0)
747 .addImm(LROffset).addReg(PPC::R1);
750 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31)
751 .addImm(FPOffset).addReg(PPC::R1);
754 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0);
757 // Callee pop calling convention. Pop parameter/linkage area. Used for tail
759 if (MF.getTarget().Options.GuaranteedTailCallOpt && RetOpcode == PPC::BLR &&
760 MF.getFunction()->getCallingConv() == CallingConv::Fast) {
761 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
762 unsigned CallerAllocatedAmt = FI->getMinReservedArea();
763 unsigned StackReg = isPPC64 ? PPC::X1 : PPC::R1;
764 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
765 unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0;
766 unsigned ADDIInstr = isPPC64 ? PPC::ADDI8 : PPC::ADDI;
767 unsigned ADDInstr = isPPC64 ? PPC::ADD8 : PPC::ADD4;
768 unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS;
769 unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI;
771 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
772 BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg)
773 .addReg(StackReg).addImm(CallerAllocatedAmt);
775 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
776 .addImm(CallerAllocatedAmt >> 16);
777 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
778 .addReg(TmpReg, RegState::Kill)
779 .addImm(CallerAllocatedAmt & 0xFFFF);
780 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
785 } else if (RetOpcode == PPC::TCRETURNdi) {
786 MBBI = MBB.getLastNonDebugInstr();
787 MachineOperand &JumpTarget = MBBI->getOperand(0);
788 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
789 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
790 } else if (RetOpcode == PPC::TCRETURNri) {
791 MBBI = MBB.getLastNonDebugInstr();
792 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
793 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
794 } else if (RetOpcode == PPC::TCRETURNai) {
795 MBBI = MBB.getLastNonDebugInstr();
796 MachineOperand &JumpTarget = MBBI->getOperand(0);
797 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
798 } else if (RetOpcode == PPC::TCRETURNdi8) {
799 MBBI = MBB.getLastNonDebugInstr();
800 MachineOperand &JumpTarget = MBBI->getOperand(0);
801 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
802 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
803 } else if (RetOpcode == PPC::TCRETURNri8) {
804 MBBI = MBB.getLastNonDebugInstr();
805 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
806 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
807 } else if (RetOpcode == PPC::TCRETURNai8) {
808 MBBI = MBB.getLastNonDebugInstr();
809 MachineOperand &JumpTarget = MBBI->getOperand(0);
810 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
814 /// MustSaveLR - Return true if this function requires that we save the LR
815 /// register onto the stack in the prolog and restore it in the epilog of the
817 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
818 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
820 // We need a save/restore of LR if there is any def of LR (which is
821 // defined by calls, including the PIC setup sequence), or if there is
822 // some use of the LR stack slot (e.g. for builtin_return_address).
823 // (LR comes in 32 and 64 bit versions.)
824 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
825 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
829 PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
830 RegScavenger *) const {
831 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
833 // Save and clear the LR state.
834 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
835 unsigned LR = RegInfo->getRARegister();
836 FI->setMustSaveLR(MustSaveLR(MF, LR));
837 MachineRegisterInfo &MRI = MF.getRegInfo();
838 MRI.setPhysRegUnused(LR);
840 // Save R31 if necessary
841 int FPSI = FI->getFramePointerSaveIndex();
842 bool isPPC64 = Subtarget.isPPC64();
843 bool isDarwinABI = Subtarget.isDarwinABI();
844 MachineFrameInfo *MFI = MF.getFrameInfo();
846 // If the frame pointer save index hasn't been defined yet.
847 if (!FPSI && needsFP(MF)) {
848 // Find out what the fix offset of the frame pointer save area.
849 int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI);
850 // Allocate the frame index for frame pointer save area.
851 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
853 FI->setFramePointerSaveIndex(FPSI);
856 // Reserve stack space to move the linkage area to in case of a tail call.
858 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
859 (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
860 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
863 // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
864 // function uses CR 2, 3, or 4.
865 if (!isPPC64 && !isDarwinABI &&
866 (MRI.isPhysRegUsed(PPC::CR2) ||
867 MRI.isPhysRegUsed(PPC::CR3) ||
868 MRI.isPhysRegUsed(PPC::CR4))) {
869 int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true);
870 FI->setCRSpillFrameIndex(FrameIdx);
874 void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
875 RegScavenger *RS) const {
876 // Early exit if not using the SVR4 ABI.
877 if (!Subtarget.isSVR4ABI()) {
878 addScavengingSpillSlot(MF, RS);
882 // Get callee saved register information.
883 MachineFrameInfo *FFI = MF.getFrameInfo();
884 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
886 // Early exit if no callee saved registers are modified!
887 if (CSI.empty() && !needsFP(MF)) {
888 addScavengingSpillSlot(MF, RS);
892 unsigned MinGPR = PPC::R31;
893 unsigned MinG8R = PPC::X31;
894 unsigned MinFPR = PPC::F31;
895 unsigned MinVR = PPC::V31;
897 bool HasGPSaveArea = false;
898 bool HasG8SaveArea = false;
899 bool HasFPSaveArea = false;
900 bool HasVRSAVESaveArea = false;
901 bool HasVRSaveArea = false;
903 SmallVector<CalleeSavedInfo, 18> GPRegs;
904 SmallVector<CalleeSavedInfo, 18> G8Regs;
905 SmallVector<CalleeSavedInfo, 18> FPRegs;
906 SmallVector<CalleeSavedInfo, 18> VRegs;
908 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
909 unsigned Reg = CSI[i].getReg();
910 if (PPC::GPRCRegClass.contains(Reg)) {
911 HasGPSaveArea = true;
913 GPRegs.push_back(CSI[i]);
918 } else if (PPC::G8RCRegClass.contains(Reg)) {
919 HasG8SaveArea = true;
921 G8Regs.push_back(CSI[i]);
926 } else if (PPC::F8RCRegClass.contains(Reg)) {
927 HasFPSaveArea = true;
929 FPRegs.push_back(CSI[i]);
934 } else if (PPC::CRBITRCRegClass.contains(Reg) ||
935 PPC::CRRCRegClass.contains(Reg)) {
936 ; // do nothing, as we already know whether CRs are spilled
937 } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
938 HasVRSAVESaveArea = true;
939 } else if (PPC::VRRCRegClass.contains(Reg)) {
940 HasVRSaveArea = true;
942 VRegs.push_back(CSI[i]);
948 llvm_unreachable("Unknown RegisterClass!");
952 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>();
954 int64_t LowerBound = 0;
956 // Take into account stack space reserved for tail calls.
958 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
959 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
960 LowerBound = TCSPDelta;
963 // The Floating-point register save area is right below the back chain word
964 // of the previous stack frame.
966 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
967 int FI = FPRegs[i].getFrameIdx();
969 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
972 LowerBound -= (31 - getPPCRegisterNumbering(MinFPR) + 1) * 8;
975 // Check whether the frame pointer register is allocated. If so, make sure it
976 // is spilled to the correct offset.
978 HasGPSaveArea = true;
980 int FI = PFI->getFramePointerSaveIndex();
981 assert(FI && "No Frame Pointer Save Slot!");
983 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
986 // General register save area starts right below the Floating-point
987 // register save area.
988 if (HasGPSaveArea || HasG8SaveArea) {
989 // Move general register save area spill slots down, taking into account
990 // the size of the Floating-point register save area.
991 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
992 int FI = GPRegs[i].getFrameIdx();
994 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
997 // Move general register save area spill slots down, taking into account
998 // the size of the Floating-point register save area.
999 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
1000 int FI = G8Regs[i].getFrameIdx();
1002 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1006 std::min<unsigned>(getPPCRegisterNumbering(MinGPR),
1007 getPPCRegisterNumbering(MinG8R));
1009 if (Subtarget.isPPC64()) {
1010 LowerBound -= (31 - MinReg + 1) * 8;
1012 LowerBound -= (31 - MinReg + 1) * 4;
1016 // For 32-bit only, the CR save area is below the general register
1017 // save area. For 64-bit SVR4, the CR save area is addressed relative
1018 // to the stack pointer and hence does not need an adjustment here.
1019 // Only CR2 (the first nonvolatile spilled) has an associated frame
1020 // index so that we have a single uniform save area.
1021 if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) {
1022 // Adjust the frame index of the CR spill slot.
1023 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1024 unsigned Reg = CSI[i].getReg();
1026 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
1027 // Leave Darwin logic as-is.
1028 || (!Subtarget.isSVR4ABI() &&
1029 (PPC::CRBITRCRegClass.contains(Reg) ||
1030 PPC::CRRCRegClass.contains(Reg)))) {
1031 int FI = CSI[i].getFrameIdx();
1033 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1037 LowerBound -= 4; // The CR save area is always 4 bytes long.
1040 if (HasVRSAVESaveArea) {
1041 // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1042 // which have the VRSAVE register class?
1043 // Adjust the frame index of the VRSAVE spill slot.
1044 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1045 unsigned Reg = CSI[i].getReg();
1047 if (PPC::VRSAVERCRegClass.contains(Reg)) {
1048 int FI = CSI[i].getFrameIdx();
1050 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1054 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
1057 if (HasVRSaveArea) {
1058 // Insert alignment padding, we need 16-byte alignment.
1059 LowerBound = (LowerBound - 15) & ~(15);
1061 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
1062 int FI = VRegs[i].getFrameIdx();
1064 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1068 addScavengingSpillSlot(MF, RS);
1072 PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
1073 RegScavenger *RS) const {
1074 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
1075 // a large stack, which will require scavenging a register to materialize a
1078 // We need to have a scavenger spill slot for spills if the frame size is
1079 // large. In case there is no free register for large-offset addressing,
1080 // this slot is used for the necessary emergency spill. Also, we need the
1081 // slot for dynamic stack allocations.
1083 // The scavenger might be invoked if the frame offset does not fit into
1084 // the 16-bit immediate. We don't know the complete frame size here
1085 // because we've not yet computed callee-saved register spills or the
1086 // needed alignment padding.
1087 unsigned StackSize = determineFrameLayout(MF, false, true);
1088 MachineFrameInfo *MFI = MF.getFrameInfo();
1089 if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) ||
1090 hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) {
1091 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1092 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1093 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
1094 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1101 PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1102 MachineBasicBlock::iterator MI,
1103 const std::vector<CalleeSavedInfo> &CSI,
1104 const TargetRegisterInfo *TRI) const {
1106 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1107 // Return false otherwise to maintain pre-existing behavior.
1108 if (!Subtarget.isSVR4ABI())
1111 MachineFunction *MF = MBB.getParent();
1112 const PPCInstrInfo &TII =
1113 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1115 bool CRSpilled = false;
1117 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1118 unsigned Reg = CSI[i].getReg();
1119 // CR2 through CR4 are the nonvolatile CR fields.
1120 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
1122 if (CRSpilled && IsCRField)
1125 // Add the callee-saved register as live-in; it's killed at the spill.
1128 // Insert the spill to the stack frame.
1131 // The first time we see a CR field, store the whole CR into the
1132 // save slot via GPR12 (available in the prolog for 32- and 64-bit).
1133 if (Subtarget.isPPC64()) {
1135 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::X12));
1136 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::STW))
1138 getKillRegState(true))
1142 // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have
1143 // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
1144 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12));
1145 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
1147 getKillRegState(true)),
1148 CSI[i].getFrameIdx()));
1151 // Record that we spill the CR in this function.
1152 PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
1153 FuncInfo->setSpillsCR();
1155 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1156 TII.storeRegToStackSlot(MBB, MI, Reg, true,
1157 CSI[i].getFrameIdx(), RC, TRI);
1164 restoreCRs(bool isPPC64, bool CR2Spilled, bool CR3Spilled, bool CR4Spilled,
1165 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1166 const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
1168 MachineFunction *MF = MBB.getParent();
1169 const PPCInstrInfo &TII =
1170 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1172 unsigned RestoreOp, MoveReg;
1176 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::LWZ), PPC::X12)
1179 RestoreOp = PPC::MTCRF8;
1182 // 32-bit: FP-relative
1183 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
1185 CSI[CSIIndex].getFrameIdx()));
1186 RestoreOp = PPC::MTCRF;
1191 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
1195 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
1199 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
1203 void PPCFrameLowering::
1204 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1205 MachineBasicBlock::iterator I) const {
1206 const PPCInstrInfo &TII =
1207 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
1208 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1209 I->getOpcode() == PPC::ADJCALLSTACKUP) {
1210 // Add (actually subtract) back the amount the callee popped on return.
1211 if (int CalleeAmt = I->getOperand(1).getImm()) {
1212 bool is64Bit = Subtarget.isPPC64();
1214 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
1215 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
1216 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
1217 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
1218 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
1219 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
1220 MachineInstr *MI = I;
1221 DebugLoc dl = MI->getDebugLoc();
1223 if (isInt<16>(CalleeAmt)) {
1224 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
1225 .addReg(StackReg, RegState::Kill)
1228 MachineBasicBlock::iterator MBBI = I;
1229 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
1230 .addImm(CalleeAmt >> 16);
1231 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
1232 .addReg(TmpReg, RegState::Kill)
1233 .addImm(CalleeAmt & 0xFFFF);
1234 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
1235 .addReg(StackReg, RegState::Kill)
1240 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
1245 PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1246 MachineBasicBlock::iterator MI,
1247 const std::vector<CalleeSavedInfo> &CSI,
1248 const TargetRegisterInfo *TRI) const {
1250 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1251 // Return false otherwise to maintain pre-existing behavior.
1252 if (!Subtarget.isSVR4ABI())
1255 MachineFunction *MF = MBB.getParent();
1256 const PPCInstrInfo &TII =
1257 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1258 bool CR2Spilled = false;
1259 bool CR3Spilled = false;
1260 bool CR4Spilled = false;
1261 unsigned CSIIndex = 0;
1263 // Initialize insertion-point logic; we will be restoring in reverse
1265 MachineBasicBlock::iterator I = MI, BeforeI = I;
1266 bool AtStart = I == MBB.begin();
1271 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1272 unsigned Reg = CSI[i].getReg();
1274 if (Reg == PPC::CR2) {
1276 // The spill slot is associated only with CR2, which is the
1277 // first nonvolatile spilled. Save it here.
1280 } else if (Reg == PPC::CR3) {
1283 } else if (Reg == PPC::CR4) {
1287 // When we first encounter a non-CR register after seeing at
1288 // least one CR register, restore all spilled CRs together.
1289 if ((CR2Spilled || CR3Spilled || CR4Spilled)
1290 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1291 restoreCRs(Subtarget.isPPC64(), CR2Spilled, CR3Spilled, CR4Spilled,
1292 MBB, I, CSI, CSIIndex);
1293 CR2Spilled = CR3Spilled = CR4Spilled = false;
1296 // Default behavior for non-CR saves.
1297 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1298 TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(),
1300 assert(I != MBB.begin() &&
1301 "loadRegFromStackSlot didn't insert any code!");
1304 // Insert in reverse order.
1313 // If we haven't yet spilled the CRs, do so now.
1314 if (CR2Spilled || CR3Spilled || CR4Spilled)
1315 restoreCRs(Subtarget.isPPC64(), CR2Spilled, CR3Spilled, CR4Spilled,
1316 MBB, I, CSI, CSIIndex);