1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PPC implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCFrameLowering.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCInstrInfo.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCSubtarget.h"
19 #include "PPCTargetMachine.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineModuleInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/RegisterScavenging.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/Target/TargetOptions.h"
31 /// VRRegNo - Map from a numbered VR register to its enum value.
33 static const uint16_t VRRegNo[] = {
34 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
35 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
36 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
37 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
40 static unsigned computeReturnSaveOffset(const PPCSubtarget &STI) {
41 if (STI.isDarwinABI())
42 return STI.isPPC64() ? 16 : 8;
44 return STI.isPPC64() ? 16 : 4;
47 static unsigned computeTOCSaveOffset(const PPCSubtarget &STI) {
48 return STI.isELFv2ABI() ? 24 : 40;
51 static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI) {
52 // For the Darwin ABI:
53 // We cannot use the TOC save slot (offset +20) in the PowerPC linkage area
54 // for saving the frame pointer (if needed.) While the published ABI has
55 // not used this slot since at least MacOSX 10.2, there is older code
56 // around that does use it, and that needs to continue to work.
57 if (STI.isDarwinABI())
58 return STI.isPPC64() ? -8U : -4U;
60 // SVR4 ABI: First slot in the general register save area.
61 return STI.isPPC64() ? -8U : -4U;
64 static unsigned computeLinkageSize(const PPCSubtarget &STI) {
65 if (STI.isDarwinABI() || STI.isPPC64())
66 return (STI.isELFv2ABI() ? 4 : 6) * (STI.isPPC64() ? 8 : 4);
72 static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI) {
73 if (STI.isDarwinABI())
74 return STI.isPPC64() ? -16U : -8U;
76 // SVR4 ABI: First slot in the general register save area.
79 : (STI.getTargetMachine().getRelocationModel() == Reloc::PIC_)
84 PPCFrameLowering::PPCFrameLowering(const PPCSubtarget &STI)
85 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
86 (STI.hasQPX() || STI.isBGQ()) ? 32 : 16, 0),
87 Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)),
88 TOCSaveOffset(computeTOCSaveOffset(Subtarget)),
89 FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)),
90 LinkageSize(computeLinkageSize(Subtarget)),
91 BasePointerSaveOffset(computeBasePointerSaveOffset(STI)) {}
93 // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
94 const PPCFrameLowering::SpillSlot *PPCFrameLowering::getCalleeSavedSpillSlots(
95 unsigned &NumEntries) const {
96 if (Subtarget.isDarwinABI()) {
98 if (Subtarget.isPPC64()) {
99 static const SpillSlot darwin64Offsets = {PPC::X31, -8};
100 return &darwin64Offsets;
102 static const SpillSlot darwinOffsets = {PPC::R31, -4};
103 return &darwinOffsets;
107 // Early exit if not using the SVR4 ABI.
108 if (!Subtarget.isSVR4ABI()) {
113 // Note that the offsets here overlap, but this is fixed up in
114 // processFunctionBeforeFrameFinalized.
116 static const SpillSlot Offsets[] = {
117 // Floating-point register save area offsets.
137 // General register save area offsets.
157 // CR save area offset. We map each of the nonvolatile CR fields
158 // to the slot for CR2, which is the first of the nonvolatile CR
159 // fields to be assigned, so that we only allocate one save slot.
160 // See PPCRegisterInfo::hasReservedSpillSlot() for more information.
163 // VRSAVE save area offset.
166 // Vector register save area
180 static const SpillSlot Offsets64[] = {
181 // Floating-point register save area offsets.
201 // General register save area offsets.
221 // VRSAVE save area offset.
224 // Vector register save area
238 if (Subtarget.isPPC64()) {
239 NumEntries = array_lengthof(Offsets64);
243 NumEntries = array_lengthof(Offsets);
249 /// RemoveVRSaveCode - We have found that this function does not need any code
250 /// to manipulate the VRSAVE register, even though it uses vector registers.
251 /// This can happen when the only registers used are known to be live in or out
252 /// of the function. Remove all of the VRSAVE related code from the function.
253 /// FIXME: The removal of the code results in a compile failure at -O0 when the
254 /// function contains a function call, as the GPR containing original VRSAVE
255 /// contents is spilled and reloaded around the call. Without the prolog code,
256 /// the spill instruction refers to an undefined register. This code needs
257 /// to account for all uses of that GPR.
258 static void RemoveVRSaveCode(MachineInstr *MI) {
259 MachineBasicBlock *Entry = MI->getParent();
260 MachineFunction *MF = Entry->getParent();
262 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
263 MachineBasicBlock::iterator MBBI = MI;
265 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
266 MBBI->eraseFromParent();
268 bool RemovedAllMTVRSAVEs = true;
269 // See if we can find and remove the MTVRSAVE instruction from all of the
271 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
272 // If last instruction is a return instruction, add an epilogue
273 if (!I->empty() && I->back().isReturn()) {
274 bool FoundIt = false;
275 for (MBBI = I->end(); MBBI != I->begin(); ) {
277 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
278 MBBI->eraseFromParent(); // remove it.
283 RemovedAllMTVRSAVEs &= FoundIt;
287 // If we found and removed all MTVRSAVE instructions, remove the read of
289 if (RemovedAllMTVRSAVEs) {
291 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
293 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
294 MBBI->eraseFromParent();
297 // Finally, nuke the UPDATE_VRSAVE.
298 MI->eraseFromParent();
301 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
302 // instruction selector. Based on the vector registers that have been used,
303 // transform this into the appropriate ORI instruction.
304 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
305 MachineFunction *MF = MI->getParent()->getParent();
306 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
307 DebugLoc dl = MI->getDebugLoc();
309 unsigned UsedRegMask = 0;
310 for (unsigned i = 0; i != 32; ++i)
311 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
312 UsedRegMask |= 1 << (31-i);
314 // Live in and live out values already must be in the mask, so don't bother
316 for (MachineRegisterInfo::livein_iterator
317 I = MF->getRegInfo().livein_begin(),
318 E = MF->getRegInfo().livein_end(); I != E; ++I) {
319 unsigned RegNo = TRI->getEncodingValue(I->first);
320 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
321 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
324 // Live out registers appear as use operands on return instructions.
325 for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end();
326 UsedRegMask != 0 && BI != BE; ++BI) {
327 const MachineBasicBlock &MBB = *BI;
328 if (MBB.empty() || !MBB.back().isReturn())
330 const MachineInstr &Ret = MBB.back();
331 for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) {
332 const MachineOperand &MO = Ret.getOperand(I);
333 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
335 unsigned RegNo = TRI->getEncodingValue(MO.getReg());
336 UsedRegMask &= ~(1 << (31-RegNo));
340 // If no registers are used, turn this into a copy.
341 if (UsedRegMask == 0) {
342 // Remove all VRSAVE code.
343 RemoveVRSaveCode(MI);
347 unsigned SrcReg = MI->getOperand(1).getReg();
348 unsigned DstReg = MI->getOperand(0).getReg();
350 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
351 if (DstReg != SrcReg)
352 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
354 .addImm(UsedRegMask);
356 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
357 .addReg(SrcReg, RegState::Kill)
358 .addImm(UsedRegMask);
359 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
360 if (DstReg != SrcReg)
361 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
363 .addImm(UsedRegMask >> 16);
365 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
366 .addReg(SrcReg, RegState::Kill)
367 .addImm(UsedRegMask >> 16);
369 if (DstReg != SrcReg)
370 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
372 .addImm(UsedRegMask >> 16);
374 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
375 .addReg(SrcReg, RegState::Kill)
376 .addImm(UsedRegMask >> 16);
378 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
379 .addReg(DstReg, RegState::Kill)
380 .addImm(UsedRegMask & 0xFFFF);
383 // Remove the old UPDATE_VRSAVE instruction.
384 MI->eraseFromParent();
387 static bool spillsCR(const MachineFunction &MF) {
388 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
389 return FuncInfo->isCRSpilled();
392 static bool spillsVRSAVE(const MachineFunction &MF) {
393 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
394 return FuncInfo->isVRSAVESpilled();
397 static bool hasSpills(const MachineFunction &MF) {
398 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
399 return FuncInfo->hasSpills();
402 static bool hasNonRISpills(const MachineFunction &MF) {
403 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
404 return FuncInfo->hasNonRISpills();
407 /// MustSaveLR - Return true if this function requires that we save the LR
408 /// register onto the stack in the prolog and restore it in the epilog of the
410 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
411 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
413 // We need a save/restore of LR if there is any def of LR (which is
414 // defined by calls, including the PIC setup sequence), or if there is
415 // some use of the LR stack slot (e.g. for builtin_return_address).
416 // (LR comes in 32 and 64 bit versions.)
417 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
418 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
421 /// determineFrameLayout - Determine the size of the frame and maximum call
423 unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF,
425 bool UseEstimate) const {
426 MachineFrameInfo *MFI = MF.getFrameInfo();
428 // Get the number of bytes to allocate from the FrameInfo
430 UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize();
432 // Get stack alignments. The frame must be aligned to the greatest of these:
433 unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI
434 unsigned MaxAlign = MFI->getMaxAlignment(); // algmt required by data in frame
435 unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1;
437 const PPCRegisterInfo *RegInfo =
438 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
440 // If we are a leaf function, and use up to 224 bytes of stack space,
441 // don't have a frame pointer, calls, or dynamic alloca then we do not need
442 // to adjust the stack pointer (we fit in the Red Zone).
443 // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate
444 // stackless code if all local vars are reg-allocated.
445 bool DisableRedZone = MF.getFunction()->hasFnAttribute(Attribute::NoRedZone);
446 unsigned LR = RegInfo->getRARegister();
447 if (!DisableRedZone &&
448 (Subtarget.isPPC64() || // 32-bit SVR4, no stack-
449 !Subtarget.isSVR4ABI() || // allocated locals.
451 FrameSize <= 224 && // Fits in red zone.
452 !MFI->hasVarSizedObjects() && // No dynamic alloca.
453 !MFI->adjustsStack() && // No calls.
454 !MustSaveLR(MF, LR) &&
455 !RegInfo->hasBasePointer(MF)) { // No special alignment.
458 MFI->setStackSize(0);
462 // Get the maximum call frame size of all the calls.
463 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
465 // Maximum call frame needs to be at least big enough for linkage area.
466 unsigned minCallFrameSize = getLinkageSize();
467 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
469 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
470 // that allocations will be aligned.
471 if (MFI->hasVarSizedObjects())
472 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
474 // Update maximum call frame size.
476 MFI->setMaxCallFrameSize(maxCallFrameSize);
478 // Include call frame size in total.
479 FrameSize += maxCallFrameSize;
481 // Make sure the frame is aligned.
482 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
484 // Update frame info.
486 MFI->setStackSize(FrameSize);
491 // hasFP - Return true if the specified function actually has a dedicated frame
493 bool PPCFrameLowering::hasFP(const MachineFunction &MF) const {
494 const MachineFrameInfo *MFI = MF.getFrameInfo();
495 // FIXME: This is pretty much broken by design: hasFP() might be called really
496 // early, before the stack layout was calculated and thus hasFP() might return
497 // true or false here depending on the time of call.
498 return (MFI->getStackSize()) && needsFP(MF);
501 // needsFP - Return true if the specified function should have a dedicated frame
502 // pointer register. This is true if the function has variable sized allocas or
503 // if frame pointer elimination is disabled.
504 bool PPCFrameLowering::needsFP(const MachineFunction &MF) const {
505 const MachineFrameInfo *MFI = MF.getFrameInfo();
507 // Naked functions have no stack frame pushed, so we don't have a frame
509 if (MF.getFunction()->hasFnAttribute(Attribute::Naked))
512 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
513 MFI->hasVarSizedObjects() ||
514 MFI->hasStackMap() || MFI->hasPatchPoint() ||
515 (MF.getTarget().Options.GuaranteedTailCallOpt &&
516 MF.getInfo<PPCFunctionInfo>()->hasFastCall());
519 void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const {
520 bool is31 = needsFP(MF);
521 unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
522 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
524 const PPCRegisterInfo *RegInfo =
525 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
526 bool HasBP = RegInfo->hasBasePointer(MF);
527 unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg;
528 unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg;
530 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
532 for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) {
534 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
535 MachineOperand &MO = MBBI->getOperand(I);
539 switch (MO.getReg()) {
558 void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
559 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
560 MachineBasicBlock::iterator MBBI = MBB.begin();
561 MachineFrameInfo *MFI = MF.getFrameInfo();
562 const PPCInstrInfo &TII =
563 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
564 const PPCRegisterInfo *RegInfo =
565 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
567 MachineModuleInfo &MMI = MF.getMMI();
568 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
570 bool needsCFI = MMI.hasDebugInfo() ||
571 MF.getFunction()->needsUnwindTableEntry();
573 // Get processor type.
574 bool isPPC64 = Subtarget.isPPC64();
576 bool isDarwinABI = Subtarget.isDarwinABI();
577 bool isSVR4ABI = Subtarget.isSVR4ABI();
578 bool isELFv2ABI = Subtarget.isELFv2ABI();
579 assert((isDarwinABI || isSVR4ABI) &&
580 "Currently only Darwin and SVR4 ABIs are supported for PowerPC.");
582 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
585 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
586 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
587 HandleVRSaveUpdate(MBBI, TII);
592 // Move MBBI back to the beginning of the function.
595 // Work out frame sizes.
596 unsigned FrameSize = determineFrameLayout(MF);
597 int NegFrameSize = -FrameSize;
598 if (!isInt<32>(NegFrameSize))
599 llvm_unreachable("Unhandled stack size!");
601 if (MFI->isFrameAddressTaken())
602 replaceFPWithRealFP(MF);
604 // Check if the link register (LR) must be saved.
605 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
606 bool MustSaveLR = FI->mustSaveLR();
607 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
608 // Do we have a frame pointer and/or base pointer for this function?
609 bool HasFP = hasFP(MF);
610 bool HasBP = RegInfo->hasBasePointer(MF);
612 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
613 unsigned BPReg = RegInfo->getBaseRegister(MF);
614 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
615 unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR;
616 unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0;
617 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
618 // ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.)
619 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8
621 const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD
623 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU
625 const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX
627 const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8
629 const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8
631 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
633 const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8
635 const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8
638 // Regarding this assert: Even though LR is saved in the caller's frame (i.e.,
639 // LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no
640 // Red Zone, an asynchronous event (a form of "callee") could claim a frame &
641 // overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR.
642 assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) &&
643 "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
645 int LROffset = getReturnSaveOffset();
650 MachineFrameInfo *FFI = MF.getFrameInfo();
651 int FPIndex = FI->getFramePointerSaveIndex();
652 assert(FPIndex && "No Frame Pointer Save Slot!");
653 FPOffset = FFI->getObjectOffset(FPIndex);
655 FPOffset = getFramePointerSaveOffset();
662 MachineFrameInfo *FFI = MF.getFrameInfo();
663 int BPIndex = FI->getBasePointerSaveIndex();
664 assert(BPIndex && "No Base Pointer Save Slot!");
665 BPOffset = FFI->getObjectOffset(BPIndex);
667 BPOffset = getBasePointerSaveOffset();
672 if (FI->usesPICBase()) {
673 MachineFrameInfo *FFI = MF.getFrameInfo();
674 int PBPIndex = FI->getPICBasePointerSaveIndex();
675 assert(PBPIndex && "No PIC Base Pointer Save Slot!");
676 PBPOffset = FFI->getObjectOffset(PBPIndex);
679 // Get stack alignments.
680 unsigned MaxAlign = MFI->getMaxAlignment();
681 if (HasBP && MaxAlign > 1)
682 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
683 "Invalid alignment!");
685 // Frames of 32KB & larger require special handling because they cannot be
686 // indexed into with a simple STDU/STWU/STD/STW immediate offset operand.
687 bool isLargeFrame = !isInt<16>(NegFrameSize);
690 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
692 assert((isPPC64 || MustSaveCRs.empty()) &&
693 "Prologue CR saving supported only in 64-bit mode");
695 if (!MustSaveCRs.empty()) { // will only occur for PPC64
696 // FIXME: In the ELFv2 ABI, we are not required to save all CR fields.
697 // If only one or two CR fields are clobbered, it could be more
698 // efficient to use mfocrf to selectively save just those fields.
699 MachineInstrBuilder MIB =
700 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg);
701 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
702 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill);
706 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
707 BuildMI(MBB, MBBI, dl, StoreInst)
712 if (FI->usesPICBase())
713 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
714 BuildMI(MBB, MBBI, dl, StoreInst)
720 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
721 BuildMI(MBB, MBBI, dl, StoreInst)
727 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
728 BuildMI(MBB, MBBI, dl, StoreInst)
733 if (!MustSaveCRs.empty()) // will only occur for PPC64
734 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
735 .addReg(TempReg, getKillRegState(true))
739 // Skip the rest if this is a leaf function & all spills fit in the Red Zone.
740 if (!FrameSize) return;
742 // Adjust stack pointer: r1 += NegFrameSize.
743 // If there is a preferred stack alignment, align R1 now
746 // Save a copy of r1 as the base pointer.
747 BuildMI(MBB, MBBI, dl, OrInst, BPReg)
752 if (HasBP && MaxAlign > 1) {
754 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)
757 .addImm(64 - Log2_32(MaxAlign));
759 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)
762 .addImm(32 - Log2_32(MaxAlign))
765 BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg)
766 .addReg(ScratchReg, RegState::Kill)
767 .addImm(NegFrameSize);
769 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg)
770 .addImm(NegFrameSize >> 16);
771 BuildMI(MBB, MBBI, dl, OrImmInst, TempReg)
772 .addReg(TempReg, RegState::Kill)
773 .addImm(NegFrameSize & 0xFFFF);
774 BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg)
775 .addReg(ScratchReg, RegState::Kill)
776 .addReg(TempReg, RegState::Kill);
778 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
779 .addReg(SPReg, RegState::Kill)
783 } else if (!isLargeFrame) {
784 BuildMI(MBB, MBBI, dl, StoreUpdtInst, SPReg)
786 .addImm(NegFrameSize)
790 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
791 .addImm(NegFrameSize >> 16);
792 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
793 .addReg(ScratchReg, RegState::Kill)
794 .addImm(NegFrameSize & 0xFFFF);
795 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
796 .addReg(SPReg, RegState::Kill)
801 // Add Call Frame Information for the instructions we generated above.
806 // Define CFA in terms of BP. Do this in preference to using FP/SP,
807 // because if the stack needed aligning then CFA won't be at a fixed
808 // offset from FP/SP.
809 unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
810 CFIIndex = MMI.addFrameInst(
811 MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
813 // Adjust the definition of CFA to account for the change in SP.
814 assert(NegFrameSize);
815 CFIIndex = MMI.addFrameInst(
816 MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize));
818 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
819 .addCFIIndex(CFIIndex);
822 // Describe where FP was saved, at a fixed offset from CFA.
823 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
824 CFIIndex = MMI.addFrameInst(
825 MCCFIInstruction::createOffset(nullptr, Reg, FPOffset));
826 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
827 .addCFIIndex(CFIIndex);
830 if (FI->usesPICBase()) {
831 // Describe where FP was saved, at a fixed offset from CFA.
832 unsigned Reg = MRI->getDwarfRegNum(PPC::R30, true);
833 CFIIndex = MMI.addFrameInst(
834 MCCFIInstruction::createOffset(nullptr, Reg, PBPOffset));
835 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
836 .addCFIIndex(CFIIndex);
840 // Describe where BP was saved, at a fixed offset from CFA.
841 unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
842 CFIIndex = MMI.addFrameInst(
843 MCCFIInstruction::createOffset(nullptr, Reg, BPOffset));
844 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
845 .addCFIIndex(CFIIndex);
849 // Describe where LR was saved, at a fixed offset from CFA.
850 unsigned Reg = MRI->getDwarfRegNum(LRReg, true);
851 CFIIndex = MMI.addFrameInst(
852 MCCFIInstruction::createOffset(nullptr, Reg, LROffset));
853 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
854 .addCFIIndex(CFIIndex);
858 // If there is a frame pointer, copy R1 into R31
860 BuildMI(MBB, MBBI, dl, OrInst, FPReg)
864 if (!HasBP && needsCFI) {
865 // Change the definition of CFA from SP+offset to FP+offset, because SP
866 // will change at every alloca.
867 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
868 unsigned CFIIndex = MMI.addFrameInst(
869 MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
871 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
872 .addCFIIndex(CFIIndex);
877 // Describe where callee saved registers were saved, at fixed offsets from
879 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
880 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
881 unsigned Reg = CSI[I].getReg();
882 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
884 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
885 // subregisters of CR2. We just need to emit a move of CR2.
886 if (PPC::CRBITRCRegClass.contains(Reg))
889 // For SVR4, don't emit a move for the CR spill slot if we haven't
891 if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
892 && MustSaveCRs.empty())
895 // For 64-bit SVR4 when we have spilled CRs, the spill location
896 // is SP+8, not a frame-relative slot.
897 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
898 // In the ELFv1 ABI, only CR2 is noted in CFI and stands in for
899 // the whole CR word. In the ELFv2 ABI, every CR that was
900 // actually saved gets its own CFI record.
901 unsigned CRReg = isELFv2ABI? Reg : (unsigned) PPC::CR2;
902 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
903 nullptr, MRI->getDwarfRegNum(CRReg, true), 8));
904 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
905 .addCFIIndex(CFIIndex);
909 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
910 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
911 nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
912 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
913 .addCFIIndex(CFIIndex);
918 void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
919 MachineBasicBlock &MBB) const {
920 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
921 assert(MBBI != MBB.end() && "Returning block has no terminator");
922 const PPCInstrInfo &TII =
923 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
924 const PPCRegisterInfo *RegInfo =
925 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
927 unsigned RetOpcode = MBBI->getOpcode();
930 assert((RetOpcode == PPC::BLR ||
931 RetOpcode == PPC::BLR8 ||
932 RetOpcode == PPC::TCRETURNri ||
933 RetOpcode == PPC::TCRETURNdi ||
934 RetOpcode == PPC::TCRETURNai ||
935 RetOpcode == PPC::TCRETURNri8 ||
936 RetOpcode == PPC::TCRETURNdi8 ||
937 RetOpcode == PPC::TCRETURNai8) &&
938 "Can only insert epilog into returning blocks");
940 // Get alignment info so we know how to restore the SP.
941 const MachineFrameInfo *MFI = MF.getFrameInfo();
943 // Get the number of bytes allocated from the FrameInfo.
944 int FrameSize = MFI->getStackSize();
946 // Get processor type.
947 bool isPPC64 = Subtarget.isPPC64();
949 bool isSVR4ABI = Subtarget.isSVR4ABI();
951 // Check if the link register (LR) has been saved.
952 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
953 bool MustSaveLR = FI->mustSaveLR();
954 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
955 // Do we have a frame pointer and/or base pointer for this function?
956 bool HasFP = hasFP(MF);
957 bool HasBP = RegInfo->hasBasePointer(MF);
959 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
960 unsigned BPReg = RegInfo->getBaseRegister(MF);
961 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
962 unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0;
963 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
964 const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8
966 const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD
968 const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8
970 const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8
972 const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8
974 const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8
977 int LROffset = getReturnSaveOffset();
982 MachineFrameInfo *FFI = MF.getFrameInfo();
983 int FPIndex = FI->getFramePointerSaveIndex();
984 assert(FPIndex && "No Frame Pointer Save Slot!");
985 FPOffset = FFI->getObjectOffset(FPIndex);
987 FPOffset = getFramePointerSaveOffset();
994 MachineFrameInfo *FFI = MF.getFrameInfo();
995 int BPIndex = FI->getBasePointerSaveIndex();
996 assert(BPIndex && "No Base Pointer Save Slot!");
997 BPOffset = FFI->getObjectOffset(BPIndex);
999 BPOffset = getBasePointerSaveOffset();
1004 if (FI->usesPICBase()) {
1005 MachineFrameInfo *FFI = MF.getFrameInfo();
1006 int PBPIndex = FI->getPICBasePointerSaveIndex();
1007 assert(PBPIndex && "No PIC Base Pointer Save Slot!");
1008 PBPOffset = FFI->getObjectOffset(PBPIndex);
1011 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
1012 RetOpcode == PPC::TCRETURNdi ||
1013 RetOpcode == PPC::TCRETURNai ||
1014 RetOpcode == PPC::TCRETURNri8 ||
1015 RetOpcode == PPC::TCRETURNdi8 ||
1016 RetOpcode == PPC::TCRETURNai8;
1019 int MaxTCRetDelta = FI->getTailCallSPDelta();
1020 MachineOperand &StackAdjust = MBBI->getOperand(1);
1021 assert(StackAdjust.isImm() && "Expecting immediate value.");
1022 // Adjust stack pointer.
1023 int StackAdj = StackAdjust.getImm();
1024 int Delta = StackAdj - MaxTCRetDelta;
1025 assert((Delta >= 0) && "Delta must be positive");
1026 if (MaxTCRetDelta>0)
1027 FrameSize += (StackAdj +Delta);
1029 FrameSize += StackAdj;
1032 // Frames of 32KB & larger require special handling because they cannot be
1033 // indexed into with a simple LD/LWZ immediate offset operand.
1034 bool isLargeFrame = !isInt<16>(FrameSize);
1037 // In the prologue, the loaded (or persistent) stack pointer value is offset
1038 // by the STDU/STDUX/STWU/STWUX instruction. Add this offset back now.
1040 // If this function contained a fastcc call and GuaranteedTailCallOpt is
1041 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
1042 // call which invalidates the stack pointer value in SP(0). So we use the
1043 // value of R31 in this case.
1044 if (FI->hasFastCall()) {
1045 assert(HasFP && "Expecting a valid frame pointer.");
1046 if (!isLargeFrame) {
1047 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1048 .addReg(FPReg).addImm(FrameSize);
1050 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1051 .addImm(FrameSize >> 16);
1052 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1053 .addReg(ScratchReg, RegState::Kill)
1054 .addImm(FrameSize & 0xFFFF);
1055 BuildMI(MBB, MBBI, dl, AddInst)
1058 .addReg(ScratchReg);
1060 } else if (!isLargeFrame && !HasBP && !MFI->hasVarSizedObjects()) {
1061 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1065 BuildMI(MBB, MBBI, dl, LoadInst, SPReg)
1073 BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
1077 assert((isPPC64 || MustSaveCRs.empty()) &&
1078 "Epilogue CR restoring supported only in 64-bit mode");
1080 if (!MustSaveCRs.empty()) // will only occur for PPC64
1081 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
1086 BuildMI(MBB, MBBI, dl, LoadInst, FPReg)
1090 if (FI->usesPICBase())
1091 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
1092 BuildMI(MBB, MBBI, dl, LoadInst)
1098 BuildMI(MBB, MBBI, dl, LoadInst, BPReg)
1102 if (!MustSaveCRs.empty()) // will only occur for PPC64
1103 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
1104 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
1105 .addReg(TempReg, getKillRegState(i == e-1));
1108 BuildMI(MBB, MBBI, dl, MTLRInst).addReg(ScratchReg);
1110 // Callee pop calling convention. Pop parameter/linkage area. Used for tail
1111 // call optimization
1112 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1113 (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) &&
1114 MF.getFunction()->getCallingConv() == CallingConv::Fast) {
1115 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1116 unsigned CallerAllocatedAmt = FI->getMinReservedArea();
1118 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
1119 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1120 .addReg(SPReg).addImm(CallerAllocatedAmt);
1122 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1123 .addImm(CallerAllocatedAmt >> 16);
1124 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1125 .addReg(ScratchReg, RegState::Kill)
1126 .addImm(CallerAllocatedAmt & 0xFFFF);
1127 BuildMI(MBB, MBBI, dl, AddInst)
1130 .addReg(ScratchReg);
1132 } else if (RetOpcode == PPC::TCRETURNdi) {
1133 MBBI = MBB.getLastNonDebugInstr();
1134 MachineOperand &JumpTarget = MBBI->getOperand(0);
1135 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
1136 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1137 } else if (RetOpcode == PPC::TCRETURNri) {
1138 MBBI = MBB.getLastNonDebugInstr();
1139 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1140 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
1141 } else if (RetOpcode == PPC::TCRETURNai) {
1142 MBBI = MBB.getLastNonDebugInstr();
1143 MachineOperand &JumpTarget = MBBI->getOperand(0);
1144 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
1145 } else if (RetOpcode == PPC::TCRETURNdi8) {
1146 MBBI = MBB.getLastNonDebugInstr();
1147 MachineOperand &JumpTarget = MBBI->getOperand(0);
1148 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
1149 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1150 } else if (RetOpcode == PPC::TCRETURNri8) {
1151 MBBI = MBB.getLastNonDebugInstr();
1152 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1153 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
1154 } else if (RetOpcode == PPC::TCRETURNai8) {
1155 MBBI = MBB.getLastNonDebugInstr();
1156 MachineOperand &JumpTarget = MBBI->getOperand(0);
1157 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
1162 PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1163 RegScavenger *) const {
1164 const PPCRegisterInfo *RegInfo =
1165 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
1167 // Save and clear the LR state.
1168 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1169 unsigned LR = RegInfo->getRARegister();
1170 FI->setMustSaveLR(MustSaveLR(MF, LR));
1171 MachineRegisterInfo &MRI = MF.getRegInfo();
1172 MRI.setPhysRegUnused(LR);
1174 // Save R31 if necessary
1175 int FPSI = FI->getFramePointerSaveIndex();
1176 bool isPPC64 = Subtarget.isPPC64();
1177 bool isDarwinABI = Subtarget.isDarwinABI();
1178 MachineFrameInfo *MFI = MF.getFrameInfo();
1180 // If the frame pointer save index hasn't been defined yet.
1181 if (!FPSI && needsFP(MF)) {
1182 // Find out what the fix offset of the frame pointer save area.
1183 int FPOffset = getFramePointerSaveOffset();
1184 // Allocate the frame index for frame pointer save area.
1185 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
1187 FI->setFramePointerSaveIndex(FPSI);
1190 int BPSI = FI->getBasePointerSaveIndex();
1191 if (!BPSI && RegInfo->hasBasePointer(MF)) {
1192 int BPOffset = getBasePointerSaveOffset();
1193 // Allocate the frame index for the base pointer save area.
1194 BPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, BPOffset, true);
1196 FI->setBasePointerSaveIndex(BPSI);
1199 // Reserve stack space for the PIC Base register (R30).
1200 // Only used in SVR4 32-bit.
1201 if (FI->usesPICBase()) {
1202 int PBPSI = FI->getPICBasePointerSaveIndex();
1203 PBPSI = MFI->CreateFixedObject(4, -8, true);
1204 FI->setPICBasePointerSaveIndex(PBPSI);
1207 // Reserve stack space to move the linkage area to in case of a tail call.
1209 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1210 (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
1211 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
1214 // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
1215 // function uses CR 2, 3, or 4.
1216 if (!isPPC64 && !isDarwinABI &&
1217 (MRI.isPhysRegUsed(PPC::CR2) ||
1218 MRI.isPhysRegUsed(PPC::CR3) ||
1219 MRI.isPhysRegUsed(PPC::CR4))) {
1220 int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true);
1221 FI->setCRSpillFrameIndex(FrameIdx);
1225 void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
1226 RegScavenger *RS) const {
1227 // Early exit if not using the SVR4 ABI.
1228 if (!Subtarget.isSVR4ABI()) {
1229 addScavengingSpillSlot(MF, RS);
1233 // Get callee saved register information.
1234 MachineFrameInfo *FFI = MF.getFrameInfo();
1235 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
1237 // Early exit if no callee saved registers are modified!
1238 if (CSI.empty() && !needsFP(MF)) {
1239 addScavengingSpillSlot(MF, RS);
1243 unsigned MinGPR = PPC::R31;
1244 unsigned MinG8R = PPC::X31;
1245 unsigned MinFPR = PPC::F31;
1246 unsigned MinVR = PPC::V31;
1248 bool HasGPSaveArea = false;
1249 bool HasG8SaveArea = false;
1250 bool HasFPSaveArea = false;
1251 bool HasVRSAVESaveArea = false;
1252 bool HasVRSaveArea = false;
1254 SmallVector<CalleeSavedInfo, 18> GPRegs;
1255 SmallVector<CalleeSavedInfo, 18> G8Regs;
1256 SmallVector<CalleeSavedInfo, 18> FPRegs;
1257 SmallVector<CalleeSavedInfo, 18> VRegs;
1259 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1260 unsigned Reg = CSI[i].getReg();
1261 if (PPC::GPRCRegClass.contains(Reg)) {
1262 HasGPSaveArea = true;
1264 GPRegs.push_back(CSI[i]);
1269 } else if (PPC::G8RCRegClass.contains(Reg)) {
1270 HasG8SaveArea = true;
1272 G8Regs.push_back(CSI[i]);
1277 } else if (PPC::F8RCRegClass.contains(Reg)) {
1278 HasFPSaveArea = true;
1280 FPRegs.push_back(CSI[i]);
1285 } else if (PPC::CRBITRCRegClass.contains(Reg) ||
1286 PPC::CRRCRegClass.contains(Reg)) {
1287 ; // do nothing, as we already know whether CRs are spilled
1288 } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1289 HasVRSAVESaveArea = true;
1290 } else if (PPC::VRRCRegClass.contains(Reg)) {
1291 HasVRSaveArea = true;
1293 VRegs.push_back(CSI[i]);
1299 llvm_unreachable("Unknown RegisterClass!");
1303 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>();
1304 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1306 int64_t LowerBound = 0;
1308 // Take into account stack space reserved for tail calls.
1310 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1311 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
1312 LowerBound = TCSPDelta;
1315 // The Floating-point register save area is right below the back chain word
1316 // of the previous stack frame.
1317 if (HasFPSaveArea) {
1318 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
1319 int FI = FPRegs[i].getFrameIdx();
1321 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1324 LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8;
1327 // Check whether the frame pointer register is allocated. If so, make sure it
1328 // is spilled to the correct offset.
1330 HasGPSaveArea = true;
1332 int FI = PFI->getFramePointerSaveIndex();
1333 assert(FI && "No Frame Pointer Save Slot!");
1335 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1338 if (PFI->usesPICBase()) {
1339 HasGPSaveArea = true;
1341 int FI = PFI->getPICBasePointerSaveIndex();
1342 assert(FI && "No PIC Base Pointer Save Slot!");
1344 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1347 const PPCRegisterInfo *RegInfo =
1348 static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
1349 if (RegInfo->hasBasePointer(MF)) {
1350 HasGPSaveArea = true;
1352 int FI = PFI->getBasePointerSaveIndex();
1353 assert(FI && "No Base Pointer Save Slot!");
1355 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1358 // General register save area starts right below the Floating-point
1359 // register save area.
1360 if (HasGPSaveArea || HasG8SaveArea) {
1361 // Move general register save area spill slots down, taking into account
1362 // the size of the Floating-point register save area.
1363 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
1364 int FI = GPRegs[i].getFrameIdx();
1366 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1369 // Move general register save area spill slots down, taking into account
1370 // the size of the Floating-point register save area.
1371 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
1372 int FI = G8Regs[i].getFrameIdx();
1374 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1378 std::min<unsigned>(TRI->getEncodingValue(MinGPR),
1379 TRI->getEncodingValue(MinG8R));
1381 if (Subtarget.isPPC64()) {
1382 LowerBound -= (31 - MinReg + 1) * 8;
1384 LowerBound -= (31 - MinReg + 1) * 4;
1388 // For 32-bit only, the CR save area is below the general register
1389 // save area. For 64-bit SVR4, the CR save area is addressed relative
1390 // to the stack pointer and hence does not need an adjustment here.
1391 // Only CR2 (the first nonvolatile spilled) has an associated frame
1392 // index so that we have a single uniform save area.
1393 if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) {
1394 // Adjust the frame index of the CR spill slot.
1395 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1396 unsigned Reg = CSI[i].getReg();
1398 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
1399 // Leave Darwin logic as-is.
1400 || (!Subtarget.isSVR4ABI() &&
1401 (PPC::CRBITRCRegClass.contains(Reg) ||
1402 PPC::CRRCRegClass.contains(Reg)))) {
1403 int FI = CSI[i].getFrameIdx();
1405 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1409 LowerBound -= 4; // The CR save area is always 4 bytes long.
1412 if (HasVRSAVESaveArea) {
1413 // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1414 // which have the VRSAVE register class?
1415 // Adjust the frame index of the VRSAVE spill slot.
1416 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1417 unsigned Reg = CSI[i].getReg();
1419 if (PPC::VRSAVERCRegClass.contains(Reg)) {
1420 int FI = CSI[i].getFrameIdx();
1422 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1426 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
1429 if (HasVRSaveArea) {
1430 // Insert alignment padding, we need 16-byte alignment.
1431 LowerBound = (LowerBound - 15) & ~(15);
1433 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
1434 int FI = VRegs[i].getFrameIdx();
1436 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1440 addScavengingSpillSlot(MF, RS);
1444 PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
1445 RegScavenger *RS) const {
1446 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
1447 // a large stack, which will require scavenging a register to materialize a
1450 // We need to have a scavenger spill slot for spills if the frame size is
1451 // large. In case there is no free register for large-offset addressing,
1452 // this slot is used for the necessary emergency spill. Also, we need the
1453 // slot for dynamic stack allocations.
1455 // The scavenger might be invoked if the frame offset does not fit into
1456 // the 16-bit immediate. We don't know the complete frame size here
1457 // because we've not yet computed callee-saved register spills or the
1458 // needed alignment padding.
1459 unsigned StackSize = determineFrameLayout(MF, false, true);
1460 MachineFrameInfo *MFI = MF.getFrameInfo();
1461 if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) ||
1462 hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) {
1463 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1464 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1465 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
1466 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1470 // Might we have over-aligned allocas?
1471 bool HasAlVars = MFI->hasVarSizedObjects() &&
1472 MFI->getMaxAlignment() > getStackAlignment();
1474 // These kinds of spills might need two registers.
1475 if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars)
1476 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1484 PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1485 MachineBasicBlock::iterator MI,
1486 const std::vector<CalleeSavedInfo> &CSI,
1487 const TargetRegisterInfo *TRI) const {
1489 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1490 // Return false otherwise to maintain pre-existing behavior.
1491 if (!Subtarget.isSVR4ABI())
1494 MachineFunction *MF = MBB.getParent();
1495 const PPCInstrInfo &TII =
1496 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
1498 bool CRSpilled = false;
1499 MachineInstrBuilder CRMIB;
1501 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1502 unsigned Reg = CSI[i].getReg();
1503 // Only Darwin actually uses the VRSAVE register, but it can still appear
1504 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1505 // Darwin, ignore it.
1506 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1509 // CR2 through CR4 are the nonvolatile CR fields.
1510 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
1512 // Add the callee-saved register as live-in; it's killed at the spill.
1515 if (CRSpilled && IsCRField) {
1516 CRMIB.addReg(Reg, RegState::ImplicitKill);
1520 // Insert the spill to the stack frame.
1522 PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
1523 if (Subtarget.isPPC64()) {
1524 // The actual spill will happen at the start of the prologue.
1525 FuncInfo->addMustSaveCR(Reg);
1528 FuncInfo->setSpillsCR();
1530 // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have
1531 // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
1532 CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
1533 .addReg(Reg, RegState::ImplicitKill);
1535 MBB.insert(MI, CRMIB);
1536 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
1538 getKillRegState(true)),
1539 CSI[i].getFrameIdx()));
1542 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1543 TII.storeRegToStackSlot(MBB, MI, Reg, true,
1544 CSI[i].getFrameIdx(), RC, TRI);
1551 restoreCRs(bool isPPC64, bool is31,
1552 bool CR2Spilled, bool CR3Spilled, bool CR4Spilled,
1553 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1554 const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
1556 MachineFunction *MF = MBB.getParent();
1557 const PPCInstrInfo &TII = *MF->getSubtarget<PPCSubtarget>().getInstrInfo();
1559 unsigned RestoreOp, MoveReg;
1562 // This is handled during epilogue generation.
1565 // 32-bit: FP-relative
1566 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
1568 CSI[CSIIndex].getFrameIdx()));
1569 RestoreOp = PPC::MTOCRF;
1574 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
1575 .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled)));
1578 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
1579 .addReg(MoveReg, getKillRegState(!CR4Spilled)));
1582 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
1583 .addReg(MoveReg, getKillRegState(true)));
1586 void PPCFrameLowering::
1587 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1588 MachineBasicBlock::iterator I) const {
1589 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1590 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1591 I->getOpcode() == PPC::ADJCALLSTACKUP) {
1592 // Add (actually subtract) back the amount the callee popped on return.
1593 if (int CalleeAmt = I->getOperand(1).getImm()) {
1594 bool is64Bit = Subtarget.isPPC64();
1596 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
1597 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
1598 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
1599 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
1600 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
1601 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
1602 MachineInstr *MI = I;
1603 DebugLoc dl = MI->getDebugLoc();
1605 if (isInt<16>(CalleeAmt)) {
1606 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
1607 .addReg(StackReg, RegState::Kill)
1610 MachineBasicBlock::iterator MBBI = I;
1611 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
1612 .addImm(CalleeAmt >> 16);
1613 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
1614 .addReg(TmpReg, RegState::Kill)
1615 .addImm(CalleeAmt & 0xFFFF);
1616 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
1617 .addReg(StackReg, RegState::Kill)
1622 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
1627 PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1628 MachineBasicBlock::iterator MI,
1629 const std::vector<CalleeSavedInfo> &CSI,
1630 const TargetRegisterInfo *TRI) const {
1632 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1633 // Return false otherwise to maintain pre-existing behavior.
1634 if (!Subtarget.isSVR4ABI())
1637 MachineFunction *MF = MBB.getParent();
1638 const PPCInstrInfo &TII =
1639 *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
1640 bool CR2Spilled = false;
1641 bool CR3Spilled = false;
1642 bool CR4Spilled = false;
1643 unsigned CSIIndex = 0;
1645 // Initialize insertion-point logic; we will be restoring in reverse
1647 MachineBasicBlock::iterator I = MI, BeforeI = I;
1648 bool AtStart = I == MBB.begin();
1653 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1654 unsigned Reg = CSI[i].getReg();
1656 // Only Darwin actually uses the VRSAVE register, but it can still appear
1657 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1658 // Darwin, ignore it.
1659 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1662 if (Reg == PPC::CR2) {
1664 // The spill slot is associated only with CR2, which is the
1665 // first nonvolatile spilled. Save it here.
1668 } else if (Reg == PPC::CR3) {
1671 } else if (Reg == PPC::CR4) {
1675 // When we first encounter a non-CR register after seeing at
1676 // least one CR register, restore all spilled CRs together.
1677 if ((CR2Spilled || CR3Spilled || CR4Spilled)
1678 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1679 bool is31 = needsFP(*MF);
1680 restoreCRs(Subtarget.isPPC64(), is31,
1681 CR2Spilled, CR3Spilled, CR4Spilled,
1682 MBB, I, CSI, CSIIndex);
1683 CR2Spilled = CR3Spilled = CR4Spilled = false;
1686 // Default behavior for non-CR saves.
1687 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1688 TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(),
1690 assert(I != MBB.begin() &&
1691 "loadRegFromStackSlot didn't insert any code!");
1694 // Insert in reverse order.
1703 // If we haven't yet spilled the CRs, do so now.
1704 if (CR2Spilled || CR3Spilled || CR4Spilled) {
1705 bool is31 = needsFP(*MF);
1706 restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled,
1707 MBB, I, CSI, CSIIndex);