1 //===-- PPCHazardRecognizers.cpp - PowerPC Hazard Recognizer Impls --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements hazard recognizers for scheduling on PowerPC processors.
12 //===----------------------------------------------------------------------===//
14 #include "PPCHazardRecognizers.h"
16 #include "PPCInstrInfo.h"
17 #include "PPCTargetMachine.h"
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/raw_ostream.h"
24 #define DEBUG_TYPE "pre-RA-sched"
26 bool PPCDispatchGroupSBHazardRecognizer::isLoadAfterStore(SUnit *SU) {
28 if (isBCTRAfterSet(SU))
31 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
38 // SU is a load; for any predecessors in this dispatch group, that are stores,
39 // and with which we have an ordering dependency, return true.
40 for (unsigned i = 0, ie = (unsigned) SU->Preds.size(); i != ie; ++i) {
41 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit());
42 if (!PredMCID || !PredMCID->mayStore())
45 if (!SU->Preds[i].isNormalMemory() && !SU->Preds[i].isBarrier())
48 for (unsigned j = 0, je = CurGroup.size(); j != je; ++j)
49 if (SU->Preds[i].getSUnit() == CurGroup[j])
56 bool PPCDispatchGroupSBHazardRecognizer::isBCTRAfterSet(SUnit *SU) {
57 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
61 if (!MCID->isBranch())
64 // SU is a branch; for any predecessors in this dispatch group, with which we
65 // have a data dependence and set the counter register, return true.
66 for (unsigned i = 0, ie = (unsigned) SU->Preds.size(); i != ie; ++i) {
67 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit());
68 if (!PredMCID || PredMCID->getSchedClass() != PPC::Sched::IIC_SprMTSPR)
71 if (SU->Preds[i].isCtrl())
74 for (unsigned j = 0, je = CurGroup.size(); j != je; ++j)
75 if (SU->Preds[i].getSUnit() == CurGroup[j])
82 // FIXME: Remove this when we don't need this:
83 namespace llvm { namespace PPC { extern int getNonRecordFormOpcode(uint16_t); } }
85 // FIXME: A lot of code in PPCDispatchGroupSBHazardRecognizer is P7 specific.
87 bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID,
89 // FIXME: Indirectly, this information is contained in the itinerary, and
90 // we should derive it from there instead of separately specifying it
92 unsigned IIC = MCID->getSchedClass();
97 case PPC::Sched::IIC_IntDivW:
98 case PPC::Sched::IIC_IntDivD:
99 case PPC::Sched::IIC_LdStLoadUpd:
100 case PPC::Sched::IIC_LdStLDU:
101 case PPC::Sched::IIC_LdStLFDU:
102 case PPC::Sched::IIC_LdStLFDUX:
103 case PPC::Sched::IIC_LdStLHA:
104 case PPC::Sched::IIC_LdStLHAU:
105 case PPC::Sched::IIC_LdStLWA:
106 case PPC::Sched::IIC_LdStSTDU:
107 case PPC::Sched::IIC_LdStSTFDU:
110 case PPC::Sched::IIC_LdStLoadUpdX:
111 case PPC::Sched::IIC_LdStLDUX:
112 case PPC::Sched::IIC_LdStLHAUX:
113 case PPC::Sched::IIC_LdStLWARX:
114 case PPC::Sched::IIC_LdStLDARX:
115 case PPC::Sched::IIC_LdStSTDUX:
116 case PPC::Sched::IIC_LdStSTDCX:
117 case PPC::Sched::IIC_LdStSTWCX:
118 case PPC::Sched::IIC_BrMCRX: // mtcr
119 // FIXME: Add sync/isync (here and in the itinerary).
124 // FIXME: record-form instructions need a different itinerary class.
125 if (NSlots == 1 && PPC::getNonRecordFormOpcode(MCID->getOpcode()) != -1)
130 // All multi-slot instructions must come first.
132 case PPC::Sched::IIC_BrCR: // cr logicals
133 case PPC::Sched::IIC_SprMFCR:
134 case PPC::Sched::IIC_SprMFCRF:
135 case PPC::Sched::IIC_SprMTSPR:
140 ScheduleHazardRecognizer::HazardType
141 PPCDispatchGroupSBHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
142 if (Stalls == 0 && isLoadAfterStore(SU))
145 return ScoreboardHazardRecognizer::getHazardType(SU, Stalls);
148 bool PPCDispatchGroupSBHazardRecognizer::ShouldPreferAnother(SUnit *SU) {
149 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
151 if (MCID && mustComeFirst(MCID, NSlots) && CurSlots)
154 return ScoreboardHazardRecognizer::ShouldPreferAnother(SU);
157 unsigned PPCDispatchGroupSBHazardRecognizer::PreEmitNoops(SUnit *SU) {
158 // We only need to fill out a maximum of 5 slots here: The 6th slot could
159 // only be a second branch, and otherwise the next instruction will start a
161 if (isLoadAfterStore(SU) && CurSlots < 6) {
163 DAG->TM.getSubtarget<PPCSubtarget>().getDarwinDirective();
164 // If we're using a special group-terminating nop, then we need only one.
165 if (Directive == PPC::DIR_PWR6 || Directive == PPC::DIR_PWR7)
171 return ScoreboardHazardRecognizer::PreEmitNoops(SU);
174 void PPCDispatchGroupSBHazardRecognizer::EmitInstruction(SUnit *SU) {
175 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
177 if (CurSlots == 5 || (MCID->isBranch() && CurBranches == 1)) {
179 CurSlots = CurBranches = 0;
181 DEBUG(dbgs() << "**** Adding to dispatch group: SU(" <<
182 SU->NodeNum << "): ");
183 DEBUG(DAG->dumpNode(SU));
186 bool MustBeFirst = mustComeFirst(MCID, NSlots);
188 // If this instruction must come first, but does not, then it starts a
190 if (MustBeFirst && CurSlots) {
191 CurSlots = CurBranches = 0;
196 CurGroup.push_back(SU);
198 if (MCID->isBranch())
203 return ScoreboardHazardRecognizer::EmitInstruction(SU);
206 void PPCDispatchGroupSBHazardRecognizer::AdvanceCycle() {
207 return ScoreboardHazardRecognizer::AdvanceCycle();
210 void PPCDispatchGroupSBHazardRecognizer::RecedeCycle() {
211 llvm_unreachable("Bottom-up scheduling not supported");
214 void PPCDispatchGroupSBHazardRecognizer::Reset() {
216 CurSlots = CurBranches = 0;
217 return ScoreboardHazardRecognizer::Reset();
220 void PPCDispatchGroupSBHazardRecognizer::EmitNoop() {
222 DAG->TM.getSubtarget<PPCSubtarget>().getDarwinDirective();
223 // If the group has now filled all of its slots, or if we're using a special
224 // group-terminating nop, the group is complete.
225 if (Directive == PPC::DIR_PWR6 || Directive == PPC::DIR_PWR7 ||
228 CurSlots = CurBranches = 0;
230 CurGroup.push_back(0);
235 //===----------------------------------------------------------------------===//
236 // PowerPC 970 Hazard Recognizer
238 // This models the dispatch group formation of the PPC970 processor. Dispatch
239 // groups are bundles of up to five instructions that can contain various mixes
240 // of instructions. The PPC970 can dispatch a peak of 4 non-branch and one
241 // branch instruction per-cycle.
243 // There are a number of restrictions to dispatch group formation: some
244 // instructions can only be issued in the first slot of a dispatch group, & some
245 // instructions fill an entire dispatch group. Additionally, only branches can
246 // issue in the 5th (last) slot.
248 // Finally, there are a number of "structural" hazards on the PPC970. These
249 // conditions cause large performance penalties due to misprediction, recovery,
250 // and replay logic that has to happen. These cases include setting a CTR and
251 // branching through it in the same dispatch group, and storing to an address,
252 // then loading from the same address within a dispatch group. To avoid these
253 // conditions, we insert no-op instructions when appropriate.
255 // FIXME: This is missing some significant cases:
256 // 1. Modeling of microcoded instructions.
257 // 2. Handling of serialized operations.
258 // 3. Handling of the esoteric cases in "Resource-based Instruction Grouping".
261 PPCHazardRecognizer970::PPCHazardRecognizer970(const TargetMachine &TM)
266 void PPCHazardRecognizer970::EndDispatchGroup() {
267 DEBUG(errs() << "=== Start of dispatch group\n");
270 // Structural hazard info.
277 PPCHazardRecognizer970::GetInstrType(unsigned Opcode,
278 bool &isFirst, bool &isSingle,
280 bool &isLoad, bool &isStore) {
281 const MCInstrDesc &MCID = TM.getInstrInfo()->get(Opcode);
283 isLoad = MCID.mayLoad();
284 isStore = MCID.mayStore();
286 uint64_t TSFlags = MCID.TSFlags;
288 isFirst = TSFlags & PPCII::PPC970_First;
289 isSingle = TSFlags & PPCII::PPC970_Single;
290 isCracked = TSFlags & PPCII::PPC970_Cracked;
291 return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask);
294 /// isLoadOfStoredAddress - If we have a load from the previously stored pointer
295 /// as indicated by StorePtr1/StorePtr2/StoreSize, return true.
296 bool PPCHazardRecognizer970::
297 isLoadOfStoredAddress(uint64_t LoadSize, int64_t LoadOffset,
298 const Value *LoadValue) const {
299 for (unsigned i = 0, e = NumStores; i != e; ++i) {
300 // Handle exact and commuted addresses.
301 if (LoadValue == StoreValue[i] && LoadOffset == StoreOffset[i])
304 // Okay, we don't have an exact match, if this is an indexed offset, see if
305 // we have overlap (which happens during fp->int conversion for example).
306 if (StoreValue[i] == LoadValue) {
307 // Okay the base pointers match, so we have [c1+r] vs [c2+r]. Check
308 // to see if the load and store actually overlap.
309 if (StoreOffset[i] < LoadOffset) {
310 if (int64_t(StoreOffset[i]+StoreSize[i]) > LoadOffset) return true;
312 if (int64_t(LoadOffset+LoadSize) > StoreOffset[i]) return true;
319 /// getHazardType - We return hazard for any non-branch instruction that would
320 /// terminate the dispatch group. We turn NoopHazard for any
321 /// instructions that wouldn't terminate the dispatch group that would cause a
323 ScheduleHazardRecognizer::HazardType PPCHazardRecognizer970::
324 getHazardType(SUnit *SU, int Stalls) {
325 assert(Stalls == 0 && "PPC hazards don't support scoreboard lookahead");
327 MachineInstr *MI = SU->getInstr();
329 if (MI->isDebugValue())
332 unsigned Opcode = MI->getOpcode();
333 bool isFirst, isSingle, isCracked, isLoad, isStore;
334 PPCII::PPC970_Unit InstrType =
335 GetInstrType(Opcode, isFirst, isSingle, isCracked,
337 if (InstrType == PPCII::PPC970_Pseudo) return NoHazard;
339 // We can only issue a PPC970_First/PPC970_Single instruction (such as
340 // crand/mtspr/etc) if this is the first cycle of the dispatch group.
341 if (NumIssued != 0 && (isFirst || isSingle))
344 // If this instruction is cracked into two ops by the decoder, we know that
345 // it is not a branch and that it cannot issue if 3 other instructions are
346 // already in the dispatch group.
347 if (isCracked && NumIssued > 2)
351 default: llvm_unreachable("Unknown instruction type!");
352 case PPCII::PPC970_FXU:
353 case PPCII::PPC970_LSU:
354 case PPCII::PPC970_FPU:
355 case PPCII::PPC970_VALU:
356 case PPCII::PPC970_VPERM:
357 // We can only issue a branch as the last instruction in a group.
358 if (NumIssued == 4) return Hazard;
360 case PPCII::PPC970_CRU:
361 // We can only issue a CR instruction in the first two slots.
362 if (NumIssued >= 2) return Hazard;
364 case PPCII::PPC970_BRU:
368 // Do not allow MTCTR and BCTRL to be in the same dispatch group.
369 if (HasCTRSet && Opcode == PPC::BCTRL)
372 // If this is a load following a store, make sure it's not to the same or
373 // overlapping address.
374 if (isLoad && NumStores && !MI->memoperands_empty()) {
375 MachineMemOperand *MO = *MI->memoperands_begin();
376 if (isLoadOfStoredAddress(MO->getSize(),
377 MO->getOffset(), MO->getValue()))
384 void PPCHazardRecognizer970::EmitInstruction(SUnit *SU) {
385 MachineInstr *MI = SU->getInstr();
387 if (MI->isDebugValue())
390 unsigned Opcode = MI->getOpcode();
391 bool isFirst, isSingle, isCracked, isLoad, isStore;
392 PPCII::PPC970_Unit InstrType =
393 GetInstrType(Opcode, isFirst, isSingle, isCracked,
395 if (InstrType == PPCII::PPC970_Pseudo) return;
397 // Update structural hazard information.
398 if (Opcode == PPC::MTCTR || Opcode == PPC::MTCTR8) HasCTRSet = true;
400 // Track the address stored to.
401 if (isStore && NumStores < 4 && !MI->memoperands_empty()) {
402 MachineMemOperand *MO = *MI->memoperands_begin();
403 StoreSize[NumStores] = MO->getSize();
404 StoreOffset[NumStores] = MO->getOffset();
405 StoreValue[NumStores] = MO->getValue();
409 if (InstrType == PPCII::PPC970_BRU || isSingle)
410 NumIssued = 4; // Terminate a d-group.
413 // If this instruction is cracked into two ops by the decoder, remember that
414 // we issued two pieces.
422 void PPCHazardRecognizer970::AdvanceCycle() {
423 assert(NumIssued < 5 && "Illegal dispatch group!");
429 void PPCHazardRecognizer970::Reset() {