1 //===-- PPCHazardRecognizers.h - PowerPC Hazard Recognizers -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines hazard recognizers for scheduling on PowerPC processors.
12 //===----------------------------------------------------------------------===//
17 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
18 #include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
19 #include "llvm/CodeGen/SelectionDAGNodes.h"
20 #include "PPCInstrInfo.h"
24 /// PPCHazardRecognizer440 - This class implements a scoreboard-based
25 /// hazard recognizer for the PPC 440 and friends.
26 class PPCHazardRecognizer440 : public ScoreboardHazardRecognizer {
27 const ScheduleDAG *DAG;
29 PPCHazardRecognizer440(const InstrItineraryData *ItinData,
30 const ScheduleDAG *DAG_) :
31 ScoreboardHazardRecognizer(ItinData, DAG_), DAG(DAG_) {}
33 virtual void EmitInstruction(SUnit *SU);
36 /// PPCHazardRecognizer970 - This class defines a finite state automata that
37 /// models the dispatch logic on the PowerPC 970 (aka G5) processor. This
38 /// promotes good dispatch group formation and implements noop insertion to
39 /// avoid structural hazards that cause significant performance penalties (e.g.
40 /// setting the CTR register then branching through it within a dispatch group),
41 /// or storing then loading from the same address within a dispatch group.
42 class PPCHazardRecognizer970 : public ScheduleHazardRecognizer {
43 const TargetInstrInfo &TII;
45 unsigned NumIssued; // Number of insts issued, including advanced cycles.
47 // Various things that can cause a structural hazard.
49 // HasCTRSet - If the CTR register is set in this group, disallow BCTRL.
52 // Was the last instruction issued a BL8_ELF
55 // StoredPtr - Keep track of the address of any store. If we see a load from
56 // the same address (or one that aliases it), disallow the store. We can have
57 // up to four stores in one dispatch group, hence we track up to 4.
59 // This is null if we haven't seen a store yet. We keep track of both
60 // operands of the store here, since we support [r+r] and [r+i] addressing.
61 const Value *StoreValue[4];
62 int64_t StoreOffset[4];
63 uint64_t StoreSize[4];
67 PPCHazardRecognizer970(const TargetInstrInfo &TII);
68 virtual HazardType getHazardType(SUnit *SU, int Stalls);
69 virtual void EmitInstruction(SUnit *SU);
70 virtual void AdvanceCycle();
74 /// EndDispatchGroup - Called when we are finishing a new dispatch group.
76 void EndDispatchGroup();
78 /// GetInstrType - Classify the specified powerpc opcode according to its
80 PPCII::PPC970_Unit GetInstrType(unsigned Opcode,
81 bool &isFirst, bool &isSingle,bool &isCracked,
82 bool &isLoad, bool &isStore);
84 bool isLoadOfStoredAddress(uint64_t LoadSize, int64_t LoadOffset,
85 const Value *LoadValue) const;
88 } // end namespace llvm