1 //===-- PPCHazardRecognizers.h - PowerPC Hazard Recognizers -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines hazard recognizers for scheduling on PowerPC processors.
12 //===----------------------------------------------------------------------===//
17 #include "llvm/CodeGen/ScheduleDAG.h"
21 /// PPCHazardRecognizer970 - This class defines a finite state automata that
22 /// models the dispatch logic on the PowerPC 970 (aka G5) processor. This
23 /// promotes good dispatch group formation and implements noop insertion to
24 /// avoid structural hazards that cause significant performance penalties (e.g.
25 /// setting the CTR register then branching through it within a dispatch group),
26 /// or storing then loading from the same address within a dispatch group.
27 class PPCHazardRecognizer970 : public HazardRecognizer {
28 unsigned NumIssued; // Number of insts issued, including advanced cycles.
30 // Number of various types of instructions in the current dispatch group.
31 unsigned NumFXU; // Number of Fixed Point (integer) instructions
32 unsigned NumLSU; // Number of Load/Store instructions
33 unsigned NumFPU; // Number of Floating Point instructions
34 bool HasCR; // True if Condition Register instruction issued
35 bool HasVALU; // True if Vector Arithmetic instruction issued
36 bool HasVPERM; // True if Vector Permute instruction issued
38 // Various things that can cause a structural hazard.
40 // HasCTRSet - If the CTR register is set in this group, disallow BCTRL.
43 // StoredPtr - Keep track of the address of any store. If we see a load from
44 // the same address (or one that aliases it), disallow the store. We only
45 // need one pointer here, because there can only be two LSU operations and we
46 // only get an LSU reject if the first is a store and the second is a load.
48 // This is null if we haven't seen a store yet. We keep track of both
49 // operands of the store here, since we support [r+r] and [r+i] addressing.
50 SDOperand StorePtr1, StorePtr2;
54 virtual void StartBasicBlock();
55 virtual HazardType getHazardType(SDNode *Node);
56 virtual void EmitInstruction(SDNode *Node);
57 virtual void AdvanceCycle();
58 virtual void EmitNoop();
61 /// EndDispatchGroup - Called when we are finishing a new dispatch group.
63 void EndDispatchGroup();
65 enum PPC970InstrType {
66 FXU, LSU_LD, LSU_ST, FPU, CR, VALU, VPERM, BR, PseudoInst
69 /// GetInstrType - Classify the specified powerpc opcode according to its
71 PPC970InstrType GetInstrType(unsigned Opcode);
73 bool isLoadOfStoredAddress(unsigned LoadSize,
74 SDOperand Ptr1, SDOperand Ptr2) const;
77 } // end namespace llvm