1 //===-- PPC32ISelDAGToDAG.cpp - PPC32 pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for 32 bit PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
16 #include "PPC32TargetMachine.h"
17 #include "PPC32ISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Constants.h"
26 #include "llvm/GlobalValue.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/MathExtras.h"
32 Statistic<> FusedFP ("ppc-codegen", "Number of fused fp operations");
33 Statistic<> FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
35 //===--------------------------------------------------------------------===//
36 /// PPC32DAGToDAGISel - PPC32 specific code to select PPC32 machine
37 /// instructions for SelectionDAG operations.
39 class PPC32DAGToDAGISel : public SelectionDAGISel {
40 PPC32TargetLowering PPC32Lowering;
41 unsigned GlobalBaseReg;
43 PPC32DAGToDAGISel(TargetMachine &TM)
44 : SelectionDAGISel(PPC32Lowering), PPC32Lowering(TM) {}
46 virtual bool runOnFunction(Function &Fn) {
47 // Make sure we re-emit a set of the global base reg if necessary
49 return SelectionDAGISel::runOnFunction(Fn);
52 /// getI32Imm - Return a target constant with the specified value, of type
54 inline SDOperand getI32Imm(unsigned Imm) {
55 return CurDAG->getTargetConstant(Imm, MVT::i32);
58 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
59 /// base register. Return the virtual register that holds this value.
60 SDOperand getGlobalBaseReg();
62 // Select - Convert the specified operand from a target-independent to a
63 // target-specific node if it hasn't already been changed.
64 SDOperand Select(SDOperand Op);
66 SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
67 unsigned OCHi, unsigned OCLo,
68 bool IsArithmetic = false,
70 SDNode *SelectBitfieldInsert(SDNode *N);
72 /// SelectCC - Select a comparison of the specified values with the
73 /// specified condition code, returning the CR# of the expression.
74 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
76 /// SelectAddr - Given the specified address, return the two operands for a
77 /// load/store instruction, and return true if it should be an indexed [r+r]
79 bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
81 SDOperand BuildSDIVSequence(SDNode *N);
82 SDOperand BuildUDIVSequence(SDNode *N);
84 /// InstructionSelectBasicBlock - This callback is invoked by
85 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
86 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
88 // Select target instructions for the DAG.
89 DAG.setRoot(Select(DAG.getRoot()));
90 DAG.RemoveDeadNodes();
92 // Emit machine code to BB.
93 ScheduleAndEmitDAG(DAG);
96 virtual const char *getPassName() const {
97 return "PowerPC DAG->DAG Pattern Instruction Selection";
102 /// getGlobalBaseReg - Output the instructions required to put the
103 /// base address to use for accessing globals into a register.
105 SDOperand PPC32DAGToDAGISel::getGlobalBaseReg() {
106 if (!GlobalBaseReg) {
107 // Insert the set of GlobalBaseReg into the first MBB of the function
108 MachineBasicBlock &FirstMBB = BB->getParent()->front();
109 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
110 SSARegMap *RegMap = BB->getParent()->getSSARegMap();
111 GlobalBaseReg = RegMap->createVirtualRegister(PPC32::GPRCRegisterClass);
112 BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
113 BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
115 return CurDAG->getRegister(GlobalBaseReg, MVT::i32);
119 // isIntImmediate - This method tests to see if a constant operand.
120 // If so Imm will receive the 32 bit value.
121 static bool isIntImmediate(SDNode *N, unsigned& Imm) {
122 if (N->getOpcode() == ISD::Constant) {
123 Imm = cast<ConstantSDNode>(N)->getValue();
129 // isOprShiftImm - Returns true if the specified operand is a shift opcode with
130 // a immediate shift count less than 32.
131 static bool isOprShiftImm(SDNode *N, unsigned& Opc, unsigned& SH) {
132 Opc = N->getOpcode();
133 return (Opc == ISD::SHL || Opc == ISD::SRL || Opc == ISD::SRA) &&
134 isIntImmediate(N->getOperand(1).Val, SH) && SH < 32;
137 // isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s with
138 // any number of 0s on either side. The 1s are allowed to wrap from LSB to
139 // MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is
140 // not, since all 1s are not contiguous.
141 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
142 if (isShiftedMask_32(Val)) {
143 // look for the first non-zero bit
144 MB = CountLeadingZeros_32(Val);
145 // look for the first zero bit after the run of ones
146 ME = CountLeadingZeros_32((Val - 1) ^ Val);
149 Val = ~Val; // invert mask
150 if (isShiftedMask_32(Val)) {
151 // effectively look for the first zero bit
152 ME = CountLeadingZeros_32(Val) - 1;
153 // effectively look for the first one bit after the run of zeros
154 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
162 // isRotateAndMask - Returns true if Mask and Shift can be folded in to a rotate
163 // and mask opcode and mask operation.
164 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
165 unsigned &SH, unsigned &MB, unsigned &ME) {
167 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
168 unsigned Opcode = N->getOpcode();
169 if (N->getNumOperands() != 2 ||
170 !isIntImmediate(N->getOperand(1).Val, Shift) || (Shift > 31))
173 if (Opcode == ISD::SHL) {
174 // apply shift left to mask if it comes first
175 if (IsShiftMask) Mask = Mask << Shift;
176 // determine which bits are made indeterminant by shift
177 Indeterminant = ~(0xFFFFFFFFu << Shift);
178 } else if (Opcode == ISD::SRA || Opcode == ISD::SRL) {
179 // apply shift right to mask if it comes first
180 if (IsShiftMask) Mask = Mask >> Shift;
181 // determine which bits are made indeterminant by shift
182 Indeterminant = ~(0xFFFFFFFFu >> Shift);
183 // adjust for the left rotate
189 // if the mask doesn't intersect any Indeterminant bits
190 if (Mask && !(Mask & Indeterminant)) {
192 // make sure the mask is still a mask (wrap arounds may not be)
193 return isRunOfOnes(Mask, MB, ME);
198 // isOpcWithIntImmediate - This method tests to see if the node is a specific
199 // opcode and that it has a immediate integer right operand.
200 // If so Imm will receive the 32 bit value.
201 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
202 return N->getOpcode() == Opc && isIntImmediate(N->getOperand(1).Val, Imm);
205 // isOprNot - Returns true if the specified operand is an xor with immediate -1.
206 static bool isOprNot(SDNode *N) {
208 return isOpcWithIntImmediate(N, ISD::XOR, Imm) && (signed)Imm == -1;
211 // Immediate constant composers.
212 // Lo16 - grabs the lo 16 bits from a 32 bit constant.
213 // Hi16 - grabs the hi 16 bits from a 32 bit constant.
214 // HA16 - computes the hi bits required if the lo bits are add/subtracted in
216 static unsigned Lo16(unsigned x) { return x & 0x0000FFFF; }
217 static unsigned Hi16(unsigned x) { return Lo16(x >> 16); }
218 static unsigned HA16(unsigned x) { return Hi16((signed)x - (signed short)x); }
220 // isIntImmediate - This method tests to see if a constant operand.
221 // If so Imm will receive the 32 bit value.
222 static bool isIntImmediate(SDOperand N, unsigned& Imm) {
223 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
224 Imm = (unsigned)CN->getSignExtended();
230 /// SelectBitfieldInsert - turn an or of two masked values into
231 /// the rotate left word immediate then mask insert (rlwimi) instruction.
232 /// Returns true on success, false if the caller still needs to select OR.
234 /// Patterns matched:
235 /// 1. or shl, and 5. or and, and
236 /// 2. or and, shl 6. or shl, shr
237 /// 3. or shr, and 7. or shr, shl
239 SDNode *PPC32DAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
240 bool IsRotate = false;
241 unsigned TgtMask = 0xFFFFFFFF, InsMask = 0xFFFFFFFF, SH = 0;
244 SDOperand Op0 = N->getOperand(0);
245 SDOperand Op1 = N->getOperand(1);
247 unsigned Op0Opc = Op0.getOpcode();
248 unsigned Op1Opc = Op1.getOpcode();
250 // Verify that we have the correct opcodes
251 if (ISD::SHL != Op0Opc && ISD::SRL != Op0Opc && ISD::AND != Op0Opc)
253 if (ISD::SHL != Op1Opc && ISD::SRL != Op1Opc && ISD::AND != Op1Opc)
256 // Generate Mask value for Target
257 if (isIntImmediate(Op0.getOperand(1), Value)) {
259 case ISD::SHL: TgtMask <<= Value; break;
260 case ISD::SRL: TgtMask >>= Value; break;
261 case ISD::AND: TgtMask &= Value; break;
267 // Generate Mask value for Insert
268 if (!isIntImmediate(Op1.getOperand(1), Value))
275 if (Op0Opc == ISD::SRL) IsRotate = true;
281 if (Op0Opc == ISD::SHL) IsRotate = true;
288 // If both of the inputs are ANDs and one of them has a logical shift by
289 // constant as its input, make that AND the inserted value so that we can
290 // combine the shift into the rotate part of the rlwimi instruction
291 bool IsAndWithShiftOp = false;
292 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
293 if (Op1.getOperand(0).getOpcode() == ISD::SHL ||
294 Op1.getOperand(0).getOpcode() == ISD::SRL) {
295 if (isIntImmediate(Op1.getOperand(0).getOperand(1), Value)) {
296 SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value;
297 IsAndWithShiftOp = true;
299 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
300 Op0.getOperand(0).getOpcode() == ISD::SRL) {
301 if (isIntImmediate(Op0.getOperand(0).getOperand(1), Value)) {
303 std::swap(TgtMask, InsMask);
304 SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value;
305 IsAndWithShiftOp = true;
310 // Verify that the Target mask and Insert mask together form a full word mask
311 // and that the Insert mask is a run of set bits (which implies both are runs
312 // of set bits). Given that, Select the arguments and generate the rlwimi
315 if (((TgtMask & InsMask) == 0) && isRunOfOnes(InsMask, MB, ME)) {
316 bool fullMask = (TgtMask ^ InsMask) == 0xFFFFFFFF;
317 bool Op0IsAND = Op0Opc == ISD::AND;
318 // Check for rotlwi / rotrwi here, a special case of bitfield insert
319 // where both bitfield halves are sourced from the same value.
320 if (IsRotate && fullMask &&
321 N->getOperand(0).getOperand(0) == N->getOperand(1).getOperand(0)) {
322 Op0 = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32,
323 Select(N->getOperand(0).getOperand(0)),
324 getI32Imm(SH), getI32Imm(0), getI32Imm(31));
327 SDOperand Tmp1 = (Op0IsAND && fullMask) ? Select(Op0.getOperand(0))
329 SDOperand Tmp2 = IsAndWithShiftOp ? Select(Op1.getOperand(0).getOperand(0))
330 : Select(Op1.getOperand(0));
331 Op0 = CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2,
332 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
338 // SelectIntImmediateExpr - Choose code for integer operations with an immediate
340 SDNode *PPC32DAGToDAGISel::SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
341 unsigned OCHi, unsigned OCLo,
344 // Check to make sure this is a constant.
345 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(RHS);
346 // Exit if not a constant.
348 // Extract immediate.
349 unsigned C = (unsigned)CN->getValue();
350 // Negate if required (ISD::SUB).
352 // Get the hi and lo portions of constant.
353 unsigned Hi = IsArithmetic ? HA16(C) : Hi16(C);
354 unsigned Lo = Lo16(C);
356 // If two instructions are needed and usage indicates it would be better to
357 // load immediate into a register, bail out.
358 if (Hi && Lo && CN->use_size() > 2) return false;
360 // Select the first operand.
361 SDOperand Opr0 = Select(LHS);
363 if (Lo) // Add in the lo-part.
364 Opr0 = CurDAG->getTargetNode(OCLo, MVT::i32, Opr0, getI32Imm(Lo));
365 if (Hi) // Add in the hi-part.
366 Opr0 = CurDAG->getTargetNode(OCHi, MVT::i32, Opr0, getI32Imm(Hi));
370 /// SelectAddr - Given the specified address, return the two operands for a
371 /// load/store instruction, and return true if it should be an indexed [r+r]
373 bool PPC32DAGToDAGISel::SelectAddr(SDOperand Addr, SDOperand &Op1,
376 if (Addr.getOpcode() == ISD::ADD) {
377 if (isIntImmediate(Addr.getOperand(1), imm) && isInt16(imm)) {
378 Op1 = getI32Imm(Lo16(imm));
379 if (FrameIndexSDNode *FI =
380 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
382 Op2 = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
384 Op2 = Select(Addr.getOperand(0));
388 Op1 = Select(Addr.getOperand(0));
389 Op2 = Select(Addr.getOperand(1));
390 return true; // [r+r]
394 // Now check if we're dealing with a global, and whether or not we should emit
395 // an optimized load or store for statics.
396 if (GlobalAddressSDNode *GN = dyn_cast<GlobalAddressSDNode>(Addr)) {
397 GlobalValue *GV = GN->getGlobal();
398 if (!GV->hasWeakLinkage() && !GV->isExternal()) {
399 Op1 = CurDAG->getTargetGlobalAddress(GV, MVT::i32);
401 Op2 = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),
404 Op2 = CurDAG->getTargetNode(PPC::LIS, MVT::i32, Op1);
407 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Addr)) {
409 Op2 = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
411 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Addr)) {
414 Op2 = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),Op1);
416 Op2 = CurDAG->getTargetNode(PPC::LIS, MVT::i32, Op1);
424 /// SelectCC - Select a comparison of the specified values with the specified
425 /// condition code, returning the CR# of the expression.
426 SDOperand PPC32DAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
428 // Always select the LHS.
431 // Use U to determine whether the SETCC immediate range is signed or not.
432 if (MVT::isInteger(LHS.getValueType())) {
433 bool U = ISD::isUnsignedIntSetCC(CC);
435 if (isIntImmediate(RHS, Imm) &&
436 ((U && isUInt16(Imm)) || (!U && isInt16(Imm))))
437 return CurDAG->getTargetNode(U ? PPC::CMPLWI : PPC::CMPWI, MVT::i32,
438 LHS, getI32Imm(Lo16(Imm)));
439 return CurDAG->getTargetNode(U ? PPC::CMPLW : PPC::CMPW, MVT::i32,
442 return CurDAG->getTargetNode(PPC::FCMPU, MVT::i32, LHS, Select(RHS));
446 /// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding
448 static unsigned getBCCForSetCC(ISD::CondCode CC) {
450 default: assert(0 && "Unknown condition!"); abort();
451 case ISD::SETEQ: return PPC::BEQ;
452 case ISD::SETNE: return PPC::BNE;
454 case ISD::SETLT: return PPC::BLT;
456 case ISD::SETLE: return PPC::BLE;
458 case ISD::SETGT: return PPC::BGT;
460 case ISD::SETGE: return PPC::BGE;
465 /// getCRIdxForSetCC - Return the index of the condition register field
466 /// associated with the SetCC condition, and whether or not the field is
467 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
468 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool& Inv) {
470 default: assert(0 && "Unknown condition!"); abort();
472 case ISD::SETLT: Inv = false; return 0;
474 case ISD::SETGE: Inv = true; return 0;
476 case ISD::SETGT: Inv = false; return 1;
478 case ISD::SETLE: Inv = true; return 1;
479 case ISD::SETEQ: Inv = false; return 2;
480 case ISD::SETNE: Inv = true; return 2;
485 // Structure used to return the necessary information to codegen an SDIV as
488 int m; // magic number
489 int s; // shift amount
493 unsigned int m; // magic number
494 int a; // add indicator
495 int s; // shift amount
498 /// magic - calculate the magic numbers required to codegen an integer sdiv as
499 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
501 static struct ms magic(int d) {
503 unsigned int ad, anc, delta, q1, r1, q2, r2, t;
504 const unsigned int two31 = 0x80000000U;
508 t = two31 + ((unsigned int)d >> 31);
509 anc = t - 1 - t%ad; // absolute value of nc
510 p = 31; // initialize p
511 q1 = two31/anc; // initialize q1 = 2p/abs(nc)
512 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc))
513 q2 = two31/ad; // initialize q2 = 2p/abs(d)
514 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d))
517 q1 = 2*q1; // update q1 = 2p/abs(nc)
518 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
519 if (r1 >= anc) { // must be unsigned comparison
523 q2 = 2*q2; // update q2 = 2p/abs(d)
524 r2 = 2*r2; // update r2 = rem(2p/abs(d))
525 if (r2 >= ad) { // must be unsigned comparison
530 } while (q1 < delta || (q1 == delta && r1 == 0));
533 if (d < 0) mag.m = -mag.m; // resulting magic number
534 mag.s = p - 32; // resulting shift
538 /// magicu - calculate the magic numbers required to codegen an integer udiv as
539 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
540 static struct mu magicu(unsigned d)
543 unsigned int nc, delta, q1, r1, q2, r2;
545 magu.a = 0; // initialize "add" indicator
547 p = 31; // initialize p
548 q1 = 0x80000000/nc; // initialize q1 = 2p/nc
549 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc)
550 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d
551 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
554 if (r1 >= nc - r1 ) {
555 q1 = 2*q1 + 1; // update q1
556 r1 = 2*r1 - nc; // update r1
559 q1 = 2*q1; // update q1
560 r1 = 2*r1; // update r1
562 if (r2 + 1 >= d - r2) {
563 if (q2 >= 0x7FFFFFFF) magu.a = 1;
564 q2 = 2*q2 + 1; // update q2
565 r2 = 2*r2 + 1 - d; // update r2
568 if (q2 >= 0x80000000) magu.a = 1;
569 q2 = 2*q2; // update q2
570 r2 = 2*r2 + 1; // update r2
573 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
574 magu.m = q2 + 1; // resulting magic number
575 magu.s = p - 32; // resulting shift
579 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
580 /// return a DAG expression to select that will generate the same value by
581 /// multiplying by a magic number. See:
582 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
583 SDOperand PPC32DAGToDAGISel::BuildSDIVSequence(SDNode *N) {
584 int d = (int)cast<ConstantSDNode>(N->getOperand(1))->getValue();
585 ms magics = magic(d);
586 // Multiply the numerator (operand 0) by the magic value
587 SDOperand Q = CurDAG->getNode(ISD::MULHS, MVT::i32, N->getOperand(0),
588 CurDAG->getConstant(magics.m, MVT::i32));
589 // If d > 0 and m < 0, add the numerator
590 if (d > 0 && magics.m < 0)
591 Q = CurDAG->getNode(ISD::ADD, MVT::i32, Q, N->getOperand(0));
592 // If d < 0 and m > 0, subtract the numerator.
593 if (d < 0 && magics.m > 0)
594 Q = CurDAG->getNode(ISD::SUB, MVT::i32, Q, N->getOperand(0));
595 // Shift right algebraic if shift value is nonzero
597 Q = CurDAG->getNode(ISD::SRA, MVT::i32, Q,
598 CurDAG->getConstant(magics.s, MVT::i32));
599 // Extract the sign bit and add it to the quotient
601 CurDAG->getNode(ISD::SRL, MVT::i32, Q, CurDAG->getConstant(31, MVT::i32));
602 return CurDAG->getNode(ISD::ADD, MVT::i32, Q, T);
605 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
606 /// return a DAG expression to select that will generate the same value by
607 /// multiplying by a magic number. See:
608 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
609 SDOperand PPC32DAGToDAGISel::BuildUDIVSequence(SDNode *N) {
610 unsigned d = (unsigned)cast<ConstantSDNode>(N->getOperand(1))->getValue();
611 mu magics = magicu(d);
612 // Multiply the numerator (operand 0) by the magic value
613 SDOperand Q = CurDAG->getNode(ISD::MULHU, MVT::i32, N->getOperand(0),
614 CurDAG->getConstant(magics.m, MVT::i32));
616 return CurDAG->getNode(ISD::SRL, MVT::i32, Q,
617 CurDAG->getConstant(magics.s, MVT::i32));
619 SDOperand NPQ = CurDAG->getNode(ISD::SUB, MVT::i32, N->getOperand(0), Q);
620 NPQ = CurDAG->getNode(ISD::SRL, MVT::i32, NPQ,
621 CurDAG->getConstant(1, MVT::i32));
622 NPQ = CurDAG->getNode(ISD::ADD, MVT::i32, NPQ, Q);
623 return CurDAG->getNode(ISD::SRL, MVT::i32, NPQ,
624 CurDAG->getConstant(magics.s-1, MVT::i32));
628 // Select - Convert the specified operand from a target-independent to a
629 // target-specific node if it hasn't already been changed.
630 SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
632 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
633 N->getOpcode() < PPCISD::FIRST_NUMBER)
634 return Op; // Already selected.
636 switch (N->getOpcode()) {
638 std::cerr << "Cannot yet select: ";
642 case ISD::EntryToken: // These leaves remain the same.
644 case ISD::AssertSext:
645 case ISD::AssertZext:
646 return Select(N->getOperand(0));
647 case ISD::TokenFactor: {
649 if (N->getNumOperands() == 2) {
650 SDOperand Op0 = Select(N->getOperand(0));
651 SDOperand Op1 = Select(N->getOperand(1));
652 New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Op0, Op1);
654 std::vector<SDOperand> Ops;
655 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
656 Ops.push_back(Select(N->getOperand(i)));
657 New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Ops);
661 CurDAG->ReplaceAllUsesWith(Op, New);
666 case ISD::CopyFromReg: {
667 SDOperand Chain = Select(N->getOperand(0));
668 if (Chain == N->getOperand(0)) return Op; // No change
669 SDOperand New = CurDAG->getCopyFromReg(Chain,
670 cast<RegisterSDNode>(N->getOperand(1))->getReg(), N->getValueType(0));
671 return New.getValue(Op.ResNo);
673 case ISD::CopyToReg: {
674 SDOperand Chain = Select(N->getOperand(0));
675 SDOperand Reg = N->getOperand(1);
676 SDOperand Val = Select(N->getOperand(2));
677 if (Chain != N->getOperand(0) || Val != N->getOperand(2)) {
678 SDOperand New = CurDAG->getNode(ISD::CopyToReg, MVT::Other,
680 CurDAG->ReplaceAllUsesWith(Op, New);
685 case ISD::Constant: {
686 assert(N->getValueType(0) == MVT::i32);
687 unsigned v = (unsigned)cast<ConstantSDNode>(N)->getValue();
688 unsigned Hi = HA16(v);
689 unsigned Lo = Lo16(v);
691 // NOTE: This doesn't use SelectNodeTo, because doing that will prevent
692 // folding shared immediates into other the second instruction that
695 SDOperand Top = CurDAG->getTargetNode(PPC::LIS, MVT::i32,
697 return CurDAG->getTargetNode(PPC::ORI, MVT::i32, Top,
698 getI32Imm(v & 0xFFFF));
700 return CurDAG->getTargetNode(PPC::LI, MVT::i32, getI32Imm(v));
702 return CurDAG->getTargetNode(PPC::LIS, MVT::i32, getI32Imm(v >> 16));
706 if (N->getValueType(0) == MVT::i32)
707 CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_GPR, MVT::i32);
709 CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_FP, N->getValueType(0));
711 case ISD::FrameIndex: {
712 int FI = cast<FrameIndexSDNode>(N)->getIndex();
713 CurDAG->SelectNodeTo(N, PPC::ADDI, MVT::i32,
714 CurDAG->getTargetFrameIndex(FI, MVT::i32),
718 case ISD::ConstantPool: {
719 Constant *C = cast<ConstantPoolSDNode>(N)->get();
720 SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i32);
722 Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),CPI);
724 Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, CPI);
725 CurDAG->SelectNodeTo(N, PPC::LA, MVT::i32, Tmp, CPI);
728 case ISD::GlobalAddress: {
729 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
731 SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i32);
733 Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(), GA);
735 Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, GA);
737 if (GV->hasWeakLinkage() || GV->isExternal())
738 CurDAG->SelectNodeTo(N, PPC::LWZ, MVT::i32, GA, Tmp);
740 CurDAG->SelectNodeTo(N, PPC::LA, MVT::i32, Tmp, GA);
743 case ISD::DYNAMIC_STACKALLOC: {
744 // FIXME: We are currently ignoring the requested alignment for handling
745 // greater than the stack alignment. This will need to be revisited at some
746 // point. Align = N.getOperand(2);
747 if (!isa<ConstantSDNode>(N->getOperand(2)) ||
748 cast<ConstantSDNode>(N->getOperand(2))->getValue() != 0) {
749 std::cerr << "Cannot allocate stack object with greater alignment than"
750 << " the stack alignment yet!";
753 SDOperand Chain = Select(N->getOperand(0));
754 SDOperand Amt = Select(N->getOperand(1));
756 SDOperand R1Reg = CurDAG->getRegister(PPC::R1, MVT::i32);
758 // Subtract the amount (guaranteed to be a multiple of the stack alignment)
759 // from the stack pointer, giving us the result pointer.
760 SDOperand Result = CurDAG->getTargetNode(PPC::SUBF, MVT::i32, Amt, R1Reg);
762 // Copy this result back into R1.
763 Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, R1Reg, Result);
765 // Copy this result back out of R1 to make sure we're not using the stack
766 // space without decrementing the stack pointer.
767 Result = CurDAG->getCopyFromReg(Chain, PPC::R1, MVT::i32);
769 // Finally, replace the DYNAMIC_STACKALLOC with the copyfromreg.
770 CurDAG->ReplaceAllUsesWith(N, Result.Val);
774 case ISD::SIGN_EXTEND_INREG:
775 switch(cast<VTSDNode>(N->getOperand(1))->getVT()) {
776 default: assert(0 && "Illegal type in SIGN_EXTEND_INREG"); break;
778 CurDAG->SelectNodeTo(N, PPC::EXTSH, MVT::i32, Select(N->getOperand(0)));
781 CurDAG->SelectNodeTo(N, PPC::EXTSB, MVT::i32, Select(N->getOperand(0)));
786 assert(N->getValueType(0) == MVT::i32);
787 CurDAG->SelectNodeTo(N, PPC::CNTLZW, MVT::i32, Select(N->getOperand(0)));
790 CurDAG->SelectNodeTo(N, PPC::FSEL, N->getValueType(0),
791 Select(N->getOperand(0)),
792 Select(N->getOperand(1)),
793 Select(N->getOperand(2)));
796 CurDAG->SelectNodeTo(N, PPC::FCTIWZ, N->getValueType(0),
797 Select(N->getOperand(0)));
800 MVT::ValueType Ty = N->getValueType(0);
801 if (Ty == MVT::i32) {
802 if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1),
803 PPC::ADDIS, PPC::ADDI, true)) {
804 CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
807 CurDAG->SelectNodeTo(N, PPC::ADD, MVT::i32, Select(N->getOperand(0)),
808 Select(N->getOperand(1)));
813 if (!NoExcessFPPrecision) { // Match FMA ops
814 if (N->getOperand(0).getOpcode() == ISD::MUL &&
815 N->getOperand(0).Val->hasOneUse()) {
816 ++FusedFP; // Statistic
817 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMADD : PPC::FMADDS, Ty,
818 Select(N->getOperand(0).getOperand(0)),
819 Select(N->getOperand(0).getOperand(1)),
820 Select(N->getOperand(1)));
822 } else if (N->getOperand(1).getOpcode() == ISD::MUL &&
823 N->getOperand(1).hasOneUse()) {
824 ++FusedFP; // Statistic
825 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMADD : PPC::FMADDS, Ty,
826 Select(N->getOperand(1).getOperand(0)),
827 Select(N->getOperand(1).getOperand(1)),
828 Select(N->getOperand(0)));
833 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FADD : PPC::FADDS, Ty,
834 Select(N->getOperand(0)), Select(N->getOperand(1)));
838 MVT::ValueType Ty = N->getValueType(0);
839 if (Ty == MVT::i32) {
841 if (isIntImmediate(N->getOperand(0), Imm) && isInt16(Imm)) {
843 CurDAG->SelectNodeTo(N, PPC::NEG, Ty, Select(N->getOperand(1)));
845 CurDAG->SelectNodeTo(N, PPC::SUBFIC, Ty, Select(N->getOperand(1)),
846 getI32Imm(Lo16(Imm)));
849 if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1),
850 PPC::ADDIS, PPC::ADDI, true, true)) {
851 CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
854 CurDAG->SelectNodeTo(N, PPC::SUBF, Ty, Select(N->getOperand(1)),
855 Select(N->getOperand(0)));
860 if (!NoExcessFPPrecision) { // Match FMA ops
861 if (N->getOperand(0).getOpcode() == ISD::MUL &&
862 N->getOperand(0).Val->hasOneUse()) {
863 ++FusedFP; // Statistic
864 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMSUB : PPC::FMSUBS, Ty,
865 Select(N->getOperand(0).getOperand(0)),
866 Select(N->getOperand(0).getOperand(1)),
867 Select(N->getOperand(1)));
869 } else if (N->getOperand(1).getOpcode() == ISD::MUL &&
870 N->getOperand(1).Val->hasOneUse()) {
871 ++FusedFP; // Statistic
872 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FNMSUB : PPC::FNMSUBS, Ty,
873 Select(N->getOperand(1).getOperand(0)),
874 Select(N->getOperand(1).getOperand(1)),
875 Select(N->getOperand(0)));
879 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FSUB : PPC::FSUBS, Ty,
880 Select(N->getOperand(0)),
881 Select(N->getOperand(1)));
886 if (isIntImmediate(N->getOperand(1), Imm) && isInt16(Imm)) {
887 CurDAG->SelectNodeTo(N, PPC::MULLI, MVT::i32,
888 Select(N->getOperand(0)), getI32Imm(Lo16(Imm)));
891 switch (N->getValueType(0)) {
892 default: assert(0 && "Unhandled multiply type!");
893 case MVT::i32: Opc = PPC::MULLW; break;
894 case MVT::f32: Opc = PPC::FMULS; break;
895 case MVT::f64: Opc = PPC::FMUL; break;
897 CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Select(N->getOperand(0)),
898 Select(N->getOperand(1)));
903 if (isIntImmediate(N->getOperand(1), Imm)) {
904 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
906 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
907 Select(N->getOperand(0)),
908 getI32Imm(Log2_32(Imm)));
909 CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
910 Op.getValue(0), Op.getValue(1));
912 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
914 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
915 Select(N->getOperand(0)),
916 getI32Imm(Log2_32(-Imm)));
918 CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, Op.getValue(0),
920 CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
923 SDOperand Result = Select(BuildSDIVSequence(N));
924 assert(Result.ResNo == 0);
925 CurDAG->ReplaceAllUsesWith(Op, Result);
932 switch (N->getValueType(0)) {
933 default: assert(0 && "Unknown type to ISD::SDIV");
934 case MVT::i32: Opc = PPC::DIVW; break;
935 case MVT::f32: Opc = PPC::FDIVS; break;
936 case MVT::f64: Opc = PPC::FDIV; break;
938 CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Select(N->getOperand(0)),
939 Select(N->getOperand(1)));
943 // If this is a divide by constant, we can emit code using some magic
944 // constants to implement it as a multiply instead.
946 if (isIntImmediate(N->getOperand(1), Imm) && Imm) {
947 SDOperand Result = Select(BuildUDIVSequence(N));
948 assert(Result.ResNo == 0);
949 CurDAG->ReplaceAllUsesWith(Op, Result);
954 CurDAG->SelectNodeTo(N, PPC::DIVWU, MVT::i32, Select(N->getOperand(0)),
955 Select(N->getOperand(1)));
959 assert(N->getValueType(0) == MVT::i32);
960 CurDAG->SelectNodeTo(N, PPC::MULHW, MVT::i32, Select(N->getOperand(0)),
961 Select(N->getOperand(1)));
964 assert(N->getValueType(0) == MVT::i32);
965 CurDAG->SelectNodeTo(N, PPC::MULHWU, MVT::i32, Select(N->getOperand(0)),
966 Select(N->getOperand(1)));
970 // If this is an and of a value rotated between 0 and 31 bits and then and'd
971 // with a mask, emit rlwinm
972 if (isIntImmediate(N->getOperand(1), Imm) && (isShiftedMask_32(Imm) ||
973 isShiftedMask_32(~Imm))) {
976 if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
977 Val = Select(N->getOperand(0).getOperand(0));
979 Val = Select(N->getOperand(0));
980 isRunOfOnes(Imm, MB, ME);
983 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Val, getI32Imm(SH),
984 getI32Imm(MB), getI32Imm(ME));
987 // Finally, check for the case where we are being asked to select
988 // and (not(a), b) or and (a, not(b)) which can be selected as andc.
989 if (isOprNot(N->getOperand(0).Val))
990 CurDAG->SelectNodeTo(N, PPC::ANDC, MVT::i32, Select(N->getOperand(1)),
991 Select(N->getOperand(0).getOperand(0)));
992 else if (isOprNot(N->getOperand(1).Val))
993 CurDAG->SelectNodeTo(N, PPC::ANDC, MVT::i32, Select(N->getOperand(0)),
994 Select(N->getOperand(1).getOperand(0)));
996 CurDAG->SelectNodeTo(N, PPC::AND, MVT::i32, Select(N->getOperand(0)),
997 Select(N->getOperand(1)));
1001 if (SDNode *I = SelectBitfieldInsert(N)) {
1002 CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
1006 if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0),
1008 PPC::ORIS, PPC::ORI)) {
1009 CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
1013 // Finally, check for the case where we are being asked to select
1014 // 'or (not(a), b)' or 'or (a, not(b))' which can be selected as orc.
1015 if (isOprNot(N->getOperand(0).Val))
1016 CurDAG->SelectNodeTo(N, PPC::ORC, MVT::i32, Select(N->getOperand(1)),
1017 Select(N->getOperand(0).getOperand(0)));
1018 else if (isOprNot(N->getOperand(1).Val))
1019 CurDAG->SelectNodeTo(N, PPC::ORC, MVT::i32, Select(N->getOperand(0)),
1020 Select(N->getOperand(1).getOperand(0)));
1022 CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Select(N->getOperand(0)),
1023 Select(N->getOperand(1)));
1026 // Check whether or not this node is a logical 'not'. This is represented
1027 // by llvm as a xor with the constant value -1 (all bits set). If this is a
1028 // 'not', then fold 'or' into 'nor', and so forth for the supported ops.
1031 SDOperand Val = Select(N->getOperand(0));
1032 switch (Val.isTargetOpcode() ? Val.getTargetOpcode() : 0) {
1033 default: Opc = 0; break;
1034 case PPC::OR: Opc = PPC::NOR; break;
1035 case PPC::AND: Opc = PPC::NAND; break;
1036 case PPC::XOR: Opc = PPC::EQV; break;
1039 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Val.getOperand(0),
1042 CurDAG->SelectNodeTo(N, PPC::NOR, MVT::i32, Val, Val);
1045 // If this is a xor with an immediate other than -1, then codegen it as high
1046 // and low 16 bit immediate xors.
1047 if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0),
1049 PPC::XORIS, PPC::XORI)) {
1050 CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
1054 // Finally, check for the case where we are being asked to select
1055 // xor (not(a), b) which is equivalent to not(xor a, b), which is eqv
1056 if (isOprNot(N->getOperand(0).Val))
1057 CurDAG->SelectNodeTo(N, PPC::EQV, MVT::i32,
1058 Select(N->getOperand(0).getOperand(0)),
1059 Select(N->getOperand(1)));
1061 CurDAG->SelectNodeTo(N, PPC::XOR, MVT::i32, Select(N->getOperand(0)),
1062 Select(N->getOperand(1)));
1065 unsigned Imm, SH, MB, ME;
1066 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
1067 isRotateAndMask(N, Imm, true, SH, MB, ME))
1068 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
1069 Select(N->getOperand(0).getOperand(0)),
1070 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
1071 else if (isIntImmediate(N->getOperand(1), Imm))
1072 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Select(N->getOperand(0)),
1073 getI32Imm(Imm), getI32Imm(0), getI32Imm(31-Imm));
1075 CurDAG->SelectNodeTo(N, PPC::SLW, MVT::i32, Select(N->getOperand(0)),
1076 Select(N->getOperand(1)));
1080 unsigned Imm, SH, MB, ME;
1081 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
1082 isRotateAndMask(N, Imm, true, SH, MB, ME))
1083 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
1084 Select(N->getOperand(0).getOperand(0)),
1085 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
1086 else if (isIntImmediate(N->getOperand(1), Imm))
1087 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Select(N->getOperand(0)),
1088 getI32Imm(32-Imm), getI32Imm(Imm), getI32Imm(31));
1090 CurDAG->SelectNodeTo(N, PPC::SRW, MVT::i32, Select(N->getOperand(0)),
1091 Select(N->getOperand(1)));
1095 unsigned Imm, SH, MB, ME;
1096 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
1097 isRotateAndMask(N, Imm, true, SH, MB, ME))
1098 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
1099 Select(N->getOperand(0).getOperand(0)),
1100 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
1101 else if (isIntImmediate(N->getOperand(1), Imm))
1102 CurDAG->SelectNodeTo(N, PPC::SRAWI, MVT::i32, Select(N->getOperand(0)),
1105 CurDAG->SelectNodeTo(N, PPC::SRAW, MVT::i32, Select(N->getOperand(0)),
1106 Select(N->getOperand(1)));
1110 CurDAG->SelectNodeTo(N, PPC::FABS, N->getValueType(0),
1111 Select(N->getOperand(0)));
1113 case ISD::FP_EXTEND:
1114 assert(MVT::f64 == N->getValueType(0) &&
1115 MVT::f32 == N->getOperand(0).getValueType() && "Illegal FP_EXTEND");
1116 // We need to emit an FMR to make sure that the result has the right value
1118 CurDAG->SelectNodeTo(N, PPC::FMR, MVT::f64, Select(N->getOperand(0)));
1121 assert(MVT::f32 == N->getValueType(0) &&
1122 MVT::f64 == N->getOperand(0).getValueType() && "Illegal FP_ROUND");
1123 CurDAG->SelectNodeTo(N, PPC::FRSP, MVT::f32, Select(N->getOperand(0)));
1126 SDOperand Val = Select(N->getOperand(0));
1127 MVT::ValueType Ty = N->getValueType(0);
1128 if (Val.Val->hasOneUse()) {
1130 switch (Val.isTargetOpcode() ? Val.getTargetOpcode() : 0) {
1131 default: Opc = 0; break;
1132 case PPC::FABS: Opc = PPC::FNABS; break;
1133 case PPC::FMADD: Opc = PPC::FNMADD; break;
1134 case PPC::FMADDS: Opc = PPC::FNMADDS; break;
1135 case PPC::FMSUB: Opc = PPC::FNMSUB; break;
1136 case PPC::FMSUBS: Opc = PPC::FNMSUBS; break;
1138 // If we inverted the opcode, then emit the new instruction with the
1139 // inverted opcode and the original instruction's operands. Otherwise,
1140 // fall through and generate a fneg instruction.
1142 if (PPC::FNABS == Opc)
1143 CurDAG->SelectNodeTo(N, Opc, Ty, Val.getOperand(0));
1145 CurDAG->SelectNodeTo(N, Opc, Ty, Val.getOperand(0),
1146 Val.getOperand(1), Val.getOperand(2));
1150 CurDAG->SelectNodeTo(N, PPC::FNEG, Ty, Val);
1154 MVT::ValueType Ty = N->getValueType(0);
1155 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FSQRT : PPC::FSQRTS, Ty,
1156 Select(N->getOperand(0)));
1160 case ISD::ADD_PARTS: {
1161 SDOperand LHSL = Select(N->getOperand(0));
1162 SDOperand LHSH = Select(N->getOperand(1));
1165 bool ME = false, ZE = false;
1166 if (isIntImmediate(N->getOperand(3), Imm)) {
1167 ME = (signed)Imm == -1;
1171 std::vector<SDOperand> Result;
1172 SDOperand CarryFromLo;
1173 if (isIntImmediate(N->getOperand(2), Imm) &&
1174 ((signed)Imm >= -32768 || (signed)Imm < 32768)) {
1175 // Codegen the low 32 bits of the add. Interestingly, there is no
1176 // shifted form of add immediate carrying.
1177 CarryFromLo = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
1178 LHSL, getI32Imm(Imm));
1180 CarryFromLo = CurDAG->getTargetNode(PPC::ADDC, MVT::i32, MVT::Flag,
1181 LHSL, Select(N->getOperand(2)));
1183 CarryFromLo = CarryFromLo.getValue(1);
1185 // Codegen the high 32 bits, adding zero, minus one, or the full value
1186 // along with the carry flag produced by addc/addic.
1189 ResultHi = CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, LHSH, CarryFromLo);
1191 ResultHi = CurDAG->getTargetNode(PPC::ADDME, MVT::i32, LHSH, CarryFromLo);
1193 ResultHi = CurDAG->getTargetNode(PPC::ADDE, MVT::i32, LHSH,
1194 Select(N->getOperand(3)), CarryFromLo);
1195 Result.push_back(CarryFromLo.getValue(0));
1196 Result.push_back(ResultHi);
1197 CurDAG->ReplaceAllUsesWith(N, Result);
1198 return Result[Op.ResNo];
1200 case ISD::SUB_PARTS: {
1201 SDOperand LHSL = Select(N->getOperand(0));
1202 SDOperand LHSH = Select(N->getOperand(1));
1203 SDOperand RHSL = Select(N->getOperand(2));
1204 SDOperand RHSH = Select(N->getOperand(3));
1206 std::vector<SDOperand> Result;
1207 Result.push_back(CurDAG->getTargetNode(PPC::SUBFC, MVT::i32, MVT::Flag,
1209 Result.push_back(CurDAG->getTargetNode(PPC::SUBFE, MVT::i32, RHSH, LHSH,
1210 Result[0].getValue(1)));
1211 CurDAG->ReplaceAllUsesWith(N, Result);
1212 return Result[Op.ResNo];
1218 case ISD::SEXTLOAD: {
1220 bool isIdx = SelectAddr(N->getOperand(1), Op1, Op2);
1222 MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ?
1223 N->getValueType(0) : cast<VTSDNode>(N->getOperand(3))->getVT();
1225 switch (TypeBeingLoaded) {
1226 default: N->dump(); assert(0 && "Cannot load this type!");
1228 case MVT::i8: Opc = isIdx ? PPC::LBZX : PPC::LBZ; break;
1230 if (N->getOpcode() == ISD::SEXTLOAD) { // SEXT load?
1231 Opc = isIdx ? PPC::LHAX : PPC::LHA;
1233 Opc = isIdx ? PPC::LHZX : PPC::LHZ;
1236 case MVT::i32: Opc = isIdx ? PPC::LWZX : PPC::LWZ; break;
1237 case MVT::f32: Opc = isIdx ? PPC::LFSX : PPC::LFS; break;
1238 case MVT::f64: Opc = isIdx ? PPC::LFDX : PPC::LFD; break;
1241 CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
1242 Op1, Op2, Select(N->getOperand(0)));
1246 case ISD::TRUNCSTORE:
1248 SDOperand AddrOp1, AddrOp2;
1249 bool isIdx = SelectAddr(N->getOperand(2), AddrOp1, AddrOp2);
1252 if (N->getOpcode() == ISD::STORE) {
1253 switch (N->getOperand(1).getValueType()) {
1254 default: assert(0 && "unknown Type in store");
1255 case MVT::i32: Opc = isIdx ? PPC::STWX : PPC::STW; break;
1256 case MVT::f64: Opc = isIdx ? PPC::STFDX : PPC::STFD; break;
1257 case MVT::f32: Opc = isIdx ? PPC::STFSX : PPC::STFS; break;
1259 } else { //ISD::TRUNCSTORE
1260 switch(cast<VTSDNode>(N->getOperand(4))->getVT()) {
1261 default: assert(0 && "unknown Type in store");
1263 case MVT::i8: Opc = isIdx ? PPC::STBX : PPC::STB; break;
1264 case MVT::i16: Opc = isIdx ? PPC::STHX : PPC::STH; break;
1268 CurDAG->SelectNodeTo(N, Opc, MVT::Other, Select(N->getOperand(1)),
1269 AddrOp1, AddrOp2, Select(N->getOperand(0)));
1275 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
1276 if (isIntImmediate(N->getOperand(1), Imm)) {
1277 // We can codegen setcc op, imm very efficiently compared to a brcond.
1278 // Check for those cases here.
1281 SDOperand Op = Select(N->getOperand(0));
1283 default: assert(0 && "Unhandled SetCC condition"); abort();
1285 Op = CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op);
1286 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(27),
1287 getI32Imm(5), getI32Imm(31));
1290 SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
1291 Op, getI32Imm(~0U));
1292 CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1));
1296 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
1297 getI32Imm(31), getI32Imm(31));
1300 SDOperand T = CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op);
1301 T = CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op);;
1302 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, T, getI32Imm(1),
1303 getI32Imm(31), getI32Imm(31));
1308 } else if (Imm == ~0U) { // setcc op, -1
1309 SDOperand Op = Select(N->getOperand(0));
1311 default: assert(0 && "Unhandled SetCC condition"); abort();
1313 Op = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
1315 CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
1316 CurDAG->getTargetNode(PPC::LI, MVT::i32,
1321 Op = CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op);
1322 SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
1323 Op, getI32Imm(~0U));
1324 CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1));
1328 SDOperand AD = CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
1330 SDOperand AN = CurDAG->getTargetNode(PPC::AND, MVT::i32, AD, Op);
1331 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, AN, getI32Imm(1),
1332 getI32Imm(31), getI32Imm(31));
1336 Op = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
1337 getI32Imm(31), getI32Imm(31));
1338 CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1));
1346 unsigned Idx = getCRIdxForSetCC(CC, Inv);
1348 SelectCC(Select(N->getOperand(0)), Select(N->getOperand(1)), CC);
1351 // Force the ccreg into CR7.
1352 SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
1354 std::vector<MVT::ValueType> VTs;
1355 VTs.push_back(MVT::Other);
1356 VTs.push_back(MVT::Flag); // NONSTANDARD CopyToReg node: defines a flag
1357 std::vector<SDOperand> Ops;
1358 Ops.push_back(CurDAG->getEntryNode());
1359 Ops.push_back(CR7Reg);
1360 Ops.push_back(CCReg);
1361 CCReg = CurDAG->getNode(ISD::CopyToReg, VTs, Ops).getValue(1);
1363 if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
1364 IntCR = CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg, CCReg);
1366 IntCR = CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg);
1369 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, IntCR,
1370 getI32Imm(32-(3-Idx)), getI32Imm(31), getI32Imm(31));
1373 CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, IntCR,
1374 getI32Imm(32-(3-Idx)), getI32Imm(31),getI32Imm(31));
1375 CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
1381 case ISD::SELECT_CC: {
1382 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1384 // handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
1385 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1386 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1387 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1388 if (N1C->isNullValue() && N3C->isNullValue() &&
1389 N2C->getValue() == 1ULL && CC == ISD::SETNE) {
1390 SDOperand LHS = Select(N->getOperand(0));
1392 CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
1393 LHS, getI32Imm(~0U));
1394 CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, Tmp, LHS,
1399 SDOperand CCReg = SelectCC(Select(N->getOperand(0)),
1400 Select(N->getOperand(1)), CC);
1401 unsigned BROpc = getBCCForSetCC(CC);
1403 bool isFP = MVT::isFloatingPoint(N->getValueType(0));
1404 unsigned SelectCCOp = isFP ? PPC::SELECT_CC_FP : PPC::SELECT_CC_Int;
1405 CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), CCReg,
1406 Select(N->getOperand(2)), Select(N->getOperand(3)),
1411 case ISD::CALLSEQ_START:
1412 case ISD::CALLSEQ_END: {
1413 unsigned Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
1414 unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
1415 PPC::ADJCALLSTACKDOWN : PPC::ADJCALLSTACKUP;
1416 CurDAG->SelectNodeTo(N, Opc, MVT::Other,
1417 getI32Imm(Amt), Select(N->getOperand(0)));
1421 case ISD::TAILCALL: {
1422 SDOperand Chain = Select(N->getOperand(0));
1424 unsigned CallOpcode;
1425 std::vector<SDOperand> CallOperands;
1427 if (GlobalAddressSDNode *GASD =
1428 dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
1429 CallOpcode = PPC::CALLpcrel;
1430 CallOperands.push_back(CurDAG->getTargetGlobalAddress(GASD->getGlobal(),
1432 } else if (ExternalSymbolSDNode *ESSDN =
1433 dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) {
1434 CallOpcode = PPC::CALLpcrel;
1435 CallOperands.push_back(N->getOperand(1));
1437 // Copy the callee address into the CTR register.
1438 SDOperand Callee = Select(N->getOperand(1));
1439 Chain = CurDAG->getTargetNode(PPC::MTCTR, MVT::Other, Callee, Chain);
1441 // Copy the callee address into R12 on darwin.
1442 SDOperand R12 = CurDAG->getRegister(PPC::R12, MVT::i32);
1443 Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, R12, Callee);
1445 CallOperands.push_back(getI32Imm(20)); // Information to encode indcall
1446 CallOperands.push_back(getI32Imm(0)); // Information to encode indcall
1447 CallOperands.push_back(R12);
1448 CallOpcode = PPC::CALLindirect;
1451 unsigned GPR_idx = 0, FPR_idx = 0;
1452 static const unsigned GPR[] = {
1453 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1454 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1456 static const unsigned FPR[] = {
1457 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1458 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1461 SDOperand InFlag; // Null incoming flag value.
1463 for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i) {
1464 unsigned DestReg = 0;
1465 MVT::ValueType RegTy = N->getOperand(i).getValueType();
1466 if (RegTy == MVT::i32) {
1467 assert(GPR_idx < 8 && "Too many int args");
1468 DestReg = GPR[GPR_idx++];
1470 assert(MVT::isFloatingPoint(N->getOperand(i).getValueType()) &&
1471 "Unpromoted integer arg?");
1472 assert(FPR_idx < 13 && "Too many fp args");
1473 DestReg = FPR[FPR_idx++];
1476 if (N->getOperand(i).getOpcode() != ISD::UNDEF) {
1477 SDOperand Val = Select(N->getOperand(i));
1478 Chain = CurDAG->getCopyToReg(Chain, DestReg, Val, InFlag);
1479 InFlag = Chain.getValue(1);
1480 CallOperands.push_back(CurDAG->getRegister(DestReg, RegTy));
1484 // Finally, once everything is in registers to pass to the call, emit the
1487 CallOperands.push_back(InFlag); // Strong dep on register copies.
1489 CallOperands.push_back(Chain); // Weak dep on whatever occurs before
1490 Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
1493 std::vector<SDOperand> CallResults;
1495 // If the call has results, copy the values out of the ret val registers.
1496 switch (N->getValueType(0)) {
1497 default: assert(0 && "Unexpected ret value!");
1498 case MVT::Other: break;
1500 if (N->getValueType(1) == MVT::i32) {
1501 Chain = CurDAG->getCopyFromReg(Chain, PPC::R4, MVT::i32,
1502 Chain.getValue(1)).getValue(1);
1503 CallResults.push_back(Chain.getValue(0));
1504 Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32,
1505 Chain.getValue(1)).getValue(1);
1506 CallResults.push_back(Chain.getValue(0));
1508 Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32,
1509 Chain.getValue(1)).getValue(1);
1510 CallResults.push_back(Chain.getValue(0));
1515 Chain = CurDAG->getCopyFromReg(Chain, PPC::F1, N->getValueType(0),
1516 Chain.getValue(1)).getValue(1);
1517 CallResults.push_back(Chain.getValue(0));
1521 CallResults.push_back(Chain);
1522 CurDAG->ReplaceAllUsesWith(N, CallResults);
1523 return CallResults[Op.ResNo];
1526 SDOperand Chain = Select(N->getOperand(0)); // Token chain.
1528 if (N->getNumOperands() == 2) {
1529 SDOperand Val = Select(N->getOperand(1));
1530 if (N->getOperand(1).getValueType() == MVT::i32) {
1531 Chain = CurDAG->getCopyToReg(Chain, PPC::R3, Val);
1533 assert(MVT::isFloatingPoint(N->getOperand(1).getValueType()));
1534 Chain = CurDAG->getCopyToReg(Chain, PPC::F1, Val);
1536 } else if (N->getNumOperands() > 1) {
1537 assert(N->getOperand(1).getValueType() == MVT::i32 &&
1538 N->getOperand(2).getValueType() == MVT::i32 &&
1539 N->getNumOperands() == 3 && "Unknown two-register ret value!");
1540 Chain = CurDAG->getCopyToReg(Chain, PPC::R4, Select(N->getOperand(1)));
1541 Chain = CurDAG->getCopyToReg(Chain, PPC::R3, Select(N->getOperand(2)));
1544 // Finally, select this to a blr (return) instruction.
1545 CurDAG->SelectNodeTo(N, PPC::BLR, MVT::Other, Chain);
1549 CurDAG->SelectNodeTo(N, PPC::B, MVT::Other, N->getOperand(1),
1550 Select(N->getOperand(0)));
1553 case ISD::BRTWOWAY_CC: {
1554 SDOperand Chain = Select(N->getOperand(0));
1555 MachineBasicBlock *Dest =
1556 cast<BasicBlockSDNode>(N->getOperand(4))->getBasicBlock();
1557 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
1558 SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
1559 unsigned Opc = getBCCForSetCC(CC);
1561 // If this is a two way branch, then grab the fallthrough basic block
1562 // argument and build a PowerPC branch pseudo-op, suitable for long branch
1563 // conversion if necessary by the branch selection pass. Otherwise, emit a
1564 // standard conditional branch.
1565 if (N->getOpcode() == ISD::BRTWOWAY_CC) {
1566 MachineBasicBlock *Fallthrough =
1567 cast<BasicBlockSDNode>(N->getOperand(5))->getBasicBlock();
1568 SDOperand CB = CurDAG->getTargetNode(PPC::COND_BRANCH, MVT::Other,
1569 CondCode, getI32Imm(Opc),
1570 N->getOperand(4), N->getOperand(5),
1572 CurDAG->SelectNodeTo(N, PPC::B, MVT::Other, N->getOperand(5), CB);
1574 // Iterate to the next basic block
1575 ilist<MachineBasicBlock>::iterator It = BB;
1578 // If the fallthrough path is off the end of the function, which would be
1579 // undefined behavior, set it to be the same as the current block because
1580 // we have nothing better to set it to, and leaving it alone will cause
1581 // the PowerPC Branch Selection pass to crash.
1582 if (It == BB->getParent()->end()) It = Dest;
1583 CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other, CondCode,
1584 getI32Imm(Opc), N->getOperand(4),
1585 CurDAG->getBasicBlock(It), Chain);
1590 return SDOperand(N, Op.ResNo);
1594 /// createPPC32ISelDag - This pass converts a legalized DAG into a
1595 /// PowerPC-specific DAG, ready for instruction scheduling.
1597 FunctionPass *llvm::createPPC32ISelDag(TargetMachine &TM) {
1598 return new PPC32DAGToDAGISel(TM);