1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "ppc-codegen"
17 #include "MCTargetDesc/PPCPredicates.h"
18 #include "PPCTargetMachine.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/GlobalAlias.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/GlobalVariable.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetOptions.h"
38 void initializePPCDAGToDAGISelPass(PassRegistry&);
42 //===--------------------------------------------------------------------===//
43 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
44 /// instructions for SelectionDAG operations.
46 class PPCDAGToDAGISel : public SelectionDAGISel {
47 const PPCTargetMachine &TM;
48 const PPCTargetLowering &PPCLowering;
49 const PPCSubtarget &PPCSubTarget;
50 unsigned GlobalBaseReg;
52 explicit PPCDAGToDAGISel(PPCTargetMachine &tm)
53 : SelectionDAGISel(tm), TM(tm),
54 PPCLowering(*TM.getTargetLowering()),
55 PPCSubTarget(*TM.getSubtargetImpl()) {
56 initializePPCDAGToDAGISelPass(*PassRegistry::getPassRegistry());
59 virtual bool runOnMachineFunction(MachineFunction &MF) {
60 // Make sure we re-emit a set of the global base reg if necessary
62 SelectionDAGISel::runOnMachineFunction(MF);
64 if (!PPCSubTarget.isSVR4ABI())
70 virtual void PostprocessISelDAG();
72 /// getI32Imm - Return a target constant with the specified value, of type
74 inline SDValue getI32Imm(unsigned Imm) {
75 return CurDAG->getTargetConstant(Imm, MVT::i32);
78 /// getI64Imm - Return a target constant with the specified value, of type
80 inline SDValue getI64Imm(uint64_t Imm) {
81 return CurDAG->getTargetConstant(Imm, MVT::i64);
84 /// getSmallIPtrImm - Return a target constant of pointer type.
85 inline SDValue getSmallIPtrImm(unsigned Imm) {
86 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy());
89 /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s
90 /// with any number of 0s on either side. The 1s are allowed to wrap from
91 /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs.
92 /// 0x0F0F0000 is not, since all 1s are not contiguous.
93 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME);
96 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
97 /// rotate and mask opcode and mask operation.
98 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask,
99 unsigned &SH, unsigned &MB, unsigned &ME);
101 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
102 /// base register. Return the virtual register that holds this value.
103 SDNode *getGlobalBaseReg();
105 // Select - Convert the specified operand from a target-independent to a
106 // target-specific node if it hasn't already been changed.
107 SDNode *Select(SDNode *N);
109 SDNode *SelectBitfieldInsert(SDNode *N);
111 /// SelectCC - Select a comparison of the specified values with the
112 /// specified condition code, returning the CR# of the expression.
113 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, DebugLoc dl);
115 /// SelectAddrImm - Returns true if the address N can be represented by
116 /// a base register plus a signed 16-bit displacement [r+imm].
117 bool SelectAddrImm(SDValue N, SDValue &Disp,
119 return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG);
122 /// SelectAddrImmOffs - Return true if the operand is valid for a preinc
123 /// immediate field. Because preinc imms have already been validated, just
125 bool SelectAddrImmOffs(SDValue N, SDValue &Out) const {
126 if (isa<ConstantSDNode>(N) || N.getOpcode() == PPCISD::Lo ||
127 N.getOpcode() == ISD::TargetGlobalAddress) {
135 /// SelectAddrIdxOffs - Return true if the operand is valid for a preinc
136 /// index field. Because preinc imms have already been validated, just
138 bool SelectAddrIdxOffs(SDValue N, SDValue &Out) const {
139 if (isa<ConstantSDNode>(N) || N.getOpcode() == PPCISD::Lo ||
140 N.getOpcode() == ISD::TargetGlobalAddress)
147 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
148 /// represented as an indexed [r+r] operation. Returns false if it can
149 /// be represented by [r+imm], which are preferred.
150 bool SelectAddrIdx(SDValue N, SDValue &Base, SDValue &Index) {
151 return PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG);
154 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
155 /// represented as an indexed [r+r] operation.
156 bool SelectAddrIdxOnly(SDValue N, SDValue &Base, SDValue &Index) {
157 return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
160 /// SelectAddrImmShift - Returns true if the address N can be represented by
161 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
162 /// for use by STD and friends.
163 bool SelectAddrImmShift(SDValue N, SDValue &Disp, SDValue &Base) {
164 return PPCLowering.SelectAddressRegImmShift(N, Disp, Base, *CurDAG);
167 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
168 /// inline asm expressions. It is always correct to compute the value into
169 /// a register. The case of adding a (possibly relocatable) constant to a
170 /// register can be improved, but it is wrong to substitute Reg+Reg for
171 /// Reg in an asm, because the load or store opcode would have to change.
172 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
174 std::vector<SDValue> &OutOps) {
175 OutOps.push_back(Op);
179 void InsertVRSaveCode(MachineFunction &MF);
181 virtual const char *getPassName() const {
182 return "PowerPC DAG->DAG Pattern Instruction Selection";
185 // Include the pieces autogenerated from the target description.
186 #include "PPCGenDAGISel.inc"
189 SDNode *SelectSETCC(SDNode *N);
193 /// InsertVRSaveCode - Once the entire function has been instruction selected,
194 /// all virtual registers are created and all machine instructions are built,
195 /// check to see if we need to save/restore VRSAVE. If so, do it.
196 void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) {
197 // Check to see if this function uses vector registers, which means we have to
198 // save and restore the VRSAVE register and update it with the regs we use.
200 // In this case, there will be virtual registers of vector type created
201 // by the scheduler. Detect them now.
202 bool HasVectorVReg = false;
203 for (unsigned i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) {
204 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
205 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) {
206 HasVectorVReg = true;
210 if (!HasVectorVReg) return; // nothing to do.
212 // If we have a vector register, we want to emit code into the entry and exit
213 // blocks to save and restore the VRSAVE register. We do this here (instead
214 // of marking all vector instructions as clobbering VRSAVE) for two reasons:
216 // 1. This (trivially) reduces the load on the register allocator, by not
217 // having to represent the live range of the VRSAVE register.
218 // 2. This (more significantly) allows us to create a temporary virtual
219 // register to hold the saved VRSAVE value, allowing this temporary to be
220 // register allocated, instead of forcing it to be spilled to the stack.
222 // Create two vregs - one to hold the VRSAVE register that is live-in to the
223 // function and one for the value after having bits or'd into it.
224 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
225 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
227 const TargetInstrInfo &TII = *TM.getInstrInfo();
228 MachineBasicBlock &EntryBB = *Fn.begin();
230 // Emit the following code into the entry block:
231 // InVRSAVE = MFVRSAVE
232 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
233 // MTVRSAVE UpdatedVRSAVE
234 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
235 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE);
236 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE),
237 UpdatedVRSAVE).addReg(InVRSAVE);
238 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
240 // Find all return blocks, outputting a restore in each epilog.
241 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
242 if (!BB->empty() && BB->back().isReturn()) {
243 IP = BB->end(); --IP;
245 // Skip over all terminator instructions, which are part of the return
247 MachineBasicBlock::iterator I2 = IP;
248 while (I2 != BB->begin() && (--I2)->isTerminator())
251 // Emit: MTVRSAVE InVRSave
252 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
258 /// getGlobalBaseReg - Output the instructions required to put the
259 /// base address to use for accessing globals into a register.
261 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
262 if (!GlobalBaseReg) {
263 const TargetInstrInfo &TII = *TM.getInstrInfo();
264 // Insert the set of GlobalBaseReg into the first MBB of the function
265 MachineBasicBlock &FirstMBB = MF->front();
266 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
269 if (PPCLowering.getPointerTy() == MVT::i32) {
270 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
271 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
272 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
274 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RCRegClass);
275 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8));
276 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg);
279 return CurDAG->getRegister(GlobalBaseReg,
280 PPCLowering.getPointerTy()).getNode();
283 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
284 /// or 64-bit immediate, and if the value can be accurately represented as a
285 /// sign extension from a 16-bit value. If so, this returns true and the
287 static bool isIntS16Immediate(SDNode *N, short &Imm) {
288 if (N->getOpcode() != ISD::Constant)
291 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
292 if (N->getValueType(0) == MVT::i32)
293 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
295 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
298 static bool isIntS16Immediate(SDValue Op, short &Imm) {
299 return isIntS16Immediate(Op.getNode(), Imm);
303 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
304 /// operand. If so Imm will receive the 32-bit value.
305 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
306 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
307 Imm = cast<ConstantSDNode>(N)->getZExtValue();
313 /// isInt64Immediate - This method tests to see if the node is a 64-bit constant
314 /// operand. If so Imm will receive the 64-bit value.
315 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
316 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
317 Imm = cast<ConstantSDNode>(N)->getZExtValue();
323 // isInt32Immediate - This method tests to see if a constant operand.
324 // If so Imm will receive the 32 bit value.
325 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
326 return isInt32Immediate(N.getNode(), Imm);
330 // isOpcWithIntImmediate - This method tests to see if the node is a specific
331 // opcode and that it has a immediate integer right operand.
332 // If so Imm will receive the 32 bit value.
333 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
334 return N->getOpcode() == Opc
335 && isInt32Immediate(N->getOperand(1).getNode(), Imm);
338 bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
339 if (isShiftedMask_32(Val)) {
340 // look for the first non-zero bit
341 MB = CountLeadingZeros_32(Val);
342 // look for the first zero bit after the run of ones
343 ME = CountLeadingZeros_32((Val - 1) ^ Val);
346 Val = ~Val; // invert mask
347 if (isShiftedMask_32(Val)) {
348 // effectively look for the first zero bit
349 ME = CountLeadingZeros_32(Val) - 1;
350 // effectively look for the first one bit after the run of zeros
351 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
359 bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
360 bool isShiftMask, unsigned &SH,
361 unsigned &MB, unsigned &ME) {
362 // Don't even go down this path for i64, since different logic will be
363 // necessary for rldicl/rldicr/rldimi.
364 if (N->getValueType(0) != MVT::i32)
368 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
369 unsigned Opcode = N->getOpcode();
370 if (N->getNumOperands() != 2 ||
371 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31))
374 if (Opcode == ISD::SHL) {
375 // apply shift left to mask if it comes first
376 if (isShiftMask) Mask = Mask << Shift;
377 // determine which bits are made indeterminant by shift
378 Indeterminant = ~(0xFFFFFFFFu << Shift);
379 } else if (Opcode == ISD::SRL) {
380 // apply shift right to mask if it comes first
381 if (isShiftMask) Mask = Mask >> Shift;
382 // determine which bits are made indeterminant by shift
383 Indeterminant = ~(0xFFFFFFFFu >> Shift);
384 // adjust for the left rotate
386 } else if (Opcode == ISD::ROTL) {
392 // if the mask doesn't intersect any Indeterminant bits
393 if (Mask && !(Mask & Indeterminant)) {
395 // make sure the mask is still a mask (wrap arounds may not be)
396 return isRunOfOnes(Mask, MB, ME);
401 /// SelectBitfieldInsert - turn an or of two masked values into
402 /// the rotate left word immediate then mask insert (rlwimi) instruction.
403 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
404 SDValue Op0 = N->getOperand(0);
405 SDValue Op1 = N->getOperand(1);
406 DebugLoc dl = N->getDebugLoc();
408 APInt LKZ, LKO, RKZ, RKO;
409 CurDAG->ComputeMaskedBits(Op0, LKZ, LKO);
410 CurDAG->ComputeMaskedBits(Op1, RKZ, RKO);
412 unsigned TargetMask = LKZ.getZExtValue();
413 unsigned InsertMask = RKZ.getZExtValue();
415 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
416 unsigned Op0Opc = Op0.getOpcode();
417 unsigned Op1Opc = Op1.getOpcode();
418 unsigned Value, SH = 0;
419 TargetMask = ~TargetMask;
420 InsertMask = ~InsertMask;
422 // If the LHS has a foldable shift and the RHS does not, then swap it to the
423 // RHS so that we can fold the shift into the insert.
424 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
425 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
426 Op0.getOperand(0).getOpcode() == ISD::SRL) {
427 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
428 Op1.getOperand(0).getOpcode() != ISD::SRL) {
430 std::swap(Op0Opc, Op1Opc);
431 std::swap(TargetMask, InsertMask);
434 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
435 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
436 Op1.getOperand(0).getOpcode() != ISD::SRL) {
438 std::swap(Op0Opc, Op1Opc);
439 std::swap(TargetMask, InsertMask);
444 if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) {
447 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
448 isInt32Immediate(Op1.getOperand(1), Value)) {
449 Op1 = Op1.getOperand(0);
450 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
452 if (Op1Opc == ISD::AND) {
453 unsigned SHOpc = Op1.getOperand(0).getOpcode();
454 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) &&
455 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
456 Op1 = Op1.getOperand(0).getOperand(0);
457 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
459 Op1 = Op1.getOperand(0);
464 SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB),
466 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
472 /// SelectCC - Select a comparison of the specified values with the specified
473 /// condition code, returning the CR# of the expression.
474 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
475 ISD::CondCode CC, DebugLoc dl) {
476 // Always select the LHS.
479 if (LHS.getValueType() == MVT::i32) {
481 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
482 if (isInt32Immediate(RHS, Imm)) {
483 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
485 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
486 getI32Imm(Imm & 0xFFFF)), 0);
487 // If this is a 16-bit signed immediate, fold it.
488 if (isInt<16>((int)Imm))
489 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
490 getI32Imm(Imm & 0xFFFF)), 0);
492 // For non-equality comparisons, the default code would materialize the
493 // constant, then compare against it, like this:
497 // Since we are just comparing for equality, we can emit this instead:
498 // xoris r0,r3,0x1234
499 // cmplwi cr0,r0,0x5678
501 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS,
502 getI32Imm(Imm >> 16)), 0);
503 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor,
504 getI32Imm(Imm & 0xFFFF)), 0);
507 } else if (ISD::isUnsignedIntSetCC(CC)) {
508 if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm))
509 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
510 getI32Imm(Imm & 0xFFFF)), 0);
514 if (isIntS16Immediate(RHS, SImm))
515 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
516 getI32Imm((int)SImm & 0xFFFF)),
520 } else if (LHS.getValueType() == MVT::i64) {
522 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
523 if (isInt64Immediate(RHS.getNode(), Imm)) {
524 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
526 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
527 getI32Imm(Imm & 0xFFFF)), 0);
528 // If this is a 16-bit signed immediate, fold it.
530 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
531 getI32Imm(Imm & 0xFFFF)), 0);
533 // For non-equality comparisons, the default code would materialize the
534 // constant, then compare against it, like this:
538 // Since we are just comparing for equality, we can emit this instead:
539 // xoris r0,r3,0x1234
540 // cmpldi cr0,r0,0x5678
542 if (isUInt<32>(Imm)) {
543 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS,
544 getI64Imm(Imm >> 16)), 0);
545 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor,
546 getI64Imm(Imm & 0xFFFF)), 0);
550 } else if (ISD::isUnsignedIntSetCC(CC)) {
551 if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm))
552 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
553 getI64Imm(Imm & 0xFFFF)), 0);
557 if (isIntS16Immediate(RHS, SImm))
558 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
559 getI64Imm(SImm & 0xFFFF)),
563 } else if (LHS.getValueType() == MVT::f32) {
566 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
569 return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0);
572 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
578 llvm_unreachable("Should be lowered by legalize!");
579 default: llvm_unreachable("Unknown condition!");
581 case ISD::SETEQ: return PPC::PRED_EQ;
583 case ISD::SETNE: return PPC::PRED_NE;
585 case ISD::SETLT: return PPC::PRED_LT;
587 case ISD::SETLE: return PPC::PRED_LE;
589 case ISD::SETGT: return PPC::PRED_GT;
591 case ISD::SETGE: return PPC::PRED_GE;
592 case ISD::SETO: return PPC::PRED_NU;
593 case ISD::SETUO: return PPC::PRED_UN;
594 // These two are invalid for floating point. Assume we have int.
595 case ISD::SETULT: return PPC::PRED_LT;
596 case ISD::SETUGT: return PPC::PRED_GT;
600 /// getCRIdxForSetCC - Return the index of the condition register field
601 /// associated with the SetCC condition, and whether or not the field is
602 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
604 /// If this returns with Other != -1, then the returned comparison is an or of
605 /// two simpler comparisons. In this case, Invert is guaranteed to be false.
606 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) {
610 default: llvm_unreachable("Unknown condition!");
612 case ISD::SETLT: return 0; // Bit #0 = SETOLT
614 case ISD::SETGT: return 1; // Bit #1 = SETOGT
616 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ
617 case ISD::SETUO: return 3; // Bit #3 = SETUO
619 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
621 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE
623 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE
624 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO
629 llvm_unreachable("Invalid branch code: should be expanded by legalize");
630 // These are invalid for floating point. Assume integer.
631 case ISD::SETULT: return 0;
632 case ISD::SETUGT: return 1;
636 // getVCmpInst: return the vector compare instruction for the specified
637 // vector type and condition code. Since this is for altivec specific code,
638 // only support the altivec types (v16i8, v8i16, v4i32, and v4f32).
639 static unsigned int getVCmpInst(MVT::SimpleValueType VecVT, ISD::CondCode CC) {
645 if (VecVT == MVT::v16i8)
646 return PPC::VCMPEQUB;
647 else if (VecVT == MVT::v8i16)
648 return PPC::VCMPEQUH;
649 else if (VecVT == MVT::v4i32)
650 return PPC::VCMPEQUW;
651 // v4f32 != v4f32 could be translate to unordered not equal
652 else if (VecVT == MVT::v4f32)
653 return PPC::VCMPEQFP;
659 if (VecVT == MVT::v16i8)
660 return PPC::VCMPGTSB;
661 else if (VecVT == MVT::v8i16)
662 return PPC::VCMPGTSH;
663 else if (VecVT == MVT::v4i32)
664 return PPC::VCMPGTSW;
665 else if (VecVT == MVT::v4f32)
666 return PPC::VCMPGTFP;
672 if (VecVT == MVT::v16i8)
673 return PPC::VCMPGTUB;
674 else if (VecVT == MVT::v8i16)
675 return PPC::VCMPGTUH;
676 else if (VecVT == MVT::v4i32)
677 return PPC::VCMPGTUW;
680 if (VecVT == MVT::v4f32)
681 return PPC::VCMPEQFP;
686 if (VecVT == MVT::v4f32)
687 return PPC::VCMPGTFP;
690 if (VecVT == MVT::v4f32)
691 return PPC::VCMPGEFP;
696 llvm_unreachable("Invalid integer vector compare condition");
699 // getVCmpEQInst: return the equal compare instruction for the specified vector
700 // type. Since this is for altivec specific code, only support the altivec
701 // types (v16i8, v8i16, v4i32, and v4f32).
702 static unsigned int getVCmpEQInst(MVT::SimpleValueType VecVT) {
705 return PPC::VCMPEQUB;
707 return PPC::VCMPEQUH;
709 return PPC::VCMPEQUW;
711 return PPC::VCMPEQFP;
713 llvm_unreachable("Invalid integer vector compare condition");
718 SDNode *PPCDAGToDAGISel::SelectSETCC(SDNode *N) {
719 DebugLoc dl = N->getDebugLoc();
721 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
722 EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy();
723 bool isPPC64 = (PtrVT == MVT::i64);
725 if (isInt32Immediate(N->getOperand(1), Imm)) {
726 // We can codegen setcc op, imm very efficiently compared to a brcond.
727 // Check for those cases here.
730 SDValue Op = N->getOperand(0);
734 Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
735 SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
736 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
741 SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
742 Op, getI32Imm(~0U)), 0);
743 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
747 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
748 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
752 SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0);
753 T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0);
754 SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
755 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
758 } else if (Imm == ~0U) { // setcc op, -1
759 SDValue Op = N->getOperand(0);
764 Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
765 Op, getI32Imm(1)), 0);
766 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
767 SDValue(CurDAG->getMachineNode(PPC::LI, dl,
773 Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0);
774 SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
776 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0),
780 SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op,
782 SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD,
784 SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
785 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
788 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
789 Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4),
791 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
798 SDValue LHS = N->getOperand(0);
799 SDValue RHS = N->getOperand(1);
801 // Altivec Vector compare instructions do not set any CR register by default and
802 // vector compare operations return the same type as the operands.
803 if (LHS.getValueType().isVector()) {
804 EVT VecVT = LHS.getValueType();
805 MVT::SimpleValueType VT = VecVT.getSimpleVT().SimpleTy;
806 unsigned int VCmpInst = getVCmpInst(VT, CC);
812 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS);
816 SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0);
817 return CurDAG->SelectNodeTo(N, PPC::VNOR, VecVT, VCmp, VCmp);
822 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, RHS, LHS);
826 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS);
830 // Small optimization: Altivec provides a 'Vector Compare Greater Than
831 // or Equal To' instruction (vcmpgefp), so in this case there is no
832 // need for extra logic for the equal compare.
833 if (VecVT.getSimpleVT().isFloatingPoint()) {
834 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS);
836 SDValue VCmpGT(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0);
837 unsigned int VCmpEQInst = getVCmpEQInst(VT);
838 SDValue VCmpEQ(CurDAG->getMachineNode(VCmpEQInst, dl, VecVT, LHS, RHS), 0);
839 return CurDAG->SelectNodeTo(N, PPC::VOR, VecVT, VCmpGT, VCmpEQ);
845 SDValue VCmpLE(CurDAG->getMachineNode(VCmpInst, dl, VecVT, RHS, LHS), 0);
846 unsigned int VCmpEQInst = getVCmpEQInst(VT);
847 SDValue VCmpEQ(CurDAG->getMachineNode(VCmpEQInst, dl, VecVT, LHS, RHS), 0);
848 return CurDAG->SelectNodeTo(N, PPC::VOR, VecVT, VCmpLE, VCmpEQ);
851 llvm_unreachable("Invalid vector compare type: should be expanded by legalize");
857 unsigned Idx = getCRIdxForSetCC(CC, Inv, OtherCondIdx);
858 SDValue CCReg = SelectCC(LHS, RHS, CC, dl);
861 // Force the ccreg into CR7.
862 SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
864 SDValue InFlag(0, 0); // Null incoming flag value.
865 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg,
868 if (PPCSubTarget.hasMFOCRF() && OtherCondIdx == -1)
869 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
872 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFCRpseud, dl, MVT::i32,
875 SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
876 getI32Imm(31), getI32Imm(31) };
877 if (OtherCondIdx == -1 && !Inv)
878 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
880 // Get the specified bit.
882 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0);
884 assert(OtherCondIdx == -1 && "Can't have split plus negation");
885 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
888 // Otherwise, we have to turn an operation like SETONE -> SETOLT | SETOGT.
889 // We already got the bit for the first part of the comparison (e.g. SETULE).
891 // Get the other bit of the comparison.
892 Ops[1] = getI32Imm((32-(3-OtherCondIdx)) & 31);
894 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0);
896 return CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Tmp, OtherCond);
900 // Select - Convert the specified operand from a target-independent to a
901 // target-specific node if it hasn't already been changed.
902 SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
903 DebugLoc dl = N->getDebugLoc();
904 if (N->isMachineOpcode())
905 return NULL; // Already selected.
907 switch (N->getOpcode()) {
910 case ISD::Constant: {
911 if (N->getValueType(0) == MVT::i64) {
913 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
914 // Assume no remaining bits.
915 unsigned Remainder = 0;
916 // Assume no shift required.
919 // If it can't be represented as a 32 bit value.
920 if (!isInt<32>(Imm)) {
921 Shift = CountTrailingZeros_64(Imm);
922 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
924 // If the shifted value fits 32 bits.
925 if (isInt<32>(ImmSh)) {
926 // Go with the shifted value.
929 // Still stuck with a 64 bit value.
936 // Intermediate operand.
939 // Handle first 32 bits.
940 unsigned Lo = Imm & 0xFFFF;
941 unsigned Hi = (Imm >> 16) & 0xFFFF;
944 if (isInt<16>(Imm)) {
946 Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo));
948 // Handle the Hi bits.
949 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
950 Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi));
952 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
953 SDValue(Result, 0), getI32Imm(Lo));
956 Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
959 // If no shift, we're done.
960 if (!Shift) return Result;
962 // Shift for next step if the upper 32-bits were not zero.
964 Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64,
967 getI32Imm(63 - Shift));
970 // Add in the last bits as required.
971 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
972 Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64,
973 SDValue(Result, 0), getI32Imm(Hi));
975 if ((Lo = Remainder & 0xFFFF)) {
976 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
977 SDValue(Result, 0), getI32Imm(Lo));
986 return SelectSETCC(N);
987 case PPCISD::GlobalBaseReg:
988 return getGlobalBaseReg();
990 case ISD::FrameIndex: {
991 int FI = cast<FrameIndexSDNode>(N)->getIndex();
992 SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
993 unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
995 return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), TFI,
997 return CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI,
1001 case PPCISD::MFCR: {
1002 SDValue InFlag = N->getOperand(1);
1003 // Use MFOCRF if supported.
1004 if (PPCSubTarget.hasMFOCRF())
1005 return CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32,
1006 N->getOperand(0), InFlag);
1008 return CurDAG->getMachineNode(PPC::MFCRpseud, dl, MVT::i32,
1009 N->getOperand(0), InFlag);
1013 // FIXME: since this depends on the setting of the carry flag from the srawi
1014 // we should really be making notes about that for the scheduler.
1015 // FIXME: It sure would be nice if we could cheaply recognize the
1016 // srl/add/sra pattern the dag combiner will generate for this as
1017 // sra/addze rather than having to handle sdiv ourselves. oh well.
1019 if (isInt32Immediate(N->getOperand(1), Imm)) {
1020 SDValue N0 = N->getOperand(0);
1021 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
1023 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue,
1024 N0, getI32Imm(Log2_32(Imm)));
1025 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
1026 SDValue(Op, 0), SDValue(Op, 1));
1027 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
1029 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue,
1030 N0, getI32Imm(Log2_32(-Imm)));
1032 SDValue(CurDAG->getMachineNode(PPC::ADDZE, dl, MVT::i32,
1033 SDValue(Op, 0), SDValue(Op, 1)),
1035 return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
1039 // Other cases are autogenerated.
1044 // Handle preincrement loads.
1045 LoadSDNode *LD = cast<LoadSDNode>(N);
1046 EVT LoadedVT = LD->getMemoryVT();
1048 // Normal loads are handled by code generated from the .td file.
1049 if (LD->getAddressingMode() != ISD::PRE_INC)
1052 SDValue Offset = LD->getOffset();
1053 if (isa<ConstantSDNode>(Offset) ||
1054 Offset.getOpcode() == ISD::TargetGlobalAddress) {
1057 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
1058 if (LD->getValueType(0) != MVT::i64) {
1059 // Handle PPC32 integer and normal FP loads.
1060 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
1061 switch (LoadedVT.getSimpleVT().SimpleTy) {
1062 default: llvm_unreachable("Invalid PPC load type!");
1063 case MVT::f64: Opcode = PPC::LFDU; break;
1064 case MVT::f32: Opcode = PPC::LFSU; break;
1065 case MVT::i32: Opcode = PPC::LWZU; break;
1066 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
1068 case MVT::i8: Opcode = PPC::LBZU; break;
1071 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
1072 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
1073 switch (LoadedVT.getSimpleVT().SimpleTy) {
1074 default: llvm_unreachable("Invalid PPC load type!");
1075 case MVT::i64: Opcode = PPC::LDU; break;
1076 case MVT::i32: Opcode = PPC::LWZU8; break;
1077 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
1079 case MVT::i8: Opcode = PPC::LBZU8; break;
1083 SDValue Chain = LD->getChain();
1084 SDValue Base = LD->getBasePtr();
1085 SDValue Ops[] = { Offset, Base, Chain };
1086 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
1087 PPCLowering.getPointerTy(),
1088 MVT::Other, Ops, 3);
1091 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
1092 if (LD->getValueType(0) != MVT::i64) {
1093 // Handle PPC32 integer and normal FP loads.
1094 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
1095 switch (LoadedVT.getSimpleVT().SimpleTy) {
1096 default: llvm_unreachable("Invalid PPC load type!");
1097 case MVT::f64: Opcode = PPC::LFDUX; break;
1098 case MVT::f32: Opcode = PPC::LFSUX; break;
1099 case MVT::i32: Opcode = PPC::LWZUX; break;
1100 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break;
1102 case MVT::i8: Opcode = PPC::LBZUX; break;
1105 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
1106 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) &&
1107 "Invalid sext update load");
1108 switch (LoadedVT.getSimpleVT().SimpleTy) {
1109 default: llvm_unreachable("Invalid PPC load type!");
1110 case MVT::i64: Opcode = PPC::LDUX; break;
1111 case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break;
1112 case MVT::i16: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8; break;
1114 case MVT::i8: Opcode = PPC::LBZUX8; break;
1118 SDValue Chain = LD->getChain();
1119 SDValue Base = LD->getBasePtr();
1120 SDValue Ops[] = { Offset, Base, Chain };
1121 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
1122 PPCLowering.getPointerTy(),
1123 MVT::Other, Ops, 3);
1128 unsigned Imm, Imm2, SH, MB, ME;
1131 // If this is an and of a value rotated between 0 and 31 bits and then and'd
1132 // with a mask, emit rlwinm
1133 if (isInt32Immediate(N->getOperand(1), Imm) &&
1134 isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) {
1135 SDValue Val = N->getOperand(0).getOperand(0);
1136 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1137 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
1139 // If this is just a masked value where the input is not handled above, and
1140 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
1141 if (isInt32Immediate(N->getOperand(1), Imm) &&
1142 isRunOfOnes(Imm, MB, ME) &&
1143 N->getOperand(0).getOpcode() != ISD::ROTL) {
1144 SDValue Val = N->getOperand(0);
1145 SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
1146 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
1148 // If this is a 64-bit zero-extension mask, emit rldicl.
1149 if (isInt64Immediate(N->getOperand(1).getNode(), Imm64) &&
1151 SDValue Val = N->getOperand(0);
1152 MB = 64 - CountTrailingOnes_64(Imm64);
1153 SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB) };
1154 return CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops, 3);
1156 // AND X, 0 -> 0, not "rlwinm 32".
1157 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
1158 ReplaceUses(SDValue(N, 0), N->getOperand(1));
1161 // ISD::OR doesn't get all the bitfield insertion fun.
1162 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
1163 if (isInt32Immediate(N->getOperand(1), Imm) &&
1164 N->getOperand(0).getOpcode() == ISD::OR &&
1165 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
1168 if (isRunOfOnes(Imm, MB, ME)) {
1169 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1170 N->getOperand(0).getOperand(1),
1171 getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
1172 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
1176 // Other cases are autogenerated.
1180 if (N->getValueType(0) == MVT::i32)
1181 if (SDNode *I = SelectBitfieldInsert(N))
1184 // Other cases are autogenerated.
1187 unsigned Imm, SH, MB, ME;
1188 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
1189 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1190 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1191 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1192 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
1195 // Other cases are autogenerated.
1199 unsigned Imm, SH, MB, ME;
1200 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
1201 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1202 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1203 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1204 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
1207 // Other cases are autogenerated.
1210 case ISD::SELECT_CC: {
1211 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1212 EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy();
1213 bool isPPC64 = (PtrVT == MVT::i64);
1215 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
1217 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1218 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1219 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1220 if (N1C->isNullValue() && N3C->isNullValue() &&
1221 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
1222 // FIXME: Implement this optzn for PPC64.
1223 N->getValueType(0) == MVT::i32) {
1225 CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
1226 N->getOperand(0), getI32Imm(~0U));
1227 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
1228 SDValue(Tmp, 0), N->getOperand(0),
1232 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
1233 unsigned BROpc = getPredicateForSetCC(CC);
1235 unsigned SelectCCOp;
1236 if (N->getValueType(0) == MVT::i32)
1237 SelectCCOp = PPC::SELECT_CC_I4;
1238 else if (N->getValueType(0) == MVT::i64)
1239 SelectCCOp = PPC::SELECT_CC_I8;
1240 else if (N->getValueType(0) == MVT::f32)
1241 SelectCCOp = PPC::SELECT_CC_F4;
1242 else if (N->getValueType(0) == MVT::f64)
1243 SelectCCOp = PPC::SELECT_CC_F8;
1245 SelectCCOp = PPC::SELECT_CC_VRRC;
1247 SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
1249 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4);
1251 case PPCISD::COND_BRANCH: {
1252 // Op #0 is the Chain.
1253 // Op #1 is the PPC::PRED_* number.
1255 // Op #3 is the Dest MBB
1256 // Op #4 is the Flag.
1257 // Prevent PPC::PRED_* from being selected into LI.
1259 getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue());
1260 SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
1261 N->getOperand(0), N->getOperand(4) };
1262 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5);
1265 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
1266 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
1267 SDValue Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode,
1268 N->getOperand(4), N->getOperand(0) };
1269 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4);
1272 // FIXME: Should custom lower this.
1273 SDValue Chain = N->getOperand(0);
1274 SDValue Target = N->getOperand(1);
1275 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
1276 unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8;
1277 Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, Target,
1279 return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);
1281 case PPCISD::TOC_ENTRY: {
1282 assert (PPCSubTarget.isPPC64() && "Only supported for 64-bit ABI");
1284 // For medium and large code model, we generate two instructions as
1285 // described below. Otherwise we allow SelectCodeCommon to handle this,
1286 // selecting one of LDtoc, LDtocJTI, and LDtocCPT.
1287 CodeModel::Model CModel = TM.getCodeModel();
1288 if (CModel != CodeModel::Medium && CModel != CodeModel::Large)
1291 // The first source operand is a TargetGlobalAddress or a
1292 // TargetJumpTable. If it is an externally defined symbol, a symbol
1293 // with common linkage, a function address, or a jump table address,
1294 // or if we are generating code for large code model, we generate:
1295 // LDtocL(<ga:@sym>, ADDIStocHA(%X2, <ga:@sym>))
1296 // Otherwise we generate:
1297 // ADDItocL(ADDIStocHA(%X2, <ga:@sym>), <ga:@sym>)
1298 SDValue GA = N->getOperand(0);
1299 SDValue TOCbase = N->getOperand(1);
1300 SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA, dl, MVT::i64,
1303 if (isa<JumpTableSDNode>(GA) || CModel == CodeModel::Large)
1304 return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
1307 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(GA)) {
1308 const GlobalValue *GValue = G->getGlobal();
1309 const GlobalAlias *GAlias = dyn_cast<GlobalAlias>(GValue);
1310 const GlobalValue *RealGValue = GAlias ?
1311 GAlias->resolveAliasedGlobal(false) : GValue;
1312 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(RealGValue);
1313 assert((GVar || isa<Function>(RealGValue)) &&
1314 "Unexpected global value subclass!");
1316 // An external variable is one without an initializer. For these,
1317 // for variables with common linkage, and for Functions, generate
1319 if (!GVar || !GVar->hasInitializer() || RealGValue->hasCommonLinkage() ||
1320 RealGValue->hasAvailableExternallyLinkage())
1321 return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
1325 return CurDAG->getMachineNode(PPC::ADDItocL, dl, MVT::i64,
1326 SDValue(Tmp, 0), GA);
1328 case PPCISD::VADD_SPLAT: {
1329 // This expands into one of three sequences, depending on whether
1330 // the first operand is odd or even, positive or negative.
1331 assert(isa<ConstantSDNode>(N->getOperand(0)) &&
1332 isa<ConstantSDNode>(N->getOperand(1)) &&
1333 "Invalid operand on VADD_SPLAT!");
1335 int Elt = N->getConstantOperandVal(0);
1336 int EltSize = N->getConstantOperandVal(1);
1337 unsigned Opc1, Opc2, Opc3;
1341 Opc1 = PPC::VSPLTISB;
1342 Opc2 = PPC::VADDUBM;
1343 Opc3 = PPC::VSUBUBM;
1345 } else if (EltSize == 2) {
1346 Opc1 = PPC::VSPLTISH;
1347 Opc2 = PPC::VADDUHM;
1348 Opc3 = PPC::VSUBUHM;
1351 assert(EltSize == 4 && "Invalid element size on VADD_SPLAT!");
1352 Opc1 = PPC::VSPLTISW;
1353 Opc2 = PPC::VADDUWM;
1354 Opc3 = PPC::VSUBUWM;
1358 if ((Elt & 1) == 0) {
1359 // Elt is even, in the range [-32,-18] + [16,30].
1361 // Convert: VADD_SPLAT elt, size
1362 // Into: tmp = VSPLTIS[BHW] elt
1363 // VADDU[BHW]M tmp, tmp
1364 // Where: [BHW] = B for size = 1, H for size = 2, W for size = 4
1365 SDValue EltVal = getI32Imm(Elt >> 1);
1366 SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
1367 SDValue TmpVal = SDValue(Tmp, 0);
1368 return CurDAG->getMachineNode(Opc2, dl, VT, TmpVal, TmpVal);
1370 } else if (Elt > 0) {
1371 // Elt is odd and positive, in the range [17,31].
1373 // Convert: VADD_SPLAT elt, size
1374 // Into: tmp1 = VSPLTIS[BHW] elt-16
1375 // tmp2 = VSPLTIS[BHW] -16
1376 // VSUBU[BHW]M tmp1, tmp2
1377 SDValue EltVal = getI32Imm(Elt - 16);
1378 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
1379 EltVal = getI32Imm(-16);
1380 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
1381 return CurDAG->getMachineNode(Opc3, dl, VT, SDValue(Tmp1, 0),
1385 // Elt is odd and negative, in the range [-31,-17].
1387 // Convert: VADD_SPLAT elt, size
1388 // Into: tmp1 = VSPLTIS[BHW] elt+16
1389 // tmp2 = VSPLTIS[BHW] -16
1390 // VADDU[BHW]M tmp1, tmp2
1391 SDValue EltVal = getI32Imm(Elt + 16);
1392 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
1393 EltVal = getI32Imm(-16);
1394 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
1395 return CurDAG->getMachineNode(Opc2, dl, VT, SDValue(Tmp1, 0),
1401 return SelectCode(N);
1404 /// PostProcessISelDAG - Perform some late peephole optimizations
1405 /// on the DAG representation.
1406 void PPCDAGToDAGISel::PostprocessISelDAG() {
1408 // Skip peepholes at -O0.
1409 if (TM.getOptLevel() == CodeGenOpt::None)
1412 // These optimizations are currently supported only for 64-bit SVR4.
1413 if (PPCSubTarget.isDarwin() || !PPCSubTarget.isPPC64())
1416 SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode());
1419 while (Position != CurDAG->allnodes_begin()) {
1420 SDNode *N = --Position;
1421 // Skip dead nodes and any non-machine opcodes.
1422 if (N->use_empty() || !N->isMachineOpcode())
1426 unsigned StorageOpcode = N->getMachineOpcode();
1428 switch (StorageOpcode) {
1459 // If this is a load or store with a zero offset, we may be able to
1460 // fold an add-immediate into the memory operation.
1461 if (!isa<ConstantSDNode>(N->getOperand(FirstOp)) ||
1462 N->getConstantOperandVal(FirstOp) != 0)
1465 SDValue Base = N->getOperand(FirstOp + 1);
1466 if (!Base.isMachineOpcode())
1470 bool ReplaceFlags = true;
1472 // When the feeding operation is an add-immediate of some sort,
1473 // determine whether we need to add relocation information to the
1474 // target flags on the immediate operand when we fold it into the
1475 // load instruction.
1477 // For something like ADDItocL, the relocation information is
1478 // inferred from the opcode; when we process it in the AsmPrinter,
1479 // we add the necessary relocation there. A load, though, can receive
1480 // relocation from various flavors of ADDIxxx, so we need to carry
1481 // the relocation information in the target flags.
1482 switch (Base.getMachineOpcode()) {
1488 // In some cases (such as TLS) the relocation information
1489 // is already in place on the operand, so copying the operand
1491 ReplaceFlags = false;
1492 // For these cases, the immediate may not be divisible by 4, in
1493 // which case the fold is illegal for DS-form instructions. (The
1494 // other cases provide aligned addresses and are always safe.)
1495 if ((StorageOpcode == PPC::LWA ||
1496 StorageOpcode == PPC::LD ||
1497 StorageOpcode == PPC::STD) &&
1498 (!isa<ConstantSDNode>(Base.getOperand(1)) ||
1499 Base.getConstantOperandVal(1) % 4 != 0))
1502 case PPC::ADDIdtprelL:
1503 Flags = PPCII::MO_DTPREL16_LO;
1505 case PPC::ADDItlsldL:
1506 Flags = PPCII::MO_TLSLD16_LO;
1509 Flags = PPCII::MO_TOC16_LO;
1513 // We found an opportunity. Reverse the operands from the add
1514 // immediate and substitute them into the load or store. If
1515 // needed, update the target flags for the immediate operand to
1516 // reflect the necessary relocation information.
1517 DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase: ");
1518 DEBUG(Base->dump(CurDAG));
1519 DEBUG(dbgs() << "\nN: ");
1520 DEBUG(N->dump(CurDAG));
1521 DEBUG(dbgs() << "\n");
1523 SDValue ImmOpnd = Base.getOperand(1);
1525 // If the relocation information isn't already present on the
1526 // immediate operand, add it now.
1528 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) {
1529 DebugLoc dl = GA->getDebugLoc();
1530 const GlobalValue *GV = GA->getGlobal();
1531 ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, 0, Flags);
1532 } else if (ConstantPoolSDNode *CP =
1533 dyn_cast<ConstantPoolSDNode>(ImmOpnd)) {
1534 const Constant *C = CP->getConstVal();
1535 ImmOpnd = CurDAG->getTargetConstantPool(C, MVT::i64,
1541 if (FirstOp == 1) // Store
1542 (void)CurDAG->UpdateNodeOperands(N, N->getOperand(0), ImmOpnd,
1543 Base.getOperand(0), N->getOperand(3));
1545 (void)CurDAG->UpdateNodeOperands(N, ImmOpnd, Base.getOperand(0),
1548 // The add-immediate may now be dead, in which case remove it.
1549 if (Base.getNode()->use_empty())
1550 CurDAG->RemoveDeadNode(Base.getNode());
1555 /// createPPCISelDag - This pass converts a legalized DAG into a
1556 /// PowerPC-specific DAG, ready for instruction scheduling.
1558 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
1559 return new PPCDAGToDAGISel(TM);
1562 static void initializePassOnce(PassRegistry &Registry) {
1563 const char *Name = "PowerPC DAG->DAG Pattern Instruction Selection";
1564 PassInfo *PI = new PassInfo(Name, "ppc-codegen", &SelectionDAGISel::ID, 0,
1566 Registry.registerPass(*PI, true);
1569 void llvm::initializePPCDAGToDAGISelPass(PassRegistry &Registry) {
1570 CALL_ONCE_INITIALIZATION(initializePassOnce);