1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "ppc-codegen"
17 #include "PPCPredicates.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCISelLowering.h"
20 #include "PPCHazardRecognizers.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
39 //===--------------------------------------------------------------------===//
40 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
41 /// instructions for SelectionDAG operations.
43 class PPCDAGToDAGISel : public SelectionDAGISel {
45 PPCTargetLowering &PPCLowering;
46 const PPCSubtarget &PPCSubTarget;
47 unsigned GlobalBaseReg;
49 explicit PPCDAGToDAGISel(PPCTargetMachine &tm)
50 : SelectionDAGISel(tm), TM(tm),
51 PPCLowering(*TM.getTargetLowering()),
52 PPCSubTarget(*TM.getSubtargetImpl()) {}
54 virtual bool runOnMachineFunction(MachineFunction &MF) {
55 // Make sure we re-emit a set of the global base reg if necessary
57 SelectionDAGISel::runOnMachineFunction(MF);
63 /// getI32Imm - Return a target constant with the specified value, of type
65 inline SDValue getI32Imm(unsigned Imm) {
66 return CurDAG->getTargetConstant(Imm, MVT::i32);
69 /// getI64Imm - Return a target constant with the specified value, of type
71 inline SDValue getI64Imm(uint64_t Imm) {
72 return CurDAG->getTargetConstant(Imm, MVT::i64);
75 /// getSmallIPtrImm - Return a target constant of pointer type.
76 inline SDValue getSmallIPtrImm(unsigned Imm) {
77 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy());
80 /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s
81 /// with any number of 0s on either side. The 1s are allowed to wrap from
82 /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs.
83 /// 0x0F0F0000 is not, since all 1s are not contiguous.
84 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME);
87 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
88 /// rotate and mask opcode and mask operation.
89 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask,
90 unsigned &SH, unsigned &MB, unsigned &ME);
92 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
93 /// base register. Return the virtual register that holds this value.
94 SDNode *getGlobalBaseReg();
96 // Select - Convert the specified operand from a target-independent to a
97 // target-specific node if it hasn't already been changed.
98 SDNode *Select(SDNode *N);
100 SDNode *SelectBitfieldInsert(SDNode *N);
102 /// SelectCC - Select a comparison of the specified values with the
103 /// specified condition code, returning the CR# of the expression.
104 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, DebugLoc dl);
106 /// SelectAddrImm - Returns true if the address N can be represented by
107 /// a base register plus a signed 16-bit displacement [r+imm].
108 bool SelectAddrImm(SDNode *Op, SDValue N, SDValue &Disp,
110 return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG);
113 /// SelectAddrImmOffs - Return true if the operand is valid for a preinc
114 /// immediate field. Because preinc imms have already been validated, just
116 bool SelectAddrImmOffs(SDNode *Op, SDValue N, SDValue &Out) const {
121 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
122 /// represented as an indexed [r+r] operation. Returns false if it can
123 /// be represented by [r+imm], which are preferred.
124 bool SelectAddrIdx(SDNode *Op, SDValue N, SDValue &Base,
126 return PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG);
129 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
130 /// represented as an indexed [r+r] operation.
131 bool SelectAddrIdxOnly(SDNode *Op, SDValue N, SDValue &Base,
133 return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
136 /// SelectAddrImmShift - Returns true if the address N can be represented by
137 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
138 /// for use by STD and friends.
139 bool SelectAddrImmShift(SDNode *Op, SDValue N, SDValue &Disp,
141 return PPCLowering.SelectAddressRegImmShift(N, Disp, Base, *CurDAG);
144 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
145 /// inline asm expressions. It is always correct to compute the value into
146 /// a register. The case of adding a (possibly relocatable) constant to a
147 /// register can be improved, but it is wrong to substitute Reg+Reg for
148 /// Reg in an asm, because the load or store opcode would have to change.
149 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
151 std::vector<SDValue> &OutOps) {
152 OutOps.push_back(Op);
156 SDValue BuildSDIVSequence(SDNode *N);
157 SDValue BuildUDIVSequence(SDNode *N);
159 void InsertVRSaveCode(MachineFunction &MF);
161 virtual const char *getPassName() const {
162 return "PowerPC DAG->DAG Pattern Instruction Selection";
165 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
166 /// this target when scheduling the DAG.
167 virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer() {
168 // Should use subtarget info to pick the right hazard recognizer. For
169 // now, always return a PPC970 recognizer.
170 const TargetInstrInfo *II = TM.getInstrInfo();
171 assert(II && "No InstrInfo?");
172 return new PPCHazardRecognizer970(*II);
175 // Include the pieces autogenerated from the target description.
176 #include "PPCGenDAGISel.inc"
179 SDNode *SelectSETCC(SDNode *N);
183 /// InsertVRSaveCode - Once the entire function has been instruction selected,
184 /// all virtual registers are created and all machine instructions are built,
185 /// check to see if we need to save/restore VRSAVE. If so, do it.
186 void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) {
187 // Check to see if this function uses vector registers, which means we have to
188 // save and restore the VRSAVE register and update it with the regs we use.
190 // In this case, there will be virtual registers of vector type created
191 // by the scheduler. Detect them now.
192 bool HasVectorVReg = false;
193 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
194 e = RegInfo->getLastVirtReg()+1; i != e; ++i)
195 if (RegInfo->getRegClass(i) == &PPC::VRRCRegClass) {
196 HasVectorVReg = true;
199 if (!HasVectorVReg) return; // nothing to do.
201 // If we have a vector register, we want to emit code into the entry and exit
202 // blocks to save and restore the VRSAVE register. We do this here (instead
203 // of marking all vector instructions as clobbering VRSAVE) for two reasons:
205 // 1. This (trivially) reduces the load on the register allocator, by not
206 // having to represent the live range of the VRSAVE register.
207 // 2. This (more significantly) allows us to create a temporary virtual
208 // register to hold the saved VRSAVE value, allowing this temporary to be
209 // register allocated, instead of forcing it to be spilled to the stack.
211 // Create two vregs - one to hold the VRSAVE register that is live-in to the
212 // function and one for the value after having bits or'd into it.
213 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
214 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
216 const TargetInstrInfo &TII = *TM.getInstrInfo();
217 MachineBasicBlock &EntryBB = *Fn.begin();
219 // Emit the following code into the entry block:
220 // InVRSAVE = MFVRSAVE
221 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
222 // MTVRSAVE UpdatedVRSAVE
223 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
224 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE);
225 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE),
226 UpdatedVRSAVE).addReg(InVRSAVE);
227 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
229 // Find all return blocks, outputting a restore in each epilog.
230 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
231 if (!BB->empty() && BB->back().getDesc().isReturn()) {
232 IP = BB->end(); --IP;
234 // Skip over all terminator instructions, which are part of the return
236 MachineBasicBlock::iterator I2 = IP;
237 while (I2 != BB->begin() && (--I2)->getDesc().isTerminator())
240 // Emit: MTVRSAVE InVRSave
241 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
247 /// getGlobalBaseReg - Output the instructions required to put the
248 /// base address to use for accessing globals into a register.
250 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
251 if (!GlobalBaseReg) {
252 const TargetInstrInfo &TII = *TM.getInstrInfo();
253 // Insert the set of GlobalBaseReg into the first MBB of the function
254 MachineBasicBlock &FirstMBB = MF->front();
255 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
258 if (PPCLowering.getPointerTy() == MVT::i32) {
259 GlobalBaseReg = RegInfo->createVirtualRegister(PPC::GPRCRegisterClass);
260 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR), PPC::LR);
261 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
263 GlobalBaseReg = RegInfo->createVirtualRegister(PPC::G8RCRegisterClass);
264 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8), PPC::LR8);
265 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg);
268 return CurDAG->getRegister(GlobalBaseReg,
269 PPCLowering.getPointerTy()).getNode();
272 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
273 /// or 64-bit immediate, and if the value can be accurately represented as a
274 /// sign extension from a 16-bit value. If so, this returns true and the
276 static bool isIntS16Immediate(SDNode *N, short &Imm) {
277 if (N->getOpcode() != ISD::Constant)
280 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
281 if (N->getValueType(0) == MVT::i32)
282 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
284 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
287 static bool isIntS16Immediate(SDValue Op, short &Imm) {
288 return isIntS16Immediate(Op.getNode(), Imm);
292 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
293 /// operand. If so Imm will receive the 32-bit value.
294 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
295 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
296 Imm = cast<ConstantSDNode>(N)->getZExtValue();
302 /// isInt64Immediate - This method tests to see if the node is a 64-bit constant
303 /// operand. If so Imm will receive the 64-bit value.
304 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
305 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
306 Imm = cast<ConstantSDNode>(N)->getZExtValue();
312 // isInt32Immediate - This method tests to see if a constant operand.
313 // If so Imm will receive the 32 bit value.
314 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
315 return isInt32Immediate(N.getNode(), Imm);
319 // isOpcWithIntImmediate - This method tests to see if the node is a specific
320 // opcode and that it has a immediate integer right operand.
321 // If so Imm will receive the 32 bit value.
322 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
323 return N->getOpcode() == Opc
324 && isInt32Immediate(N->getOperand(1).getNode(), Imm);
327 bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
328 if (isShiftedMask_32(Val)) {
329 // look for the first non-zero bit
330 MB = CountLeadingZeros_32(Val);
331 // look for the first zero bit after the run of ones
332 ME = CountLeadingZeros_32((Val - 1) ^ Val);
335 Val = ~Val; // invert mask
336 if (isShiftedMask_32(Val)) {
337 // effectively look for the first zero bit
338 ME = CountLeadingZeros_32(Val) - 1;
339 // effectively look for the first one bit after the run of zeros
340 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
348 bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
349 bool isShiftMask, unsigned &SH,
350 unsigned &MB, unsigned &ME) {
351 // Don't even go down this path for i64, since different logic will be
352 // necessary for rldicl/rldicr/rldimi.
353 if (N->getValueType(0) != MVT::i32)
357 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
358 unsigned Opcode = N->getOpcode();
359 if (N->getNumOperands() != 2 ||
360 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31))
363 if (Opcode == ISD::SHL) {
364 // apply shift left to mask if it comes first
365 if (isShiftMask) Mask = Mask << Shift;
366 // determine which bits are made indeterminant by shift
367 Indeterminant = ~(0xFFFFFFFFu << Shift);
368 } else if (Opcode == ISD::SRL) {
369 // apply shift right to mask if it comes first
370 if (isShiftMask) Mask = Mask >> Shift;
371 // determine which bits are made indeterminant by shift
372 Indeterminant = ~(0xFFFFFFFFu >> Shift);
373 // adjust for the left rotate
375 } else if (Opcode == ISD::ROTL) {
381 // if the mask doesn't intersect any Indeterminant bits
382 if (Mask && !(Mask & Indeterminant)) {
384 // make sure the mask is still a mask (wrap arounds may not be)
385 return isRunOfOnes(Mask, MB, ME);
390 /// SelectBitfieldInsert - turn an or of two masked values into
391 /// the rotate left word immediate then mask insert (rlwimi) instruction.
392 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
393 SDValue Op0 = N->getOperand(0);
394 SDValue Op1 = N->getOperand(1);
395 DebugLoc dl = N->getDebugLoc();
397 APInt LKZ, LKO, RKZ, RKO;
398 CurDAG->ComputeMaskedBits(Op0, APInt::getAllOnesValue(32), LKZ, LKO);
399 CurDAG->ComputeMaskedBits(Op1, APInt::getAllOnesValue(32), RKZ, RKO);
401 unsigned TargetMask = LKZ.getZExtValue();
402 unsigned InsertMask = RKZ.getZExtValue();
404 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
405 unsigned Op0Opc = Op0.getOpcode();
406 unsigned Op1Opc = Op1.getOpcode();
407 unsigned Value, SH = 0;
408 TargetMask = ~TargetMask;
409 InsertMask = ~InsertMask;
411 // If the LHS has a foldable shift and the RHS does not, then swap it to the
412 // RHS so that we can fold the shift into the insert.
413 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
414 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
415 Op0.getOperand(0).getOpcode() == ISD::SRL) {
416 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
417 Op1.getOperand(0).getOpcode() != ISD::SRL) {
419 std::swap(Op0Opc, Op1Opc);
420 std::swap(TargetMask, InsertMask);
423 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
424 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
425 Op1.getOperand(0).getOpcode() != ISD::SRL) {
427 std::swap(Op0Opc, Op1Opc);
428 std::swap(TargetMask, InsertMask);
433 if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) {
436 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
437 isInt32Immediate(Op1.getOperand(1), Value)) {
438 Op1 = Op1.getOperand(0);
439 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
441 if (Op1Opc == ISD::AND) {
442 unsigned SHOpc = Op1.getOperand(0).getOpcode();
443 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) &&
444 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
445 Op1 = Op1.getOperand(0).getOperand(0);
446 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
448 Op1 = Op1.getOperand(0);
453 SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB),
455 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
461 /// SelectCC - Select a comparison of the specified values with the specified
462 /// condition code, returning the CR# of the expression.
463 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
464 ISD::CondCode CC, DebugLoc dl) {
465 // Always select the LHS.
468 if (LHS.getValueType() == MVT::i32) {
470 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
471 if (isInt32Immediate(RHS, Imm)) {
472 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
474 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
475 getI32Imm(Imm & 0xFFFF)), 0);
476 // If this is a 16-bit signed immediate, fold it.
477 if (isInt<16>((int)Imm))
478 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
479 getI32Imm(Imm & 0xFFFF)), 0);
481 // For non-equality comparisons, the default code would materialize the
482 // constant, then compare against it, like this:
486 // Since we are just comparing for equality, we can emit this instead:
487 // xoris r0,r3,0x1234
488 // cmplwi cr0,r0,0x5678
490 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS,
491 getI32Imm(Imm >> 16)), 0);
492 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor,
493 getI32Imm(Imm & 0xFFFF)), 0);
496 } else if (ISD::isUnsignedIntSetCC(CC)) {
497 if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm))
498 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
499 getI32Imm(Imm & 0xFFFF)), 0);
503 if (isIntS16Immediate(RHS, SImm))
504 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
505 getI32Imm((int)SImm & 0xFFFF)),
509 } else if (LHS.getValueType() == MVT::i64) {
511 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
512 if (isInt64Immediate(RHS.getNode(), Imm)) {
513 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
515 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
516 getI32Imm(Imm & 0xFFFF)), 0);
517 // If this is a 16-bit signed immediate, fold it.
519 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
520 getI32Imm(Imm & 0xFFFF)), 0);
522 // For non-equality comparisons, the default code would materialize the
523 // constant, then compare against it, like this:
527 // Since we are just comparing for equality, we can emit this instead:
528 // xoris r0,r3,0x1234
529 // cmpldi cr0,r0,0x5678
531 if (isUInt<32>(Imm)) {
532 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS,
533 getI64Imm(Imm >> 16)), 0);
534 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor,
535 getI64Imm(Imm & 0xFFFF)), 0);
539 } else if (ISD::isUnsignedIntSetCC(CC)) {
540 if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm))
541 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
542 getI64Imm(Imm & 0xFFFF)), 0);
546 if (isIntS16Immediate(RHS, SImm))
547 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
548 getI64Imm(SImm & 0xFFFF)),
552 } else if (LHS.getValueType() == MVT::f32) {
555 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
558 return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0);
561 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
567 llvm_unreachable("Should be lowered by legalize!");
568 default: llvm_unreachable("Unknown condition!");
570 case ISD::SETEQ: return PPC::PRED_EQ;
572 case ISD::SETNE: return PPC::PRED_NE;
574 case ISD::SETLT: return PPC::PRED_LT;
576 case ISD::SETLE: return PPC::PRED_LE;
578 case ISD::SETGT: return PPC::PRED_GT;
580 case ISD::SETGE: return PPC::PRED_GE;
581 case ISD::SETO: return PPC::PRED_NU;
582 case ISD::SETUO: return PPC::PRED_UN;
583 // These two are invalid for floating point. Assume we have int.
584 case ISD::SETULT: return PPC::PRED_LT;
585 case ISD::SETUGT: return PPC::PRED_GT;
589 /// getCRIdxForSetCC - Return the index of the condition register field
590 /// associated with the SetCC condition, and whether or not the field is
591 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
593 /// If this returns with Other != -1, then the returned comparison is an or of
594 /// two simpler comparisons. In this case, Invert is guaranteed to be false.
595 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) {
599 default: llvm_unreachable("Unknown condition!");
601 case ISD::SETLT: return 0; // Bit #0 = SETOLT
603 case ISD::SETGT: return 1; // Bit #1 = SETOGT
605 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ
606 case ISD::SETUO: return 3; // Bit #3 = SETUO
608 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
610 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE
612 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE
613 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO
618 llvm_unreachable("Invalid branch code: should be expanded by legalize");
619 // These are invalid for floating point. Assume integer.
620 case ISD::SETULT: return 0;
621 case ISD::SETUGT: return 1;
626 SDNode *PPCDAGToDAGISel::SelectSETCC(SDNode *N) {
627 DebugLoc dl = N->getDebugLoc();
629 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
630 if (isInt32Immediate(N->getOperand(1), Imm)) {
631 // We can codegen setcc op, imm very efficiently compared to a brcond.
632 // Check for those cases here.
635 SDValue Op = N->getOperand(0);
639 Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
640 SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
641 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
645 SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
646 Op, getI32Imm(~0U)), 0);
647 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
651 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
652 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
656 SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0);
657 T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0);
658 SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
659 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
662 } else if (Imm == ~0U) { // setcc op, -1
663 SDValue Op = N->getOperand(0);
667 Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
668 Op, getI32Imm(1)), 0);
669 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
670 SDValue(CurDAG->getMachineNode(PPC::LI, dl,
675 Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0);
676 SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
678 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0),
682 SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op,
684 SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD,
686 SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
687 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
690 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
691 Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4),
693 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
702 unsigned Idx = getCRIdxForSetCC(CC, Inv, OtherCondIdx);
703 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
706 // Force the ccreg into CR7.
707 SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
709 SDValue InFlag(0, 0); // Null incoming flag value.
710 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg,
713 if (PPCSubTarget.isGigaProcessor() && OtherCondIdx == -1)
714 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
717 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFCR, dl, MVT::i32, CCReg), 0);
719 SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
720 getI32Imm(31), getI32Imm(31) };
721 if (OtherCondIdx == -1 && !Inv)
722 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
724 // Get the specified bit.
726 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0);
728 assert(OtherCondIdx == -1 && "Can't have split plus negation");
729 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
732 // Otherwise, we have to turn an operation like SETONE -> SETOLT | SETOGT.
733 // We already got the bit for the first part of the comparison (e.g. SETULE).
735 // Get the other bit of the comparison.
736 Ops[1] = getI32Imm((32-(3-OtherCondIdx)) & 31);
738 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0);
740 return CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Tmp, OtherCond);
744 // Select - Convert the specified operand from a target-independent to a
745 // target-specific node if it hasn't already been changed.
746 SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
747 DebugLoc dl = N->getDebugLoc();
748 if (N->isMachineOpcode())
749 return NULL; // Already selected.
751 switch (N->getOpcode()) {
754 case ISD::Constant: {
755 if (N->getValueType(0) == MVT::i64) {
757 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
758 // Assume no remaining bits.
759 unsigned Remainder = 0;
760 // Assume no shift required.
763 // If it can't be represented as a 32 bit value.
764 if (!isInt<32>(Imm)) {
765 Shift = CountTrailingZeros_64(Imm);
766 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
768 // If the shifted value fits 32 bits.
769 if (isInt<32>(ImmSh)) {
770 // Go with the shifted value.
773 // Still stuck with a 64 bit value.
780 // Intermediate operand.
783 // Handle first 32 bits.
784 unsigned Lo = Imm & 0xFFFF;
785 unsigned Hi = (Imm >> 16) & 0xFFFF;
788 if (isInt<16>(Imm)) {
790 Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo));
792 // Handle the Hi bits.
793 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
794 Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi));
796 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
797 SDValue(Result, 0), getI32Imm(Lo));
800 Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
803 // If no shift, we're done.
804 if (!Shift) return Result;
806 // Shift for next step if the upper 32-bits were not zero.
808 Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64,
811 getI32Imm(63 - Shift));
814 // Add in the last bits as required.
815 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
816 Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64,
817 SDValue(Result, 0), getI32Imm(Hi));
819 if ((Lo = Remainder & 0xFFFF)) {
820 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
821 SDValue(Result, 0), getI32Imm(Lo));
830 return SelectSETCC(N);
831 case PPCISD::GlobalBaseReg:
832 return getGlobalBaseReg();
834 case ISD::FrameIndex: {
835 int FI = cast<FrameIndexSDNode>(N)->getIndex();
836 SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
837 unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
839 return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), TFI,
841 return CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI,
846 SDValue InFlag = N->getOperand(1);
847 // Use MFOCRF if supported.
848 if (PPCSubTarget.isGigaProcessor())
849 return CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32,
850 N->getOperand(0), InFlag);
852 return CurDAG->getMachineNode(PPC::MFCR, dl, MVT::i32, InFlag);
856 // FIXME: since this depends on the setting of the carry flag from the srawi
857 // we should really be making notes about that for the scheduler.
858 // FIXME: It sure would be nice if we could cheaply recognize the
859 // srl/add/sra pattern the dag combiner will generate for this as
860 // sra/addze rather than having to handle sdiv ourselves. oh well.
862 if (isInt32Immediate(N->getOperand(1), Imm)) {
863 SDValue N0 = N->getOperand(0);
864 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
866 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Flag,
867 N0, getI32Imm(Log2_32(Imm)));
868 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
869 SDValue(Op, 0), SDValue(Op, 1));
870 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
872 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Flag,
873 N0, getI32Imm(Log2_32(-Imm)));
875 SDValue(CurDAG->getMachineNode(PPC::ADDZE, dl, MVT::i32,
876 SDValue(Op, 0), SDValue(Op, 1)),
878 return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
882 // Other cases are autogenerated.
887 // Handle preincrement loads.
888 LoadSDNode *LD = cast<LoadSDNode>(N);
889 EVT LoadedVT = LD->getMemoryVT();
891 // Normal loads are handled by code generated from the .td file.
892 if (LD->getAddressingMode() != ISD::PRE_INC)
895 SDValue Offset = LD->getOffset();
896 if (isa<ConstantSDNode>(Offset) ||
897 Offset.getOpcode() == ISD::TargetGlobalAddress) {
900 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
901 if (LD->getValueType(0) != MVT::i64) {
902 // Handle PPC32 integer and normal FP loads.
903 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
904 switch (LoadedVT.getSimpleVT().SimpleTy) {
905 default: llvm_unreachable("Invalid PPC load type!");
906 case MVT::f64: Opcode = PPC::LFDU; break;
907 case MVT::f32: Opcode = PPC::LFSU; break;
908 case MVT::i32: Opcode = PPC::LWZU; break;
909 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
911 case MVT::i8: Opcode = PPC::LBZU; break;
914 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
915 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
916 switch (LoadedVT.getSimpleVT().SimpleTy) {
917 default: llvm_unreachable("Invalid PPC load type!");
918 case MVT::i64: Opcode = PPC::LDU; break;
919 case MVT::i32: Opcode = PPC::LWZU8; break;
920 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
922 case MVT::i8: Opcode = PPC::LBZU8; break;
926 SDValue Chain = LD->getChain();
927 SDValue Base = LD->getBasePtr();
928 SDValue Ops[] = { Offset, Base, Chain };
930 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
931 PPCLowering.getPointerTy(),
934 llvm_unreachable("R+R preindex loads not supported yet!");
939 unsigned Imm, Imm2, SH, MB, ME;
941 // If this is an and of a value rotated between 0 and 31 bits and then and'd
942 // with a mask, emit rlwinm
943 if (isInt32Immediate(N->getOperand(1), Imm) &&
944 isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) {
945 SDValue Val = N->getOperand(0).getOperand(0);
946 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
947 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
949 // If this is just a masked value where the input is not handled above, and
950 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
951 if (isInt32Immediate(N->getOperand(1), Imm) &&
952 isRunOfOnes(Imm, MB, ME) &&
953 N->getOperand(0).getOpcode() != ISD::ROTL) {
954 SDValue Val = N->getOperand(0);
955 SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
956 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
958 // AND X, 0 -> 0, not "rlwinm 32".
959 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
960 ReplaceUses(SDValue(N, 0), N->getOperand(1));
963 // ISD::OR doesn't get all the bitfield insertion fun.
964 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
965 if (isInt32Immediate(N->getOperand(1), Imm) &&
966 N->getOperand(0).getOpcode() == ISD::OR &&
967 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
970 if (isRunOfOnes(Imm, MB, ME)) {
971 SDValue Ops[] = { N->getOperand(0).getOperand(0),
972 N->getOperand(0).getOperand(1),
973 getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
974 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
978 // Other cases are autogenerated.
982 if (N->getValueType(0) == MVT::i32)
983 if (SDNode *I = SelectBitfieldInsert(N))
986 // Other cases are autogenerated.
989 unsigned Imm, SH, MB, ME;
990 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
991 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
992 SDValue Ops[] = { N->getOperand(0).getOperand(0),
993 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
994 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
997 // Other cases are autogenerated.
1001 unsigned Imm, SH, MB, ME;
1002 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
1003 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1004 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1005 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1006 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
1009 // Other cases are autogenerated.
1012 case ISD::SELECT_CC: {
1013 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1015 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
1016 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1017 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1018 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1019 if (N1C->isNullValue() && N3C->isNullValue() &&
1020 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
1021 // FIXME: Implement this optzn for PPC64.
1022 N->getValueType(0) == MVT::i32) {
1024 CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
1025 N->getOperand(0), getI32Imm(~0U));
1026 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
1027 SDValue(Tmp, 0), N->getOperand(0),
1031 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
1032 unsigned BROpc = getPredicateForSetCC(CC);
1034 unsigned SelectCCOp;
1035 if (N->getValueType(0) == MVT::i32)
1036 SelectCCOp = PPC::SELECT_CC_I4;
1037 else if (N->getValueType(0) == MVT::i64)
1038 SelectCCOp = PPC::SELECT_CC_I8;
1039 else if (N->getValueType(0) == MVT::f32)
1040 SelectCCOp = PPC::SELECT_CC_F4;
1041 else if (N->getValueType(0) == MVT::f64)
1042 SelectCCOp = PPC::SELECT_CC_F8;
1044 SelectCCOp = PPC::SELECT_CC_VRRC;
1046 SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
1048 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4);
1050 case PPCISD::COND_BRANCH: {
1051 // Op #0 is the Chain.
1052 // Op #1 is the PPC::PRED_* number.
1054 // Op #3 is the Dest MBB
1055 // Op #4 is the Flag.
1056 // Prevent PPC::PRED_* from being selected into LI.
1058 getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue());
1059 SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
1060 N->getOperand(0), N->getOperand(4) };
1061 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5);
1064 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
1065 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
1066 SDValue Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode,
1067 N->getOperand(4), N->getOperand(0) };
1068 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4);
1071 // FIXME: Should custom lower this.
1072 SDValue Chain = N->getOperand(0);
1073 SDValue Target = N->getOperand(1);
1074 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
1075 Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Target,
1077 return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain);
1081 return SelectCode(N);
1086 /// createPPCISelDag - This pass converts a legalized DAG into a
1087 /// PowerPC-specific DAG, ready for instruction scheduling.
1089 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
1090 return new PPCDAGToDAGISel(TM);