1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "ppc-codegen"
17 #include "PPCPredicates.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCISelLowering.h"
20 #include "PPCHazardRecognizers.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/SelectionDAGISel.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Constants.h"
28 #include "llvm/GlobalValue.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Support/Compiler.h"
36 //===--------------------------------------------------------------------===//
37 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
38 /// instructions for SelectionDAG operations.
40 class VISIBILITY_HIDDEN PPCDAGToDAGISel : public SelectionDAGISel {
42 PPCTargetLowering &PPCLowering;
43 const PPCSubtarget &PPCSubTarget;
44 unsigned GlobalBaseReg;
46 explicit PPCDAGToDAGISel(PPCTargetMachine &tm)
47 : SelectionDAGISel(tm), TM(tm),
48 PPCLowering(*TM.getTargetLowering()),
49 PPCSubTarget(*TM.getSubtargetImpl()) {}
51 virtual bool runOnFunction(Function &Fn) {
52 // Make sure we re-emit a set of the global base reg if necessary
54 SelectionDAGISel::runOnFunction(Fn);
60 /// getI32Imm - Return a target constant with the specified value, of type
62 inline SDValue getI32Imm(unsigned Imm) {
63 return CurDAG->getTargetConstant(Imm, MVT::i32);
66 /// getI64Imm - Return a target constant with the specified value, of type
68 inline SDValue getI64Imm(uint64_t Imm) {
69 return CurDAG->getTargetConstant(Imm, MVT::i64);
72 /// getSmallIPtrImm - Return a target constant of pointer type.
73 inline SDValue getSmallIPtrImm(unsigned Imm) {
74 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy());
77 /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s
78 /// with any number of 0s on either side. The 1s are allowed to wrap from
79 /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs.
80 /// 0x0F0F0000 is not, since all 1s are not contiguous.
81 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME);
84 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
85 /// rotate and mask opcode and mask operation.
86 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
87 unsigned &SH, unsigned &MB, unsigned &ME);
89 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
90 /// base register. Return the virtual register that holds this value.
91 SDNode *getGlobalBaseReg();
93 // Select - Convert the specified operand from a target-independent to a
94 // target-specific node if it hasn't already been changed.
95 SDNode *Select(SDValue Op);
97 SDNode *SelectBitfieldInsert(SDNode *N);
99 /// SelectCC - Select a comparison of the specified values with the
100 /// specified condition code, returning the CR# of the expression.
101 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, DebugLoc dl);
103 /// SelectAddrImm - Returns true if the address N can be represented by
104 /// a base register plus a signed 16-bit displacement [r+imm].
105 bool SelectAddrImm(SDValue Op, SDValue N, SDValue &Disp,
107 return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG);
110 /// SelectAddrImmOffs - Return true if the operand is valid for a preinc
111 /// immediate field. Because preinc imms have already been validated, just
113 bool SelectAddrImmOffs(SDValue Op, SDValue N, SDValue &Out) const {
118 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
119 /// represented as an indexed [r+r] operation. Returns false if it can
120 /// be represented by [r+imm], which are preferred.
121 bool SelectAddrIdx(SDValue Op, SDValue N, SDValue &Base,
123 return PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG);
126 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
127 /// represented as an indexed [r+r] operation.
128 bool SelectAddrIdxOnly(SDValue Op, SDValue N, SDValue &Base,
130 return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
133 /// SelectAddrImmShift - Returns true if the address N can be represented by
134 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
135 /// for use by STD and friends.
136 bool SelectAddrImmShift(SDValue Op, SDValue N, SDValue &Disp,
138 return PPCLowering.SelectAddressRegImmShift(N, Disp, Base, *CurDAG);
141 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
142 /// inline asm expressions.
143 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
145 std::vector<SDValue> &OutOps) {
147 switch (ConstraintCode) {
148 default: return true;
150 if (!SelectAddrIdx(Op, Op, Op0, Op1))
151 SelectAddrImm(Op, Op, Op0, Op1);
153 case 'o': // offsetable
154 if (!SelectAddrImm(Op, Op, Op0, Op1)) {
156 Op1 = getSmallIPtrImm(0);
159 case 'v': // not offsetable
160 SelectAddrIdxOnly(Op, Op, Op0, Op1);
164 OutOps.push_back(Op0);
165 OutOps.push_back(Op1);
169 SDValue BuildSDIVSequence(SDNode *N);
170 SDValue BuildUDIVSequence(SDNode *N);
172 /// InstructionSelect - This callback is invoked by
173 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
174 virtual void InstructionSelect();
176 void InsertVRSaveCode(Function &Fn);
178 virtual const char *getPassName() const {
179 return "PowerPC DAG->DAG Pattern Instruction Selection";
182 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
183 /// this target when scheduling the DAG.
184 virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer() {
185 // Should use subtarget info to pick the right hazard recognizer. For
186 // now, always return a PPC970 recognizer.
187 const TargetInstrInfo *II = TM.getInstrInfo();
188 assert(II && "No InstrInfo?");
189 return new PPCHazardRecognizer970(*II);
192 // Include the pieces autogenerated from the target description.
193 #include "PPCGenDAGISel.inc"
196 SDNode *SelectSETCC(SDValue Op);
200 /// InstructionSelect - This callback is invoked by
201 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
202 void PPCDAGToDAGISel::InstructionSelect() {
205 // Select target instructions for the DAG.
207 CurDAG->RemoveDeadNodes();
210 /// InsertVRSaveCode - Once the entire function has been instruction selected,
211 /// all virtual registers are created and all machine instructions are built,
212 /// check to see if we need to save/restore VRSAVE. If so, do it.
213 void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) {
214 // Check to see if this function uses vector registers, which means we have to
215 // save and restore the VRSAVE register and update it with the regs we use.
217 // In this case, there will be virtual registers of vector type type created
218 // by the scheduler. Detect them now.
219 MachineFunction &Fn = MachineFunction::get(&F);
220 bool HasVectorVReg = false;
221 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
222 e = RegInfo->getLastVirtReg()+1; i != e; ++i)
223 if (RegInfo->getRegClass(i) == &PPC::VRRCRegClass) {
224 HasVectorVReg = true;
227 if (!HasVectorVReg) return; // nothing to do.
229 // If we have a vector register, we want to emit code into the entry and exit
230 // blocks to save and restore the VRSAVE register. We do this here (instead
231 // of marking all vector instructions as clobbering VRSAVE) for two reasons:
233 // 1. This (trivially) reduces the load on the register allocator, by not
234 // having to represent the live range of the VRSAVE register.
235 // 2. This (more significantly) allows us to create a temporary virtual
236 // register to hold the saved VRSAVE value, allowing this temporary to be
237 // register allocated, instead of forcing it to be spilled to the stack.
239 // Create two vregs - one to hold the VRSAVE register that is live-in to the
240 // function and one for the value after having bits or'd into it.
241 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
242 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
244 const TargetInstrInfo &TII = *TM.getInstrInfo();
245 MachineBasicBlock &EntryBB = *Fn.begin();
246 DebugLoc dl = DebugLoc::getUnknownLoc();
247 // Emit the following code into the entry block:
248 // InVRSAVE = MFVRSAVE
249 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
250 // MTVRSAVE UpdatedVRSAVE
251 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
252 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE);
253 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE),
254 UpdatedVRSAVE).addReg(InVRSAVE);
255 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
257 // Find all return blocks, outputting a restore in each epilog.
258 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
259 if (!BB->empty() && BB->back().getDesc().isReturn()) {
260 IP = BB->end(); --IP;
262 // Skip over all terminator instructions, which are part of the return
264 MachineBasicBlock::iterator I2 = IP;
265 while (I2 != BB->begin() && (--I2)->getDesc().isTerminator())
268 // Emit: MTVRSAVE InVRSave
269 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
275 /// getGlobalBaseReg - Output the instructions required to put the
276 /// base address to use for accessing globals into a register.
278 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
279 if (!GlobalBaseReg) {
280 const TargetInstrInfo &TII = *TM.getInstrInfo();
281 // Insert the set of GlobalBaseReg into the first MBB of the function
282 MachineBasicBlock &FirstMBB = BB->getParent()->front();
283 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
284 DebugLoc dl = DebugLoc::getUnknownLoc();
286 if (PPCLowering.getPointerTy() == MVT::i32) {
287 GlobalBaseReg = RegInfo->createVirtualRegister(PPC::GPRCRegisterClass);
288 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR), PPC::LR);
289 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
291 GlobalBaseReg = RegInfo->createVirtualRegister(PPC::G8RCRegisterClass);
292 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8), PPC::LR8);
293 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg);
296 return CurDAG->getRegister(GlobalBaseReg,
297 PPCLowering.getPointerTy()).getNode();
300 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
301 /// or 64-bit immediate, and if the value can be accurately represented as a
302 /// sign extension from a 16-bit value. If so, this returns true and the
304 static bool isIntS16Immediate(SDNode *N, short &Imm) {
305 if (N->getOpcode() != ISD::Constant)
308 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
309 if (N->getValueType(0) == MVT::i32)
310 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
312 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
315 static bool isIntS16Immediate(SDValue Op, short &Imm) {
316 return isIntS16Immediate(Op.getNode(), Imm);
320 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
321 /// operand. If so Imm will receive the 32-bit value.
322 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
323 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
324 Imm = cast<ConstantSDNode>(N)->getZExtValue();
330 /// isInt64Immediate - This method tests to see if the node is a 64-bit constant
331 /// operand. If so Imm will receive the 64-bit value.
332 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
333 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
334 Imm = cast<ConstantSDNode>(N)->getZExtValue();
340 // isInt32Immediate - This method tests to see if a constant operand.
341 // If so Imm will receive the 32 bit value.
342 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
343 return isInt32Immediate(N.getNode(), Imm);
347 // isOpcWithIntImmediate - This method tests to see if the node is a specific
348 // opcode and that it has a immediate integer right operand.
349 // If so Imm will receive the 32 bit value.
350 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
351 return N->getOpcode() == Opc
352 && isInt32Immediate(N->getOperand(1).getNode(), Imm);
355 bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
356 if (isShiftedMask_32(Val)) {
357 // look for the first non-zero bit
358 MB = CountLeadingZeros_32(Val);
359 // look for the first zero bit after the run of ones
360 ME = CountLeadingZeros_32((Val - 1) ^ Val);
363 Val = ~Val; // invert mask
364 if (isShiftedMask_32(Val)) {
365 // effectively look for the first zero bit
366 ME = CountLeadingZeros_32(Val) - 1;
367 // effectively look for the first one bit after the run of zeros
368 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
376 bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
377 bool IsShiftMask, unsigned &SH,
378 unsigned &MB, unsigned &ME) {
379 // Don't even go down this path for i64, since different logic will be
380 // necessary for rldicl/rldicr/rldimi.
381 if (N->getValueType(0) != MVT::i32)
385 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
386 unsigned Opcode = N->getOpcode();
387 if (N->getNumOperands() != 2 ||
388 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31))
391 if (Opcode == ISD::SHL) {
392 // apply shift left to mask if it comes first
393 if (IsShiftMask) Mask = Mask << Shift;
394 // determine which bits are made indeterminant by shift
395 Indeterminant = ~(0xFFFFFFFFu << Shift);
396 } else if (Opcode == ISD::SRL) {
397 // apply shift right to mask if it comes first
398 if (IsShiftMask) Mask = Mask >> Shift;
399 // determine which bits are made indeterminant by shift
400 Indeterminant = ~(0xFFFFFFFFu >> Shift);
401 // adjust for the left rotate
403 } else if (Opcode == ISD::ROTL) {
409 // if the mask doesn't intersect any Indeterminant bits
410 if (Mask && !(Mask & Indeterminant)) {
412 // make sure the mask is still a mask (wrap arounds may not be)
413 return isRunOfOnes(Mask, MB, ME);
418 /// SelectBitfieldInsert - turn an or of two masked values into
419 /// the rotate left word immediate then mask insert (rlwimi) instruction.
420 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
421 SDValue Op0 = N->getOperand(0);
422 SDValue Op1 = N->getOperand(1);
423 DebugLoc dl = N->getDebugLoc();
425 APInt LKZ, LKO, RKZ, RKO;
426 CurDAG->ComputeMaskedBits(Op0, APInt::getAllOnesValue(32), LKZ, LKO);
427 CurDAG->ComputeMaskedBits(Op1, APInt::getAllOnesValue(32), RKZ, RKO);
429 unsigned TargetMask = LKZ.getZExtValue();
430 unsigned InsertMask = RKZ.getZExtValue();
432 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
433 unsigned Op0Opc = Op0.getOpcode();
434 unsigned Op1Opc = Op1.getOpcode();
435 unsigned Value, SH = 0;
436 TargetMask = ~TargetMask;
437 InsertMask = ~InsertMask;
439 // If the LHS has a foldable shift and the RHS does not, then swap it to the
440 // RHS so that we can fold the shift into the insert.
441 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
442 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
443 Op0.getOperand(0).getOpcode() == ISD::SRL) {
444 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
445 Op1.getOperand(0).getOpcode() != ISD::SRL) {
447 std::swap(Op0Opc, Op1Opc);
448 std::swap(TargetMask, InsertMask);
451 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
452 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
453 Op1.getOperand(0).getOpcode() != ISD::SRL) {
455 std::swap(Op0Opc, Op1Opc);
456 std::swap(TargetMask, InsertMask);
461 if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) {
462 SDValue Tmp1, Tmp2, Tmp3;
463 bool DisjointMask = (TargetMask ^ InsertMask) == 0xFFFFFFFF;
465 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
466 isInt32Immediate(Op1.getOperand(1), Value)) {
467 Op1 = Op1.getOperand(0);
468 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
470 if (Op1Opc == ISD::AND) {
471 unsigned SHOpc = Op1.getOperand(0).getOpcode();
472 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) &&
473 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
474 Op1 = Op1.getOperand(0).getOperand(0);
475 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
477 Op1 = Op1.getOperand(0);
481 Tmp3 = (Op0Opc == ISD::AND && DisjointMask) ? Op0.getOperand(0) : Op0;
483 SDValue Ops[] = { Tmp3, Op1, getI32Imm(SH), getI32Imm(MB),
485 return CurDAG->getTargetNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
491 /// SelectCC - Select a comparison of the specified values with the specified
492 /// condition code, returning the CR# of the expression.
493 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
494 ISD::CondCode CC, DebugLoc dl) {
495 // Always select the LHS.
498 if (LHS.getValueType() == MVT::i32) {
500 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
501 if (isInt32Immediate(RHS, Imm)) {
502 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
504 return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, LHS,
505 getI32Imm(Imm & 0xFFFF)), 0);
506 // If this is a 16-bit signed immediate, fold it.
507 if (isInt16((int)Imm))
508 return SDValue(CurDAG->getTargetNode(PPC::CMPWI, dl, MVT::i32, LHS,
509 getI32Imm(Imm & 0xFFFF)), 0);
511 // For non-equality comparisons, the default code would materialize the
512 // constant, then compare against it, like this:
516 // Since we are just comparing for equality, we can emit this instead:
517 // xoris r0,r3,0x1234
518 // cmplwi cr0,r0,0x5678
520 SDValue Xor(CurDAG->getTargetNode(PPC::XORIS, dl, MVT::i32, LHS,
521 getI32Imm(Imm >> 16)), 0);
522 return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, Xor,
523 getI32Imm(Imm & 0xFFFF)), 0);
526 } else if (ISD::isUnsignedIntSetCC(CC)) {
527 if (isInt32Immediate(RHS, Imm) && isUInt16(Imm))
528 return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, LHS,
529 getI32Imm(Imm & 0xFFFF)), 0);
533 if (isIntS16Immediate(RHS, SImm))
534 return SDValue(CurDAG->getTargetNode(PPC::CMPWI, dl, MVT::i32, LHS,
535 getI32Imm((int)SImm & 0xFFFF)),
539 } else if (LHS.getValueType() == MVT::i64) {
541 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
542 if (isInt64Immediate(RHS.getNode(), Imm)) {
543 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
545 return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, LHS,
546 getI32Imm(Imm & 0xFFFF)), 0);
547 // If this is a 16-bit signed immediate, fold it.
549 return SDValue(CurDAG->getTargetNode(PPC::CMPDI, dl, MVT::i64, LHS,
550 getI32Imm(Imm & 0xFFFF)), 0);
552 // For non-equality comparisons, the default code would materialize the
553 // constant, then compare against it, like this:
557 // Since we are just comparing for equality, we can emit this instead:
558 // xoris r0,r3,0x1234
559 // cmpldi cr0,r0,0x5678
562 SDValue Xor(CurDAG->getTargetNode(PPC::XORIS8, dl, MVT::i64, LHS,
563 getI64Imm(Imm >> 16)), 0);
564 return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, Xor,
565 getI64Imm(Imm & 0xFFFF)), 0);
569 } else if (ISD::isUnsignedIntSetCC(CC)) {
570 if (isInt64Immediate(RHS.getNode(), Imm) && isUInt16(Imm))
571 return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, LHS,
572 getI64Imm(Imm & 0xFFFF)), 0);
576 if (isIntS16Immediate(RHS, SImm))
577 return SDValue(CurDAG->getTargetNode(PPC::CMPDI, dl, MVT::i64, LHS,
578 getI64Imm(SImm & 0xFFFF)),
582 } else if (LHS.getValueType() == MVT::f32) {
585 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
588 return SDValue(CurDAG->getTargetNode(Opc, dl, MVT::i32, LHS, RHS), 0);
591 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
597 assert(0 && "Should be lowered by legalize!");
598 default: assert(0 && "Unknown condition!"); abort();
600 case ISD::SETEQ: return PPC::PRED_EQ;
602 case ISD::SETNE: return PPC::PRED_NE;
604 case ISD::SETLT: return PPC::PRED_LT;
606 case ISD::SETLE: return PPC::PRED_LE;
608 case ISD::SETGT: return PPC::PRED_GT;
610 case ISD::SETGE: return PPC::PRED_GE;
611 case ISD::SETO: return PPC::PRED_NU;
612 case ISD::SETUO: return PPC::PRED_UN;
613 // These two are invalid for floating point. Assume we have int.
614 case ISD::SETULT: return PPC::PRED_LT;
615 case ISD::SETUGT: return PPC::PRED_GT;
619 /// getCRIdxForSetCC - Return the index of the condition register field
620 /// associated with the SetCC condition, and whether or not the field is
621 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
623 /// If this returns with Other != -1, then the returned comparison is an or of
624 /// two simpler comparisons. In this case, Invert is guaranteed to be false.
625 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) {
629 default: assert(0 && "Unknown condition!"); abort();
631 case ISD::SETLT: return 0; // Bit #0 = SETOLT
633 case ISD::SETGT: return 1; // Bit #1 = SETOGT
635 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ
636 case ISD::SETUO: return 3; // Bit #3 = SETUO
638 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
640 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE
642 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE
643 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO
648 assert(0 && "Invalid branch code: should be expanded by legalize");
649 // These are invalid for floating point. Assume integer.
650 case ISD::SETULT: return 0;
651 case ISD::SETUGT: return 1;
656 SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) {
657 SDNode *N = Op.getNode();
658 DebugLoc dl = N->getDebugLoc();
660 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
661 if (isInt32Immediate(N->getOperand(1), Imm)) {
662 // We can codegen setcc op, imm very efficiently compared to a brcond.
663 // Check for those cases here.
666 SDValue Op = N->getOperand(0);
670 Op = SDValue(CurDAG->getTargetNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
671 SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
672 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
676 SDValue(CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
677 Op, getI32Imm(~0U)), 0);
678 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
682 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
683 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
687 SDValue(CurDAG->getTargetNode(PPC::NEG, dl, MVT::i32, Op), 0);
688 T = SDValue(CurDAG->getTargetNode(PPC::ANDC, dl, MVT::i32, T, Op), 0);
689 SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
690 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
693 } else if (Imm == ~0U) { // setcc op, -1
694 SDValue Op = N->getOperand(0);
698 Op = SDValue(CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
699 Op, getI32Imm(1)), 0);
700 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
701 SDValue(CurDAG->getTargetNode(PPC::LI, dl,
706 Op = SDValue(CurDAG->getTargetNode(PPC::NOR, dl, MVT::i32, Op, Op), 0);
707 SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
709 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0),
713 SDValue AD = SDValue(CurDAG->getTargetNode(PPC::ADDI, dl, MVT::i32, Op,
715 SDValue AN = SDValue(CurDAG->getTargetNode(PPC::AND, dl, MVT::i32, AD,
717 SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
718 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
721 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
722 Op = SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4),
724 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
733 unsigned Idx = getCRIdxForSetCC(CC, Inv, OtherCondIdx);
734 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
737 // Force the ccreg into CR7.
738 SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
740 SDValue InFlag(0, 0); // Null incoming flag value.
741 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg,
744 if (PPCSubTarget.isGigaProcessor() && OtherCondIdx == -1)
745 IntCR = SDValue(CurDAG->getTargetNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
748 IntCR = SDValue(CurDAG->getTargetNode(PPC::MFCR, dl, MVT::i32, CCReg), 0);
750 SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
751 getI32Imm(31), getI32Imm(31) };
752 if (OtherCondIdx == -1 && !Inv)
753 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
755 // Get the specified bit.
757 SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0);
759 assert(OtherCondIdx == -1 && "Can't have split plus negation");
760 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
763 // Otherwise, we have to turn an operation like SETONE -> SETOLT | SETOGT.
764 // We already got the bit for the first part of the comparison (e.g. SETULE).
766 // Get the other bit of the comparison.
767 Ops[1] = getI32Imm((32-(3-OtherCondIdx)) & 31);
769 SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0);
771 return CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Tmp, OtherCond);
775 // Select - Convert the specified operand from a target-independent to a
776 // target-specific node if it hasn't already been changed.
777 SDNode *PPCDAGToDAGISel::Select(SDValue Op) {
778 SDNode *N = Op.getNode();
779 DebugLoc dl = Op.getDebugLoc();
780 if (N->isMachineOpcode())
781 return NULL; // Already selected.
783 switch (N->getOpcode()) {
786 case ISD::Constant: {
787 if (N->getValueType(0) == MVT::i64) {
789 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
790 // Assume no remaining bits.
791 unsigned Remainder = 0;
792 // Assume no shift required.
795 // If it can't be represented as a 32 bit value.
797 Shift = CountTrailingZeros_64(Imm);
798 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
800 // If the shifted value fits 32 bits.
801 if (isInt32(ImmSh)) {
802 // Go with the shifted value.
805 // Still stuck with a 64 bit value.
812 // Intermediate operand.
815 // Handle first 32 bits.
816 unsigned Lo = Imm & 0xFFFF;
817 unsigned Hi = (Imm >> 16) & 0xFFFF;
822 Result = CurDAG->getTargetNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo));
824 // Handle the Hi bits.
825 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
826 Result = CurDAG->getTargetNode(OpC, dl, MVT::i64, getI32Imm(Hi));
828 Result = CurDAG->getTargetNode(PPC::ORI8, dl, MVT::i64,
829 SDValue(Result, 0), getI32Imm(Lo));
832 Result = CurDAG->getTargetNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
835 // If no shift, we're done.
836 if (!Shift) return Result;
838 // Shift for next step if the upper 32-bits were not zero.
840 Result = CurDAG->getTargetNode(PPC::RLDICR, dl, MVT::i64,
842 getI32Imm(Shift), getI32Imm(63 - Shift));
845 // Add in the last bits as required.
846 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
847 Result = CurDAG->getTargetNode(PPC::ORIS8, dl, MVT::i64,
848 SDValue(Result, 0), getI32Imm(Hi));
850 if ((Lo = Remainder & 0xFFFF)) {
851 Result = CurDAG->getTargetNode(PPC::ORI8, dl, MVT::i64,
852 SDValue(Result, 0), getI32Imm(Lo));
861 return SelectSETCC(Op);
862 case PPCISD::GlobalBaseReg:
863 return getGlobalBaseReg();
865 case ISD::FrameIndex: {
866 int FI = cast<FrameIndexSDNode>(N)->getIndex();
867 SDValue TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType());
868 unsigned Opc = Op.getValueType() == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
870 return CurDAG->SelectNodeTo(N, Opc, Op.getValueType(), TFI,
872 return CurDAG->getTargetNode(Opc, dl, Op.getValueType(), TFI,
877 SDValue InFlag = N->getOperand(1);
878 // Use MFOCRF if supported.
879 if (PPCSubTarget.isGigaProcessor())
880 return CurDAG->getTargetNode(PPC::MFOCRF, dl, MVT::i32,
881 N->getOperand(0), InFlag);
883 return CurDAG->getTargetNode(PPC::MFCR, dl, MVT::i32, InFlag);
887 // FIXME: since this depends on the setting of the carry flag from the srawi
888 // we should really be making notes about that for the scheduler.
889 // FIXME: It sure would be nice if we could cheaply recognize the
890 // srl/add/sra pattern the dag combiner will generate for this as
891 // sra/addze rather than having to handle sdiv ourselves. oh well.
893 if (isInt32Immediate(N->getOperand(1), Imm)) {
894 SDValue N0 = N->getOperand(0);
895 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
897 CurDAG->getTargetNode(PPC::SRAWI, dl, MVT::i32, MVT::Flag,
898 N0, getI32Imm(Log2_32(Imm)));
899 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
900 SDValue(Op, 0), SDValue(Op, 1));
901 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
903 CurDAG->getTargetNode(PPC::SRAWI, dl, MVT::i32, MVT::Flag,
904 N0, getI32Imm(Log2_32(-Imm)));
906 SDValue(CurDAG->getTargetNode(PPC::ADDZE, dl, MVT::i32,
907 SDValue(Op, 0), SDValue(Op, 1)),
909 return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
913 // Other cases are autogenerated.
918 // Handle preincrement loads.
919 LoadSDNode *LD = cast<LoadSDNode>(Op);
920 MVT LoadedVT = LD->getMemoryVT();
922 // Normal loads are handled by code generated from the .td file.
923 if (LD->getAddressingMode() != ISD::PRE_INC)
926 SDValue Offset = LD->getOffset();
927 if (isa<ConstantSDNode>(Offset) ||
928 Offset.getOpcode() == ISD::TargetGlobalAddress) {
931 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
932 if (LD->getValueType(0) != MVT::i64) {
933 // Handle PPC32 integer and normal FP loads.
934 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
935 switch (LoadedVT.getSimpleVT()) {
936 default: assert(0 && "Invalid PPC load type!");
937 case MVT::f64: Opcode = PPC::LFDU; break;
938 case MVT::f32: Opcode = PPC::LFSU; break;
939 case MVT::i32: Opcode = PPC::LWZU; break;
940 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
942 case MVT::i8: Opcode = PPC::LBZU; break;
945 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
946 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
947 switch (LoadedVT.getSimpleVT()) {
948 default: assert(0 && "Invalid PPC load type!");
949 case MVT::i64: Opcode = PPC::LDU; break;
950 case MVT::i32: Opcode = PPC::LWZU8; break;
951 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
953 case MVT::i8: Opcode = PPC::LBZU8; break;
957 SDValue Chain = LD->getChain();
958 SDValue Base = LD->getBasePtr();
959 SDValue Ops[] = { Offset, Base, Chain };
961 return CurDAG->getTargetNode(Opcode, dl, LD->getValueType(0),
962 PPCLowering.getPointerTy(),
965 assert(0 && "R+R preindex loads not supported yet!");
970 unsigned Imm, Imm2, SH, MB, ME;
972 // If this is an and of a value rotated between 0 and 31 bits and then and'd
973 // with a mask, emit rlwinm
974 if (isInt32Immediate(N->getOperand(1), Imm) &&
975 isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) {
976 SDValue Val = N->getOperand(0).getOperand(0);
977 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
978 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
980 // If this is just a masked value where the input is not handled above, and
981 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
982 if (isInt32Immediate(N->getOperand(1), Imm) &&
983 isRunOfOnes(Imm, MB, ME) &&
984 N->getOperand(0).getOpcode() != ISD::ROTL) {
985 SDValue Val = N->getOperand(0);
986 SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
987 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
989 // AND X, 0 -> 0, not "rlwinm 32".
990 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
991 ReplaceUses(SDValue(N, 0), N->getOperand(1));
994 // ISD::OR doesn't get all the bitfield insertion fun.
995 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
996 if (isInt32Immediate(N->getOperand(1), Imm) &&
997 N->getOperand(0).getOpcode() == ISD::OR &&
998 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
1001 if (isRunOfOnes(Imm, MB, ME)) {
1002 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1003 N->getOperand(0).getOperand(1),
1004 getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
1005 return CurDAG->getTargetNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5);
1009 // Other cases are autogenerated.
1013 if (N->getValueType(0) == MVT::i32)
1014 if (SDNode *I = SelectBitfieldInsert(N))
1017 // Other cases are autogenerated.
1020 unsigned Imm, SH, MB, ME;
1021 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
1022 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1023 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1024 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1025 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
1028 // Other cases are autogenerated.
1032 unsigned Imm, SH, MB, ME;
1033 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
1034 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1035 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1036 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1037 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
1040 // Other cases are autogenerated.
1043 case ISD::SELECT_CC: {
1044 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1046 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
1047 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1048 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1049 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1050 if (N1C->isNullValue() && N3C->isNullValue() &&
1051 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
1052 // FIXME: Implement this optzn for PPC64.
1053 N->getValueType(0) == MVT::i32) {
1055 CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag,
1056 N->getOperand(0), getI32Imm(~0U));
1057 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
1058 SDValue(Tmp, 0), N->getOperand(0),
1062 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
1063 unsigned BROpc = getPredicateForSetCC(CC);
1065 unsigned SelectCCOp;
1066 if (N->getValueType(0) == MVT::i32)
1067 SelectCCOp = PPC::SELECT_CC_I4;
1068 else if (N->getValueType(0) == MVT::i64)
1069 SelectCCOp = PPC::SELECT_CC_I8;
1070 else if (N->getValueType(0) == MVT::f32)
1071 SelectCCOp = PPC::SELECT_CC_F4;
1072 else if (N->getValueType(0) == MVT::f64)
1073 SelectCCOp = PPC::SELECT_CC_F8;
1075 SelectCCOp = PPC::SELECT_CC_VRRC;
1077 SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
1079 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4);
1081 case PPCISD::COND_BRANCH: {
1082 // Op #0 is the Chain.
1083 // Op #1 is the PPC::PRED_* number.
1085 // Op #3 is the Dest MBB
1086 // Op #4 is the Flag.
1087 // Prevent PPC::PRED_* from being selected into LI.
1089 getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue());
1090 SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
1091 N->getOperand(0), N->getOperand(4) };
1092 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5);
1095 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
1096 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
1097 SDValue Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode,
1098 N->getOperand(4), N->getOperand(0) };
1099 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4);
1102 // FIXME: Should custom lower this.
1103 SDValue Chain = N->getOperand(0);
1104 SDValue Target = N->getOperand(1);
1105 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
1106 Chain = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Target,
1108 return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain);
1110 case ISD::DECLARE: {
1111 SDValue Chain = N->getOperand(0);
1112 SDValue N1 = N->getOperand(1);
1113 SDValue N2 = N->getOperand(2);
1114 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N1);
1116 // FIXME: We need to handle this for VLAs.
1118 ReplaceUses(Op.getValue(0), Chain);
1122 if (N2.getOpcode() == ISD::ADD) {
1123 if (N2.getOperand(0).getOpcode() == ISD::ADD &&
1124 N2.getOperand(0).getOperand(0).getOpcode() == PPCISD::GlobalBaseReg &&
1125 N2.getOperand(0).getOperand(1).getOpcode() == PPCISD::Hi &&
1126 N2.getOperand(1).getOpcode() == PPCISD::Lo)
1127 N2 = N2.getOperand(0).getOperand(1).getOperand(0);
1128 else if (N2.getOperand(0).getOpcode() == ISD::ADD &&
1129 N2.getOperand(0).getOperand(0).getOpcode() == PPCISD::GlobalBaseReg &&
1130 N2.getOperand(0).getOperand(1).getOpcode() == PPCISD::Lo &&
1131 N2.getOperand(1).getOpcode() == PPCISD::Hi)
1132 N2 = N2.getOperand(0).getOperand(1).getOperand(0);
1133 else if (N2.getOperand(0).getOpcode() == PPCISD::Hi &&
1134 N2.getOperand(1).getOpcode() == PPCISD::Lo)
1135 N2 = N2.getOperand(0).getOperand(0);
1138 // If we don't have a global address here, the debug info is mangled, just
1140 if (!isa<GlobalAddressSDNode>(N2)) {
1141 ReplaceUses(Op.getValue(0), Chain);
1144 int FI = cast<FrameIndexSDNode>(N1)->getIndex();
1145 GlobalValue *GV = cast<GlobalAddressSDNode>(N2)->getGlobal();
1146 SDValue Tmp1 = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1147 SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy());
1148 return CurDAG->SelectNodeTo(N, TargetInstrInfo::DECLARE,
1149 MVT::Other, Tmp1, Tmp2, Chain);
1153 return SelectCode(Op);
1158 /// createPPCISelDag - This pass converts a legalized DAG into a
1159 /// PowerPC-specific DAG, ready for instruction scheduling.
1161 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
1162 return new PPCDAGToDAGISel(TM);