1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
16 #include "PPCTargetMachine.h"
17 #include "PPCISelLowering.h"
18 #include "PPCHazardRecognizers.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Constants.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/Support/Compiler.h"
38 Statistic<> FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
40 //===--------------------------------------------------------------------===//
41 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
42 /// instructions for SelectionDAG operations.
44 class VISIBILITY_HIDDEN PPCDAGToDAGISel : public SelectionDAGISel {
46 PPCTargetLowering PPCLowering;
47 unsigned GlobalBaseReg;
49 PPCDAGToDAGISel(PPCTargetMachine &tm)
50 : SelectionDAGISel(PPCLowering), TM(tm),
51 PPCLowering(*TM.getTargetLowering()) {}
53 virtual bool runOnFunction(Function &Fn) {
54 // Make sure we re-emit a set of the global base reg if necessary
56 SelectionDAGISel::runOnFunction(Fn);
62 /// getI32Imm - Return a target constant with the specified value, of type
64 inline SDOperand getI32Imm(unsigned Imm) {
65 return CurDAG->getTargetConstant(Imm, MVT::i32);
68 /// getI64Imm - Return a target constant with the specified value, of type
70 inline SDOperand getI64Imm(uint64_t Imm) {
71 return CurDAG->getTargetConstant(Imm, MVT::i64);
74 /// getSmallIPtrImm - Return a target constant of pointer type.
75 inline SDOperand getSmallIPtrImm(unsigned Imm) {
76 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy());
80 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
81 /// base register. Return the virtual register that holds this value.
82 SDNode *getGlobalBaseReg();
84 // Select - Convert the specified operand from a target-independent to a
85 // target-specific node if it hasn't already been changed.
86 SDNode *Select(SDOperand Op);
88 SDNode *SelectBitfieldInsert(SDNode *N);
90 /// SelectCC - Select a comparison of the specified values with the
91 /// specified condition code, returning the CR# of the expression.
92 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
94 /// SelectAddrImm - Returns true if the address N can be represented by
95 /// a base register plus a signed 16-bit displacement [r+imm].
96 bool SelectAddrImm(SDOperand N, SDOperand &Disp, SDOperand &Base);
98 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
99 /// represented as an indexed [r+r] operation. Returns false if it can
100 /// be represented by [r+imm], which are preferred.
101 bool SelectAddrIdx(SDOperand N, SDOperand &Base, SDOperand &Index);
103 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
104 /// represented as an indexed [r+r] operation.
105 bool SelectAddrIdxOnly(SDOperand N, SDOperand &Base, SDOperand &Index);
107 /// SelectAddrImmShift - Returns true if the address N can be represented by
108 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
109 /// for use by STD and friends.
110 bool SelectAddrImmShift(SDOperand N, SDOperand &Disp, SDOperand &Base);
112 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
113 /// inline asm expressions.
114 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
116 std::vector<SDOperand> &OutOps,
119 switch (ConstraintCode) {
120 default: return true;
122 if (!SelectAddrIdx(Op, Op0, Op1))
123 SelectAddrImm(Op, Op0, Op1);
125 case 'o': // offsetable
126 if (!SelectAddrImm(Op, Op0, Op1)) {
128 AddToISelQueue(Op0); // r+0.
129 Op1 = getSmallIPtrImm(0);
132 case 'v': // not offsetable
133 SelectAddrIdxOnly(Op, Op0, Op1);
137 OutOps.push_back(Op0);
138 OutOps.push_back(Op1);
142 SDOperand BuildSDIVSequence(SDNode *N);
143 SDOperand BuildUDIVSequence(SDNode *N);
145 /// InstructionSelectBasicBlock - This callback is invoked by
146 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
147 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
149 void InsertVRSaveCode(Function &Fn);
151 virtual const char *getPassName() const {
152 return "PowerPC DAG->DAG Pattern Instruction Selection";
155 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
156 /// this target when scheduling the DAG.
157 virtual HazardRecognizer *CreateTargetHazardRecognizer() {
158 // Should use subtarget info to pick the right hazard recognizer. For
159 // now, always return a PPC970 recognizer.
160 const TargetInstrInfo *II = PPCLowering.getTargetMachine().getInstrInfo();
161 assert(II && "No InstrInfo?");
162 return new PPCHazardRecognizer970(*II);
165 // Include the pieces autogenerated from the target description.
166 #include "PPCGenDAGISel.inc"
169 SDNode *SelectSETCC(SDOperand Op);
170 SDNode *MySelect_PPCbctrl(SDOperand N);
171 SDNode *MySelect_PPCcall(SDOperand N);
175 /// InstructionSelectBasicBlock - This callback is invoked by
176 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
177 void PPCDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
180 // Select target instructions for the DAG.
181 DAG.setRoot(SelectRoot(DAG.getRoot()));
182 DAG.RemoveDeadNodes();
184 // Emit machine code to BB.
185 ScheduleAndEmitDAG(DAG);
188 /// InsertVRSaveCode - Once the entire function has been instruction selected,
189 /// all virtual registers are created and all machine instructions are built,
190 /// check to see if we need to save/restore VRSAVE. If so, do it.
191 void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) {
192 // Check to see if this function uses vector registers, which means we have to
193 // save and restore the VRSAVE register and update it with the regs we use.
195 // In this case, there will be virtual registers of vector type type created
196 // by the scheduler. Detect them now.
197 MachineFunction &Fn = MachineFunction::get(&F);
198 SSARegMap *RegMap = Fn.getSSARegMap();
199 bool HasVectorVReg = false;
200 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
201 e = RegMap->getLastVirtReg()+1; i != e; ++i)
202 if (RegMap->getRegClass(i) == &PPC::VRRCRegClass) {
203 HasVectorVReg = true;
206 if (!HasVectorVReg) return; // nothing to do.
208 // If we have a vector register, we want to emit code into the entry and exit
209 // blocks to save and restore the VRSAVE register. We do this here (instead
210 // of marking all vector instructions as clobbering VRSAVE) for two reasons:
212 // 1. This (trivially) reduces the load on the register allocator, by not
213 // having to represent the live range of the VRSAVE register.
214 // 2. This (more significantly) allows us to create a temporary virtual
215 // register to hold the saved VRSAVE value, allowing this temporary to be
216 // register allocated, instead of forcing it to be spilled to the stack.
218 // Create two vregs - one to hold the VRSAVE register that is live-in to the
219 // function and one for the value after having bits or'd into it.
220 unsigned InVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
221 unsigned UpdatedVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
223 MachineBasicBlock &EntryBB = *Fn.begin();
224 // Emit the following code into the entry block:
225 // InVRSAVE = MFVRSAVE
226 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
227 // MTVRSAVE UpdatedVRSAVE
228 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
229 BuildMI(EntryBB, IP, PPC::MFVRSAVE, 0, InVRSAVE);
230 BuildMI(EntryBB, IP, PPC::UPDATE_VRSAVE, 1, UpdatedVRSAVE).addReg(InVRSAVE);
231 BuildMI(EntryBB, IP, PPC::MTVRSAVE, 1).addReg(UpdatedVRSAVE);
233 // Find all return blocks, outputting a restore in each epilog.
234 const TargetInstrInfo &TII = *TM.getInstrInfo();
235 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
236 if (!BB->empty() && TII.isReturn(BB->back().getOpcode())) {
237 IP = BB->end(); --IP;
239 // Skip over all terminator instructions, which are part of the return
241 MachineBasicBlock::iterator I2 = IP;
242 while (I2 != BB->begin() && TII.isTerminatorInstr((--I2)->getOpcode()))
245 // Emit: MTVRSAVE InVRSave
246 BuildMI(*BB, IP, PPC::MTVRSAVE, 1).addReg(InVRSAVE);
252 /// getGlobalBaseReg - Output the instructions required to put the
253 /// base address to use for accessing globals into a register.
255 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
256 if (!GlobalBaseReg) {
257 // Insert the set of GlobalBaseReg into the first MBB of the function
258 MachineBasicBlock &FirstMBB = BB->getParent()->front();
259 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
260 SSARegMap *RegMap = BB->getParent()->getSSARegMap();
262 if (PPCLowering.getPointerTy() == MVT::i32)
263 GlobalBaseReg = RegMap->createVirtualRegister(PPC::GPRCRegisterClass);
265 GlobalBaseReg = RegMap->createVirtualRegister(PPC::G8RCRegisterClass);
267 BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
268 BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
270 return CurDAG->getRegister(GlobalBaseReg, PPCLowering.getPointerTy()).Val;
273 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
274 /// or 64-bit immediate, and if the value can be accurately represented as a
275 /// sign extension from a 16-bit value. If so, this returns true and the
277 static bool isIntS16Immediate(SDNode *N, short &Imm) {
278 if (N->getOpcode() != ISD::Constant)
281 Imm = (short)cast<ConstantSDNode>(N)->getValue();
282 if (N->getValueType(0) == MVT::i32)
283 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue();
285 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
288 static bool isIntS16Immediate(SDOperand Op, short &Imm) {
289 return isIntS16Immediate(Op.Val, Imm);
293 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
294 /// operand. If so Imm will receive the 32-bit value.
295 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
296 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
297 Imm = cast<ConstantSDNode>(N)->getValue();
303 /// isInt64Immediate - This method tests to see if the node is a 64-bit constant
304 /// operand. If so Imm will receive the 64-bit value.
305 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
306 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
307 Imm = cast<ConstantSDNode>(N)->getValue();
313 // isInt32Immediate - This method tests to see if a constant operand.
314 // If so Imm will receive the 32 bit value.
315 static bool isInt32Immediate(SDOperand N, unsigned &Imm) {
316 return isInt32Immediate(N.Val, Imm);
320 // isOpcWithIntImmediate - This method tests to see if the node is a specific
321 // opcode and that it has a immediate integer right operand.
322 // If so Imm will receive the 32 bit value.
323 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
324 return N->getOpcode() == Opc && isInt32Immediate(N->getOperand(1).Val, Imm);
328 // isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s with
329 // any number of 0s on either side. The 1s are allowed to wrap from LSB to
330 // MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is
331 // not, since all 1s are not contiguous.
332 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
333 if (isShiftedMask_32(Val)) {
334 // look for the first non-zero bit
335 MB = CountLeadingZeros_32(Val);
336 // look for the first zero bit after the run of ones
337 ME = CountLeadingZeros_32((Val - 1) ^ Val);
340 Val = ~Val; // invert mask
341 if (isShiftedMask_32(Val)) {
342 // effectively look for the first zero bit
343 ME = CountLeadingZeros_32(Val) - 1;
344 // effectively look for the first one bit after the run of zeros
345 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
353 // isRotateAndMask - Returns true if Mask and Shift can be folded into a rotate
354 // and mask opcode and mask operation.
355 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
356 unsigned &SH, unsigned &MB, unsigned &ME) {
357 // Don't even go down this path for i64, since different logic will be
358 // necessary for rldicl/rldicr/rldimi.
359 if (N->getValueType(0) != MVT::i32)
363 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
364 unsigned Opcode = N->getOpcode();
365 if (N->getNumOperands() != 2 ||
366 !isInt32Immediate(N->getOperand(1).Val, Shift) || (Shift > 31))
369 if (Opcode == ISD::SHL) {
370 // apply shift left to mask if it comes first
371 if (IsShiftMask) Mask = Mask << Shift;
372 // determine which bits are made indeterminant by shift
373 Indeterminant = ~(0xFFFFFFFFu << Shift);
374 } else if (Opcode == ISD::SRL) {
375 // apply shift right to mask if it comes first
376 if (IsShiftMask) Mask = Mask >> Shift;
377 // determine which bits are made indeterminant by shift
378 Indeterminant = ~(0xFFFFFFFFu >> Shift);
379 // adjust for the left rotate
385 // if the mask doesn't intersect any Indeterminant bits
386 if (Mask && !(Mask & Indeterminant)) {
388 // make sure the mask is still a mask (wrap arounds may not be)
389 return isRunOfOnes(Mask, MB, ME);
394 /// SelectBitfieldInsert - turn an or of two masked values into
395 /// the rotate left word immediate then mask insert (rlwimi) instruction.
396 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
397 SDOperand Op0 = N->getOperand(0);
398 SDOperand Op1 = N->getOperand(1);
400 uint64_t LKZ, LKO, RKZ, RKO;
401 TLI.ComputeMaskedBits(Op0, 0xFFFFFFFFULL, LKZ, LKO);
402 TLI.ComputeMaskedBits(Op1, 0xFFFFFFFFULL, RKZ, RKO);
404 unsigned TargetMask = LKZ;
405 unsigned InsertMask = RKZ;
407 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
408 unsigned Op0Opc = Op0.getOpcode();
409 unsigned Op1Opc = Op1.getOpcode();
410 unsigned Value, SH = 0;
411 TargetMask = ~TargetMask;
412 InsertMask = ~InsertMask;
414 // If the LHS has a foldable shift and the RHS does not, then swap it to the
415 // RHS so that we can fold the shift into the insert.
416 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
417 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
418 Op0.getOperand(0).getOpcode() == ISD::SRL) {
419 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
420 Op1.getOperand(0).getOpcode() != ISD::SRL) {
422 std::swap(Op0Opc, Op1Opc);
423 std::swap(TargetMask, InsertMask);
426 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
427 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
428 Op1.getOperand(0).getOpcode() != ISD::SRL) {
430 std::swap(Op0Opc, Op1Opc);
431 std::swap(TargetMask, InsertMask);
436 if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) {
437 SDOperand Tmp1, Tmp2, Tmp3;
438 bool DisjointMask = (TargetMask ^ InsertMask) == 0xFFFFFFFF;
440 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
441 isInt32Immediate(Op1.getOperand(1), Value)) {
442 Op1 = Op1.getOperand(0);
443 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
445 if (Op1Opc == ISD::AND) {
446 unsigned SHOpc = Op1.getOperand(0).getOpcode();
447 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) &&
448 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
449 Op1 = Op1.getOperand(0).getOperand(0);
450 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
452 Op1 = Op1.getOperand(0);
456 Tmp3 = (Op0Opc == ISD::AND && DisjointMask) ? Op0.getOperand(0) : Op0;
457 AddToISelQueue(Tmp3);
460 SDOperand Ops[] = { Tmp3, Op1, getI32Imm(SH), getI32Imm(MB),
462 return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5);
468 /// SelectAddrImm - Returns true if the address N can be represented by
469 /// a base register plus a signed 16-bit displacement [r+imm].
470 bool PPCDAGToDAGISel::SelectAddrImm(SDOperand N, SDOperand &Disp,
472 // If this can be more profitably realized as r+r, fail.
473 if (SelectAddrIdx(N, Disp, Base))
476 if (N.getOpcode() == ISD::ADD) {
478 if (isIntS16Immediate(N.getOperand(1), imm)) {
479 Disp = getI32Imm((int)imm & 0xFFFF);
480 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
481 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
483 Base = N.getOperand(0);
485 return true; // [r+i]
486 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
487 // Match LOAD (ADD (X, Lo(G))).
488 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
489 && "Cannot handle constant offsets yet!");
490 Disp = N.getOperand(1).getOperand(0); // The global address.
491 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
492 Disp.getOpcode() == ISD::TargetConstantPool ||
493 Disp.getOpcode() == ISD::TargetJumpTable);
494 Base = N.getOperand(0);
495 return true; // [&g+r]
497 } else if (N.getOpcode() == ISD::OR) {
499 if (isIntS16Immediate(N.getOperand(1), imm)) {
500 // If this is an or of disjoint bitfields, we can codegen this as an add
501 // (for better address arithmetic) if the LHS and RHS of the OR are
502 // provably disjoint.
503 uint64_t LHSKnownZero, LHSKnownOne;
504 PPCLowering.ComputeMaskedBits(N.getOperand(0), ~0U,
505 LHSKnownZero, LHSKnownOne);
506 if ((LHSKnownZero|~(unsigned)imm) == ~0U) {
507 // If all of the bits are known zero on the LHS or RHS, the add won't
509 Base = N.getOperand(0);
510 Disp = getI32Imm((int)imm & 0xFFFF);
514 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
515 // Loading from a constant address.
517 // If this address fits entirely in a 16-bit sext immediate field, codegen
520 if (isIntS16Immediate(CN, Imm)) {
521 Disp = CurDAG->getTargetConstant(Imm, CN->getValueType(0));
522 Base = CurDAG->getRegister(PPC::R0, CN->getValueType(0));
526 // FIXME: Handle small sext constant offsets in PPC64 mode also!
527 if (CN->getValueType(0) == MVT::i32) {
528 int Addr = (int)CN->getValue();
530 // Otherwise, break this down into an LIS + disp.
531 Disp = getI32Imm((short)Addr);
532 Base = CurDAG->getConstant(Addr - (signed short)Addr, MVT::i32);
537 Disp = getSmallIPtrImm(0);
538 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
539 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
542 return true; // [r+0]
545 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
546 /// represented as an indexed [r+r] operation. Returns false if it can
547 /// be represented by [r+imm], which are preferred.
548 bool PPCDAGToDAGISel::SelectAddrIdx(SDOperand N, SDOperand &Base,
551 if (N.getOpcode() == ISD::ADD) {
552 if (isIntS16Immediate(N.getOperand(1), imm))
554 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
557 Base = N.getOperand(0);
558 Index = N.getOperand(1);
560 } else if (N.getOpcode() == ISD::OR) {
561 if (isIntS16Immediate(N.getOperand(1), imm))
562 return false; // r+i can fold it if we can.
564 // If this is an or of disjoint bitfields, we can codegen this as an add
565 // (for better address arithmetic) if the LHS and RHS of the OR are provably
567 uint64_t LHSKnownZero, LHSKnownOne;
568 uint64_t RHSKnownZero, RHSKnownOne;
569 PPCLowering.ComputeMaskedBits(N.getOperand(0), ~0U,
570 LHSKnownZero, LHSKnownOne);
573 PPCLowering.ComputeMaskedBits(N.getOperand(1), ~0U,
574 RHSKnownZero, RHSKnownOne);
575 // If all of the bits are known zero on the LHS or RHS, the add won't
577 if ((LHSKnownZero | RHSKnownZero) == ~0U) {
578 Base = N.getOperand(0);
579 Index = N.getOperand(1);
588 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
589 /// represented as an indexed [r+r] operation.
590 bool PPCDAGToDAGISel::SelectAddrIdxOnly(SDOperand N, SDOperand &Base,
592 // Check to see if we can easily represent this as an [r+r] address. This
593 // will fail if it thinks that the address is more profitably represented as
594 // reg+imm, e.g. where imm = 0.
595 if (SelectAddrIdx(N, Base, Index))
598 // If the operand is an addition, always emit this as [r+r], since this is
599 // better (for code size, and execution, as the memop does the add for free)
600 // than emitting an explicit add.
601 if (N.getOpcode() == ISD::ADD) {
602 Base = N.getOperand(0);
603 Index = N.getOperand(1);
607 // Otherwise, do it the hard way, using R0 as the base register.
608 Base = CurDAG->getRegister(PPC::R0, N.getValueType());
613 /// SelectAddrImmShift - Returns true if the address N can be represented by
614 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
615 /// for use by STD and friends.
616 bool PPCDAGToDAGISel::SelectAddrImmShift(SDOperand N, SDOperand &Disp,
618 // If this can be more profitably realized as r+r, fail.
619 if (SelectAddrIdx(N, Disp, Base))
622 if (N.getOpcode() == ISD::ADD) {
624 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
625 Disp = getI32Imm(((int)imm & 0xFFFF) >> 2);
626 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
627 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
629 Base = N.getOperand(0);
631 return true; // [r+i]
632 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
633 // Match LOAD (ADD (X, Lo(G))).
634 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
635 && "Cannot handle constant offsets yet!");
636 Disp = N.getOperand(1).getOperand(0); // The global address.
637 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
638 Disp.getOpcode() == ISD::TargetConstantPool ||
639 Disp.getOpcode() == ISD::TargetJumpTable);
640 Base = N.getOperand(0);
641 return true; // [&g+r]
643 } else if (N.getOpcode() == ISD::OR) {
645 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
646 // If this is an or of disjoint bitfields, we can codegen this as an add
647 // (for better address arithmetic) if the LHS and RHS of the OR are
648 // provably disjoint.
649 uint64_t LHSKnownZero, LHSKnownOne;
650 PPCLowering.ComputeMaskedBits(N.getOperand(0), ~0U,
651 LHSKnownZero, LHSKnownOne);
652 if ((LHSKnownZero|~(unsigned)imm) == ~0U) {
653 // If all of the bits are known zero on the LHS or RHS, the add won't
655 Base = N.getOperand(0);
656 Disp = getI32Imm(((int)imm & 0xFFFF) >> 2);
660 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
661 // Loading from a constant address.
663 // If this address fits entirely in a 14-bit sext immediate field, codegen
666 if (isIntS16Immediate(CN, Imm)) {
667 Disp = getSmallIPtrImm((unsigned short)Imm >> 2);
668 Base = CurDAG->getRegister(PPC::R0, CN->getValueType(0));
672 // FIXME: Handle small sext constant offsets in PPC64 mode also!
673 if (CN->getValueType(0) == MVT::i32) {
674 int Addr = (int)CN->getValue();
676 // Otherwise, break this down into an LIS + disp.
677 Disp = getI32Imm((short)Addr >> 2);
678 Base = CurDAG->getConstant(Addr - (signed short)Addr, MVT::i32);
683 Disp = getSmallIPtrImm(0);
684 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
685 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
688 return true; // [r+0]
692 /// SelectCC - Select a comparison of the specified values with the specified
693 /// condition code, returning the CR# of the expression.
694 SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
696 // Always select the LHS.
700 if (LHS.getValueType() == MVT::i32) {
702 if (ISD::isUnsignedIntSetCC(CC)) {
703 if (isInt32Immediate(RHS, Imm) && isUInt16(Imm))
704 return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS,
705 getI32Imm(Imm & 0xFFFF)), 0);
709 if (isIntS16Immediate(RHS, SImm))
710 return SDOperand(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS,
711 getI32Imm((int)SImm & 0xFFFF)),
715 } else if (LHS.getValueType() == MVT::i64) {
717 if (ISD::isUnsignedIntSetCC(CC)) {
718 if (isInt64Immediate(RHS.Val, Imm) && isUInt16(Imm))
719 return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS,
720 getI64Imm(Imm & 0xFFFF)), 0);
724 if (isIntS16Immediate(RHS, SImm))
725 return SDOperand(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS,
726 getI64Imm((int)SImm & 0xFFFF)),
730 } else if (LHS.getValueType() == MVT::f32) {
733 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
737 return SDOperand(CurDAG->getTargetNode(Opc, MVT::i32, LHS, RHS), 0);
740 /// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding
742 static unsigned getBCCForSetCC(ISD::CondCode CC) {
744 default: assert(0 && "Unknown condition!"); abort();
745 case ISD::SETOEQ: // FIXME: This is incorrect see PR642.
747 case ISD::SETEQ: return PPC::BEQ;
748 case ISD::SETONE: // FIXME: This is incorrect see PR642.
750 case ISD::SETNE: return PPC::BNE;
751 case ISD::SETOLT: // FIXME: This is incorrect see PR642.
753 case ISD::SETLT: return PPC::BLT;
754 case ISD::SETOLE: // FIXME: This is incorrect see PR642.
756 case ISD::SETLE: return PPC::BLE;
757 case ISD::SETOGT: // FIXME: This is incorrect see PR642.
759 case ISD::SETGT: return PPC::BGT;
760 case ISD::SETOGE: // FIXME: This is incorrect see PR642.
762 case ISD::SETGE: return PPC::BGE;
764 case ISD::SETO: return PPC::BUN;
765 case ISD::SETUO: return PPC::BNU;
770 /// getCRIdxForSetCC - Return the index of the condition register field
771 /// associated with the SetCC condition, and whether or not the field is
772 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
773 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool& Inv) {
775 default: assert(0 && "Unknown condition!"); abort();
776 case ISD::SETOLT: // FIXME: This is incorrect see PR642.
778 case ISD::SETLT: Inv = false; return 0;
779 case ISD::SETOGE: // FIXME: This is incorrect see PR642.
781 case ISD::SETGE: Inv = true; return 0;
782 case ISD::SETOGT: // FIXME: This is incorrect see PR642.
784 case ISD::SETGT: Inv = false; return 1;
785 case ISD::SETOLE: // FIXME: This is incorrect see PR642.
787 case ISD::SETLE: Inv = true; return 1;
788 case ISD::SETOEQ: // FIXME: This is incorrect see PR642.
790 case ISD::SETEQ: Inv = false; return 2;
791 case ISD::SETONE: // FIXME: This is incorrect see PR642.
793 case ISD::SETNE: Inv = true; return 2;
794 case ISD::SETO: Inv = true; return 3;
795 case ISD::SETUO: Inv = false; return 3;
800 SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
803 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
804 if (isInt32Immediate(N->getOperand(1), Imm)) {
805 // We can codegen setcc op, imm very efficiently compared to a brcond.
806 // Check for those cases here.
809 SDOperand Op = N->getOperand(0);
814 Op = SDOperand(CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op), 0);
815 SDOperand Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
816 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
820 SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
821 Op, getI32Imm(~0U)), 0);
822 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
826 SDOperand Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
827 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
831 SDOperand(CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op), 0);
832 T = SDOperand(CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op), 0);
833 SDOperand Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
834 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
837 } else if (Imm == ~0U) { // setcc op, -1
838 SDOperand Op = N->getOperand(0);
843 Op = SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
844 Op, getI32Imm(1)), 0);
845 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
846 SDOperand(CurDAG->getTargetNode(PPC::LI, MVT::i32,
850 Op = SDOperand(CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op), 0);
851 SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
853 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDOperand(AD, 0),
854 Op, SDOperand(AD, 1));
857 SDOperand AD = SDOperand(CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
859 SDOperand AN = SDOperand(CurDAG->getTargetNode(PPC::AND, MVT::i32, AD,
861 SDOperand Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
862 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
865 SDOperand Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
866 Op = SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
867 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
875 unsigned Idx = getCRIdxForSetCC(CC, Inv);
876 SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
879 // Force the ccreg into CR7.
880 SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
882 SDOperand InFlag(0, 0); // Null incoming flag value.
883 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), CR7Reg, CCReg,
886 if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
887 IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg,
890 IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg), 0);
892 SDOperand Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
893 getI32Imm(31), getI32Imm(31) };
895 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
898 SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
899 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
904 // Select - Convert the specified operand from a target-independent to a
905 // target-specific node if it hasn't already been changed.
906 SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
908 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
909 N->getOpcode() < PPCISD::FIRST_NUMBER)
910 return NULL; // Already selected.
912 switch (N->getOpcode()) {
915 return SelectSETCC(Op);
916 case PPCISD::GlobalBaseReg:
917 return getGlobalBaseReg();
919 case ISD::FrameIndex: {
920 int FI = cast<FrameIndexSDNode>(N)->getIndex();
921 SDOperand TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType());
922 unsigned Opc = Op.getValueType() == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
924 return CurDAG->SelectNodeTo(N, Opc, Op.getValueType(), TFI,
926 return CurDAG->getTargetNode(Opc, Op.getValueType(), TFI,
931 SDOperand InFlag = N->getOperand(1);
932 AddToISelQueue(InFlag);
933 // Use MFOCRF if supported.
934 if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
935 return CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32,
936 N->getOperand(0), InFlag);
938 return CurDAG->getTargetNode(PPC::MFCR, MVT::i32, InFlag);
942 // FIXME: since this depends on the setting of the carry flag from the srawi
943 // we should really be making notes about that for the scheduler.
944 // FIXME: It sure would be nice if we could cheaply recognize the
945 // srl/add/sra pattern the dag combiner will generate for this as
946 // sra/addze rather than having to handle sdiv ourselves. oh well.
948 if (isInt32Immediate(N->getOperand(1), Imm)) {
949 SDOperand N0 = N->getOperand(0);
951 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
953 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
954 N0, getI32Imm(Log2_32(Imm)));
955 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
956 SDOperand(Op, 0), SDOperand(Op, 1));
957 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
959 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
960 N0, getI32Imm(Log2_32(-Imm)));
962 SDOperand(CurDAG->getTargetNode(PPC::ADDZE, MVT::i32,
963 SDOperand(Op, 0), SDOperand(Op, 1)),
965 return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
969 // Other cases are autogenerated.
974 // If this is an and of a value rotated between 0 and 31 bits and then and'd
975 // with a mask, emit rlwinm
976 if (isInt32Immediate(N->getOperand(1), Imm) &&
977 (isShiftedMask_32(Imm) || isShiftedMask_32(~Imm))) {
980 if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
981 Val = N->getOperand(0).getOperand(0);
983 } else if (Imm == 0) {
984 // AND X, 0 -> 0, not "rlwinm 32".
985 AddToISelQueue(N->getOperand(1));
986 ReplaceUses(SDOperand(N, 0), N->getOperand(1));
989 Val = N->getOperand(0);
991 isRunOfOnes(Imm, MB, ME);
994 SDOperand Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
995 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
997 // ISD::OR doesn't get all the bitfield insertion fun.
998 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
999 if (isInt32Immediate(N->getOperand(1), Imm) &&
1000 N->getOperand(0).getOpcode() == ISD::OR &&
1001 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
1004 if (isRunOfOnes(Imm, MB, ME)) {
1005 AddToISelQueue(N->getOperand(0).getOperand(0));
1006 AddToISelQueue(N->getOperand(0).getOperand(1));
1007 SDOperand Ops[] = { N->getOperand(0).getOperand(0),
1008 N->getOperand(0).getOperand(1),
1009 getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
1010 return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5);
1014 // Other cases are autogenerated.
1018 if (N->getValueType(0) == MVT::i32)
1019 if (SDNode *I = SelectBitfieldInsert(N))
1022 // Other cases are autogenerated.
1025 unsigned Imm, SH, MB, ME;
1026 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
1027 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1028 AddToISelQueue(N->getOperand(0).getOperand(0));
1029 SDOperand Ops[] = { N->getOperand(0).getOperand(0),
1030 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1031 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
1034 // Other cases are autogenerated.
1038 unsigned Imm, SH, MB, ME;
1039 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
1040 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1041 AddToISelQueue(N->getOperand(0).getOperand(0));
1042 SDOperand Ops[] = { N->getOperand(0).getOperand(0),
1043 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1044 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
1047 // Other cases are autogenerated.
1050 case ISD::SELECT_CC: {
1051 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1053 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
1054 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1055 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1056 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1057 if (N1C->isNullValue() && N3C->isNullValue() &&
1058 N2C->getValue() == 1ULL && CC == ISD::SETNE &&
1059 // FIXME: Implement this optzn for PPC64.
1060 N->getValueType(0) == MVT::i32) {
1061 AddToISelQueue(N->getOperand(0));
1063 CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
1064 N->getOperand(0), getI32Imm(~0U));
1065 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
1066 SDOperand(Tmp, 0), N->getOperand(0),
1070 SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
1071 unsigned BROpc = getBCCForSetCC(CC);
1073 bool isFP = MVT::isFloatingPoint(N->getValueType(0));
1074 unsigned SelectCCOp;
1075 if (N->getValueType(0) == MVT::i32)
1076 SelectCCOp = PPC::SELECT_CC_I4;
1077 else if (N->getValueType(0) == MVT::i64)
1078 SelectCCOp = PPC::SELECT_CC_I8;
1079 else if (N->getValueType(0) == MVT::f32)
1080 SelectCCOp = PPC::SELECT_CC_F4;
1081 else if (N->getValueType(0) == MVT::f64)
1082 SelectCCOp = PPC::SELECT_CC_F8;
1084 SelectCCOp = PPC::SELECT_CC_VRRC;
1086 AddToISelQueue(N->getOperand(2));
1087 AddToISelQueue(N->getOperand(3));
1088 SDOperand Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
1090 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4);
1093 AddToISelQueue(N->getOperand(0));
1094 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
1095 SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
1096 SDOperand Ops[] = { CondCode, getI32Imm(getBCCForSetCC(CC)),
1097 N->getOperand(4), N->getOperand(0) };
1098 return CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other, Ops, 4);
1101 // FIXME: Should custom lower this.
1102 SDOperand Chain = N->getOperand(0);
1103 SDOperand Target = N->getOperand(1);
1104 AddToISelQueue(Chain);
1105 AddToISelQueue(Target);
1106 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
1107 Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, Target,
1109 return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain);
1111 // FIXME: These are manually selected because tblgen isn't handling varargs
1113 case PPCISD::BCTRL: return MySelect_PPCbctrl(Op);
1114 case PPCISD::CALL: return MySelect_PPCcall(Op);
1117 return SelectCode(Op);
1121 // FIXME: This is manually selected because tblgen isn't handling varargs nodes
1123 SDNode *PPCDAGToDAGISel::MySelect_PPCbctrl(SDOperand N) {
1124 SDOperand Chain(0, 0);
1127 N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag;
1129 SmallVector<SDOperand, 8> Ops;
1130 // Push varargs arguments, including optional flag.
1131 for (unsigned i = 1, e = N.getNumOperands()-hasFlag; i != e; ++i) {
1132 Chain = N.getOperand(i);
1133 AddToISelQueue(Chain);
1134 Ops.push_back(Chain);
1137 Chain = N.getOperand(0);
1138 AddToISelQueue(Chain);
1139 Ops.push_back(Chain);
1142 Chain = N.getOperand(N.getNumOperands()-1);
1143 AddToISelQueue(Chain);
1144 Ops.push_back(Chain);
1147 return CurDAG->getTargetNode(PPC::BCTRL, MVT::Other, MVT::Flag,
1148 &Ops[0], Ops.size());
1151 // FIXME: This is manually selected because tblgen isn't handling varargs nodes
1153 SDNode *PPCDAGToDAGISel::MySelect_PPCcall(SDOperand N) {
1154 SDOperand Chain(0, 0);
1156 SDOperand Tmp0(0, 0);
1158 Chain = N.getOperand(0);
1159 N1 = N.getOperand(1);
1161 // Pattern: (PPCcall:void (imm:i32):$func)
1162 // Emits: (BLA:void (imm:i32):$func)
1163 // Pattern complexity = 4 cost = 1
1164 if (N1.getOpcode() == ISD::Constant) {
1165 unsigned Tmp0C = (unsigned)cast<ConstantSDNode>(N1)->getValue();
1167 SmallVector<SDOperand, 8> Ops;
1168 Ops.push_back(CurDAG->getTargetConstant(Tmp0C, MVT::i32));
1171 N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag;
1173 // Push varargs arguments, not including optional flag.
1174 for (unsigned i = 2, e = N.getNumOperands()-hasFlag; i != e; ++i) {
1175 Chain = N.getOperand(i);
1176 AddToISelQueue(Chain);
1177 Ops.push_back(Chain);
1179 Chain = N.getOperand(0);
1180 AddToISelQueue(Chain);
1181 Ops.push_back(Chain);
1183 Chain = N.getOperand(N.getNumOperands()-1);
1184 AddToISelQueue(Chain);
1185 Ops.push_back(Chain);
1187 return CurDAG->getTargetNode(PPC::BLA, MVT::Other, MVT::Flag,
1188 &Ops[0], Ops.size());
1191 // Pattern: (PPCcall:void (tglobaladdr:i32):$dst)
1192 // Emits: (BL:void (tglobaladdr:i32):$dst)
1193 // Pattern complexity = 4 cost = 1
1194 if (N1.getOpcode() == ISD::TargetGlobalAddress) {
1195 SmallVector<SDOperand, 8> Ops;
1199 N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag;
1201 // Push varargs arguments, not including optional flag.
1202 for (unsigned i = 2, e = N.getNumOperands()-hasFlag; i != e; ++i) {
1203 Chain = N.getOperand(i);
1204 AddToISelQueue(Chain);
1205 Ops.push_back(Chain);
1207 Chain = N.getOperand(0);
1208 AddToISelQueue(Chain);
1209 Ops.push_back(Chain);
1211 Chain = N.getOperand(N.getNumOperands()-1);
1212 AddToISelQueue(Chain);
1213 Ops.push_back(Chain);
1216 return CurDAG->getTargetNode(PPC::BL, MVT::Other, MVT::Flag,
1217 &Ops[0], Ops.size());
1220 // Pattern: (PPCcall:void (texternalsym:i32):$dst)
1221 // Emits: (BL:void (texternalsym:i32):$dst)
1222 // Pattern complexity = 4 cost = 1
1223 if (N1.getOpcode() == ISD::TargetExternalSymbol) {
1224 std::vector<SDOperand> Ops;
1228 N.getOperand(N.getNumOperands()-1).getValueType() == MVT::Flag;
1230 // Push varargs arguments, not including optional flag.
1231 for (unsigned i = 2, e = N.getNumOperands()-hasFlag; i != e; ++i) {
1232 Chain = N.getOperand(i);
1233 AddToISelQueue(Chain);
1234 Ops.push_back(Chain);
1236 Chain = N.getOperand(0);
1237 AddToISelQueue(Chain);
1238 Ops.push_back(Chain);
1240 Chain = N.getOperand(N.getNumOperands()-1);
1241 AddToISelQueue(Chain);
1242 Ops.push_back(Chain);
1245 return CurDAG->getTargetNode(PPC::BL, MVT::Other, MVT::Flag,
1246 &Ops[0], Ops.size());
1248 std::cerr << "Cannot yet select: ";
1249 N.Val->dump(CurDAG);
1257 /// createPPCISelDag - This pass converts a legalized DAG into a
1258 /// PowerPC-specific DAG, ready for instruction scheduling.
1260 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
1261 return new PPCDAGToDAGISel(TM);