1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
16 #include "PPCTargetMachine.h"
17 #include "PPCISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Constants.h"
26 #include "llvm/GlobalValue.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/MathExtras.h"
32 Statistic<> FusedFP ("ppc-codegen", "Number of fused fp operations");
33 Statistic<> FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
35 //===--------------------------------------------------------------------===//
36 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
37 /// instructions for SelectionDAG operations.
39 class PPCDAGToDAGISel : public SelectionDAGISel {
40 PPCTargetLowering PPCLowering;
41 unsigned GlobalBaseReg;
43 PPCDAGToDAGISel(TargetMachine &TM)
44 : SelectionDAGISel(PPCLowering), PPCLowering(TM) {}
46 virtual bool runOnFunction(Function &Fn) {
47 // Make sure we re-emit a set of the global base reg if necessary
49 return SelectionDAGISel::runOnFunction(Fn);
52 /// getI32Imm - Return a target constant with the specified value, of type
54 inline SDOperand getI32Imm(unsigned Imm) {
55 return CurDAG->getTargetConstant(Imm, MVT::i32);
58 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
59 /// base register. Return the virtual register that holds this value.
60 SDOperand getGlobalBaseReg();
62 // Select - Convert the specified operand from a target-independent to a
63 // target-specific node if it hasn't already been changed.
64 SDOperand Select(SDOperand Op);
66 SDNode *SelectBitfieldInsert(SDNode *N);
68 /// SelectCC - Select a comparison of the specified values with the
69 /// specified condition code, returning the CR# of the expression.
70 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
72 /// SelectAddr - Given the specified address, return the two operands for a
73 /// load/store instruction, and return true if it should be an indexed [r+r]
75 bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
77 SDOperand BuildSDIVSequence(SDNode *N);
78 SDOperand BuildUDIVSequence(SDNode *N);
80 /// InstructionSelectBasicBlock - This callback is invoked by
81 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
82 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
84 virtual const char *getPassName() const {
85 return "PowerPC DAG->DAG Pattern Instruction Selection";
88 // Include the pieces autogenerated from the target description.
89 #include "PPCGenDAGISel.inc"
92 SDOperand SelectDYNAMIC_STACKALLOC(SDOperand Op);
93 SDOperand SelectADD_PARTS(SDOperand Op);
94 SDOperand SelectSUB_PARTS(SDOperand Op);
95 SDOperand SelectSETCC(SDOperand Op);
96 SDOperand SelectCALL(SDOperand Op);
100 /// InstructionSelectBasicBlock - This callback is invoked by
101 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
102 void PPCDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
105 // The selection process is inherently a bottom-up recursive process (users
106 // select their uses before themselves). Given infinite stack space, we
107 // could just start selecting on the root and traverse the whole graph. In
108 // practice however, this causes us to run out of stack space on large basic
109 // blocks. To avoid this problem, select the entry node, then all its uses,
110 // iteratively instead of recursively.
111 std::vector<SDOperand> Worklist;
112 Worklist.push_back(DAG.getEntryNode());
114 // Note that we can do this in the PPC target (scanning forward across token
115 // chain edges) because no nodes ever get folded across these edges. On a
116 // target like X86 which supports load/modify/store operations, this would
117 // have to be more careful.
118 while (!Worklist.empty()) {
119 SDOperand Node = Worklist.back();
122 // Chose from the least deep of the top two nodes.
123 if (!Worklist.empty() &&
124 Worklist.back().Val->getNodeDepth() < Node.Val->getNodeDepth())
125 std::swap(Worklist.back(), Node);
127 if ((Node.Val->getOpcode() >= ISD::BUILTIN_OP_END &&
128 Node.Val->getOpcode() < PPCISD::FIRST_NUMBER) ||
129 CodeGenMap.count(Node)) continue;
131 for (SDNode::use_iterator UI = Node.Val->use_begin(),
132 E = Node.Val->use_end(); UI != E; ++UI) {
133 // Scan the values. If this use has a value that is a token chain, add it
136 for (unsigned i = 0, e = User->getNumValues(); i != e; ++i)
137 if (User->getValueType(i) == MVT::Other) {
138 Worklist.push_back(SDOperand(User, i));
143 // Finally, legalize this node.
147 // Select target instructions for the DAG.
148 DAG.setRoot(Select(DAG.getRoot()));
150 DAG.RemoveDeadNodes();
152 // Emit machine code to BB.
153 ScheduleAndEmitDAG(DAG);
156 /// getGlobalBaseReg - Output the instructions required to put the
157 /// base address to use for accessing globals into a register.
159 SDOperand PPCDAGToDAGISel::getGlobalBaseReg() {
160 if (!GlobalBaseReg) {
161 // Insert the set of GlobalBaseReg into the first MBB of the function
162 MachineBasicBlock &FirstMBB = BB->getParent()->front();
163 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
164 SSARegMap *RegMap = BB->getParent()->getSSARegMap();
165 // FIXME: when we get to LP64, we will need to create the appropriate
166 // type of register here.
167 GlobalBaseReg = RegMap->createVirtualRegister(PPC::GPRCRegisterClass);
168 BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
169 BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
171 return CurDAG->getRegister(GlobalBaseReg, MVT::i32);
175 // isIntImmediate - This method tests to see if a constant operand.
176 // If so Imm will receive the 32 bit value.
177 static bool isIntImmediate(SDNode *N, unsigned& Imm) {
178 if (N->getOpcode() == ISD::Constant) {
179 Imm = cast<ConstantSDNode>(N)->getValue();
185 // isOprShiftImm - Returns true if the specified operand is a shift opcode with
186 // a immediate shift count less than 32.
187 static bool isOprShiftImm(SDNode *N, unsigned& Opc, unsigned& SH) {
188 Opc = N->getOpcode();
189 return (Opc == ISD::SHL || Opc == ISD::SRL || Opc == ISD::SRA) &&
190 isIntImmediate(N->getOperand(1).Val, SH) && SH < 32;
193 // isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s with
194 // any number of 0s on either side. The 1s are allowed to wrap from LSB to
195 // MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is
196 // not, since all 1s are not contiguous.
197 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
198 if (isShiftedMask_32(Val)) {
199 // look for the first non-zero bit
200 MB = CountLeadingZeros_32(Val);
201 // look for the first zero bit after the run of ones
202 ME = CountLeadingZeros_32((Val - 1) ^ Val);
205 Val = ~Val; // invert mask
206 if (isShiftedMask_32(Val)) {
207 // effectively look for the first zero bit
208 ME = CountLeadingZeros_32(Val) - 1;
209 // effectively look for the first one bit after the run of zeros
210 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
218 // isRotateAndMask - Returns true if Mask and Shift can be folded into a rotate
219 // and mask opcode and mask operation.
220 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
221 unsigned &SH, unsigned &MB, unsigned &ME) {
222 // Don't even go down this path for i64, since different logic will be
223 // necessary for rldicl/rldicr/rldimi.
224 if (N->getValueType(0) != MVT::i32)
228 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
229 unsigned Opcode = N->getOpcode();
230 if (N->getNumOperands() != 2 ||
231 !isIntImmediate(N->getOperand(1).Val, Shift) || (Shift > 31))
234 if (Opcode == ISD::SHL) {
235 // apply shift left to mask if it comes first
236 if (IsShiftMask) Mask = Mask << Shift;
237 // determine which bits are made indeterminant by shift
238 Indeterminant = ~(0xFFFFFFFFu << Shift);
239 } else if (Opcode == ISD::SRL) {
240 // apply shift right to mask if it comes first
241 if (IsShiftMask) Mask = Mask >> Shift;
242 // determine which bits are made indeterminant by shift
243 Indeterminant = ~(0xFFFFFFFFu >> Shift);
244 // adjust for the left rotate
250 // if the mask doesn't intersect any Indeterminant bits
251 if (Mask && !(Mask & Indeterminant)) {
253 // make sure the mask is still a mask (wrap arounds may not be)
254 return isRunOfOnes(Mask, MB, ME);
259 // isOpcWithIntImmediate - This method tests to see if the node is a specific
260 // opcode and that it has a immediate integer right operand.
261 // If so Imm will receive the 32 bit value.
262 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
263 return N->getOpcode() == Opc && isIntImmediate(N->getOperand(1).Val, Imm);
266 // isOprNot - Returns true if the specified operand is an xor with immediate -1.
267 static bool isOprNot(SDNode *N) {
269 return isOpcWithIntImmediate(N, ISD::XOR, Imm) && (signed)Imm == -1;
272 // Immediate constant composers.
273 // Lo16 - grabs the lo 16 bits from a 32 bit constant.
274 // Hi16 - grabs the hi 16 bits from a 32 bit constant.
275 // HA16 - computes the hi bits required if the lo bits are add/subtracted in
277 static unsigned Lo16(unsigned x) { return x & 0x0000FFFF; }
278 static unsigned Hi16(unsigned x) { return Lo16(x >> 16); }
279 static unsigned HA16(unsigned x) { return Hi16((signed)x - (signed short)x); }
281 // isIntImmediate - This method tests to see if a constant operand.
282 // If so Imm will receive the 32 bit value.
283 static bool isIntImmediate(SDOperand N, unsigned& Imm) {
284 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
285 Imm = (unsigned)CN->getSignExtended();
291 /// SelectBitfieldInsert - turn an or of two masked values into
292 /// the rotate left word immediate then mask insert (rlwimi) instruction.
293 /// Returns true on success, false if the caller still needs to select OR.
295 /// Patterns matched:
296 /// 1. or shl, and 5. or and, and
297 /// 2. or and, shl 6. or shl, shr
298 /// 3. or shr, and 7. or shr, shl
300 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
301 bool IsRotate = false;
302 unsigned TgtMask = 0xFFFFFFFF, InsMask = 0xFFFFFFFF, SH = 0;
305 SDOperand Op0 = N->getOperand(0);
306 SDOperand Op1 = N->getOperand(1);
308 unsigned Op0Opc = Op0.getOpcode();
309 unsigned Op1Opc = Op1.getOpcode();
311 // Verify that we have the correct opcodes
312 if (ISD::SHL != Op0Opc && ISD::SRL != Op0Opc && ISD::AND != Op0Opc)
314 if (ISD::SHL != Op1Opc && ISD::SRL != Op1Opc && ISD::AND != Op1Opc)
317 // Generate Mask value for Target
318 if (isIntImmediate(Op0.getOperand(1), Value)) {
320 case ISD::SHL: TgtMask <<= Value; break;
321 case ISD::SRL: TgtMask >>= Value; break;
322 case ISD::AND: TgtMask &= Value; break;
328 // Generate Mask value for Insert
329 if (!isIntImmediate(Op1.getOperand(1), Value))
336 if (Op0Opc == ISD::SRL) IsRotate = true;
342 if (Op0Opc == ISD::SHL) IsRotate = true;
349 // If both of the inputs are ANDs and one of them has a logical shift by
350 // constant as its input, make that AND the inserted value so that we can
351 // combine the shift into the rotate part of the rlwimi instruction
352 bool IsAndWithShiftOp = false;
353 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
354 if (Op1.getOperand(0).getOpcode() == ISD::SHL ||
355 Op1.getOperand(0).getOpcode() == ISD::SRL) {
356 if (isIntImmediate(Op1.getOperand(0).getOperand(1), Value)) {
357 SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value;
358 IsAndWithShiftOp = true;
360 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
361 Op0.getOperand(0).getOpcode() == ISD::SRL) {
362 if (isIntImmediate(Op0.getOperand(0).getOperand(1), Value)) {
364 std::swap(TgtMask, InsMask);
365 SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value;
366 IsAndWithShiftOp = true;
371 // Verify that the Target mask and Insert mask together form a full word mask
372 // and that the Insert mask is a run of set bits (which implies both are runs
373 // of set bits). Given that, Select the arguments and generate the rlwimi
376 if (((TgtMask & InsMask) == 0) && isRunOfOnes(InsMask, MB, ME)) {
377 bool fullMask = (TgtMask ^ InsMask) == 0xFFFFFFFF;
378 bool Op0IsAND = Op0Opc == ISD::AND;
379 // Check for rotlwi / rotrwi here, a special case of bitfield insert
380 // where both bitfield halves are sourced from the same value.
381 if (IsRotate && fullMask &&
382 N->getOperand(0).getOperand(0) == N->getOperand(1).getOperand(0)) {
383 Op0 = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32,
384 Select(N->getOperand(0).getOperand(0)),
385 getI32Imm(SH), getI32Imm(0), getI32Imm(31));
388 SDOperand Tmp1 = (Op0IsAND && fullMask) ? Select(Op0.getOperand(0))
390 SDOperand Tmp2 = IsAndWithShiftOp ? Select(Op1.getOperand(0).getOperand(0))
391 : Select(Op1.getOperand(0));
392 Op0 = CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2,
393 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
399 /// SelectAddr - Given the specified address, return the two operands for a
400 /// load/store instruction, and return true if it should be an indexed [r+r]
402 bool PPCDAGToDAGISel::SelectAddr(SDOperand Addr, SDOperand &Op1,
405 if (Addr.getOpcode() == ISD::ADD) {
406 if (isIntImmediate(Addr.getOperand(1), imm) && isInt16(imm)) {
407 Op1 = getI32Imm(Lo16(imm));
408 if (FrameIndexSDNode *FI =
409 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
411 Op2 = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
413 Op2 = Select(Addr.getOperand(0));
416 } else if (Addr.getOperand(1).getOpcode() == PPCISD::Lo) {
417 // Match LOAD (ADD (X, Lo(G))).
418 assert(!cast<ConstantSDNode>(Addr.getOperand(1).getOperand(1))->getValue()
419 && "Cannot handle constant offsets yet!");
420 Op1 = Addr.getOperand(1).getOperand(0); // The global address.
421 assert(Op1.getOpcode() == ISD::TargetGlobalAddress);
422 Op2 = Select(Addr.getOperand(0));
423 return false; // [&g+r]
425 Op1 = Select(Addr.getOperand(0));
426 Op2 = Select(Addr.getOperand(1));
427 return true; // [r+r]
431 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Addr)) {
433 Op2 = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
435 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Addr)) {
438 Op2 = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),Op1);
440 Op2 = CurDAG->getTargetNode(PPC::LIS, MVT::i32, Op1);
448 /// SelectCC - Select a comparison of the specified values with the specified
449 /// condition code, returning the CR# of the expression.
450 SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
452 // Always select the LHS.
455 // Use U to determine whether the SETCC immediate range is signed or not.
456 if (MVT::isInteger(LHS.getValueType())) {
457 bool U = ISD::isUnsignedIntSetCC(CC);
459 if (isIntImmediate(RHS, Imm) &&
460 ((U && isUInt16(Imm)) || (!U && isInt16(Imm))))
461 return CurDAG->getTargetNode(U ? PPC::CMPLWI : PPC::CMPWI, MVT::i32,
462 LHS, getI32Imm(Lo16(Imm)));
463 return CurDAG->getTargetNode(U ? PPC::CMPLW : PPC::CMPW, MVT::i32,
465 } else if (LHS.getValueType() == MVT::f32) {
466 return CurDAG->getTargetNode(PPC::FCMPUS, MVT::i32, LHS, Select(RHS));
468 return CurDAG->getTargetNode(PPC::FCMPUD, MVT::i32, LHS, Select(RHS));
472 /// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding
474 static unsigned getBCCForSetCC(ISD::CondCode CC) {
476 default: assert(0 && "Unknown condition!"); abort();
477 case ISD::SETOEQ: // FIXME: This is incorrect see PR642.
478 case ISD::SETEQ: return PPC::BEQ;
479 case ISD::SETONE: // FIXME: This is incorrect see PR642.
480 case ISD::SETNE: return PPC::BNE;
481 case ISD::SETOLT: // FIXME: This is incorrect see PR642.
483 case ISD::SETLT: return PPC::BLT;
484 case ISD::SETOLE: // FIXME: This is incorrect see PR642.
486 case ISD::SETLE: return PPC::BLE;
487 case ISD::SETOGT: // FIXME: This is incorrect see PR642.
489 case ISD::SETGT: return PPC::BGT;
490 case ISD::SETOGE: // FIXME: This is incorrect see PR642.
492 case ISD::SETGE: return PPC::BGE;
494 case ISD::SETO: return PPC::BUN;
495 case ISD::SETUO: return PPC::BNU;
500 /// getCRIdxForSetCC - Return the index of the condition register field
501 /// associated with the SetCC condition, and whether or not the field is
502 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
503 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool& Inv) {
505 default: assert(0 && "Unknown condition!"); abort();
506 case ISD::SETOLT: // FIXME: This is incorrect see PR642.
508 case ISD::SETLT: Inv = false; return 0;
509 case ISD::SETOGE: // FIXME: This is incorrect see PR642.
511 case ISD::SETGE: Inv = true; return 0;
512 case ISD::SETOGT: // FIXME: This is incorrect see PR642.
514 case ISD::SETGT: Inv = false; return 1;
515 case ISD::SETOLE: // FIXME: This is incorrect see PR642.
517 case ISD::SETLE: Inv = true; return 1;
518 case ISD::SETOEQ: // FIXME: This is incorrect see PR642.
519 case ISD::SETEQ: Inv = false; return 2;
520 case ISD::SETONE: // FIXME: This is incorrect see PR642.
521 case ISD::SETNE: Inv = true; return 2;
522 case ISD::SETO: Inv = true; return 3;
523 case ISD::SETUO: Inv = false; return 3;
528 SDOperand PPCDAGToDAGISel::SelectDYNAMIC_STACKALLOC(SDOperand Op) {
531 // FIXME: We are currently ignoring the requested alignment for handling
532 // greater than the stack alignment. This will need to be revisited at some
533 // point. Align = N.getOperand(2);
534 if (!isa<ConstantSDNode>(N->getOperand(2)) ||
535 cast<ConstantSDNode>(N->getOperand(2))->getValue() != 0) {
536 std::cerr << "Cannot allocate stack object with greater alignment than"
537 << " the stack alignment yet!";
540 SDOperand Chain = Select(N->getOperand(0));
541 SDOperand Amt = Select(N->getOperand(1));
543 SDOperand R1Reg = CurDAG->getRegister(PPC::R1, MVT::i32);
545 SDOperand R1Val = CurDAG->getCopyFromReg(Chain, PPC::R1, MVT::i32);
546 Chain = R1Val.getValue(1);
548 // Subtract the amount (guaranteed to be a multiple of the stack alignment)
549 // from the stack pointer, giving us the result pointer.
550 SDOperand Result = CurDAG->getTargetNode(PPC::SUBF, MVT::i32, Amt, R1Val);
552 // Copy this result back into R1.
553 Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, R1Reg, Result);
555 // Copy this result back out of R1 to make sure we're not using the stack
556 // space without decrementing the stack pointer.
557 Result = CurDAG->getCopyFromReg(Chain, PPC::R1, MVT::i32);
559 // Finally, replace the DYNAMIC_STACKALLOC with the copyfromreg.
560 CodeGenMap[Op.getValue(0)] = Result;
561 CodeGenMap[Op.getValue(1)] = Result.getValue(1);
562 return SDOperand(Result.Val, Op.ResNo);
565 SDOperand PPCDAGToDAGISel::SelectADD_PARTS(SDOperand Op) {
567 SDOperand LHSL = Select(N->getOperand(0));
568 SDOperand LHSH = Select(N->getOperand(1));
571 bool ME = false, ZE = false;
572 if (isIntImmediate(N->getOperand(3), Imm)) {
573 ME = (signed)Imm == -1;
577 std::vector<SDOperand> Result;
578 SDOperand CarryFromLo;
579 if (isIntImmediate(N->getOperand(2), Imm) &&
580 ((signed)Imm >= -32768 || (signed)Imm < 32768)) {
581 // Codegen the low 32 bits of the add. Interestingly, there is no
582 // shifted form of add immediate carrying.
583 CarryFromLo = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
584 LHSL, getI32Imm(Imm));
586 CarryFromLo = CurDAG->getTargetNode(PPC::ADDC, MVT::i32, MVT::Flag,
587 LHSL, Select(N->getOperand(2)));
589 CarryFromLo = CarryFromLo.getValue(1);
591 // Codegen the high 32 bits, adding zero, minus one, or the full value
592 // along with the carry flag produced by addc/addic.
595 ResultHi = CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, LHSH, CarryFromLo);
597 ResultHi = CurDAG->getTargetNode(PPC::ADDME, MVT::i32, LHSH, CarryFromLo);
599 ResultHi = CurDAG->getTargetNode(PPC::ADDE, MVT::i32, LHSH,
600 Select(N->getOperand(3)), CarryFromLo);
601 Result.push_back(CarryFromLo.getValue(0));
602 Result.push_back(ResultHi);
604 CodeGenMap[Op.getValue(0)] = Result[0];
605 CodeGenMap[Op.getValue(1)] = Result[1];
606 return Result[Op.ResNo];
608 SDOperand PPCDAGToDAGISel::SelectSUB_PARTS(SDOperand Op) {
610 SDOperand LHSL = Select(N->getOperand(0));
611 SDOperand LHSH = Select(N->getOperand(1));
612 SDOperand RHSL = Select(N->getOperand(2));
613 SDOperand RHSH = Select(N->getOperand(3));
615 std::vector<SDOperand> Result;
616 Result.push_back(CurDAG->getTargetNode(PPC::SUBFC, MVT::i32, MVT::Flag,
618 Result.push_back(CurDAG->getTargetNode(PPC::SUBFE, MVT::i32, RHSH, LHSH,
619 Result[0].getValue(1)));
620 CodeGenMap[Op.getValue(0)] = Result[0];
621 CodeGenMap[Op.getValue(1)] = Result[1];
622 return Result[Op.ResNo];
625 SDOperand PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
628 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
629 if (isIntImmediate(N->getOperand(1), Imm)) {
630 // We can codegen setcc op, imm very efficiently compared to a brcond.
631 // Check for those cases here.
634 SDOperand Op = Select(N->getOperand(0));
638 Op = CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op);
639 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(27),
640 getI32Imm(5), getI32Imm(31));
641 return SDOperand(N, 0);
643 SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
645 CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1));
646 return SDOperand(N, 0);
649 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
650 getI32Imm(31), getI32Imm(31));
651 return SDOperand(N, 0);
653 SDOperand T = CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op);
654 T = CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op);;
655 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, T, getI32Imm(1),
656 getI32Imm(31), getI32Imm(31));
657 return SDOperand(N, 0);
660 } else if (Imm == ~0U) { // setcc op, -1
661 SDOperand Op = Select(N->getOperand(0));
665 Op = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
667 CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
668 CurDAG->getTargetNode(PPC::LI, MVT::i32,
671 return SDOperand(N, 0);
673 Op = CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op);
674 SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
676 CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1));
677 return SDOperand(N, 0);
680 SDOperand AD = CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
682 SDOperand AN = CurDAG->getTargetNode(PPC::AND, MVT::i32, AD, Op);
683 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, AN, getI32Imm(1),
684 getI32Imm(31), getI32Imm(31));
685 return SDOperand(N, 0);
688 Op = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
689 getI32Imm(31), getI32Imm(31));
690 CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1));
691 return SDOperand(N, 0);
697 unsigned Idx = getCRIdxForSetCC(CC, Inv);
698 SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
701 // Force the ccreg into CR7.
702 SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
704 std::vector<MVT::ValueType> VTs;
705 VTs.push_back(MVT::Other);
706 VTs.push_back(MVT::Flag); // NONSTANDARD CopyToReg node: defines a flag
707 std::vector<SDOperand> Ops;
708 Ops.push_back(CurDAG->getEntryNode());
709 Ops.push_back(CR7Reg);
710 Ops.push_back(CCReg);
711 CCReg = CurDAG->getNode(ISD::CopyToReg, VTs, Ops).getValue(1);
713 if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
714 IntCR = CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg, CCReg);
716 IntCR = CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg);
719 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, IntCR,
720 getI32Imm((32-(3-Idx)) & 31),
721 getI32Imm(31), getI32Imm(31));
724 CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, IntCR,
725 getI32Imm((32-(3-Idx)) & 31),
726 getI32Imm(31),getI32Imm(31));
727 CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
730 return SDOperand(N, 0);
733 /// isCallCompatibleAddress - Return true if the specified 32-bit value is
734 /// representable in the immediate field of a Bx instruction.
735 static bool isCallCompatibleAddress(ConstantSDNode *C) {
736 int Addr = C->getValue();
737 if (Addr & 3) return false; // Low 2 bits are implicitly zero.
738 return (Addr << 6 >> 6) == Addr; // Top 6 bits have to be sext of immediate.
741 SDOperand PPCDAGToDAGISel::SelectCALL(SDOperand Op) {
743 SDOperand Chain = Select(N->getOperand(0));
746 std::vector<SDOperand> CallOperands;
748 if (GlobalAddressSDNode *GASD =
749 dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
750 CallOpcode = PPC::BL;
751 CallOperands.push_back(N->getOperand(1));
752 } else if (ExternalSymbolSDNode *ESSDN =
753 dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) {
754 CallOpcode = PPC::BL;
755 CallOperands.push_back(N->getOperand(1));
756 } else if (isa<ConstantSDNode>(N->getOperand(1)) &&
757 isCallCompatibleAddress(cast<ConstantSDNode>(N->getOperand(1)))) {
758 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(1));
759 CallOpcode = PPC::BLA;
760 CallOperands.push_back(getI32Imm((int)C->getValue() >> 2));
762 // Copy the callee address into the CTR register.
763 SDOperand Callee = Select(N->getOperand(1));
764 Chain = CurDAG->getTargetNode(PPC::MTCTR, MVT::Other, Callee, Chain);
766 // Copy the callee address into R12 on darwin.
767 SDOperand R12 = CurDAG->getRegister(PPC::R12, MVT::i32);
768 Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, R12, Callee);
770 CallOperands.push_back(R12);
771 CallOpcode = PPC::BCTRL;
774 unsigned GPR_idx = 0, FPR_idx = 0;
775 static const unsigned GPR[] = {
776 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
777 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
779 static const unsigned FPR[] = {
780 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
781 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
784 SDOperand InFlag; // Null incoming flag value.
786 for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i) {
787 unsigned DestReg = 0;
788 MVT::ValueType RegTy = N->getOperand(i).getValueType();
789 if (RegTy == MVT::i32) {
790 assert(GPR_idx < 8 && "Too many int args");
791 DestReg = GPR[GPR_idx++];
793 assert(MVT::isFloatingPoint(N->getOperand(i).getValueType()) &&
794 "Unpromoted integer arg?");
795 assert(FPR_idx < 13 && "Too many fp args");
796 DestReg = FPR[FPR_idx++];
799 if (N->getOperand(i).getOpcode() != ISD::UNDEF) {
800 SDOperand Val = Select(N->getOperand(i));
801 Chain = CurDAG->getCopyToReg(Chain, DestReg, Val, InFlag);
802 InFlag = Chain.getValue(1);
803 CallOperands.push_back(CurDAG->getRegister(DestReg, RegTy));
807 // Finally, once everything is in registers to pass to the call, emit the
810 CallOperands.push_back(InFlag); // Strong dep on register copies.
812 CallOperands.push_back(Chain); // Weak dep on whatever occurs before
813 Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
816 std::vector<SDOperand> CallResults;
818 // If the call has results, copy the values out of the ret val registers.
819 switch (N->getValueType(0)) {
820 default: assert(0 && "Unexpected ret value!");
821 case MVT::Other: break;
823 if (N->getValueType(1) == MVT::i32) {
824 Chain = CurDAG->getCopyFromReg(Chain, PPC::R4, MVT::i32,
825 Chain.getValue(1)).getValue(1);
826 CallResults.push_back(Chain.getValue(0));
827 Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32,
828 Chain.getValue(2)).getValue(1);
829 CallResults.push_back(Chain.getValue(0));
831 Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32,
832 Chain.getValue(1)).getValue(1);
833 CallResults.push_back(Chain.getValue(0));
838 Chain = CurDAG->getCopyFromReg(Chain, PPC::F1, N->getValueType(0),
839 Chain.getValue(1)).getValue(1);
840 CallResults.push_back(Chain.getValue(0));
844 CallResults.push_back(Chain);
845 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
846 CodeGenMap[Op.getValue(i)] = CallResults[i];
847 return CallResults[Op.ResNo];
850 // Select - Convert the specified operand from a target-independent to a
851 // target-specific node if it hasn't already been changed.
852 SDOperand PPCDAGToDAGISel::Select(SDOperand Op) {
854 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
855 N->getOpcode() < PPCISD::FIRST_NUMBER)
856 return Op; // Already selected.
858 // If this has already been converted, use it.
859 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
860 if (CGMI != CodeGenMap.end()) return CGMI->second;
862 switch (N->getOpcode()) {
864 case ISD::DYNAMIC_STACKALLOC: return SelectDYNAMIC_STACKALLOC(Op);
865 case ISD::ADD_PARTS: return SelectADD_PARTS(Op);
866 case ISD::SUB_PARTS: return SelectSUB_PARTS(Op);
867 case ISD::SETCC: return SelectSETCC(Op);
868 case ISD::CALL: return SelectCALL(Op);
869 case ISD::TAILCALL: return SelectCALL(Op);
870 case PPCISD::GlobalBaseReg: return getGlobalBaseReg();
872 case ISD::FrameIndex: {
873 int FI = cast<FrameIndexSDNode>(N)->getIndex();
874 if (N->hasOneUse()) {
875 CurDAG->SelectNodeTo(N, PPC::ADDI, MVT::i32,
876 CurDAG->getTargetFrameIndex(FI, MVT::i32),
878 return SDOperand(N, 0);
880 return CurDAG->getTargetNode(PPC::ADDI, MVT::i32,
881 CurDAG->getTargetFrameIndex(FI, MVT::i32),
884 case ISD::ConstantPool: {
885 Constant *C = cast<ConstantPoolSDNode>(N)->get();
886 SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i32);
888 Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),CPI);
890 Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, CPI);
891 if (N->hasOneUse()) {
892 CurDAG->SelectNodeTo(N, PPC::LA, MVT::i32, Tmp, CPI);
893 return SDOperand(N, 0);
895 return CurDAG->getTargetNode(PPC::LA, MVT::i32, Tmp, CPI);
898 MVT::ValueType Ty = N->getValueType(0);
899 if (!NoExcessFPPrecision) { // Match FMA ops
900 if (N->getOperand(0).getOpcode() == ISD::FMUL &&
901 N->getOperand(0).Val->hasOneUse()) {
902 ++FusedFP; // Statistic
903 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMADD : PPC::FMADDS, Ty,
904 Select(N->getOperand(0).getOperand(0)),
905 Select(N->getOperand(0).getOperand(1)),
906 Select(N->getOperand(1)));
907 return SDOperand(N, 0);
908 } else if (N->getOperand(1).getOpcode() == ISD::FMUL &&
909 N->getOperand(1).hasOneUse()) {
910 ++FusedFP; // Statistic
911 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMADD : PPC::FMADDS, Ty,
912 Select(N->getOperand(1).getOperand(0)),
913 Select(N->getOperand(1).getOperand(1)),
914 Select(N->getOperand(0)));
915 return SDOperand(N, 0);
919 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FADD : PPC::FADDS, Ty,
920 Select(N->getOperand(0)), Select(N->getOperand(1)));
921 return SDOperand(N, 0);
924 MVT::ValueType Ty = N->getValueType(0);
926 if (!NoExcessFPPrecision) { // Match FMA ops
927 if (N->getOperand(0).getOpcode() == ISD::FMUL &&
928 N->getOperand(0).Val->hasOneUse()) {
929 ++FusedFP; // Statistic
930 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMSUB : PPC::FMSUBS, Ty,
931 Select(N->getOperand(0).getOperand(0)),
932 Select(N->getOperand(0).getOperand(1)),
933 Select(N->getOperand(1)));
934 return SDOperand(N, 0);
935 } else if (N->getOperand(1).getOpcode() == ISD::FMUL &&
936 N->getOperand(1).Val->hasOneUse()) {
937 ++FusedFP; // Statistic
938 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FNMSUB : PPC::FNMSUBS, Ty,
939 Select(N->getOperand(1).getOperand(0)),
940 Select(N->getOperand(1).getOperand(1)),
941 Select(N->getOperand(0)));
942 return SDOperand(N, 0);
945 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FSUB : PPC::FSUBS, Ty,
946 Select(N->getOperand(0)),
947 Select(N->getOperand(1)));
948 return SDOperand(N, 0);
951 // FIXME: since this depends on the setting of the carry flag from the srawi
952 // we should really be making notes about that for the scheduler.
953 // FIXME: It sure would be nice if we could cheaply recognize the
954 // srl/add/sra pattern the dag combiner will generate for this as
955 // sra/addze rather than having to handle sdiv ourselves. oh well.
957 if (isIntImmediate(N->getOperand(1), Imm)) {
958 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
960 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
961 Select(N->getOperand(0)),
962 getI32Imm(Log2_32(Imm)));
963 CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
964 Op.getValue(0), Op.getValue(1));
965 return SDOperand(N, 0);
966 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
968 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
969 Select(N->getOperand(0)),
970 getI32Imm(Log2_32(-Imm)));
972 CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, Op.getValue(0),
974 CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
975 return SDOperand(N, 0);
979 // Other cases are autogenerated.
984 // If this is an and of a value rotated between 0 and 31 bits and then and'd
985 // with a mask, emit rlwinm
986 if (isIntImmediate(N->getOperand(1), Imm) && (isShiftedMask_32(Imm) ||
987 isShiftedMask_32(~Imm))) {
990 if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
991 Val = Select(N->getOperand(0).getOperand(0));
992 } else if (Imm == 0) {
993 // AND X, 0 -> 0, not "rlwinm 32".
994 return Select(N->getOperand(1));
996 Val = Select(N->getOperand(0));
997 isRunOfOnes(Imm, MB, ME);
1000 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Val, getI32Imm(SH),
1001 getI32Imm(MB), getI32Imm(ME));
1002 return SDOperand(N, 0);
1005 // Other cases are autogenerated.
1009 if (SDNode *I = SelectBitfieldInsert(N))
1010 return CodeGenMap[Op] = SDOperand(I, 0);
1012 // Other cases are autogenerated.
1015 unsigned Imm, SH, MB, ME;
1016 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
1017 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1018 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
1019 Select(N->getOperand(0).getOperand(0)),
1020 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
1021 return SDOperand(N, 0);
1024 // Other cases are autogenerated.
1028 unsigned Imm, SH, MB, ME;
1029 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
1030 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1031 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
1032 Select(N->getOperand(0).getOperand(0)),
1033 getI32Imm(SH & 0x1F), getI32Imm(MB), getI32Imm(ME));
1034 return SDOperand(N, 0);
1037 // Other cases are autogenerated.
1041 SDOperand Val = Select(N->getOperand(0));
1042 MVT::ValueType Ty = N->getValueType(0);
1043 if (N->getOperand(0).Val->hasOneUse()) {
1045 switch (Val.isTargetOpcode() ? Val.getTargetOpcode() : 0) {
1046 default: Opc = 0; break;
1047 case PPC::FABSS: Opc = PPC::FNABSS; break;
1048 case PPC::FABSD: Opc = PPC::FNABSD; break;
1049 case PPC::FMADD: Opc = PPC::FNMADD; break;
1050 case PPC::FMADDS: Opc = PPC::FNMADDS; break;
1051 case PPC::FMSUB: Opc = PPC::FNMSUB; break;
1052 case PPC::FMSUBS: Opc = PPC::FNMSUBS; break;
1054 // If we inverted the opcode, then emit the new instruction with the
1055 // inverted opcode and the original instruction's operands. Otherwise,
1056 // fall through and generate a fneg instruction.
1058 if (Opc == PPC::FNABSS || Opc == PPC::FNABSD)
1059 CurDAG->SelectNodeTo(N, Opc, Ty, Val.getOperand(0));
1061 CurDAG->SelectNodeTo(N, Opc, Ty, Val.getOperand(0),
1062 Val.getOperand(1), Val.getOperand(2));
1063 return SDOperand(N, 0);
1067 CurDAG->SelectNodeTo(N, PPC::FNEGS, MVT::f32, Val);
1069 CurDAG->SelectNodeTo(N, PPC::FNEGD, MVT::f64, Val);
1070 return SDOperand(N, 0);
1075 case ISD::SEXTLOAD: {
1077 bool isIdx = SelectAddr(N->getOperand(1), Op1, Op2);
1079 MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ?
1080 N->getValueType(0) : cast<VTSDNode>(N->getOperand(3))->getVT();
1082 switch (TypeBeingLoaded) {
1083 default: N->dump(); assert(0 && "Cannot load this type!");
1085 case MVT::i8: Opc = isIdx ? PPC::LBZX : PPC::LBZ; break;
1087 if (N->getOpcode() == ISD::SEXTLOAD) { // SEXT load?
1088 Opc = isIdx ? PPC::LHAX : PPC::LHA;
1090 Opc = isIdx ? PPC::LHZX : PPC::LHZ;
1093 case MVT::i32: Opc = isIdx ? PPC::LWZX : PPC::LWZ; break;
1094 case MVT::f32: Opc = isIdx ? PPC::LFSX : PPC::LFS; break;
1095 case MVT::f64: Opc = isIdx ? PPC::LFDX : PPC::LFD; break;
1098 // If this is an f32 -> f64 load, emit the f32 load, then use an 'extending
1100 if (TypeBeingLoaded != MVT::f32 || N->getOpcode() == ISD::LOAD) {
1101 CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
1102 Op1, Op2, Select(N->getOperand(0)));
1103 return SDOperand(N, Op.ResNo);
1105 std::vector<SDOperand> Ops;
1108 Ops.push_back(Select(N->getOperand(0)));
1109 SDOperand Res = CurDAG->getTargetNode(Opc, MVT::f32, MVT::Other, Ops);
1110 SDOperand Ext = CurDAG->getTargetNode(PPC::FMRSD, MVT::f64, Res);
1111 CodeGenMap[Op.getValue(0)] = Ext;
1112 CodeGenMap[Op.getValue(1)] = Res.getValue(1);
1114 return Res.getValue(1);
1119 case ISD::TRUNCSTORE:
1121 SDOperand AddrOp1, AddrOp2;
1122 bool isIdx = SelectAddr(N->getOperand(2), AddrOp1, AddrOp2);
1125 if (N->getOpcode() == ISD::STORE) {
1126 switch (N->getOperand(1).getValueType()) {
1127 default: assert(0 && "unknown Type in store");
1128 case MVT::i32: Opc = isIdx ? PPC::STWX : PPC::STW; break;
1129 case MVT::f64: Opc = isIdx ? PPC::STFDX : PPC::STFD; break;
1130 case MVT::f32: Opc = isIdx ? PPC::STFSX : PPC::STFS; break;
1132 } else { //ISD::TRUNCSTORE
1133 switch(cast<VTSDNode>(N->getOperand(4))->getVT()) {
1134 default: assert(0 && "unknown Type in store");
1135 case MVT::i8: Opc = isIdx ? PPC::STBX : PPC::STB; break;
1136 case MVT::i16: Opc = isIdx ? PPC::STHX : PPC::STH; break;
1140 CurDAG->SelectNodeTo(N, Opc, MVT::Other, Select(N->getOperand(1)),
1141 AddrOp1, AddrOp2, Select(N->getOperand(0)));
1142 return SDOperand(N, 0);
1145 case ISD::SELECT_CC: {
1146 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1148 // handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
1149 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1150 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1151 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1152 if (N1C->isNullValue() && N3C->isNullValue() &&
1153 N2C->getValue() == 1ULL && CC == ISD::SETNE) {
1154 SDOperand LHS = Select(N->getOperand(0));
1156 CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
1157 LHS, getI32Imm(~0U));
1158 CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, Tmp, LHS,
1160 return SDOperand(N, 0);
1163 SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
1164 unsigned BROpc = getBCCForSetCC(CC);
1166 bool isFP = MVT::isFloatingPoint(N->getValueType(0));
1167 unsigned SelectCCOp;
1168 if (MVT::isInteger(N->getValueType(0)))
1169 SelectCCOp = PPC::SELECT_CC_Int;
1170 else if (N->getValueType(0) == MVT::f32)
1171 SelectCCOp = PPC::SELECT_CC_F4;
1173 SelectCCOp = PPC::SELECT_CC_F8;
1174 CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), CCReg,
1175 Select(N->getOperand(2)), Select(N->getOperand(3)),
1177 return SDOperand(N, 0);
1180 case ISD::CALLSEQ_START:
1181 case ISD::CALLSEQ_END: {
1182 unsigned Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
1183 unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
1184 PPC::ADJCALLSTACKDOWN : PPC::ADJCALLSTACKUP;
1185 CurDAG->SelectNodeTo(N, Opc, MVT::Other,
1186 getI32Imm(Amt), Select(N->getOperand(0)));
1187 return SDOperand(N, 0);
1190 SDOperand Chain = Select(N->getOperand(0)); // Token chain.
1192 if (N->getNumOperands() == 2) {
1193 SDOperand Val = Select(N->getOperand(1));
1194 if (N->getOperand(1).getValueType() == MVT::i32) {
1195 Chain = CurDAG->getCopyToReg(Chain, PPC::R3, Val);
1197 assert(MVT::isFloatingPoint(N->getOperand(1).getValueType()));
1198 Chain = CurDAG->getCopyToReg(Chain, PPC::F1, Val);
1200 } else if (N->getNumOperands() > 1) {
1201 assert(N->getOperand(1).getValueType() == MVT::i32 &&
1202 N->getOperand(2).getValueType() == MVT::i32 &&
1203 N->getNumOperands() == 3 && "Unknown two-register ret value!");
1204 Chain = CurDAG->getCopyToReg(Chain, PPC::R4, Select(N->getOperand(1)));
1205 Chain = CurDAG->getCopyToReg(Chain, PPC::R3, Select(N->getOperand(2)));
1208 // Finally, select this to a blr (return) instruction.
1209 CurDAG->SelectNodeTo(N, PPC::BLR, MVT::Other, Chain);
1210 return SDOperand(N, 0);
1213 CurDAG->SelectNodeTo(N, PPC::B, MVT::Other, N->getOperand(1),
1214 Select(N->getOperand(0)));
1215 return SDOperand(N, 0);
1217 case ISD::BRTWOWAY_CC: {
1218 SDOperand Chain = Select(N->getOperand(0));
1219 MachineBasicBlock *Dest =
1220 cast<BasicBlockSDNode>(N->getOperand(4))->getBasicBlock();
1221 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
1222 SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
1224 // If this is a two way branch, then grab the fallthrough basic block
1225 // argument and build a PowerPC branch pseudo-op, suitable for long branch
1226 // conversion if necessary by the branch selection pass. Otherwise, emit a
1227 // standard conditional branch.
1228 if (N->getOpcode() == ISD::BRTWOWAY_CC) {
1229 SDOperand CondTrueBlock = N->getOperand(4);
1230 SDOperand CondFalseBlock = N->getOperand(5);
1232 // If the false case is the current basic block, then this is a self loop.
1233 // We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an
1234 // extra dispatch group to the loop. Instead, invert the condition and
1235 // emit "Loop: ... br!cond Loop; br Out
1236 if (cast<BasicBlockSDNode>(CondFalseBlock)->getBasicBlock() == BB) {
1237 std::swap(CondTrueBlock, CondFalseBlock);
1238 CC = getSetCCInverse(CC,
1239 MVT::isInteger(N->getOperand(2).getValueType()));
1242 unsigned Opc = getBCCForSetCC(CC);
1243 SDOperand CB = CurDAG->getTargetNode(PPC::COND_BRANCH, MVT::Other,
1244 CondCode, getI32Imm(Opc),
1245 CondTrueBlock, CondFalseBlock,
1247 CurDAG->SelectNodeTo(N, PPC::B, MVT::Other, CondFalseBlock, CB);
1249 // Iterate to the next basic block
1250 ilist<MachineBasicBlock>::iterator It = BB;
1253 // If the fallthrough path is off the end of the function, which would be
1254 // undefined behavior, set it to be the same as the current block because
1255 // we have nothing better to set it to, and leaving it alone will cause
1256 // the PowerPC Branch Selection pass to crash.
1257 if (It == BB->getParent()->end()) It = Dest;
1258 CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other, CondCode,
1259 getI32Imm(getBCCForSetCC(CC)), N->getOperand(4),
1260 CurDAG->getBasicBlock(It), Chain);
1262 return SDOperand(N, 0);
1266 return SelectCode(Op);
1270 /// createPPCISelDag - This pass converts a legalized DAG into a
1271 /// PowerPC-specific DAG, ready for instruction scheduling.
1273 FunctionPass *llvm::createPPCISelDag(TargetMachine &TM) {
1274 return new PPCDAGToDAGISel(TM);