1 //===-- PPC32ISelDAGToDAG.cpp - PPC32 pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for 32 bit PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
16 #include "PPC32TargetMachine.h"
17 #include "PPC32ISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Constants.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/MathExtras.h"
33 Statistic<> FusedFP ("ppc-codegen", "Number of fused fp operations");
34 Statistic<> FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
36 //===--------------------------------------------------------------------===//
37 /// PPC32DAGToDAGISel - PPC32 specific code to select PPC32 machine
38 /// instructions for SelectionDAG operations.
40 class PPC32DAGToDAGISel : public SelectionDAGISel {
41 PPC32TargetLowering PPC32Lowering;
42 unsigned GlobalBaseReg;
44 PPC32DAGToDAGISel(TargetMachine &TM)
45 : SelectionDAGISel(PPC32Lowering), PPC32Lowering(TM) {}
47 virtual bool runOnFunction(Function &Fn) {
48 // Make sure we re-emit a set of the global base reg if necessary
50 return SelectionDAGISel::runOnFunction(Fn);
53 /// getI32Imm - Return a target constant with the specified value, of type
55 inline SDOperand getI32Imm(unsigned Imm) {
56 return CurDAG->getTargetConstant(Imm, MVT::i32);
59 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
60 /// base register. Return the virtual register that holds this value.
61 SDOperand getGlobalBaseReg();
63 // Select - Convert the specified operand from a target-independent to a
64 // target-specific node if it hasn't already been changed.
65 SDOperand Select(SDOperand Op);
67 SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
68 unsigned OCHi, unsigned OCLo,
69 bool IsArithmetic = false,
71 SDNode *SelectBitfieldInsert(SDNode *N);
73 /// SelectCC - Select a comparison of the specified values with the
74 /// specified condition code, returning the CR# of the expression.
75 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
77 /// SelectAddr - Given the specified address, return the two operands for a
78 /// load/store instruction, and return true if it should be an indexed [r+r]
80 bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
82 SDOperand BuildSDIVSequence(SDNode *N);
83 SDOperand BuildUDIVSequence(SDNode *N);
85 /// InstructionSelectBasicBlock - This callback is invoked by
86 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
87 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
89 // Select target instructions for the DAG.
90 DAG.setRoot(Select(DAG.getRoot()));
91 DAG.RemoveDeadNodes();
93 // Emit machine code to BB.
94 ScheduleAndEmitDAG(DAG);
97 virtual const char *getPassName() const {
98 return "PowerPC DAG->DAG Pattern Instruction Selection";
103 /// getGlobalBaseReg - Output the instructions required to put the
104 /// base address to use for accessing globals into a register.
106 SDOperand PPC32DAGToDAGISel::getGlobalBaseReg() {
107 if (!GlobalBaseReg) {
108 // Insert the set of GlobalBaseReg into the first MBB of the function
109 MachineBasicBlock &FirstMBB = BB->getParent()->front();
110 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
111 SSARegMap *RegMap = BB->getParent()->getSSARegMap();
112 GlobalBaseReg = RegMap->createVirtualRegister(PPC32::GPRCRegisterClass);
113 BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
114 BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
116 return CurDAG->getRegister(GlobalBaseReg, MVT::i32);
120 // isIntImmediate - This method tests to see if a constant operand.
121 // If so Imm will receive the 32 bit value.
122 static bool isIntImmediate(SDNode *N, unsigned& Imm) {
123 if (N->getOpcode() == ISD::Constant) {
124 Imm = cast<ConstantSDNode>(N)->getValue();
130 // isOprShiftImm - Returns true if the specified operand is a shift opcode with
131 // a immediate shift count less than 32.
132 static bool isOprShiftImm(SDNode *N, unsigned& Opc, unsigned& SH) {
133 Opc = N->getOpcode();
134 return (Opc == ISD::SHL || Opc == ISD::SRL || Opc == ISD::SRA) &&
135 isIntImmediate(N->getOperand(1).Val, SH) && SH < 32;
138 // isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s with
139 // any number of 0s on either side. The 1s are allowed to wrap from LSB to
140 // MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is
141 // not, since all 1s are not contiguous.
142 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
143 if (isShiftedMask_32(Val)) {
144 // look for the first non-zero bit
145 MB = CountLeadingZeros_32(Val);
146 // look for the first zero bit after the run of ones
147 ME = CountLeadingZeros_32((Val - 1) ^ Val);
150 Val = ~Val; // invert mask
151 if (isShiftedMask_32(Val)) {
152 // effectively look for the first zero bit
153 ME = CountLeadingZeros_32(Val) - 1;
154 // effectively look for the first one bit after the run of zeros
155 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
163 // isRotateAndMask - Returns true if Mask and Shift can be folded in to a rotate
164 // and mask opcode and mask operation.
165 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
166 unsigned &SH, unsigned &MB, unsigned &ME) {
168 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
169 unsigned Opcode = N->getOpcode();
170 if (!isIntImmediate(N->getOperand(1).Val, Shift) || (Shift > 31))
173 if (Opcode == ISD::SHL) {
174 // apply shift left to mask if it comes first
175 if (IsShiftMask) Mask = Mask << Shift;
176 // determine which bits are made indeterminant by shift
177 Indeterminant = ~(0xFFFFFFFFu << Shift);
178 } else if (Opcode == ISD::SRA || Opcode == ISD::SRL) {
179 // apply shift right to mask if it comes first
180 if (IsShiftMask) Mask = Mask >> Shift;
181 // determine which bits are made indeterminant by shift
182 Indeterminant = ~(0xFFFFFFFFu >> Shift);
183 // adjust for the left rotate
189 // if the mask doesn't intersect any Indeterminant bits
190 if (Mask && !(Mask & Indeterminant)) {
192 // make sure the mask is still a mask (wrap arounds may not be)
193 return isRunOfOnes(Mask, MB, ME);
198 // isOpcWithIntImmediate - This method tests to see if the node is a specific
199 // opcode and that it has a immediate integer right operand.
200 // If so Imm will receive the 32 bit value.
201 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
202 return N->getOpcode() == Opc && isIntImmediate(N->getOperand(1).Val, Imm);
205 // isOprNot - Returns true if the specified operand is an xor with immediate -1.
206 static bool isOprNot(SDNode *N) {
208 return isOpcWithIntImmediate(N, ISD::XOR, Imm) && (signed)Imm == -1;
211 // Immediate constant composers.
212 // Lo16 - grabs the lo 16 bits from a 32 bit constant.
213 // Hi16 - grabs the hi 16 bits from a 32 bit constant.
214 // HA16 - computes the hi bits required if the lo bits are add/subtracted in
216 static unsigned Lo16(unsigned x) { return x & 0x0000FFFF; }
217 static unsigned Hi16(unsigned x) { return Lo16(x >> 16); }
218 static unsigned HA16(unsigned x) { return Hi16((signed)x - (signed short)x); }
220 // isIntImmediate - This method tests to see if a constant operand.
221 // If so Imm will receive the 32 bit value.
222 static bool isIntImmediate(SDOperand N, unsigned& Imm) {
223 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
224 Imm = (unsigned)CN->getSignExtended();
230 /// SelectBitfieldInsert - turn an or of two masked values into
231 /// the rotate left word immediate then mask insert (rlwimi) instruction.
232 /// Returns true on success, false if the caller still needs to select OR.
234 /// Patterns matched:
235 /// 1. or shl, and 5. or and, and
236 /// 2. or and, shl 6. or shl, shr
237 /// 3. or shr, and 7. or shr, shl
239 SDNode *PPC32DAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
240 bool IsRotate = false;
241 unsigned TgtMask = 0xFFFFFFFF, InsMask = 0xFFFFFFFF, SH = 0;
244 SDOperand Op0 = N->getOperand(0);
245 SDOperand Op1 = N->getOperand(1);
247 unsigned Op0Opc = Op0.getOpcode();
248 unsigned Op1Opc = Op1.getOpcode();
250 // Verify that we have the correct opcodes
251 if (ISD::SHL != Op0Opc && ISD::SRL != Op0Opc && ISD::AND != Op0Opc)
253 if (ISD::SHL != Op1Opc && ISD::SRL != Op1Opc && ISD::AND != Op1Opc)
256 // Generate Mask value for Target
257 if (isIntImmediate(Op0.getOperand(1), Value)) {
259 case ISD::SHL: TgtMask <<= Value; break;
260 case ISD::SRL: TgtMask >>= Value; break;
261 case ISD::AND: TgtMask &= Value; break;
267 // Generate Mask value for Insert
268 if (isIntImmediate(Op1.getOperand(1), Value)) {
273 if (Op0Opc == ISD::SRL) IsRotate = true;
279 if (Op0Opc == ISD::SHL) IsRotate = true;
289 // If both of the inputs are ANDs and one of them has a logical shift by
290 // constant as its input, make that AND the inserted value so that we can
291 // combine the shift into the rotate part of the rlwimi instruction
292 bool IsAndWithShiftOp = false;
293 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
294 if (Op1.getOperand(0).getOpcode() == ISD::SHL ||
295 Op1.getOperand(0).getOpcode() == ISD::SRL) {
296 if (isIntImmediate(Op1.getOperand(0).getOperand(1), Value)) {
297 SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value;
298 IsAndWithShiftOp = true;
300 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
301 Op0.getOperand(0).getOpcode() == ISD::SRL) {
302 if (isIntImmediate(Op0.getOperand(0).getOperand(1), Value)) {
304 std::swap(TgtMask, InsMask);
305 SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value;
306 IsAndWithShiftOp = true;
311 // Verify that the Target mask and Insert mask together form a full word mask
312 // and that the Insert mask is a run of set bits (which implies both are runs
313 // of set bits). Given that, Select the arguments and generate the rlwimi
316 if (((TgtMask & InsMask) == 0) && isRunOfOnes(InsMask, MB, ME)) {
317 bool fullMask = (TgtMask ^ InsMask) == 0xFFFFFFFF;
318 bool Op0IsAND = Op0Opc == ISD::AND;
319 // Check for rotlwi / rotrwi here, a special case of bitfield insert
320 // where both bitfield halves are sourced from the same value.
321 if (IsRotate && fullMask &&
322 N->getOperand(0).getOperand(0) == N->getOperand(1).getOperand(0)) {
323 Op0 = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32,
324 Select(N->getOperand(0).getOperand(0)),
325 getI32Imm(SH), getI32Imm(0), getI32Imm(31));
328 SDOperand Tmp1 = (Op0IsAND && fullMask) ? Select(Op0.getOperand(0))
330 SDOperand Tmp2 = IsAndWithShiftOp ? Select(Op1.getOperand(0).getOperand(0))
331 : Select(Op1.getOperand(0));
332 Op0 = CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2,
333 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
339 // SelectIntImmediateExpr - Choose code for integer operations with an immediate
341 SDNode *PPC32DAGToDAGISel::SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
342 unsigned OCHi, unsigned OCLo,
345 // Check to make sure this is a constant.
346 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(RHS);
347 // Exit if not a constant.
349 // Extract immediate.
350 unsigned C = (unsigned)CN->getValue();
351 // Negate if required (ISD::SUB).
353 // Get the hi and lo portions of constant.
354 unsigned Hi = IsArithmetic ? HA16(C) : Hi16(C);
355 unsigned Lo = Lo16(C);
357 // If two instructions are needed and usage indicates it would be better to
358 // load immediate into a register, bail out.
359 if (Hi && Lo && CN->use_size() > 2) return false;
361 // Select the first operand.
362 SDOperand Opr0 = Select(LHS);
364 if (Lo) // Add in the lo-part.
365 Opr0 = CurDAG->getTargetNode(OCLo, MVT::i32, Opr0, getI32Imm(Lo));
366 if (Hi) // Add in the hi-part.
367 Opr0 = CurDAG->getTargetNode(OCHi, MVT::i32, Opr0, getI32Imm(Hi));
371 /// SelectAddr - Given the specified address, return the two operands for a
372 /// load/store instruction, and return true if it should be an indexed [r+r]
374 bool PPC32DAGToDAGISel::SelectAddr(SDOperand Addr, SDOperand &Op1,
377 if (Addr.getOpcode() == ISD::ADD) {
378 if (isIntImmediate(Addr.getOperand(1), imm) && isInt16(imm)) {
379 Op1 = getI32Imm(Lo16(imm));
380 if (FrameIndexSDNode *FI =
381 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
383 Op2 = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
385 Op2 = Select(Addr.getOperand(0));
389 Op1 = Select(Addr.getOperand(0));
390 Op2 = Select(Addr.getOperand(1));
391 return true; // [r+r]
395 // Now check if we're dealing with a global, and whether or not we should emit
396 // an optimized load or store for statics.
397 if (GlobalAddressSDNode *GN = dyn_cast<GlobalAddressSDNode>(Addr)) {
398 GlobalValue *GV = GN->getGlobal();
399 if (!GV->hasWeakLinkage() && !GV->isExternal()) {
400 Op1 = CurDAG->getTargetGlobalAddress(GV, MVT::i32);
402 Op2 = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),
405 Op2 = CurDAG->getTargetNode(PPC::LIS, MVT::i32, Op1);
408 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Addr)) {
410 Op2 = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
412 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Addr)) {
415 Op2 = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),Op1);
417 Op2 = CurDAG->getTargetNode(PPC::LIS, MVT::i32, Op1);
425 /// SelectCC - Select a comparison of the specified values with the specified
426 /// condition code, returning the CR# of the expression.
427 SDOperand PPC32DAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
429 // Always select the LHS.
432 // Use U to determine whether the SETCC immediate range is signed or not.
433 if (MVT::isInteger(LHS.getValueType())) {
434 bool U = ISD::isUnsignedIntSetCC(CC);
436 if (isIntImmediate(RHS, Imm) &&
437 ((U && isUInt16(Imm)) || (!U && isInt16(Imm))))
438 return CurDAG->getTargetNode(U ? PPC::CMPLWI : PPC::CMPWI, MVT::i32,
439 LHS, getI32Imm(Lo16(Imm)));
440 return CurDAG->getTargetNode(U ? PPC::CMPLW : PPC::CMPW, MVT::i32,
443 return CurDAG->getTargetNode(PPC::FCMPU, MVT::i32, LHS, Select(RHS));
447 /// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding
449 static unsigned getBCCForSetCC(ISD::CondCode CC) {
451 default: assert(0 && "Unknown condition!"); abort();
452 case ISD::SETEQ: return PPC::BEQ;
453 case ISD::SETNE: return PPC::BNE;
455 case ISD::SETLT: return PPC::BLT;
457 case ISD::SETLE: return PPC::BLE;
459 case ISD::SETGT: return PPC::BGT;
461 case ISD::SETGE: return PPC::BGE;
466 /// getCRIdxForSetCC - Return the index of the condition register field
467 /// associated with the SetCC condition, and whether or not the field is
468 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
469 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool& Inv) {
471 default: assert(0 && "Unknown condition!"); abort();
473 case ISD::SETLT: Inv = false; return 0;
475 case ISD::SETGE: Inv = true; return 0;
477 case ISD::SETGT: Inv = false; return 1;
479 case ISD::SETLE: Inv = true; return 1;
480 case ISD::SETEQ: Inv = false; return 2;
481 case ISD::SETNE: Inv = true; return 2;
486 // Structure used to return the necessary information to codegen an SDIV as
489 int m; // magic number
490 int s; // shift amount
494 unsigned int m; // magic number
495 int a; // add indicator
496 int s; // shift amount
499 /// magic - calculate the magic numbers required to codegen an integer sdiv as
500 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
502 static struct ms magic(int d) {
504 unsigned int ad, anc, delta, q1, r1, q2, r2, t;
505 const unsigned int two31 = 0x80000000U;
509 t = two31 + ((unsigned int)d >> 31);
510 anc = t - 1 - t%ad; // absolute value of nc
511 p = 31; // initialize p
512 q1 = two31/anc; // initialize q1 = 2p/abs(nc)
513 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc))
514 q2 = two31/ad; // initialize q2 = 2p/abs(d)
515 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d))
518 q1 = 2*q1; // update q1 = 2p/abs(nc)
519 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
520 if (r1 >= anc) { // must be unsigned comparison
524 q2 = 2*q2; // update q2 = 2p/abs(d)
525 r2 = 2*r2; // update r2 = rem(2p/abs(d))
526 if (r2 >= ad) { // must be unsigned comparison
531 } while (q1 < delta || (q1 == delta && r1 == 0));
534 if (d < 0) mag.m = -mag.m; // resulting magic number
535 mag.s = p - 32; // resulting shift
539 /// magicu - calculate the magic numbers required to codegen an integer udiv as
540 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
541 static struct mu magicu(unsigned d)
544 unsigned int nc, delta, q1, r1, q2, r2;
546 magu.a = 0; // initialize "add" indicator
548 p = 31; // initialize p
549 q1 = 0x80000000/nc; // initialize q1 = 2p/nc
550 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc)
551 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d
552 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
555 if (r1 >= nc - r1 ) {
556 q1 = 2*q1 + 1; // update q1
557 r1 = 2*r1 - nc; // update r1
560 q1 = 2*q1; // update q1
561 r1 = 2*r1; // update r1
563 if (r2 + 1 >= d - r2) {
564 if (q2 >= 0x7FFFFFFF) magu.a = 1;
565 q2 = 2*q2 + 1; // update q2
566 r2 = 2*r2 + 1 - d; // update r2
569 if (q2 >= 0x80000000) magu.a = 1;
570 q2 = 2*q2; // update q2
571 r2 = 2*r2 + 1; // update r2
574 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
575 magu.m = q2 + 1; // resulting magic number
576 magu.s = p - 32; // resulting shift
580 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
581 /// return a DAG expression to select that will generate the same value by
582 /// multiplying by a magic number. See:
583 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
584 SDOperand PPC32DAGToDAGISel::BuildSDIVSequence(SDNode *N) {
585 int d = (int)cast<ConstantSDNode>(N->getOperand(1))->getValue();
586 ms magics = magic(d);
587 // Multiply the numerator (operand 0) by the magic value
588 SDOperand Q = CurDAG->getNode(ISD::MULHS, MVT::i32, N->getOperand(0),
589 CurDAG->getConstant(magics.m, MVT::i32));
590 // If d > 0 and m < 0, add the numerator
591 if (d > 0 && magics.m < 0)
592 Q = CurDAG->getNode(ISD::ADD, MVT::i32, Q, N->getOperand(0));
593 // If d < 0 and m > 0, subtract the numerator.
594 if (d < 0 && magics.m > 0)
595 Q = CurDAG->getNode(ISD::SUB, MVT::i32, Q, N->getOperand(0));
596 // Shift right algebraic if shift value is nonzero
598 Q = CurDAG->getNode(ISD::SRA, MVT::i32, Q,
599 CurDAG->getConstant(magics.s, MVT::i32));
600 // Extract the sign bit and add it to the quotient
602 CurDAG->getNode(ISD::SRL, MVT::i32, Q, CurDAG->getConstant(31, MVT::i32));
603 return CurDAG->getNode(ISD::ADD, MVT::i32, Q, T);
606 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
607 /// return a DAG expression to select that will generate the same value by
608 /// multiplying by a magic number. See:
609 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
610 SDOperand PPC32DAGToDAGISel::BuildUDIVSequence(SDNode *N) {
611 unsigned d = (unsigned)cast<ConstantSDNode>(N->getOperand(1))->getValue();
612 mu magics = magicu(d);
613 // Multiply the numerator (operand 0) by the magic value
614 SDOperand Q = CurDAG->getNode(ISD::MULHU, MVT::i32, N->getOperand(0),
615 CurDAG->getConstant(magics.m, MVT::i32));
617 return CurDAG->getNode(ISD::SRL, MVT::i32, Q,
618 CurDAG->getConstant(magics.s, MVT::i32));
620 SDOperand NPQ = CurDAG->getNode(ISD::SUB, MVT::i32, N->getOperand(0), Q);
621 NPQ = CurDAG->getNode(ISD::SRL, MVT::i32, NPQ,
622 CurDAG->getConstant(1, MVT::i32));
623 NPQ = CurDAG->getNode(ISD::ADD, MVT::i32, NPQ, Q);
624 return CurDAG->getNode(ISD::SRL, MVT::i32, NPQ,
625 CurDAG->getConstant(magics.s-1, MVT::i32));
629 // Select - Convert the specified operand from a target-independent to a
630 // target-specific node if it hasn't already been changed.
631 SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
633 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
634 N->getOpcode() < PPCISD::FIRST_NUMBER)
635 return Op; // Already selected.
637 switch (N->getOpcode()) {
639 std::cerr << "Cannot yet select: ";
643 case ISD::EntryToken: // These leaves remain the same.
645 case ISD::TokenFactor: {
647 if (N->getNumOperands() == 2) {
648 SDOperand Op0 = Select(N->getOperand(0));
649 SDOperand Op1 = Select(N->getOperand(1));
650 New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Op0, Op1);
652 std::vector<SDOperand> Ops;
653 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
654 Ops.push_back(Select(N->getOperand(i)));
655 New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Ops);
659 CurDAG->ReplaceAllUsesWith(Op, New);
664 case ISD::CopyFromReg: {
665 SDOperand Chain = Select(N->getOperand(0));
666 if (Chain == N->getOperand(0)) return Op; // No change
667 SDOperand New = CurDAG->getCopyFromReg(Chain,
668 cast<RegisterSDNode>(N->getOperand(1))->getReg(), N->getValueType(0));
669 return New.getValue(Op.ResNo);
671 case ISD::CopyToReg: {
672 SDOperand Chain = Select(N->getOperand(0));
673 SDOperand Reg = N->getOperand(1);
674 SDOperand Val = Select(N->getOperand(2));
675 if (Chain != N->getOperand(0) || Val != N->getOperand(2)) {
676 SDOperand New = CurDAG->getNode(ISD::CopyToReg, MVT::Other,
678 CurDAG->ReplaceAllUsesWith(Op, New);
683 case ISD::Constant: {
684 assert(N->getValueType(0) == MVT::i32);
685 unsigned v = (unsigned)cast<ConstantSDNode>(N)->getValue();
686 unsigned Hi = HA16(v);
687 unsigned Lo = Lo16(v);
689 // NOTE: This doesn't use SelectNodeTo, because doing that will prevent
690 // folding shared immediates into other the second instruction that
693 SDOperand Top = CurDAG->getTargetNode(PPC::LIS, MVT::i32,
695 return CurDAG->getTargetNode(PPC::ORI, MVT::i32, Top,
696 getI32Imm(v & 0xFFFF));
698 return CurDAG->getTargetNode(PPC::LI, MVT::i32, getI32Imm(v));
700 return CurDAG->getTargetNode(PPC::LIS, MVT::i32, getI32Imm(v >> 16));
704 if (N->getValueType(0) == MVT::i32)
705 CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_GPR, MVT::i32);
707 CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_FP, N->getValueType(0));
709 case ISD::FrameIndex: {
710 int FI = cast<FrameIndexSDNode>(N)->getIndex();
711 CurDAG->SelectNodeTo(N, PPC::ADDI, MVT::i32,
712 CurDAG->getTargetFrameIndex(FI, MVT::i32),
716 case ISD::ConstantPool: {
717 Constant *C = cast<ConstantPoolSDNode>(N)->get();
718 SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i32);
720 Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),CPI);
722 Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, CPI);
723 CurDAG->SelectNodeTo(N, PPC::LA, MVT::i32, Tmp, CPI);
726 case ISD::GlobalAddress: {
727 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
729 SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i32);
731 Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(), GA);
733 Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, GA);
735 if (GV->hasWeakLinkage() || GV->isExternal())
736 CurDAG->SelectNodeTo(N, PPC::LWZ, MVT::i32, GA, Tmp);
738 CurDAG->SelectNodeTo(N, PPC::LA, MVT::i32, Tmp, GA);
741 case ISD::SIGN_EXTEND_INREG:
742 switch(cast<VTSDNode>(N->getOperand(1))->getVT()) {
743 default: assert(0 && "Illegal type in SIGN_EXTEND_INREG"); break;
745 CurDAG->SelectNodeTo(N, PPC::EXTSH, MVT::i32, Select(N->getOperand(0)));
748 CurDAG->SelectNodeTo(N, PPC::EXTSB, MVT::i32, Select(N->getOperand(0)));
753 assert(N->getValueType(0) == MVT::i32);
754 CurDAG->SelectNodeTo(N, PPC::CNTLZW, MVT::i32, Select(N->getOperand(0)));
757 CurDAG->SelectNodeTo(N, PPC::FSEL, N->getValueType(0),
758 Select(N->getOperand(0)),
759 Select(N->getOperand(1)),
760 Select(N->getOperand(2)));
763 MVT::ValueType Ty = N->getValueType(0);
764 if (Ty == MVT::i32) {
765 if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1),
766 PPC::ADDIS, PPC::ADDI, true)) {
767 CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
770 CurDAG->SelectNodeTo(N, PPC::ADD, MVT::i32, Select(N->getOperand(0)),
771 Select(N->getOperand(1)));
776 if (!NoExcessFPPrecision) { // Match FMA ops
777 if (N->getOperand(0).getOpcode() == ISD::MUL &&
778 N->getOperand(0).Val->hasOneUse()) {
779 ++FusedFP; // Statistic
780 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMADD : PPC::FMADDS, Ty,
781 Select(N->getOperand(0).getOperand(0)),
782 Select(N->getOperand(0).getOperand(1)),
783 Select(N->getOperand(1)));
785 } else if (N->getOperand(1).getOpcode() == ISD::MUL &&
786 N->getOperand(1).hasOneUse()) {
787 ++FusedFP; // Statistic
788 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMADD : PPC::FMADDS, Ty,
789 Select(N->getOperand(1).getOperand(0)),
790 Select(N->getOperand(1).getOperand(1)),
791 Select(N->getOperand(0)));
796 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FADD : PPC::FADDS, Ty,
797 Select(N->getOperand(0)), Select(N->getOperand(1)));
801 MVT::ValueType Ty = N->getValueType(0);
802 if (Ty == MVT::i32) {
804 if (isIntImmediate(N->getOperand(0), Imm) && isInt16(Imm)) {
806 CurDAG->SelectNodeTo(N, PPC::NEG, Ty, Select(N->getOperand(1)));
808 CurDAG->SelectNodeTo(N, PPC::SUBFIC, Ty, Select(N->getOperand(1)),
809 getI32Imm(Lo16(Imm)));
812 if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1),
813 PPC::ADDIS, PPC::ADDI, true, true)) {
814 CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
817 CurDAG->SelectNodeTo(N, PPC::SUBF, Ty, Select(N->getOperand(1)),
818 Select(N->getOperand(0)));
823 if (!NoExcessFPPrecision) { // Match FMA ops
824 if (N->getOperand(0).getOpcode() == ISD::MUL &&
825 N->getOperand(0).Val->hasOneUse()) {
826 ++FusedFP; // Statistic
827 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMSUB : PPC::FMSUBS, Ty,
828 Select(N->getOperand(0).getOperand(0)),
829 Select(N->getOperand(0).getOperand(1)),
830 Select(N->getOperand(1)));
832 } else if (N->getOperand(1).getOpcode() == ISD::MUL &&
833 N->getOperand(1).Val->hasOneUse()) {
834 ++FusedFP; // Statistic
835 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FNMSUB : PPC::FNMSUBS, Ty,
836 Select(N->getOperand(1).getOperand(0)),
837 Select(N->getOperand(1).getOperand(1)),
838 Select(N->getOperand(0)));
842 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FSUB : PPC::FSUBS, Ty,
843 Select(N->getOperand(0)),
844 Select(N->getOperand(1)));
849 if (isIntImmediate(N->getOperand(1), Imm) && isInt16(Imm)) {
850 CurDAG->SelectNodeTo(N, PPC::MULLI, MVT::i32,
851 Select(N->getOperand(0)), getI32Imm(Lo16(Imm)));
854 switch (N->getValueType(0)) {
855 default: assert(0 && "Unhandled multiply type!");
856 case MVT::i32: Opc = PPC::MULLW; break;
857 case MVT::f32: Opc = PPC::FMULS; break;
858 case MVT::f64: Opc = PPC::FMUL; break;
860 CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Select(N->getOperand(0)),
861 Select(N->getOperand(1)));
866 if (isIntImmediate(N->getOperand(1), Imm)) {
867 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
869 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
870 Select(N->getOperand(0)),
871 getI32Imm(Log2_32(Imm)));
872 CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
873 Op.getValue(0), Op.getValue(1));
875 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
877 CurDAG->getTargetNode(PPC::SRAWI, MVT::Flag, MVT::i32,
878 Select(N->getOperand(0)),
879 getI32Imm(Log2_32(-Imm)));
881 CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, Op.getValue(1),
883 CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
886 SDOperand Result = Select(BuildSDIVSequence(N));
887 assert(Result.ResNo == 0);
888 CurDAG->ReplaceAllUsesWith(Op, Result);
895 switch (N->getValueType(0)) {
896 default: assert(0 && "Unknown type to ISD::SDIV");
897 case MVT::i32: Opc = PPC::DIVW; break;
898 case MVT::f32: Opc = PPC::FDIVS; break;
899 case MVT::f64: Opc = PPC::FDIV; break;
901 CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Select(N->getOperand(0)),
902 Select(N->getOperand(1)));
906 // If this is a divide by constant, we can emit code using some magic
907 // constants to implement it as a multiply instead.
909 if (isIntImmediate(N->getOperand(1), Imm) && Imm) {
910 SDOperand Result = Select(BuildUDIVSequence(N));
911 assert(Result.ResNo == 0);
912 CurDAG->ReplaceAllUsesWith(Op, Result);
917 CurDAG->SelectNodeTo(N, PPC::DIVWU, MVT::i32, Select(N->getOperand(0)),
918 Select(N->getOperand(1)));
922 assert(N->getValueType(0) == MVT::i32);
923 CurDAG->SelectNodeTo(N, PPC::MULHW, MVT::i32, Select(N->getOperand(0)),
924 Select(N->getOperand(1)));
927 assert(N->getValueType(0) == MVT::i32);
928 CurDAG->SelectNodeTo(N, PPC::MULHWU, MVT::i32, Select(N->getOperand(0)),
929 Select(N->getOperand(1)));
933 // If this is an and of a value rotated between 0 and 31 bits and then and'd
934 // with a mask, emit rlwinm
935 if (isIntImmediate(N->getOperand(1), Imm) && (isShiftedMask_32(Imm) ||
936 isShiftedMask_32(~Imm))) {
939 if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
940 Val = Select(N->getOperand(0).getOperand(0));
942 Val = Select(N->getOperand(0));
943 isRunOfOnes(Imm, MB, ME);
946 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Val, getI32Imm(SH),
947 getI32Imm(MB), getI32Imm(ME));
950 // If this is an and with an immediate that isn't a mask, then codegen it as
951 // high and low 16 bit immediate ands.
952 if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0),
954 PPC::ANDISo, PPC::ANDIo)) {
955 CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
959 // Finally, check for the case where we are being asked to select
960 // and (not(a), b) or and (a, not(b)) which can be selected as andc.
961 if (isOprNot(N->getOperand(0).Val))
962 CurDAG->SelectNodeTo(N, PPC::ANDC, MVT::i32, Select(N->getOperand(1)),
963 Select(N->getOperand(0).getOperand(0)));
964 else if (isOprNot(N->getOperand(1).Val))
965 CurDAG->SelectNodeTo(N, PPC::ANDC, MVT::i32, Select(N->getOperand(0)),
966 Select(N->getOperand(1).getOperand(0)));
968 CurDAG->SelectNodeTo(N, PPC::AND, MVT::i32, Select(N->getOperand(0)),
969 Select(N->getOperand(1)));
973 if (SDNode *I = SelectBitfieldInsert(N)) {
974 CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
978 if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0),
980 PPC::ORIS, PPC::ORI)) {
981 CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
985 // Finally, check for the case where we are being asked to select
986 // 'or (not(a), b)' or 'or (a, not(b))' which can be selected as orc.
987 if (isOprNot(N->getOperand(0).Val))
988 CurDAG->SelectNodeTo(N, PPC::ORC, MVT::i32, Select(N->getOperand(1)),
989 Select(N->getOperand(0).getOperand(0)));
990 else if (isOprNot(N->getOperand(1).Val))
991 CurDAG->SelectNodeTo(N, PPC::ORC, MVT::i32, Select(N->getOperand(0)),
992 Select(N->getOperand(1).getOperand(0)));
994 CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Select(N->getOperand(0)),
995 Select(N->getOperand(1)));
998 // Check whether or not this node is a logical 'not'. This is represented
999 // by llvm as a xor with the constant value -1 (all bits set). If this is a
1000 // 'not', then fold 'or' into 'nor', and so forth for the supported ops.
1003 SDOperand Val = Select(N->getOperand(0));
1004 switch (Val.isTargetOpcode() ? Val.getTargetOpcode() : 0) {
1005 default: Opc = 0; break;
1006 case PPC::OR: Opc = PPC::NOR; break;
1007 case PPC::AND: Opc = PPC::NAND; break;
1008 case PPC::XOR: Opc = PPC::EQV; break;
1011 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Val.getOperand(0),
1014 CurDAG->SelectNodeTo(N, PPC::NOR, MVT::i32, Val, Val);
1017 // If this is a xor with an immediate other than -1, then codegen it as high
1018 // and low 16 bit immediate xors.
1019 if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0),
1021 PPC::XORIS, PPC::XORI)) {
1022 CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
1026 // Finally, check for the case where we are being asked to select
1027 // xor (not(a), b) which is equivalent to not(xor a, b), which is eqv
1028 if (isOprNot(N->getOperand(0).Val))
1029 CurDAG->SelectNodeTo(N, PPC::EQV, MVT::i32,
1030 Select(N->getOperand(0).getOperand(0)),
1031 Select(N->getOperand(1)));
1033 CurDAG->SelectNodeTo(N, PPC::XOR, MVT::i32, Select(N->getOperand(0)),
1034 Select(N->getOperand(1)));
1037 unsigned Imm, SH, MB, ME;
1038 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
1039 isRotateAndMask(N, Imm, true, SH, MB, ME))
1040 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
1041 Select(N->getOperand(0).getOperand(0)),
1042 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
1043 else if (isIntImmediate(N->getOperand(1), Imm))
1044 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Select(N->getOperand(0)),
1045 getI32Imm(Imm), getI32Imm(0), getI32Imm(31-Imm));
1047 CurDAG->SelectNodeTo(N, PPC::SLW, MVT::i32, Select(N->getOperand(0)),
1048 Select(N->getOperand(1)));
1052 unsigned Imm, SH, MB, ME;
1053 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
1054 isRotateAndMask(N, Imm, true, SH, MB, ME))
1055 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
1056 Select(N->getOperand(0).getOperand(0)),
1057 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
1058 else if (isIntImmediate(N->getOperand(1), Imm))
1059 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Select(N->getOperand(0)),
1060 getI32Imm(32-Imm), getI32Imm(Imm), getI32Imm(31));
1062 CurDAG->SelectNodeTo(N, PPC::SRW, MVT::i32, Select(N->getOperand(0)),
1063 Select(N->getOperand(1)));
1067 unsigned Imm, SH, MB, ME;
1068 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
1069 isRotateAndMask(N, Imm, true, SH, MB, ME))
1070 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
1071 Select(N->getOperand(0).getOperand(0)),
1072 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
1073 else if (isIntImmediate(N->getOperand(1), Imm))
1074 CurDAG->SelectNodeTo(N, PPC::SRAWI, MVT::i32, Select(N->getOperand(0)),
1077 CurDAG->SelectNodeTo(N, PPC::SRAW, MVT::i32, Select(N->getOperand(0)),
1078 Select(N->getOperand(1)));
1082 CurDAG->SelectNodeTo(N, PPC::FABS, N->getValueType(0),
1083 Select(N->getOperand(0)));
1085 case ISD::FP_EXTEND: {
1086 assert(MVT::f64 == N->getValueType(0) &&
1087 MVT::f32 == N->getOperand(0).getValueType() && "Illegal FP_EXTEND");
1088 std::vector<SDOperand> Tmp;
1089 Tmp.push_back(Select(N->getOperand(0)));
1090 CurDAG->ReplaceAllUsesWith(N, Tmp); // Just use the operand as the result.
1094 assert(MVT::f32 == N->getValueType(0) &&
1095 MVT::f64 == N->getOperand(0).getValueType() && "Illegal FP_ROUND");
1096 CurDAG->SelectNodeTo(N, PPC::FRSP, MVT::f32, Select(N->getOperand(0)));
1098 case ISD::FP_TO_SINT: {
1099 SDOperand In = Select(N->getOperand(0));
1100 In = CurDAG->getTargetNode(PPC::FCTIWZ, MVT::f64, In);
1102 int FrameIdx = BB->getParent()->getFrameInfo()->CreateStackObject(8, 8);
1103 SDOperand FI = CurDAG->getTargetFrameIndex(FrameIdx, MVT::f64);
1104 SDOperand ST = CurDAG->getTargetNode(PPC::STFD, MVT::Other, In, getI32Imm(0), FI);
1105 CurDAG->SelectNodeTo(N, PPC::LWZ, MVT::i32, MVT::Other, getI32Imm(4), FI, ST);
1109 SDOperand Val = Select(N->getOperand(0));
1110 MVT::ValueType Ty = N->getValueType(0);
1111 if (Val.Val->hasOneUse()) {
1113 switch (Val.isTargetOpcode() ? Val.getTargetOpcode() : 0) {
1114 default: Opc = 0; break;
1115 case PPC::FABS: Opc = PPC::FNABS; break;
1116 case PPC::FMADD: Opc = PPC::FNMADD; break;
1117 case PPC::FMADDS: Opc = PPC::FNMADDS; break;
1118 case PPC::FMSUB: Opc = PPC::FNMSUB; break;
1119 case PPC::FMSUBS: Opc = PPC::FNMSUBS; break;
1121 // If we inverted the opcode, then emit the new instruction with the
1122 // inverted opcode and the original instruction's operands. Otherwise,
1123 // fall through and generate a fneg instruction.
1125 if (PPC::FNABS == Opc)
1126 CurDAG->SelectNodeTo(N, Opc, Ty, Val.getOperand(0));
1128 CurDAG->SelectNodeTo(N, Opc, Ty, Val.getOperand(0),
1129 Val.getOperand(1), Val.getOperand(2));
1133 CurDAG->SelectNodeTo(N, PPC::FNEG, Ty, Val);
1137 MVT::ValueType Ty = N->getValueType(0);
1138 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FSQRT : PPC::FSQRTS, Ty,
1139 Select(N->getOperand(0)));
1143 case ISD::ADD_PARTS: {
1144 SDOperand LHSL = Select(N->getOperand(0));
1145 SDOperand LHSH = Select(N->getOperand(1));
1148 bool ME = false, ZE = false;
1149 if (isIntImmediate(N->getOperand(3), Imm)) {
1150 ME = (signed)Imm == -1;
1154 std::vector<SDOperand> Result;
1155 SDOperand CarryFromLo;
1156 if (isIntImmediate(N->getOperand(2), Imm) &&
1157 ((signed)Imm >= -32768 || (signed)Imm < 32768)) {
1158 // Codegen the low 32 bits of the add. Interestingly, there is no
1159 // shifted form of add immediate carrying.
1160 CarryFromLo = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
1161 LHSL, getI32Imm(Imm));
1163 CarryFromLo = CurDAG->getTargetNode(PPC::ADDC, MVT::i32, MVT::Flag,
1164 LHSL, Select(N->getOperand(2)));
1166 CarryFromLo = CarryFromLo.getValue(1);
1168 // Codegen the high 32 bits, adding zero, minus one, or the full value
1169 // along with the carry flag produced by addc/addic.
1172 ResultHi = CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, LHSH, CarryFromLo);
1174 ResultHi = CurDAG->getTargetNode(PPC::ADDME, MVT::i32, LHSH, CarryFromLo);
1176 ResultHi = CurDAG->getTargetNode(PPC::ADDE, MVT::i32, LHSH,
1177 Select(N->getOperand(3)), CarryFromLo);
1178 Result.push_back(ResultHi);
1179 Result.push_back(CarryFromLo.getValue(0));
1180 CurDAG->ReplaceAllUsesWith(N, Result);
1181 return Result[Op.ResNo];
1183 case ISD::SUB_PARTS: {
1184 SDOperand LHSL = Select(N->getOperand(0));
1185 SDOperand LHSH = Select(N->getOperand(1));
1186 SDOperand RHSL = Select(N->getOperand(2));
1187 SDOperand RHSH = Select(N->getOperand(3));
1189 std::vector<SDOperand> Result;
1190 Result.push_back(CurDAG->getTargetNode(PPC::SUBFC, MVT::i32, MVT::Flag,
1192 Result.push_back(CurDAG->getTargetNode(PPC::SUBFE, MVT::i32, RHSH, LHSH,
1193 Result[0].getValue(1)));
1194 CurDAG->ReplaceAllUsesWith(N, Result);
1195 return Result[Op.ResNo];
1197 case ISD::SHL_PARTS: {
1198 SDOperand HI = Select(N->getOperand(0));
1199 SDOperand LO = Select(N->getOperand(1));
1200 SDOperand SH = Select(N->getOperand(2));
1201 SDOperand SH_LO_R = CurDAG->getTargetNode(PPC::SUBFIC, MVT::i32, MVT::Flag,
1203 SDOperand SH_LO_L = CurDAG->getTargetNode(PPC::ADDI, MVT::i32, SH,
1204 getI32Imm((unsigned)-32));
1205 SDOperand HI_SHL = CurDAG->getTargetNode(PPC::SLW, MVT::i32, HI, SH);
1206 SDOperand HI_LOR = CurDAG->getTargetNode(PPC::SRW, MVT::i32, LO, SH_LO_R);
1207 SDOperand HI_LOL = CurDAG->getTargetNode(PPC::SLW, MVT::i32, LO, SH_LO_L);
1208 SDOperand HI_OR = CurDAG->getTargetNode(PPC::OR, MVT::i32, HI_SHL, HI_LOR);
1210 std::vector<SDOperand> Result;
1211 Result.push_back(CurDAG->getTargetNode(PPC::SLW, MVT::i32, LO, SH));
1212 Result.push_back(CurDAG->getTargetNode(PPC::OR, MVT::i32, HI_OR, HI_LOL));
1213 CurDAG->ReplaceAllUsesWith(N, Result);
1214 return Result[Op.ResNo];
1216 case ISD::SRL_PARTS: {
1217 SDOperand HI = Select(N->getOperand(0));
1218 SDOperand LO = Select(N->getOperand(1));
1219 SDOperand SH = Select(N->getOperand(2));
1220 SDOperand SH_HI_L = CurDAG->getTargetNode(PPC::SUBFIC, MVT::i32, MVT::Flag,
1222 SDOperand SH_HI_R = CurDAG->getTargetNode(PPC::ADDI, MVT::i32, SH,
1223 getI32Imm((unsigned)-32));
1224 SDOperand LO_SHR = CurDAG->getTargetNode(PPC::SRW, MVT::i32, LO, SH);
1225 SDOperand LO_HIL = CurDAG->getTargetNode(PPC::SLW, MVT::i32, HI, SH_HI_L);
1226 SDOperand LO_HIR = CurDAG->getTargetNode(PPC::SRW, MVT::i32, HI, SH_HI_R);
1227 SDOperand LO_OR = CurDAG->getTargetNode(PPC::OR, MVT::i32, LO_SHR, LO_HIL);
1229 std::vector<SDOperand> Result;
1230 Result.push_back(CurDAG->getTargetNode(PPC::OR, MVT::i32, LO_OR, LO_HIR));
1231 Result.push_back(CurDAG->getTargetNode(PPC::SRW, MVT::i32, HI, SH));
1232 CurDAG->ReplaceAllUsesWith(N, Result);
1233 return Result[Op.ResNo];
1239 case ISD::SEXTLOAD: {
1241 bool isIdx = SelectAddr(N->getOperand(1), Op1, Op2);
1243 MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ?
1244 N->getValueType(0) : cast<VTSDNode>(N->getOperand(3))->getVT();
1246 switch (TypeBeingLoaded) {
1247 default: N->dump(); assert(0 && "Cannot load this type!");
1249 case MVT::i8: Opc = isIdx ? PPC::LBZX : PPC::LBZ; break;
1251 if (N->getOpcode() == ISD::SEXTLOAD) { // SEXT load?
1252 Opc = isIdx ? PPC::LHAX : PPC::LHA;
1254 Opc = isIdx ? PPC::LHZX : PPC::LHZ;
1257 case MVT::i32: Opc = isIdx ? PPC::LWZX : PPC::LWZ; break;
1258 case MVT::f32: Opc = isIdx ? PPC::LFSX : PPC::LFS; break;
1259 case MVT::f64: Opc = isIdx ? PPC::LFDX : PPC::LFD; break;
1262 CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
1263 Op1, Op2, Select(N->getOperand(0)));
1267 case ISD::TRUNCSTORE:
1269 SDOperand AddrOp1, AddrOp2;
1270 bool isIdx = SelectAddr(N->getOperand(2), AddrOp1, AddrOp2);
1273 if (N->getOpcode() == ISD::STORE) {
1274 switch (N->getOperand(1).getValueType()) {
1275 default: assert(0 && "unknown Type in store");
1276 case MVT::i32: Opc = isIdx ? PPC::STWX : PPC::STW; break;
1277 case MVT::f64: Opc = isIdx ? PPC::STFDX : PPC::STFD; break;
1278 case MVT::f32: Opc = isIdx ? PPC::STFSX : PPC::STFS; break;
1280 } else { //ISD::TRUNCSTORE
1281 switch(cast<VTSDNode>(N->getOperand(4))->getVT()) {
1282 default: assert(0 && "unknown Type in store");
1284 case MVT::i8: Opc = isIdx ? PPC::STBX : PPC::STB; break;
1285 case MVT::i16: Opc = isIdx ? PPC::STHX : PPC::STH; break;
1289 CurDAG->SelectNodeTo(N, Opc, MVT::Other, Select(N->getOperand(1)),
1290 AddrOp1, AddrOp2, Select(N->getOperand(0)));
1296 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
1297 if (isIntImmediate(N->getOperand(1), Imm)) {
1298 // We can codegen setcc op, imm very efficiently compared to a brcond.
1299 // Check for those cases here.
1302 SDOperand Op = Select(N->getOperand(0));
1304 default: assert(0 && "Unhandled SetCC condition"); abort();
1306 Op = CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op);
1307 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(27),
1308 getI32Imm(5), getI32Imm(31));
1311 SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
1312 Op, getI32Imm(~0U));
1313 CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1));
1317 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
1318 getI32Imm(31), getI32Imm(31));
1321 SDOperand T = CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op);
1322 T = CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op);;
1323 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, T, getI32Imm(1),
1324 getI32Imm(31), getI32Imm(31));
1329 } else if (Imm == ~0U) { // setcc op, -1
1330 SDOperand Op = Select(N->getOperand(0));
1332 default: assert(0 && "Unhandled SetCC condition"); abort();
1334 Op = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
1336 CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
1337 CurDAG->getTargetNode(PPC::LI, MVT::i32,
1342 Op = CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op);
1343 SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, Op,
1345 CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1));
1349 SDOperand AD = CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
1351 SDOperand AN = CurDAG->getTargetNode(PPC::AND, MVT::i32, AD, Op);
1352 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, AN, getI32Imm(1),
1353 getI32Imm(31), getI32Imm(31));
1357 Op = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
1358 getI32Imm(31), getI32Imm(31));
1359 CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1));
1367 unsigned Idx = getCRIdxForSetCC(CC, Inv);
1369 SelectCC(Select(N->getOperand(0)), Select(N->getOperand(1)), CC);
1372 // Force the ccreg into CR7.
1373 SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
1375 std::vector<MVT::ValueType> VTs;
1376 VTs.push_back(MVT::Other);
1377 VTs.push_back(MVT::Flag); // NONSTANDARD CopyToReg node: defines a flag
1378 std::vector<SDOperand> Ops;
1379 Ops.push_back(CurDAG->getEntryNode());
1380 Ops.push_back(CR7Reg);
1381 Ops.push_back(CCReg);
1382 CCReg = CurDAG->getNode(ISD::CopyToReg, VTs, Ops).getValue(1);
1384 if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
1385 IntCR = CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg, CCReg);
1387 IntCR = CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg);
1390 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, IntCR,
1391 getI32Imm(32-(3-Idx)), getI32Imm(31), getI32Imm(31));
1394 CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, IntCR,
1395 getI32Imm(32-(3-Idx)), getI32Imm(31),getI32Imm(31));
1396 CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
1402 case ISD::SELECT_CC: {
1403 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1405 // handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
1406 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1407 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1408 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1409 if (N1C->isNullValue() && N3C->isNullValue() &&
1410 N2C->getValue() == 1ULL && CC == ISD::SETNE) {
1411 SDOperand LHS = Select(N->getOperand(0));
1413 CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
1414 LHS, getI32Imm(~0U));
1415 CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, Tmp, LHS,
1420 SDOperand CCReg = SelectCC(Select(N->getOperand(0)),
1421 Select(N->getOperand(1)), CC);
1422 unsigned BROpc = getBCCForSetCC(CC);
1424 bool isFP = MVT::isFloatingPoint(N->getValueType(0));
1425 unsigned SelectCCOp = isFP ? PPC::SELECT_CC_FP : PPC::SELECT_CC_Int;
1426 CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), CCReg,
1427 Select(N->getOperand(2)), Select(N->getOperand(3)),
1432 case ISD::CALLSEQ_START:
1433 case ISD::CALLSEQ_END: {
1434 unsigned Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
1435 unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
1436 PPC::ADJCALLSTACKDOWN : PPC::ADJCALLSTACKUP;
1437 CurDAG->SelectNodeTo(N, Opc, MVT::Other,
1438 getI32Imm(Amt), Select(N->getOperand(0)));
1442 case ISD::TAILCALL: {
1443 SDOperand Chain = Select(N->getOperand(0));
1445 unsigned CallOpcode;
1446 std::vector<SDOperand> CallOperands;
1448 if (GlobalAddressSDNode *GASD =
1449 dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
1450 CallOpcode = PPC::CALLpcrel;
1451 CallOperands.push_back(CurDAG->getTargetGlobalAddress(GASD->getGlobal(),
1453 } else if (ExternalSymbolSDNode *ESSDN =
1454 dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) {
1455 CallOpcode = PPC::CALLpcrel;
1456 CallOperands.push_back(N->getOperand(1));
1458 // Copy the callee address into the CTR register.
1459 SDOperand Callee = Select(N->getOperand(1));
1460 Chain = CurDAG->getTargetNode(PPC::MTCTR, MVT::Other, Callee, Chain);
1462 // Copy the callee address into R12 on darwin.
1463 SDOperand R12 = CurDAG->getRegister(PPC::R12, MVT::i32);
1464 Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, R12, Callee);
1466 CallOperands.push_back(getI32Imm(20)); // Information to encode indcall
1467 CallOperands.push_back(getI32Imm(0)); // Information to encode indcall
1468 CallOperands.push_back(R12);
1469 CallOpcode = PPC::CALLindirect;
1472 unsigned GPR_idx = 0, FPR_idx = 0;
1473 static const unsigned GPR[] = {
1474 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1475 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1477 static const unsigned FPR[] = {
1478 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1479 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1482 for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i) {
1483 unsigned DestReg = 0;
1484 MVT::ValueType RegTy;
1485 if (N->getOperand(i).getValueType() == MVT::i32) {
1486 assert(GPR_idx < 8 && "Too many int args");
1487 DestReg = GPR[GPR_idx++];
1490 assert(MVT::isFloatingPoint(N->getOperand(i).getValueType()) &&
1491 "Unpromoted integer arg?");
1492 assert(FPR_idx < 13 && "Too many fp args");
1493 DestReg = FPR[FPR_idx++];
1494 RegTy = MVT::f64; // Even if this is really f32!
1497 if (N->getOperand(i).getOpcode() != ISD::UNDEF) {
1498 SDOperand Reg = CurDAG->getRegister(DestReg, RegTy);
1499 Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, Reg,
1500 Select(N->getOperand(i)));
1501 CallOperands.push_back(Reg);
1505 // Finally, once everything is in registers to pass to the call, emit the
1507 CallOperands.push_back(Chain);
1508 Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, CallOperands);
1510 std::vector<SDOperand> CallResults;
1512 // If the call has results, copy the values out of the ret val registers.
1513 switch (N->getValueType(0)) {
1514 default: assert(0 && "Unexpected ret value!");
1515 case MVT::Other: break;
1517 if (N->getValueType(1) == MVT::i32) {
1518 Chain = CurDAG->getCopyFromReg(Chain, PPC::R4, MVT::i32).getValue(1);
1519 CallResults.push_back(Chain.getValue(0));
1520 Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32).getValue(1);
1521 CallResults.push_back(Chain.getValue(0));
1523 Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32).getValue(1);
1524 CallResults.push_back(Chain.getValue(0));
1529 Chain = CurDAG->getCopyFromReg(Chain, PPC::F1, MVT::f64).getValue(1);
1530 CallResults.push_back(Chain.getValue(0));
1534 CallResults.push_back(Chain);
1535 CurDAG->ReplaceAllUsesWith(N, CallResults);
1536 return CallResults[Op.ResNo];
1539 SDOperand Chain = Select(N->getOperand(0)); // Token chain.
1541 if (N->getNumOperands() > 1) {
1542 SDOperand Val = Select(N->getOperand(1));
1543 switch (N->getOperand(1).getValueType()) {
1544 default: assert(0 && "Unknown return type!");
1547 Chain = CurDAG->getCopyToReg(Chain, PPC::F1, Val);
1550 Chain = CurDAG->getCopyToReg(Chain, PPC::R3, Val);
1554 if (N->getNumOperands() > 2) {
1555 assert(N->getOperand(1).getValueType() == MVT::i32 &&
1556 N->getOperand(2).getValueType() == MVT::i32 &&
1557 N->getNumOperands() == 3 && "Unknown two-register ret value!");
1558 Val = Select(N->getOperand(2));
1559 Chain = CurDAG->getCopyToReg(Chain, PPC::R4, Val);
1563 // Finally, select this to a blr (return) instruction.
1564 CurDAG->SelectNodeTo(N, PPC::BLR, MVT::Other, Chain);
1568 CurDAG->SelectNodeTo(N, PPC::B, MVT::Other, N->getOperand(1),
1569 Select(N->getOperand(0)));
1572 case ISD::BRTWOWAY_CC: {
1573 SDOperand Chain = Select(N->getOperand(0));
1574 MachineBasicBlock *Dest =
1575 cast<BasicBlockSDNode>(N->getOperand(4))->getBasicBlock();
1576 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
1577 SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
1578 unsigned Opc = getBCCForSetCC(CC);
1580 // If this is a two way branch, then grab the fallthrough basic block
1581 // argument and build a PowerPC branch pseudo-op, suitable for long branch
1582 // conversion if necessary by the branch selection pass. Otherwise, emit a
1583 // standard conditional branch.
1584 if (N->getOpcode() == ISD::BRTWOWAY_CC) {
1585 MachineBasicBlock *Fallthrough =
1586 cast<BasicBlockSDNode>(N->getOperand(5))->getBasicBlock();
1587 SDOperand CB = CurDAG->getTargetNode(PPC::COND_BRANCH, MVT::Other,
1588 CondCode, getI32Imm(Opc),
1589 N->getOperand(4), N->getOperand(5),
1591 CurDAG->SelectNodeTo(N, PPC::B, MVT::Other, N->getOperand(5), CB);
1593 // Iterate to the next basic block
1594 ilist<MachineBasicBlock>::iterator It = BB;
1597 // If the fallthrough path is off the end of the function, which would be
1598 // undefined behavior, set it to be the same as the current block because
1599 // we have nothing better to set it to, and leaving it alone will cause
1600 // the PowerPC Branch Selection pass to crash.
1601 if (It == BB->getParent()->end()) It = Dest;
1602 CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other, CondCode,
1603 getI32Imm(Opc), N->getOperand(4),
1604 CurDAG->getBasicBlock(It), Chain);
1609 return SDOperand(N, Op.ResNo);
1613 /// createPPC32ISelDag - This pass converts a legalized DAG into a
1614 /// PowerPC-specific DAG, ready for instruction scheduling.
1616 FunctionPass *llvm::createPPC32ISelDag(TargetMachine &TM) {
1617 return new PPC32DAGToDAGISel(TM);