1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
16 #include "MCTargetDesc/PPCPredicates.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCTargetMachine.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/GlobalAlias.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/GlobalVariable.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetOptions.h"
38 #define DEBUG_TYPE "ppc-codegen"
40 // FIXME: Remove this once the bug has been fixed!
41 cl::opt<bool> ANDIGlueBug("expose-ppc-andi-glue-bug",
42 cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden);
45 void initializePPCDAGToDAGISelPass(PassRegistry&);
49 //===--------------------------------------------------------------------===//
50 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
51 /// instructions for SelectionDAG operations.
53 class PPCDAGToDAGISel : public SelectionDAGISel {
54 const PPCTargetMachine &TM;
55 const PPCTargetLowering *PPCLowering;
56 const PPCSubtarget *PPCSubTarget;
57 unsigned GlobalBaseReg;
59 explicit PPCDAGToDAGISel(PPCTargetMachine &tm)
60 : SelectionDAGISel(tm), TM(tm),
61 PPCLowering(TM.getTargetLowering()),
62 PPCSubTarget(TM.getSubtargetImpl()) {
63 initializePPCDAGToDAGISelPass(*PassRegistry::getPassRegistry());
66 bool runOnMachineFunction(MachineFunction &MF) override {
67 // Make sure we re-emit a set of the global base reg if necessary
69 PPCLowering = TM.getTargetLowering();
70 PPCSubTarget = TM.getSubtargetImpl();
71 SelectionDAGISel::runOnMachineFunction(MF);
73 if (!PPCSubTarget->isSVR4ABI())
79 void PostprocessISelDAG() override;
81 /// getI32Imm - Return a target constant with the specified value, of type
83 inline SDValue getI32Imm(unsigned Imm) {
84 return CurDAG->getTargetConstant(Imm, MVT::i32);
87 /// getI64Imm - Return a target constant with the specified value, of type
89 inline SDValue getI64Imm(uint64_t Imm) {
90 return CurDAG->getTargetConstant(Imm, MVT::i64);
93 /// getSmallIPtrImm - Return a target constant of pointer type.
94 inline SDValue getSmallIPtrImm(unsigned Imm) {
95 return CurDAG->getTargetConstant(Imm, PPCLowering->getPointerTy());
98 /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s
99 /// with any number of 0s on either side. The 1s are allowed to wrap from
100 /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs.
101 /// 0x0F0F0000 is not, since all 1s are not contiguous.
102 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME);
105 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
106 /// rotate and mask opcode and mask operation.
107 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask,
108 unsigned &SH, unsigned &MB, unsigned &ME);
110 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
111 /// base register. Return the virtual register that holds this value.
112 SDNode *getGlobalBaseReg();
114 // Select - Convert the specified operand from a target-independent to a
115 // target-specific node if it hasn't already been changed.
116 SDNode *Select(SDNode *N) override;
118 SDNode *SelectBitfieldInsert(SDNode *N);
120 /// SelectCC - Select a comparison of the specified values with the
121 /// specified condition code, returning the CR# of the expression.
122 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl);
124 /// SelectAddrImm - Returns true if the address N can be represented by
125 /// a base register plus a signed 16-bit displacement [r+imm].
126 bool SelectAddrImm(SDValue N, SDValue &Disp,
128 return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, false);
131 /// SelectAddrImmOffs - Return true if the operand is valid for a preinc
132 /// immediate field. Note that the operand at this point is already the
133 /// result of a prior SelectAddressRegImm call.
134 bool SelectAddrImmOffs(SDValue N, SDValue &Out) const {
135 if (N.getOpcode() == ISD::TargetConstant ||
136 N.getOpcode() == ISD::TargetGlobalAddress) {
144 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
145 /// represented as an indexed [r+r] operation. Returns false if it can
146 /// be represented by [r+imm], which are preferred.
147 bool SelectAddrIdx(SDValue N, SDValue &Base, SDValue &Index) {
148 return PPCLowering->SelectAddressRegReg(N, Base, Index, *CurDAG);
151 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
152 /// represented as an indexed [r+r] operation.
153 bool SelectAddrIdxOnly(SDValue N, SDValue &Base, SDValue &Index) {
154 return PPCLowering->SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
157 /// SelectAddrImmX4 - Returns true if the address N can be represented by
158 /// a base register plus a signed 16-bit displacement that is a multiple of 4.
159 /// Suitable for use by STD and friends.
160 bool SelectAddrImmX4(SDValue N, SDValue &Disp, SDValue &Base) {
161 return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, true);
164 // Select an address into a single register.
165 bool SelectAddr(SDValue N, SDValue &Base) {
170 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
171 /// inline asm expressions. It is always correct to compute the value into
172 /// a register. The case of adding a (possibly relocatable) constant to a
173 /// register can be improved, but it is wrong to substitute Reg+Reg for
174 /// Reg in an asm, because the load or store opcode would have to change.
175 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
177 std::vector<SDValue> &OutOps) override {
178 OutOps.push_back(Op);
182 void InsertVRSaveCode(MachineFunction &MF);
184 const char *getPassName() const override {
185 return "PowerPC DAG->DAG Pattern Instruction Selection";
188 // Include the pieces autogenerated from the target description.
189 #include "PPCGenDAGISel.inc"
192 SDNode *SelectSETCC(SDNode *N);
194 void PeepholePPC64();
195 void PeepholeCROps();
197 bool AllUsersSelectZero(SDNode *N);
198 void SwapAllSelectUsers(SDNode *N);
202 /// InsertVRSaveCode - Once the entire function has been instruction selected,
203 /// all virtual registers are created and all machine instructions are built,
204 /// check to see if we need to save/restore VRSAVE. If so, do it.
205 void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) {
206 // Check to see if this function uses vector registers, which means we have to
207 // save and restore the VRSAVE register and update it with the regs we use.
209 // In this case, there will be virtual registers of vector type created
210 // by the scheduler. Detect them now.
211 bool HasVectorVReg = false;
212 for (unsigned i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) {
213 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
214 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) {
215 HasVectorVReg = true;
219 if (!HasVectorVReg) return; // nothing to do.
221 // If we have a vector register, we want to emit code into the entry and exit
222 // blocks to save and restore the VRSAVE register. We do this here (instead
223 // of marking all vector instructions as clobbering VRSAVE) for two reasons:
225 // 1. This (trivially) reduces the load on the register allocator, by not
226 // having to represent the live range of the VRSAVE register.
227 // 2. This (more significantly) allows us to create a temporary virtual
228 // register to hold the saved VRSAVE value, allowing this temporary to be
229 // register allocated, instead of forcing it to be spilled to the stack.
231 // Create two vregs - one to hold the VRSAVE register that is live-in to the
232 // function and one for the value after having bits or'd into it.
233 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
234 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
236 const TargetInstrInfo &TII = *TM.getInstrInfo();
237 MachineBasicBlock &EntryBB = *Fn.begin();
239 // Emit the following code into the entry block:
240 // InVRSAVE = MFVRSAVE
241 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
242 // MTVRSAVE UpdatedVRSAVE
243 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
244 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE);
245 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE),
246 UpdatedVRSAVE).addReg(InVRSAVE);
247 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
249 // Find all return blocks, outputting a restore in each epilog.
250 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
251 if (!BB->empty() && BB->back().isReturn()) {
252 IP = BB->end(); --IP;
254 // Skip over all terminator instructions, which are part of the return
256 MachineBasicBlock::iterator I2 = IP;
257 while (I2 != BB->begin() && (--I2)->isTerminator())
260 // Emit: MTVRSAVE InVRSave
261 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
267 /// getGlobalBaseReg - Output the instructions required to put the
268 /// base address to use for accessing globals into a register.
270 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
271 if (!GlobalBaseReg) {
272 const TargetInstrInfo &TII = *TM.getInstrInfo();
273 // Insert the set of GlobalBaseReg into the first MBB of the function
274 MachineBasicBlock &FirstMBB = MF->front();
275 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
278 if (PPCLowering->getPointerTy() == MVT::i32) {
279 if (PPCSubTarget->isTargetELF())
280 GlobalBaseReg = PPC::R30;
283 RegInfo->createVirtualRegister(&PPC::GPRC_NOR0RegClass);
284 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
285 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
286 if (PPCSubTarget->isTargetELF()) {
287 unsigned TempReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
288 BuildMI(FirstMBB, MBBI, dl,
289 TII.get(PPC::GetGBRO), TempReg).addReg(GlobalBaseReg);
290 BuildMI(FirstMBB, MBBI, dl,
291 TII.get(PPC::UpdateGBR)).addReg(GlobalBaseReg).addReg(TempReg);
292 MF->getInfo<PPCFunctionInfo>()->setUsesPICBase(true);
295 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RC_NOX0RegClass);
296 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8));
297 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg);
300 return CurDAG->getRegister(GlobalBaseReg,
301 PPCLowering->getPointerTy()).getNode();
304 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
305 /// or 64-bit immediate, and if the value can be accurately represented as a
306 /// sign extension from a 16-bit value. If so, this returns true and the
308 static bool isIntS16Immediate(SDNode *N, short &Imm) {
309 if (N->getOpcode() != ISD::Constant)
312 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
313 if (N->getValueType(0) == MVT::i32)
314 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
316 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
319 static bool isIntS16Immediate(SDValue Op, short &Imm) {
320 return isIntS16Immediate(Op.getNode(), Imm);
324 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
325 /// operand. If so Imm will receive the 32-bit value.
326 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
327 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
328 Imm = cast<ConstantSDNode>(N)->getZExtValue();
334 /// isInt64Immediate - This method tests to see if the node is a 64-bit constant
335 /// operand. If so Imm will receive the 64-bit value.
336 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
337 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
338 Imm = cast<ConstantSDNode>(N)->getZExtValue();
344 // isInt32Immediate - This method tests to see if a constant operand.
345 // If so Imm will receive the 32 bit value.
346 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
347 return isInt32Immediate(N.getNode(), Imm);
351 // isOpcWithIntImmediate - This method tests to see if the node is a specific
352 // opcode and that it has a immediate integer right operand.
353 // If so Imm will receive the 32 bit value.
354 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
355 return N->getOpcode() == Opc
356 && isInt32Immediate(N->getOperand(1).getNode(), Imm);
359 bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
363 if (isShiftedMask_32(Val)) {
364 // look for the first non-zero bit
365 MB = countLeadingZeros(Val);
366 // look for the first zero bit after the run of ones
367 ME = countLeadingZeros((Val - 1) ^ Val);
370 Val = ~Val; // invert mask
371 if (isShiftedMask_32(Val)) {
372 // effectively look for the first zero bit
373 ME = countLeadingZeros(Val) - 1;
374 // effectively look for the first one bit after the run of zeros
375 MB = countLeadingZeros((Val - 1) ^ Val) + 1;
383 bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
384 bool isShiftMask, unsigned &SH,
385 unsigned &MB, unsigned &ME) {
386 // Don't even go down this path for i64, since different logic will be
387 // necessary for rldicl/rldicr/rldimi.
388 if (N->getValueType(0) != MVT::i32)
392 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
393 unsigned Opcode = N->getOpcode();
394 if (N->getNumOperands() != 2 ||
395 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31))
398 if (Opcode == ISD::SHL) {
399 // apply shift left to mask if it comes first
400 if (isShiftMask) Mask = Mask << Shift;
401 // determine which bits are made indeterminant by shift
402 Indeterminant = ~(0xFFFFFFFFu << Shift);
403 } else if (Opcode == ISD::SRL) {
404 // apply shift right to mask if it comes first
405 if (isShiftMask) Mask = Mask >> Shift;
406 // determine which bits are made indeterminant by shift
407 Indeterminant = ~(0xFFFFFFFFu >> Shift);
408 // adjust for the left rotate
410 } else if (Opcode == ISD::ROTL) {
416 // if the mask doesn't intersect any Indeterminant bits
417 if (Mask && !(Mask & Indeterminant)) {
419 // make sure the mask is still a mask (wrap arounds may not be)
420 return isRunOfOnes(Mask, MB, ME);
425 /// SelectBitfieldInsert - turn an or of two masked values into
426 /// the rotate left word immediate then mask insert (rlwimi) instruction.
427 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
428 SDValue Op0 = N->getOperand(0);
429 SDValue Op1 = N->getOperand(1);
432 APInt LKZ, LKO, RKZ, RKO;
433 CurDAG->computeKnownBits(Op0, LKZ, LKO);
434 CurDAG->computeKnownBits(Op1, RKZ, RKO);
436 unsigned TargetMask = LKZ.getZExtValue();
437 unsigned InsertMask = RKZ.getZExtValue();
439 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
440 unsigned Op0Opc = Op0.getOpcode();
441 unsigned Op1Opc = Op1.getOpcode();
442 unsigned Value, SH = 0;
443 TargetMask = ~TargetMask;
444 InsertMask = ~InsertMask;
446 // If the LHS has a foldable shift and the RHS does not, then swap it to the
447 // RHS so that we can fold the shift into the insert.
448 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
449 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
450 Op0.getOperand(0).getOpcode() == ISD::SRL) {
451 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
452 Op1.getOperand(0).getOpcode() != ISD::SRL) {
454 std::swap(Op0Opc, Op1Opc);
455 std::swap(TargetMask, InsertMask);
458 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
459 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
460 Op1.getOperand(0).getOpcode() != ISD::SRL) {
462 std::swap(Op0Opc, Op1Opc);
463 std::swap(TargetMask, InsertMask);
468 if (isRunOfOnes(InsertMask, MB, ME)) {
471 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
472 isInt32Immediate(Op1.getOperand(1), Value)) {
473 Op1 = Op1.getOperand(0);
474 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
476 if (Op1Opc == ISD::AND) {
477 // The AND mask might not be a constant, and we need to make sure that
478 // if we're going to fold the masking with the insert, all bits not
479 // know to be zero in the mask are known to be one.
481 CurDAG->computeKnownBits(Op1.getOperand(1), MKZ, MKO);
482 bool CanFoldMask = InsertMask == MKO.getZExtValue();
484 unsigned SHOpc = Op1.getOperand(0).getOpcode();
485 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && CanFoldMask &&
486 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
487 // Note that Value must be in range here (less than 32) because
488 // otherwise there would not be any bits set in InsertMask.
489 Op1 = Op1.getOperand(0).getOperand(0);
490 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
495 SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB),
497 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops);
503 /// SelectCC - Select a comparison of the specified values with the specified
504 /// condition code, returning the CR# of the expression.
505 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
506 ISD::CondCode CC, SDLoc dl) {
507 // Always select the LHS.
510 if (LHS.getValueType() == MVT::i32) {
512 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
513 if (isInt32Immediate(RHS, Imm)) {
514 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
516 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
517 getI32Imm(Imm & 0xFFFF)), 0);
518 // If this is a 16-bit signed immediate, fold it.
519 if (isInt<16>((int)Imm))
520 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
521 getI32Imm(Imm & 0xFFFF)), 0);
523 // For non-equality comparisons, the default code would materialize the
524 // constant, then compare against it, like this:
528 // Since we are just comparing for equality, we can emit this instead:
529 // xoris r0,r3,0x1234
530 // cmplwi cr0,r0,0x5678
532 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS,
533 getI32Imm(Imm >> 16)), 0);
534 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor,
535 getI32Imm(Imm & 0xFFFF)), 0);
538 } else if (ISD::isUnsignedIntSetCC(CC)) {
539 if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm))
540 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
541 getI32Imm(Imm & 0xFFFF)), 0);
545 if (isIntS16Immediate(RHS, SImm))
546 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
547 getI32Imm((int)SImm & 0xFFFF)),
551 } else if (LHS.getValueType() == MVT::i64) {
553 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
554 if (isInt64Immediate(RHS.getNode(), Imm)) {
555 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
557 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
558 getI32Imm(Imm & 0xFFFF)), 0);
559 // If this is a 16-bit signed immediate, fold it.
561 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
562 getI32Imm(Imm & 0xFFFF)), 0);
564 // For non-equality comparisons, the default code would materialize the
565 // constant, then compare against it, like this:
569 // Since we are just comparing for equality, we can emit this instead:
570 // xoris r0,r3,0x1234
571 // cmpldi cr0,r0,0x5678
573 if (isUInt<32>(Imm)) {
574 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS,
575 getI64Imm(Imm >> 16)), 0);
576 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor,
577 getI64Imm(Imm & 0xFFFF)), 0);
581 } else if (ISD::isUnsignedIntSetCC(CC)) {
582 if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm))
583 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
584 getI64Imm(Imm & 0xFFFF)), 0);
588 if (isIntS16Immediate(RHS, SImm))
589 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
590 getI64Imm(SImm & 0xFFFF)),
594 } else if (LHS.getValueType() == MVT::f32) {
597 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
598 Opc = PPCSubTarget->hasVSX() ? PPC::XSCMPUDP : PPC::FCMPUD;
600 return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0);
603 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
609 llvm_unreachable("Should be lowered by legalize!");
610 default: llvm_unreachable("Unknown condition!");
612 case ISD::SETEQ: return PPC::PRED_EQ;
614 case ISD::SETNE: return PPC::PRED_NE;
616 case ISD::SETLT: return PPC::PRED_LT;
618 case ISD::SETLE: return PPC::PRED_LE;
620 case ISD::SETGT: return PPC::PRED_GT;
622 case ISD::SETGE: return PPC::PRED_GE;
623 case ISD::SETO: return PPC::PRED_NU;
624 case ISD::SETUO: return PPC::PRED_UN;
625 // These two are invalid for floating point. Assume we have int.
626 case ISD::SETULT: return PPC::PRED_LT;
627 case ISD::SETUGT: return PPC::PRED_GT;
631 /// getCRIdxForSetCC - Return the index of the condition register field
632 /// associated with the SetCC condition, and whether or not the field is
633 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
634 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) {
637 default: llvm_unreachable("Unknown condition!");
639 case ISD::SETLT: return 0; // Bit #0 = SETOLT
641 case ISD::SETGT: return 1; // Bit #1 = SETOGT
643 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ
644 case ISD::SETUO: return 3; // Bit #3 = SETUO
646 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
648 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE
650 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE
651 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO
656 llvm_unreachable("Invalid branch code: should be expanded by legalize");
657 // These are invalid for floating point. Assume integer.
658 case ISD::SETULT: return 0;
659 case ISD::SETUGT: return 1;
663 // getVCmpInst: return the vector compare instruction for the specified
664 // vector type and condition code. Since this is for altivec specific code,
665 // only support the altivec types (v16i8, v8i16, v4i32, and v4f32).
666 static unsigned int getVCmpInst(MVT::SimpleValueType VecVT, ISD::CondCode CC,
673 if (VecVT == MVT::v16i8)
674 return PPC::VCMPEQUB;
675 else if (VecVT == MVT::v8i16)
676 return PPC::VCMPEQUH;
677 else if (VecVT == MVT::v4i32)
678 return PPC::VCMPEQUW;
679 // v4f32 != v4f32 could be translate to unordered not equal
680 else if (VecVT == MVT::v4f32)
681 return HasVSX ? PPC::XVCMPEQSP : PPC::VCMPEQFP;
682 else if (VecVT == MVT::v2f64)
683 return PPC::XVCMPEQDP;
689 if (VecVT == MVT::v16i8)
690 return PPC::VCMPGTSB;
691 else if (VecVT == MVT::v8i16)
692 return PPC::VCMPGTSH;
693 else if (VecVT == MVT::v4i32)
694 return PPC::VCMPGTSW;
695 else if (VecVT == MVT::v4f32)
696 return HasVSX ? PPC::XVCMPGTSP : PPC::VCMPGTFP;
697 else if (VecVT == MVT::v2f64)
698 return PPC::XVCMPGTDP;
704 if (VecVT == MVT::v16i8)
705 return PPC::VCMPGTUB;
706 else if (VecVT == MVT::v8i16)
707 return PPC::VCMPGTUH;
708 else if (VecVT == MVT::v4i32)
709 return PPC::VCMPGTUW;
712 if (VecVT == MVT::v4f32)
713 return HasVSX ? PPC::XVCMPEQSP : PPC::VCMPEQFP;
714 else if (VecVT == MVT::v2f64)
715 return PPC::XVCMPEQDP;
720 if (VecVT == MVT::v4f32)
721 return HasVSX ? PPC::XVCMPGTSP : PPC::VCMPGTFP;
722 else if (VecVT == MVT::v2f64)
723 return PPC::XVCMPGTDP;
726 if (VecVT == MVT::v4f32)
727 return HasVSX ? PPC::XVCMPGESP : PPC::VCMPGEFP;
728 else if (VecVT == MVT::v2f64)
729 return PPC::XVCMPGEDP;
734 llvm_unreachable("Invalid integer vector compare condition");
737 // getVCmpEQInst: return the equal compare instruction for the specified vector
738 // type. Since this is for altivec specific code, only support the altivec
739 // types (v16i8, v8i16, v4i32, and v4f32).
740 static unsigned int getVCmpEQInst(MVT::SimpleValueType VecVT, bool HasVSX) {
743 return PPC::VCMPEQUB;
745 return PPC::VCMPEQUH;
747 return PPC::VCMPEQUW;
749 return HasVSX ? PPC::XVCMPEQSP : PPC::VCMPEQFP;
751 return PPC::XVCMPEQDP;
753 llvm_unreachable("Invalid integer vector compare condition");
757 SDNode *PPCDAGToDAGISel::SelectSETCC(SDNode *N) {
760 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
761 EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy();
762 bool isPPC64 = (PtrVT == MVT::i64);
764 if (!PPCSubTarget->useCRBits() &&
765 isInt32Immediate(N->getOperand(1), Imm)) {
766 // We can codegen setcc op, imm very efficiently compared to a brcond.
767 // Check for those cases here.
770 SDValue Op = N->getOperand(0);
774 Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
775 SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
776 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
781 SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
782 Op, getI32Imm(~0U)), 0);
783 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
787 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
788 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
792 SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0);
793 T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0);
794 SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
795 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
798 } else if (Imm == ~0U) { // setcc op, -1
799 SDValue Op = N->getOperand(0);
804 Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
805 Op, getI32Imm(1)), 0);
806 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
807 SDValue(CurDAG->getMachineNode(PPC::LI, dl,
813 Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0);
814 SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
816 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0),
820 SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op,
822 SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD,
824 SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
825 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
828 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
829 Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops),
831 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
838 SDValue LHS = N->getOperand(0);
839 SDValue RHS = N->getOperand(1);
841 // Altivec Vector compare instructions do not set any CR register by default and
842 // vector compare operations return the same type as the operands.
843 if (LHS.getValueType().isVector()) {
844 EVT VecVT = LHS.getValueType();
845 MVT::SimpleValueType VT = VecVT.getSimpleVT().SimpleTy;
846 unsigned int VCmpInst = getVCmpInst(VT, CC, PPCSubTarget->hasVSX());
852 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS);
856 SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0);
857 return CurDAG->SelectNodeTo(N, PPCSubTarget->hasVSX() ? PPC::XXLNOR :
864 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, RHS, LHS);
868 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS);
872 // Small optimization: Altivec provides a 'Vector Compare Greater Than
873 // or Equal To' instruction (vcmpgefp), so in this case there is no
874 // need for extra logic for the equal compare.
875 if (VecVT.getSimpleVT().isFloatingPoint()) {
876 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS);
878 SDValue VCmpGT(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0);
879 unsigned int VCmpEQInst = getVCmpEQInst(VT, PPCSubTarget->hasVSX());
880 SDValue VCmpEQ(CurDAG->getMachineNode(VCmpEQInst, dl, VecVT, LHS, RHS), 0);
881 return CurDAG->SelectNodeTo(N, PPCSubTarget->hasVSX() ? PPC::XXLOR :
883 VecVT, VCmpGT, VCmpEQ);
889 SDValue VCmpLE(CurDAG->getMachineNode(VCmpInst, dl, VecVT, RHS, LHS), 0);
890 unsigned int VCmpEQInst = getVCmpEQInst(VT, PPCSubTarget->hasVSX());
891 SDValue VCmpEQ(CurDAG->getMachineNode(VCmpEQInst, dl, VecVT, LHS, RHS), 0);
892 return CurDAG->SelectNodeTo(N, PPCSubTarget->hasVSX() ? PPC::XXLOR :
894 VecVT, VCmpLE, VCmpEQ);
897 llvm_unreachable("Invalid vector compare type: should be expanded by legalize");
901 if (PPCSubTarget->useCRBits())
905 unsigned Idx = getCRIdxForSetCC(CC, Inv);
906 SDValue CCReg = SelectCC(LHS, RHS, CC, dl);
909 // Force the ccreg into CR7.
910 SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
912 SDValue InFlag(nullptr, 0); // Null incoming flag value.
913 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg,
916 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
919 SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
920 getI32Imm(31), getI32Imm(31) };
922 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
924 // Get the specified bit.
926 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
927 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
931 // Select - Convert the specified operand from a target-independent to a
932 // target-specific node if it hasn't already been changed.
933 SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
935 if (N->isMachineOpcode()) {
937 return nullptr; // Already selected.
940 switch (N->getOpcode()) {
943 case ISD::Constant: {
944 if (N->getValueType(0) == MVT::i64) {
946 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
947 // Assume no remaining bits.
948 unsigned Remainder = 0;
949 // Assume no shift required.
952 // If it can't be represented as a 32 bit value.
953 if (!isInt<32>(Imm)) {
954 Shift = countTrailingZeros<uint64_t>(Imm);
955 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
957 // If the shifted value fits 32 bits.
958 if (isInt<32>(ImmSh)) {
959 // Go with the shifted value.
962 // Still stuck with a 64 bit value.
969 // Intermediate operand.
972 // Handle first 32 bits.
973 unsigned Lo = Imm & 0xFFFF;
974 unsigned Hi = (Imm >> 16) & 0xFFFF;
977 if (isInt<16>(Imm)) {
979 Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo));
981 // Handle the Hi bits.
982 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
983 Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi));
985 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
986 SDValue(Result, 0), getI32Imm(Lo));
989 Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
992 // If no shift, we're done.
993 if (!Shift) return Result;
995 // Shift for next step if the upper 32-bits were not zero.
997 Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64,
1000 getI32Imm(63 - Shift));
1003 // Add in the last bits as required.
1004 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
1005 Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64,
1006 SDValue(Result, 0), getI32Imm(Hi));
1008 if ((Lo = Remainder & 0xFFFF)) {
1009 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
1010 SDValue(Result, 0), getI32Imm(Lo));
1019 SDNode *SN = SelectSETCC(N);
1024 case PPCISD::GlobalBaseReg:
1025 return getGlobalBaseReg();
1027 case ISD::FrameIndex: {
1028 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1029 SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
1030 unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
1032 return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), TFI,
1033 getSmallIPtrImm(0));
1034 return CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI,
1035 getSmallIPtrImm(0));
1038 case PPCISD::MFOCRF: {
1039 SDValue InFlag = N->getOperand(1);
1040 return CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32,
1041 N->getOperand(0), InFlag);
1045 // FIXME: since this depends on the setting of the carry flag from the srawi
1046 // we should really be making notes about that for the scheduler.
1047 // FIXME: It sure would be nice if we could cheaply recognize the
1048 // srl/add/sra pattern the dag combiner will generate for this as
1049 // sra/addze rather than having to handle sdiv ourselves. oh well.
1051 if (isInt32Immediate(N->getOperand(1), Imm)) {
1052 SDValue N0 = N->getOperand(0);
1053 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
1055 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue,
1056 N0, getI32Imm(Log2_32(Imm)));
1057 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
1058 SDValue(Op, 0), SDValue(Op, 1));
1059 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
1061 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue,
1062 N0, getI32Imm(Log2_32(-Imm)));
1064 SDValue(CurDAG->getMachineNode(PPC::ADDZE, dl, MVT::i32,
1065 SDValue(Op, 0), SDValue(Op, 1)),
1067 return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
1071 // Other cases are autogenerated.
1076 // Handle preincrement loads.
1077 LoadSDNode *LD = cast<LoadSDNode>(N);
1078 EVT LoadedVT = LD->getMemoryVT();
1080 // Normal loads are handled by code generated from the .td file.
1081 if (LD->getAddressingMode() != ISD::PRE_INC)
1084 SDValue Offset = LD->getOffset();
1085 if (Offset.getOpcode() == ISD::TargetConstant ||
1086 Offset.getOpcode() == ISD::TargetGlobalAddress) {
1089 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
1090 if (LD->getValueType(0) != MVT::i64) {
1091 // Handle PPC32 integer and normal FP loads.
1092 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
1093 switch (LoadedVT.getSimpleVT().SimpleTy) {
1094 default: llvm_unreachable("Invalid PPC load type!");
1095 case MVT::f64: Opcode = PPC::LFDU; break;
1096 case MVT::f32: Opcode = PPC::LFSU; break;
1097 case MVT::i32: Opcode = PPC::LWZU; break;
1098 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
1100 case MVT::i8: Opcode = PPC::LBZU; break;
1103 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
1104 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
1105 switch (LoadedVT.getSimpleVT().SimpleTy) {
1106 default: llvm_unreachable("Invalid PPC load type!");
1107 case MVT::i64: Opcode = PPC::LDU; break;
1108 case MVT::i32: Opcode = PPC::LWZU8; break;
1109 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
1111 case MVT::i8: Opcode = PPC::LBZU8; break;
1115 SDValue Chain = LD->getChain();
1116 SDValue Base = LD->getBasePtr();
1117 SDValue Ops[] = { Offset, Base, Chain };
1118 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
1119 PPCLowering->getPointerTy(),
1123 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
1124 if (LD->getValueType(0) != MVT::i64) {
1125 // Handle PPC32 integer and normal FP loads.
1126 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
1127 switch (LoadedVT.getSimpleVT().SimpleTy) {
1128 default: llvm_unreachable("Invalid PPC load type!");
1129 case MVT::f64: Opcode = PPC::LFDUX; break;
1130 case MVT::f32: Opcode = PPC::LFSUX; break;
1131 case MVT::i32: Opcode = PPC::LWZUX; break;
1132 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break;
1134 case MVT::i8: Opcode = PPC::LBZUX; break;
1137 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
1138 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) &&
1139 "Invalid sext update load");
1140 switch (LoadedVT.getSimpleVT().SimpleTy) {
1141 default: llvm_unreachable("Invalid PPC load type!");
1142 case MVT::i64: Opcode = PPC::LDUX; break;
1143 case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break;
1144 case MVT::i16: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8; break;
1146 case MVT::i8: Opcode = PPC::LBZUX8; break;
1150 SDValue Chain = LD->getChain();
1151 SDValue Base = LD->getBasePtr();
1152 SDValue Ops[] = { Base, Offset, Chain };
1153 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
1154 PPCLowering->getPointerTy(),
1160 unsigned Imm, Imm2, SH, MB, ME;
1163 // If this is an and of a value rotated between 0 and 31 bits and then and'd
1164 // with a mask, emit rlwinm
1165 if (isInt32Immediate(N->getOperand(1), Imm) &&
1166 isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) {
1167 SDValue Val = N->getOperand(0).getOperand(0);
1168 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1169 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
1171 // If this is just a masked value where the input is not handled above, and
1172 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
1173 if (isInt32Immediate(N->getOperand(1), Imm) &&
1174 isRunOfOnes(Imm, MB, ME) &&
1175 N->getOperand(0).getOpcode() != ISD::ROTL) {
1176 SDValue Val = N->getOperand(0);
1177 SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
1178 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
1180 // If this is a 64-bit zero-extension mask, emit rldicl.
1181 if (isInt64Immediate(N->getOperand(1).getNode(), Imm64) &&
1183 SDValue Val = N->getOperand(0);
1184 MB = 64 - CountTrailingOnes_64(Imm64);
1187 // If the operand is a logical right shift, we can fold it into this
1188 // instruction: rldicl(rldicl(x, 64-n, n), 0, mb) -> rldicl(x, 64-n, mb)
1189 // for n <= mb. The right shift is really a left rotate followed by a
1190 // mask, and this mask is a more-restrictive sub-mask of the mask implied
1192 if (Val.getOpcode() == ISD::SRL &&
1193 isInt32Immediate(Val.getOperand(1).getNode(), Imm) && Imm <= MB) {
1194 assert(Imm < 64 && "Illegal shift amount");
1195 Val = Val.getOperand(0);
1199 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB) };
1200 return CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops);
1202 // AND X, 0 -> 0, not "rlwinm 32".
1203 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
1204 ReplaceUses(SDValue(N, 0), N->getOperand(1));
1207 // ISD::OR doesn't get all the bitfield insertion fun.
1208 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
1209 if (isInt32Immediate(N->getOperand(1), Imm) &&
1210 N->getOperand(0).getOpcode() == ISD::OR &&
1211 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
1214 if (isRunOfOnes(Imm, MB, ME)) {
1215 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1216 N->getOperand(0).getOperand(1),
1217 getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
1218 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops);
1222 // Other cases are autogenerated.
1226 if (N->getValueType(0) == MVT::i32)
1227 if (SDNode *I = SelectBitfieldInsert(N))
1230 // Other cases are autogenerated.
1233 unsigned Imm, SH, MB, ME;
1234 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
1235 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1236 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1237 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1238 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
1241 // Other cases are autogenerated.
1245 unsigned Imm, SH, MB, ME;
1246 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
1247 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1248 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1249 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1250 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
1253 // Other cases are autogenerated.
1256 // FIXME: Remove this once the ANDI glue bug is fixed:
1257 case PPCISD::ANDIo_1_EQ_BIT:
1258 case PPCISD::ANDIo_1_GT_BIT: {
1262 EVT InVT = N->getOperand(0).getValueType();
1263 assert((InVT == MVT::i64 || InVT == MVT::i32) &&
1264 "Invalid input type for ANDIo_1_EQ_BIT");
1266 unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDIo8 : PPC::ANDIo;
1267 SDValue AndI(CurDAG->getMachineNode(Opcode, dl, InVT, MVT::Glue,
1269 CurDAG->getTargetConstant(1, InVT)), 0);
1270 SDValue CR0Reg = CurDAG->getRegister(PPC::CR0, MVT::i32);
1272 CurDAG->getTargetConstant(N->getOpcode() == PPCISD::ANDIo_1_EQ_BIT ?
1273 PPC::sub_eq : PPC::sub_gt, MVT::i32);
1275 return CurDAG->SelectNodeTo(N, TargetOpcode::EXTRACT_SUBREG, MVT::i1,
1277 SDValue(AndI.getNode(), 1) /* glue */);
1279 case ISD::SELECT_CC: {
1280 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1281 EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy();
1282 bool isPPC64 = (PtrVT == MVT::i64);
1284 // If this is a select of i1 operands, we'll pattern match it.
1285 if (PPCSubTarget->useCRBits() &&
1286 N->getOperand(0).getValueType() == MVT::i1)
1289 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
1291 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1292 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1293 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1294 if (N1C->isNullValue() && N3C->isNullValue() &&
1295 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
1296 // FIXME: Implement this optzn for PPC64.
1297 N->getValueType(0) == MVT::i32) {
1299 CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
1300 N->getOperand(0), getI32Imm(~0U));
1301 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
1302 SDValue(Tmp, 0), N->getOperand(0),
1306 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
1308 if (N->getValueType(0) == MVT::i1) {
1309 // An i1 select is: (c & t) | (!c & f).
1311 unsigned Idx = getCRIdxForSetCC(CC, Inv);
1315 default: llvm_unreachable("Invalid CC index");
1316 case 0: SRI = PPC::sub_lt; break;
1317 case 1: SRI = PPC::sub_gt; break;
1318 case 2: SRI = PPC::sub_eq; break;
1319 case 3: SRI = PPC::sub_un; break;
1322 SDValue CCBit = CurDAG->getTargetExtractSubreg(SRI, dl, MVT::i1, CCReg);
1324 SDValue NotCCBit(CurDAG->getMachineNode(PPC::CRNOR, dl, MVT::i1,
1326 SDValue C = Inv ? NotCCBit : CCBit,
1327 NotC = Inv ? CCBit : NotCCBit;
1329 SDValue CAndT(CurDAG->getMachineNode(PPC::CRAND, dl, MVT::i1,
1330 C, N->getOperand(2)), 0);
1331 SDValue NotCAndF(CurDAG->getMachineNode(PPC::CRAND, dl, MVT::i1,
1332 NotC, N->getOperand(3)), 0);
1334 return CurDAG->SelectNodeTo(N, PPC::CROR, MVT::i1, CAndT, NotCAndF);
1337 unsigned BROpc = getPredicateForSetCC(CC);
1339 unsigned SelectCCOp;
1340 if (N->getValueType(0) == MVT::i32)
1341 SelectCCOp = PPC::SELECT_CC_I4;
1342 else if (N->getValueType(0) == MVT::i64)
1343 SelectCCOp = PPC::SELECT_CC_I8;
1344 else if (N->getValueType(0) == MVT::f32)
1345 SelectCCOp = PPC::SELECT_CC_F4;
1346 else if (N->getValueType(0) == MVT::f64)
1347 SelectCCOp = PPC::SELECT_CC_F8;
1349 SelectCCOp = PPC::SELECT_CC_VRRC;
1351 SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
1353 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops);
1356 if (PPCSubTarget->hasVSX()) {
1357 SDValue Ops[] = { N->getOperand(2), N->getOperand(1), N->getOperand(0) };
1358 return CurDAG->SelectNodeTo(N, PPC::XXSEL, N->getValueType(0), Ops);
1362 case ISD::VECTOR_SHUFFLE:
1363 if (PPCSubTarget->hasVSX() && (N->getValueType(0) == MVT::v2f64 ||
1364 N->getValueType(0) == MVT::v2i64)) {
1365 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
1367 SDValue Op1 = N->getOperand(SVN->getMaskElt(0) < 2 ? 0 : 1),
1368 Op2 = N->getOperand(SVN->getMaskElt(1) < 2 ? 0 : 1);
1371 for (int i = 0; i < 2; ++i)
1372 if (SVN->getMaskElt(i) <= 0 || SVN->getMaskElt(i) == 2)
1377 SDValue DMV = CurDAG->getTargetConstant(DM[1] | (DM[0] << 1), MVT::i32);
1379 if (Op1 == Op2 && DM[0] == 0 && DM[1] == 0 &&
1380 Op1.getOpcode() == ISD::SCALAR_TO_VECTOR &&
1381 isa<LoadSDNode>(Op1.getOperand(0))) {
1382 LoadSDNode *LD = cast<LoadSDNode>(Op1.getOperand(0));
1383 SDValue Base, Offset;
1385 if (LD->isUnindexed() &&
1386 SelectAddrIdxOnly(LD->getBasePtr(), Base, Offset)) {
1387 SDValue Chain = LD->getChain();
1388 SDValue Ops[] = { Base, Offset, Chain };
1389 return CurDAG->SelectNodeTo(N, PPC::LXVDSX,
1390 N->getValueType(0), Ops);
1394 SDValue Ops[] = { Op1, Op2, DMV };
1395 return CurDAG->SelectNodeTo(N, PPC::XXPERMDI, N->getValueType(0), Ops);
1401 bool IsPPC64 = PPCSubTarget->isPPC64();
1402 SDValue Ops[] = { N->getOperand(1), N->getOperand(0) };
1403 return CurDAG->SelectNodeTo(N, N->getOpcode() == PPCISD::BDNZ ?
1404 (IsPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
1405 (IsPPC64 ? PPC::BDZ8 : PPC::BDZ),
1408 case PPCISD::COND_BRANCH: {
1409 // Op #0 is the Chain.
1410 // Op #1 is the PPC::PRED_* number.
1412 // Op #3 is the Dest MBB
1413 // Op #4 is the Flag.
1414 // Prevent PPC::PRED_* from being selected into LI.
1416 getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue());
1417 SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
1418 N->getOperand(0), N->getOperand(4) };
1419 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
1422 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
1423 unsigned PCC = getPredicateForSetCC(CC);
1425 if (N->getOperand(2).getValueType() == MVT::i1) {
1429 default: llvm_unreachable("Unexpected Boolean-operand predicate");
1430 case PPC::PRED_LT: Opc = PPC::CRANDC; Swap = true; break;
1431 case PPC::PRED_LE: Opc = PPC::CRORC; Swap = true; break;
1432 case PPC::PRED_EQ: Opc = PPC::CREQV; Swap = false; break;
1433 case PPC::PRED_GE: Opc = PPC::CRORC; Swap = false; break;
1434 case PPC::PRED_GT: Opc = PPC::CRANDC; Swap = false; break;
1435 case PPC::PRED_NE: Opc = PPC::CRXOR; Swap = false; break;
1438 SDValue BitComp(CurDAG->getMachineNode(Opc, dl, MVT::i1,
1439 N->getOperand(Swap ? 3 : 2),
1440 N->getOperand(Swap ? 2 : 3)), 0);
1441 return CurDAG->SelectNodeTo(N, PPC::BC, MVT::Other,
1442 BitComp, N->getOperand(4), N->getOperand(0));
1445 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
1446 SDValue Ops[] = { getI32Imm(PCC), CondCode,
1447 N->getOperand(4), N->getOperand(0) };
1448 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
1451 // FIXME: Should custom lower this.
1452 SDValue Chain = N->getOperand(0);
1453 SDValue Target = N->getOperand(1);
1454 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
1455 unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8;
1456 Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, Target,
1458 return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);
1460 case PPCISD::TOC_ENTRY: {
1461 if (PPCSubTarget->isSVR4ABI() && !PPCSubTarget->isPPC64()) {
1462 SDValue GA = N->getOperand(0);
1463 return CurDAG->getMachineNode(PPC::LWZtoc, dl, MVT::i32, GA,
1466 assert (PPCSubTarget->isPPC64() &&
1467 "Only supported for 64-bit ABI and 32-bit SVR4");
1469 // For medium and large code model, we generate two instructions as
1470 // described below. Otherwise we allow SelectCodeCommon to handle this,
1471 // selecting one of LDtoc, LDtocJTI, and LDtocCPT.
1472 CodeModel::Model CModel = TM.getCodeModel();
1473 if (CModel != CodeModel::Medium && CModel != CodeModel::Large)
1476 // The first source operand is a TargetGlobalAddress or a TargetJumpTable.
1477 // If it is an externally defined symbol, a symbol with common linkage,
1478 // a non-local function address, or a jump table address, or if we are
1479 // generating code for large code model, we generate:
1480 // LDtocL(<ga:@sym>, ADDIStocHA(%X2, <ga:@sym>))
1481 // Otherwise we generate:
1482 // ADDItocL(ADDIStocHA(%X2, <ga:@sym>), <ga:@sym>)
1483 SDValue GA = N->getOperand(0);
1484 SDValue TOCbase = N->getOperand(1);
1485 SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA, dl, MVT::i64,
1488 if (isa<JumpTableSDNode>(GA) || CModel == CodeModel::Large)
1489 return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
1492 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(GA)) {
1493 const GlobalValue *GValue = G->getGlobal();
1494 if ((GValue->getType()->getElementType()->isFunctionTy() &&
1495 (GValue->isDeclaration() || GValue->isWeakForLinker())) ||
1496 GValue->isDeclaration() || GValue->hasCommonLinkage() ||
1497 GValue->hasAvailableExternallyLinkage())
1498 return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
1502 return CurDAG->getMachineNode(PPC::ADDItocL, dl, MVT::i64,
1503 SDValue(Tmp, 0), GA);
1505 case PPCISD::VADD_SPLAT: {
1506 // This expands into one of three sequences, depending on whether
1507 // the first operand is odd or even, positive or negative.
1508 assert(isa<ConstantSDNode>(N->getOperand(0)) &&
1509 isa<ConstantSDNode>(N->getOperand(1)) &&
1510 "Invalid operand on VADD_SPLAT!");
1512 int Elt = N->getConstantOperandVal(0);
1513 int EltSize = N->getConstantOperandVal(1);
1514 unsigned Opc1, Opc2, Opc3;
1518 Opc1 = PPC::VSPLTISB;
1519 Opc2 = PPC::VADDUBM;
1520 Opc3 = PPC::VSUBUBM;
1522 } else if (EltSize == 2) {
1523 Opc1 = PPC::VSPLTISH;
1524 Opc2 = PPC::VADDUHM;
1525 Opc3 = PPC::VSUBUHM;
1528 assert(EltSize == 4 && "Invalid element size on VADD_SPLAT!");
1529 Opc1 = PPC::VSPLTISW;
1530 Opc2 = PPC::VADDUWM;
1531 Opc3 = PPC::VSUBUWM;
1535 if ((Elt & 1) == 0) {
1536 // Elt is even, in the range [-32,-18] + [16,30].
1538 // Convert: VADD_SPLAT elt, size
1539 // Into: tmp = VSPLTIS[BHW] elt
1540 // VADDU[BHW]M tmp, tmp
1541 // Where: [BHW] = B for size = 1, H for size = 2, W for size = 4
1542 SDValue EltVal = getI32Imm(Elt >> 1);
1543 SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
1544 SDValue TmpVal = SDValue(Tmp, 0);
1545 return CurDAG->getMachineNode(Opc2, dl, VT, TmpVal, TmpVal);
1547 } else if (Elt > 0) {
1548 // Elt is odd and positive, in the range [17,31].
1550 // Convert: VADD_SPLAT elt, size
1551 // Into: tmp1 = VSPLTIS[BHW] elt-16
1552 // tmp2 = VSPLTIS[BHW] -16
1553 // VSUBU[BHW]M tmp1, tmp2
1554 SDValue EltVal = getI32Imm(Elt - 16);
1555 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
1556 EltVal = getI32Imm(-16);
1557 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
1558 return CurDAG->getMachineNode(Opc3, dl, VT, SDValue(Tmp1, 0),
1562 // Elt is odd and negative, in the range [-31,-17].
1564 // Convert: VADD_SPLAT elt, size
1565 // Into: tmp1 = VSPLTIS[BHW] elt+16
1566 // tmp2 = VSPLTIS[BHW] -16
1567 // VADDU[BHW]M tmp1, tmp2
1568 SDValue EltVal = getI32Imm(Elt + 16);
1569 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
1570 EltVal = getI32Imm(-16);
1571 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
1572 return CurDAG->getMachineNode(Opc2, dl, VT, SDValue(Tmp1, 0),
1578 return SelectCode(N);
1581 /// PostprocessISelDAG - Perform some late peephole optimizations
1582 /// on the DAG representation.
1583 void PPCDAGToDAGISel::PostprocessISelDAG() {
1585 // Skip peepholes at -O0.
1586 if (TM.getOptLevel() == CodeGenOpt::None)
1593 // Check if all users of this node will become isel where the second operand
1594 // is the constant zero. If this is so, and if we can negate the condition,
1595 // then we can flip the true and false operands. This will allow the zero to
1596 // be folded with the isel so that we don't need to materialize a register
1598 bool PPCDAGToDAGISel::AllUsersSelectZero(SDNode *N) {
1599 // If we're not using isel, then this does not matter.
1600 if (!PPCSubTarget->hasISEL())
1603 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
1606 if (!User->isMachineOpcode())
1608 if (User->getMachineOpcode() != PPC::SELECT_I4 &&
1609 User->getMachineOpcode() != PPC::SELECT_I8)
1612 SDNode *Op2 = User->getOperand(2).getNode();
1613 if (!Op2->isMachineOpcode())
1616 if (Op2->getMachineOpcode() != PPC::LI &&
1617 Op2->getMachineOpcode() != PPC::LI8)
1620 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op2->getOperand(0));
1624 if (!C->isNullValue())
1631 void PPCDAGToDAGISel::SwapAllSelectUsers(SDNode *N) {
1632 SmallVector<SDNode *, 4> ToReplace;
1633 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
1636 assert((User->getMachineOpcode() == PPC::SELECT_I4 ||
1637 User->getMachineOpcode() == PPC::SELECT_I8) &&
1638 "Must have all select users");
1639 ToReplace.push_back(User);
1642 for (SmallVector<SDNode *, 4>::iterator UI = ToReplace.begin(),
1643 UE = ToReplace.end(); UI != UE; ++UI) {
1646 CurDAG->getMachineNode(User->getMachineOpcode(), SDLoc(User),
1647 User->getValueType(0), User->getOperand(0),
1648 User->getOperand(2),
1649 User->getOperand(1));
1651 DEBUG(dbgs() << "CR Peephole replacing:\nOld: ");
1652 DEBUG(User->dump(CurDAG));
1653 DEBUG(dbgs() << "\nNew: ");
1654 DEBUG(ResNode->dump(CurDAG));
1655 DEBUG(dbgs() << "\n");
1657 ReplaceUses(User, ResNode);
1661 void PPCDAGToDAGISel::PeepholeCROps() {
1665 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
1666 E = CurDAG->allnodes_end(); I != E; ++I) {
1667 MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(I);
1668 if (!MachineNode || MachineNode->use_empty())
1670 SDNode *ResNode = MachineNode;
1672 bool Op1Set = false, Op1Unset = false,
1674 Op2Set = false, Op2Unset = false,
1677 unsigned Opcode = MachineNode->getMachineOpcode();
1688 SDValue Op = MachineNode->getOperand(1);
1689 if (Op.isMachineOpcode()) {
1690 if (Op.getMachineOpcode() == PPC::CRSET)
1692 else if (Op.getMachineOpcode() == PPC::CRUNSET)
1694 else if (Op.getMachineOpcode() == PPC::CRNOR &&
1695 Op.getOperand(0) == Op.getOperand(1))
1701 case PPC::SELECT_I4:
1702 case PPC::SELECT_I8:
1703 case PPC::SELECT_F4:
1704 case PPC::SELECT_F8:
1705 case PPC::SELECT_VRRC: {
1706 SDValue Op = MachineNode->getOperand(0);
1707 if (Op.isMachineOpcode()) {
1708 if (Op.getMachineOpcode() == PPC::CRSET)
1710 else if (Op.getMachineOpcode() == PPC::CRUNSET)
1712 else if (Op.getMachineOpcode() == PPC::CRNOR &&
1713 Op.getOperand(0) == Op.getOperand(1))
1720 bool SelectSwap = false;
1724 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
1726 ResNode = MachineNode->getOperand(0).getNode();
1729 ResNode = MachineNode->getOperand(1).getNode();
1732 ResNode = MachineNode->getOperand(0).getNode();
1733 else if (Op1Unset || Op2Unset)
1734 // x & 0 = 0 & y = 0
1735 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
1738 // ~x & y = andc(y, x)
1739 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
1740 MVT::i1, MachineNode->getOperand(1),
1741 MachineNode->getOperand(0).
1744 // x & ~y = andc(x, y)
1745 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
1746 MVT::i1, MachineNode->getOperand(0),
1747 MachineNode->getOperand(1).
1749 else if (AllUsersSelectZero(MachineNode))
1750 ResNode = CurDAG->getMachineNode(PPC::CRNAND, SDLoc(MachineNode),
1751 MVT::i1, MachineNode->getOperand(0),
1752 MachineNode->getOperand(1)),
1756 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
1757 // nand(x, x) -> nor(x, x)
1758 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1759 MVT::i1, MachineNode->getOperand(0),
1760 MachineNode->getOperand(0));
1762 // nand(1, y) -> nor(y, y)
1763 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1764 MVT::i1, MachineNode->getOperand(1),
1765 MachineNode->getOperand(1));
1767 // nand(x, 1) -> nor(x, x)
1768 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1769 MVT::i1, MachineNode->getOperand(0),
1770 MachineNode->getOperand(0));
1771 else if (Op1Unset || Op2Unset)
1772 // nand(x, 0) = nand(0, y) = 1
1773 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
1776 // nand(~x, y) = ~(~x & y) = x | ~y = orc(x, y)
1777 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
1778 MVT::i1, MachineNode->getOperand(0).
1780 MachineNode->getOperand(1));
1782 // nand(x, ~y) = ~x | y = orc(y, x)
1783 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
1784 MVT::i1, MachineNode->getOperand(1).
1786 MachineNode->getOperand(0));
1787 else if (AllUsersSelectZero(MachineNode))
1788 ResNode = CurDAG->getMachineNode(PPC::CRAND, SDLoc(MachineNode),
1789 MVT::i1, MachineNode->getOperand(0),
1790 MachineNode->getOperand(1)),
1794 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
1796 ResNode = MachineNode->getOperand(0).getNode();
1797 else if (Op1Set || Op2Set)
1798 // x | 1 = 1 | y = 1
1799 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
1803 ResNode = MachineNode->getOperand(1).getNode();
1806 ResNode = MachineNode->getOperand(0).getNode();
1808 // ~x | y = orc(y, x)
1809 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
1810 MVT::i1, MachineNode->getOperand(1),
1811 MachineNode->getOperand(0).
1814 // x | ~y = orc(x, y)
1815 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
1816 MVT::i1, MachineNode->getOperand(0),
1817 MachineNode->getOperand(1).
1819 else if (AllUsersSelectZero(MachineNode))
1820 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1821 MVT::i1, MachineNode->getOperand(0),
1822 MachineNode->getOperand(1)),
1826 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
1828 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
1831 // xor(1, y) -> nor(y, y)
1832 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1833 MVT::i1, MachineNode->getOperand(1),
1834 MachineNode->getOperand(1));
1836 // xor(x, 1) -> nor(x, x)
1837 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1838 MVT::i1, MachineNode->getOperand(0),
1839 MachineNode->getOperand(0));
1842 ResNode = MachineNode->getOperand(1).getNode();
1845 ResNode = MachineNode->getOperand(0).getNode();
1847 // xor(~x, y) = eqv(x, y)
1848 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
1849 MVT::i1, MachineNode->getOperand(0).
1851 MachineNode->getOperand(1));
1853 // xor(x, ~y) = eqv(x, y)
1854 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
1855 MVT::i1, MachineNode->getOperand(0),
1856 MachineNode->getOperand(1).
1858 else if (AllUsersSelectZero(MachineNode))
1859 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
1860 MVT::i1, MachineNode->getOperand(0),
1861 MachineNode->getOperand(1)),
1865 if (Op1Set || Op2Set)
1867 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
1870 // nor(0, y) = ~y -> nor(y, y)
1871 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1872 MVT::i1, MachineNode->getOperand(1),
1873 MachineNode->getOperand(1));
1876 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1877 MVT::i1, MachineNode->getOperand(0),
1878 MachineNode->getOperand(0));
1880 // nor(~x, y) = andc(x, y)
1881 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
1882 MVT::i1, MachineNode->getOperand(0).
1884 MachineNode->getOperand(1));
1886 // nor(x, ~y) = andc(y, x)
1887 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
1888 MVT::i1, MachineNode->getOperand(1).
1890 MachineNode->getOperand(0));
1891 else if (AllUsersSelectZero(MachineNode))
1892 ResNode = CurDAG->getMachineNode(PPC::CROR, SDLoc(MachineNode),
1893 MVT::i1, MachineNode->getOperand(0),
1894 MachineNode->getOperand(1)),
1898 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
1900 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
1904 ResNode = MachineNode->getOperand(1).getNode();
1907 ResNode = MachineNode->getOperand(0).getNode();
1909 // eqv(0, y) = ~y -> nor(y, y)
1910 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1911 MVT::i1, MachineNode->getOperand(1),
1912 MachineNode->getOperand(1));
1915 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1916 MVT::i1, MachineNode->getOperand(0),
1917 MachineNode->getOperand(0));
1919 // eqv(~x, y) = xor(x, y)
1920 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
1921 MVT::i1, MachineNode->getOperand(0).
1923 MachineNode->getOperand(1));
1925 // eqv(x, ~y) = xor(x, y)
1926 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
1927 MVT::i1, MachineNode->getOperand(0),
1928 MachineNode->getOperand(1).
1930 else if (AllUsersSelectZero(MachineNode))
1931 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
1932 MVT::i1, MachineNode->getOperand(0),
1933 MachineNode->getOperand(1)),
1937 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
1939 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
1943 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1944 MVT::i1, MachineNode->getOperand(1),
1945 MachineNode->getOperand(1));
1946 else if (Op1Unset || Op2Set)
1947 // andc(0, y) = andc(x, 1) = 0
1948 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
1952 ResNode = MachineNode->getOperand(0).getNode();
1954 // andc(~x, y) = ~(x | y) = nor(x, y)
1955 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1956 MVT::i1, MachineNode->getOperand(0).
1958 MachineNode->getOperand(1));
1960 // andc(x, ~y) = x & y
1961 ResNode = CurDAG->getMachineNode(PPC::CRAND, SDLoc(MachineNode),
1962 MVT::i1, MachineNode->getOperand(0),
1963 MachineNode->getOperand(1).
1965 else if (AllUsersSelectZero(MachineNode))
1966 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
1967 MVT::i1, MachineNode->getOperand(1),
1968 MachineNode->getOperand(0)),
1972 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
1974 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
1976 else if (Op1Set || Op2Unset)
1977 // orc(1, y) = orc(x, 0) = 1
1978 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
1982 ResNode = MachineNode->getOperand(0).getNode();
1985 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
1986 MVT::i1, MachineNode->getOperand(1),
1987 MachineNode->getOperand(1));
1989 // orc(~x, y) = ~(x & y) = nand(x, y)
1990 ResNode = CurDAG->getMachineNode(PPC::CRNAND, SDLoc(MachineNode),
1991 MVT::i1, MachineNode->getOperand(0).
1993 MachineNode->getOperand(1));
1995 // orc(x, ~y) = x | y
1996 ResNode = CurDAG->getMachineNode(PPC::CROR, SDLoc(MachineNode),
1997 MVT::i1, MachineNode->getOperand(0),
1998 MachineNode->getOperand(1).
2000 else if (AllUsersSelectZero(MachineNode))
2001 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
2002 MVT::i1, MachineNode->getOperand(1),
2003 MachineNode->getOperand(0)),
2006 case PPC::SELECT_I4:
2007 case PPC::SELECT_I8:
2008 case PPC::SELECT_F4:
2009 case PPC::SELECT_F8:
2010 case PPC::SELECT_VRRC:
2012 ResNode = MachineNode->getOperand(1).getNode();
2014 ResNode = MachineNode->getOperand(2).getNode();
2016 ResNode = CurDAG->getMachineNode(MachineNode->getMachineOpcode(),
2018 MachineNode->getValueType(0),
2019 MachineNode->getOperand(0).
2021 MachineNode->getOperand(2),
2022 MachineNode->getOperand(1));
2027 ResNode = CurDAG->getMachineNode(Opcode == PPC::BC ? PPC::BCn :
2031 MachineNode->getOperand(0).
2033 MachineNode->getOperand(1),
2034 MachineNode->getOperand(2));
2035 // FIXME: Handle Op1Set, Op1Unset here too.
2039 // If we're inverting this node because it is used only by selects that
2040 // we'd like to swap, then swap the selects before the node replacement.
2042 SwapAllSelectUsers(MachineNode);
2044 if (ResNode != MachineNode) {
2045 DEBUG(dbgs() << "CR Peephole replacing:\nOld: ");
2046 DEBUG(MachineNode->dump(CurDAG));
2047 DEBUG(dbgs() << "\nNew: ");
2048 DEBUG(ResNode->dump(CurDAG));
2049 DEBUG(dbgs() << "\n");
2051 ReplaceUses(MachineNode, ResNode);
2056 CurDAG->RemoveDeadNodes();
2057 } while (IsModified);
2060 void PPCDAGToDAGISel::PeepholePPC64() {
2061 // These optimizations are currently supported only for 64-bit SVR4.
2062 if (PPCSubTarget->isDarwin() || !PPCSubTarget->isPPC64())
2065 SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode());
2068 while (Position != CurDAG->allnodes_begin()) {
2069 SDNode *N = --Position;
2070 // Skip dead nodes and any non-machine opcodes.
2071 if (N->use_empty() || !N->isMachineOpcode())
2075 unsigned StorageOpcode = N->getMachineOpcode();
2077 switch (StorageOpcode) {
2108 // If this is a load or store with a zero offset, we may be able to
2109 // fold an add-immediate into the memory operation.
2110 if (!isa<ConstantSDNode>(N->getOperand(FirstOp)) ||
2111 N->getConstantOperandVal(FirstOp) != 0)
2114 SDValue Base = N->getOperand(FirstOp + 1);
2115 if (!Base.isMachineOpcode())
2119 bool ReplaceFlags = true;
2121 // When the feeding operation is an add-immediate of some sort,
2122 // determine whether we need to add relocation information to the
2123 // target flags on the immediate operand when we fold it into the
2124 // load instruction.
2126 // For something like ADDItocL, the relocation information is
2127 // inferred from the opcode; when we process it in the AsmPrinter,
2128 // we add the necessary relocation there. A load, though, can receive
2129 // relocation from various flavors of ADDIxxx, so we need to carry
2130 // the relocation information in the target flags.
2131 switch (Base.getMachineOpcode()) {
2136 // In some cases (such as TLS) the relocation information
2137 // is already in place on the operand, so copying the operand
2139 ReplaceFlags = false;
2140 // For these cases, the immediate may not be divisible by 4, in
2141 // which case the fold is illegal for DS-form instructions. (The
2142 // other cases provide aligned addresses and are always safe.)
2143 if ((StorageOpcode == PPC::LWA ||
2144 StorageOpcode == PPC::LD ||
2145 StorageOpcode == PPC::STD) &&
2146 (!isa<ConstantSDNode>(Base.getOperand(1)) ||
2147 Base.getConstantOperandVal(1) % 4 != 0))
2150 case PPC::ADDIdtprelL:
2151 Flags = PPCII::MO_DTPREL_LO;
2153 case PPC::ADDItlsldL:
2154 Flags = PPCII::MO_TLSLD_LO;
2157 Flags = PPCII::MO_TOC_LO;
2161 // We found an opportunity. Reverse the operands from the add
2162 // immediate and substitute them into the load or store. If
2163 // needed, update the target flags for the immediate operand to
2164 // reflect the necessary relocation information.
2165 DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase: ");
2166 DEBUG(Base->dump(CurDAG));
2167 DEBUG(dbgs() << "\nN: ");
2168 DEBUG(N->dump(CurDAG));
2169 DEBUG(dbgs() << "\n");
2171 SDValue ImmOpnd = Base.getOperand(1);
2173 // If the relocation information isn't already present on the
2174 // immediate operand, add it now.
2176 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) {
2178 const GlobalValue *GV = GA->getGlobal();
2179 // We can't perform this optimization for data whose alignment
2180 // is insufficient for the instruction encoding.
2181 if (GV->getAlignment() < 4 &&
2182 (StorageOpcode == PPC::LD || StorageOpcode == PPC::STD ||
2183 StorageOpcode == PPC::LWA)) {
2184 DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n");
2187 ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, 0, Flags);
2188 } else if (ConstantPoolSDNode *CP =
2189 dyn_cast<ConstantPoolSDNode>(ImmOpnd)) {
2190 const Constant *C = CP->getConstVal();
2191 ImmOpnd = CurDAG->getTargetConstantPool(C, MVT::i64,
2197 if (FirstOp == 1) // Store
2198 (void)CurDAG->UpdateNodeOperands(N, N->getOperand(0), ImmOpnd,
2199 Base.getOperand(0), N->getOperand(3));
2201 (void)CurDAG->UpdateNodeOperands(N, ImmOpnd, Base.getOperand(0),
2204 // The add-immediate may now be dead, in which case remove it.
2205 if (Base.getNode()->use_empty())
2206 CurDAG->RemoveDeadNode(Base.getNode());
2211 /// createPPCISelDag - This pass converts a legalized DAG into a
2212 /// PowerPC-specific DAG, ready for instruction scheduling.
2214 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
2215 return new PPCDAGToDAGISel(TM);
2218 static void initializePassOnce(PassRegistry &Registry) {
2219 const char *Name = "PowerPC DAG->DAG Pattern Instruction Selection";
2220 PassInfo *PI = new PassInfo(Name, "ppc-codegen", &SelectionDAGISel::ID,
2221 nullptr, false, false);
2222 Registry.registerPass(*PI, true);
2225 void llvm::initializePPCDAGToDAGISelPass(PassRegistry &Registry) {
2226 CALL_ONCE_INITIALIZATION(initializePassOnce);